* c:\fossee\esim\library\subcircuitlibrary\74lvc1g97\74lvc1g97.cir

* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
* u8  net-_u6-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and
* u6  net-_u2-pad2_ net-_u6-pad2_ d_inverter
* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad4_ d_or
* u9  net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ d_and
* u7  net-_u3-pad2_ net-_u7-pad2_ d_inverter
* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
* u5  net-_u4-pad2_ net-_u5-pad2_ d_inverter
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
a1 net-_u1-pad2_ net-_u3-pad2_ u3
a2 [net-_u6-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8
a3 net-_u2-pad2_ net-_u6-pad2_ u6
a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad4_ u10
a5 [net-_u7-pad2_ net-_u4-pad2_ ] net-_u10-pad2_ u9
a6 net-_u3-pad2_ net-_u7-pad2_ u7
a7 net-_u1-pad1_ net-_u2-pad2_ u2
a8 net-_u1-pad3_ net-_u4-pad2_ u4
a9 net-_u4-pad2_ net-_u5-pad2_ u5
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end