* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\4bitadder_2nd_test\4bitadder_2nd_test.cir .include 4_OR.sub .include 3_and.sub .include 4_and.sub * u2 /cin net-_u2-pad2_ d_inverter * u4 /b1 /a1 net-_u10-pad1_ d_nor * u8 /b1 /a1 net-_u7-pad1_ d_nand * u12 /b2 /a2 net-_u12-pad3_ d_nor * u15 /b2 /a2 net-_u14-pad1_ d_nand * u18 /b3 /a3 net-_u18-pad3_ d_nor * u21 /b3 /a3 net-_u21-pad3_ d_nand * u25 /b4 /a4 net-_u25-pad3_ d_nor * u26 /b4 /a4 net-_u26-pad3_ d_nand * u1 /cin /a1 /s1 /b1 /s2 /a2 /b2 /a3 /b3 /s3 /a4 /b4 /s4 /cout port * u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter * u6 net-_u10-pad1_ net-_u6-pad2_ d_inverter * u7 net-_u7-pad1_ net-_u6-pad2_ net-_u5-pad1_ d_and * u5 net-_u5-pad1_ net-_u3-pad2_ /s1 d_xor * u9 net-_u7-pad1_ net-_u2-pad2_ net-_u10-pad2_ d_and * u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor * u13 net-_u12-pad3_ net-_u13-pad2_ d_inverter * u14 net-_u14-pad1_ net-_u13-pad2_ net-_u11-pad1_ d_and * u11 net-_u11-pad1_ net-_u10-pad3_ /s2 d_xor x1 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_u16-pad2_ 3_and * u17 net-_u10-pad1_ net-_u14-pad1_ net-_u16-pad1_ d_and * u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or * u20 net-_u12-pad3_ net-_u16-pad3_ net-_u19-pad1_ d_or * u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter * u23 net-_u18-pad3_ net-_u23-pad2_ d_inverter * u24 net-_u21-pad3_ net-_u23-pad2_ net-_u22-pad1_ d_and * u22 net-_u22-pad1_ net-_u19-pad2_ /s3 d_xor x2 net-_u21-pad3_ net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x2-pad5_ 4_and x3 net-_u10-pad1_ net-_u21-pad3_ net-_u14-pad1_ net-_x3-pad4_ 3_and * u28 net-_u12-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_and x4 net-_u18-pad3_ net-_u28-pad3_ net-_x3-pad4_ net-_x2-pad5_ net-_u27-pad1_ 4_OR * u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter * u29 net-_u29-pad1_ net-_u27-pad2_ /s4 d_xor * u30 net-_u25-pad3_ net-_u30-pad2_ d_inverter * u31 net-_u26-pad3_ net-_u30-pad2_ net-_u29-pad1_ d_and x5 net-_u14-pad1_ net-_u7-pad1_ net-_u2-pad2_ net-_x5-pad4_ 3_and x6 net-_u26-pad3_ net-_u21-pad3_ net-_x5-pad4_ net-_x6-pad4_ 3_and x7 net-_u10-pad1_ net-_u26-pad3_ net-_u21-pad3_ net-_u14-pad1_ net-_x7-pad5_ 4_and x8 net-_u12-pad3_ net-_u26-pad3_ net-_u21-pad3_ net-_x8-pad4_ 3_and * u32 net-_u18-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_and x9 net-_u32-pad3_ net-_x8-pad4_ net-_x7-pad5_ net-_x6-pad4_ net-_u33-pad2_ 4_OR * u33 net-_u25-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or * u34 net-_u33-pad3_ /cout d_inverter a1 /cin net-_u2-pad2_ u2 a2 [/b1 /a1 ] net-_u10-pad1_ u4 a3 [/b1 /a1 ] net-_u7-pad1_ u8 a4 [/b2 /a2 ] net-_u12-pad3_ u12 a5 [/b2 /a2 ] net-_u14-pad1_ u15 a6 [/b3 /a3 ] net-_u18-pad3_ u18 a7 [/b3 /a3 ] net-_u21-pad3_ u21 a8 [/b4 /a4 ] net-_u25-pad3_ u25 a9 [/b4 /a4 ] net-_u26-pad3_ u26 a10 net-_u2-pad2_ net-_u3-pad2_ u3 a11 net-_u10-pad1_ net-_u6-pad2_ u6 a12 [net-_u7-pad1_ net-_u6-pad2_ ] net-_u5-pad1_ u7 a13 [net-_u5-pad1_ net-_u3-pad2_ ] /s1 u5 a14 [net-_u7-pad1_ net-_u2-pad2_ ] net-_u10-pad2_ u9 a15 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 a16 net-_u12-pad3_ net-_u13-pad2_ u13 a17 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u11-pad1_ u14 a18 [net-_u11-pad1_ net-_u10-pad3_ ] /s2 u11 a19 [net-_u10-pad1_ net-_u14-pad1_ ] net-_u16-pad1_ u17 a20 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 a21 [net-_u12-pad3_ net-_u16-pad3_ ] net-_u19-pad1_ u20 a22 net-_u19-pad1_ net-_u19-pad2_ u19 a23 net-_u18-pad3_ net-_u23-pad2_ u23 a24 [net-_u21-pad3_ net-_u23-pad2_ ] net-_u22-pad1_ u24 a25 [net-_u22-pad1_ net-_u19-pad2_ ] /s3 u22 a26 [net-_u12-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28 a27 net-_u27-pad1_ net-_u27-pad2_ u27 a28 [net-_u29-pad1_ net-_u27-pad2_ ] /s4 u29 a29 net-_u25-pad3_ net-_u30-pad2_ u30 a30 [net-_u26-pad3_ net-_u30-pad2_ ] net-_u29-pad1_ u31 a31 [net-_u18-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 a32 [net-_u25-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 a33 net-_u33-pad3_ /cout u34 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u22 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u29 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) .tran 0e-00 0e-00 0e-00 * Control Statements .control run print allv > plot_data_v.txt print alli > plot_data_i.txt .endc .end