* Subcircuit 74HC27
.subckt 74HC27 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
* c:\fossee\esim\library\subcircuitlibrary\74hc27\74hc27.cir
* u2  net-_u1-pad2_ net-_u1-pad1_ net-_u2-pad3_ d_or
* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_or
* u6  net-_u4-pad3_ net-_u1-pad4_ d_inverter
* u13  net-_u1-pad12_ net-_u1-pad10_ net-_u11-pad1_ d_or
* u11  net-_u11-pad1_ net-_u1-pad8_ net-_u11-pad3_ d_or
* u9  net-_u11-pad3_ net-_u1-pad6_ d_inverter
* u12  net-_u1-pad11_ net-_u1-pad9_ net-_u10-pad1_ d_or
* u10  net-_u10-pad1_ net-_u1-pad7_ net-_u10-pad3_ d_or
* u8  net-_u10-pad3_ net-_u1-pad5_ d_inverter
a1 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u2-pad3_ u2
a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
a3 net-_u4-pad3_ net-_u1-pad4_ u6
a4 [net-_u1-pad12_ net-_u1-pad10_ ] net-_u11-pad1_ u13
a5 [net-_u11-pad1_ net-_u1-pad8_ ] net-_u11-pad3_ u11
a6 net-_u11-pad3_ net-_u1-pad6_ u9
a7 [net-_u1-pad11_ net-_u1-pad9_ ] net-_u10-pad1_ u12
a8 [net-_u10-pad1_ net-_u1-pad7_ ] net-_u10-pad3_ u10
a9 net-_u10-pad3_ net-_u1-pad5_ u8
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements

.ends 74HC27