* c:\fossee\esim\library\subcircuitlibrary\74hc125\74hc125.cir

* u4  net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ d_tristate
* u5  net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ d_tristate
* u8  net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ d_tristate
* u9  net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ d_tristate
* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
* u6  net-_u1-pad7_ net-_u6-pad2_ d_inverter
* u7  net-_u1-pad9_ net-_u7-pad2_ d_inverter
a1 net-_u1-pad3_ net-_u2-pad2_ net-_u1-pad5_ u4
a2 net-_u1-pad4_ net-_u3-pad2_ net-_u1-pad6_ u5
a3 net-_u1-pad11_ net-_u6-pad2_ net-_u1-pad8_ u8
a4 net-_u1-pad12_ net-_u7-pad2_ net-_u1-pad10_ u9
a5 net-_u1-pad1_ net-_u2-pad2_ u2
a6 net-_u1-pad2_ net-_u3-pad2_ u3
a7 net-_u1-pad7_ net-_u6-pad2_ u6
a8 net-_u1-pad9_ net-_u7-pad2_ u7
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end