* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir

.include 3_and.sub
x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
* Schematic Name: d_and, NgSpice Name: d_and
.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end