* OPA171 - Rev. B * Created by Ian Williams; January 17, 2017 * Created with Green-Williams-Lis Op Amp Macro-model Architecture * Copyright 2017 by Texas Instruments Corporation ****************************************************** * MACRO-MODEL SIMULATED PARAMETERS: ****************************************************** * OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol) * UNITY GAIN BANDWIDTH (GBW) * INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR) * POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR) * DIFFERENTIAL INPUT IMPEDANCE (Zid) * COMMON-MODE INPUT IMPEDANCE (Zic) * OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo) * OUTPUT CURRENT THROUGH THE SUPPLY (Iout) * INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en) * INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in) * OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo) * SHORT-CIRCUIT OUTPUT CURRENT (Isc) * QUIESCENT CURRENT (Iq) * SETTLING TIME VS. CAPACITIVE LOAD (ts) * SLEW RATE (SR) * SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD * LARGE SIGNAL RESPONSE * OVERLOAD RECOVERY TIME (tor) * INPUT BIAS CURRENT (Ib) * INPUT OFFSET CURRENT (Ios) * INPUT OFFSET VOLTAGE (Vos) * INPUT COMMON-MODE VOLTAGE RANGE (Vcm) * INPUT/OUTPUT ESD CELLS (ESDin, ESDout) ****************************************************** .subckt OPA171 IN+ IN- VCC VEE OUT ****************************************************** * MODEL DEFINITIONS: .model BB_SW VSWITCH(Ron=50 Roff=1e9 Von=700e-3 Voff=0) .model ESD_SW VSWITCH(Ron=50 Roff=1e9 Von=500e-3 Voff=100e-3) .model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3) .model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0) .model R_NOISELESS RES(T_ABS=-273.15) ****************************************************** V_OS N041 en_n 214.023e-6 R1 N043 N042 R_NOISELESS 1e-3 R2 N049 ESDn R_NOISELESS 1e-3 R3 N063 0 R_NOISELESS 1e12 C1 N063 0 1 R4 VCC_B N062 R_NOISELESS 1e-3 C2 N062 0 1e-15 C3 N064 0 1e-15 R5 N064 VEE_B R_NOISELESS 1e-3 G_PSR N043 N044 N005 N014 1e-3 R6 MID N047 R_NOISELESS 1e9 VCM_MIN N048 VEE_B -0.1 R7 N048 MID R_NOISELESS 1e9 VCM_MAX N047 VCC_B -2 XVCM_CLAMP N044 MID N045 MID N047 N048 VCCS_EXT_LIM R8 N045 MID R_NOISELESS 1 C4 VCM_CLAMP MID 1e-15 R9 N045 VCM_CLAMP R_NOISELESS 1e-3 V4 N061 OUT 0 R10 MID N051 R_NOISELESS 1e9 R11 MID N052 R_NOISELESS 1e9 XIQp VIMON MID VCC MID VCCS_LIM_IQ XIQn MID VIMON VEE MID VCCS_LIM_IQ R12 VCC_B N016 R_NOISELESS 1e3 R13 N029 VEE_B R_NOISELESS 1e3 XCLAWp VIMON MID N016 VCC_B VCCS_LIM_CLAWp XCLAWn MID VIMON VEE_B N029 VCCS_LIM_CLAWn R14 VEE_CLP MID R_NOISELESS 1e3 R15 MID VCC_CLP R_NOISELESS 1e3 R16 N017 N016 R_NOISELESS 1e-3 R17 N030 N029 R_NOISELESS 1e-3 C5 MID N017 1e-15 C6 N030 MID 1e-15 R18 VOUT_S N052 R_NOISELESS 100 C7 VOUT_S MID 1e-9 G2 MID VCC_CLP N017 MID 1e-3 G3 MID VEE_CLP N030 MID 1e-3 XCL_AMP N013 N039 VIMON MID N020 N027 CLAMP_AMP_LO V_ISCp N013 MID 25 V_ISCn N039 MID -35 XOL_SENSE MID N068 OLN OLP OL_SENSE R19 N039 MID R_NOISELESS 1e9 R20 N027 MID R_NOISELESS 1 C8 N028 MID 1e-15 R21 MID N020 R_NOISELESS 1 R22 MID N013 R_NOISELESS 1e9 C9 MID N021 1e-15 XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N018 N025 CLAMP_AMP_LO R23 VEE_CLP MID R_NOISELESS 1e9 R24 N025 MID R_NOISELESS 1 C10 N026 MID 1e-15 R25 MID N018 R_NOISELESS 1 R26 MID VCC_CLP R_NOISELESS 1e9 C11 MID N019 1e-15 XCL_SRC N021 N028 CL_CLAMP MID VCCS_LIM_4 XCLAW_SRC N019 N026 CLAW_CLAMP MID VCCS_LIM_3 R27 N018 N019 R_NOISELESS 1e-3 R28 N026 N025 R_NOISELESS 1e-3 R29 N020 N021 R_NOISELESS 1e-3 R30 N028 N027 R_NOISELESS 1e-3 R31 N068 MID R_NOISELESS 1 R32 N068 SW_OL R_NOISELESS 100 C12 SW_OL MID 10e-12 R33 VIMON N051 R_NOISELESS 100 C13 VIMON MID 1e-9 C_DIFF en_p ESDn 3e-12 C_CMn ESDn MID 3e-12 C_CMp MID en_p 3e-12 I_Q VCC VEE 475e-6 I_B N044 MID 8e-12 I_OS N049 MID 4e-12 R36 N037 MID R_NOISELESS 1 R37 N040 MID R_NOISELESS 1e9 R38 MID N023 R_NOISELESS 1 R39 MID N015 R_NOISELESS 1e9 XGR_AMP N015 N040 N022 MID N023 N037 CLAMP_AMP_HI XGR_SRC N024 N038 CLAMP MID VCCS_LIM_GR C17 MID N024 1e-15 C18 N038 MID 1e-15 V_GRn N040 MID -50 V_GRp N015 MID 50 R40 N023 N024 R_NOISELESS 1e-3 R41 N038 N037 R_NOISELESS 1e-3 R42 VSENSE N022 R_NOISELESS 1e-3 C19 MID N022 1e-15 R43 MID VSENSE R_NOISELESS 1e3 G_CMR N041 N042 N012 MID 1e-3 G8 MID CLAW_CLAMP N050 MID 1e-3 R45 MID CLAW_CLAMP R_NOISELESS 1e3 G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3 R46 MID CL_CLAMP R_NOISELESS 1e3 R47 N059 VCLP R_NOISELESS 100 C24 MID VCLP 100e-12 E4 N059 MID CL_CLAMP MID 1 E5 N052 MID OUT MID 1 H1 N051 MID V4 1e3 S1 N054 N053 SW_OL MID OL_SW R52 MID en_p R_NOISELESS 1e9 R53 ESDn MID R_NOISELESS 1e9 R_CMR N042 N041 R_NOISELESS 1e3 R59 N062 N063 R_NOISELESS 1e6 R60 N063 N064 R_NOISELESS 1e6 R_PSR N044 N043 R_NOISELESS 1e3 G15 MID VSENSE CLAMP MID 1e-3 V_ORp N036 VCLP 3 V_ORn N031 VCLP -3 V11 N033 N032 0 V12 N034 N035 0 H2 OLN MID V11 -1 H3 OLP MID V12 1 S2 VCC ESDn ESDn VCC ESD_SW S3 VCC en_p en_p VCC ESD_SW S4 ESDn VEE VEE ESDn ESD_SW S5 en_p VEE VEE en_p ESD_SW S6 VCC OUT OUT VCC ESD_SW S7 OUT VEE VEE OUT ESD_SW E1 MID 0 N063 0 1 G16 0 VCC_B VCC 0 1 G17 0 VEE_B VEE 0 1 R88 VCC_B 0 R_NOISELESS 1 R89 VEE_B 0 R_NOISELESS 1 S8 N034 CLAMP CLAMP N034 OR_SW S9 CLAMP N033 N033 CLAMP OR_SW Xi_np en_n MID FEMT Xi_nn ESDn MID FEMT XVCCS_LIM_1 VCM_CLAMP N049 MID N046 VCCS_LIM_1 XVCCS_LIM_2 N046 MID MID CLAMP VCCS_LIM_2 R44 N046 MID R_NOISELESS 1e6 R58 CLAMP MID R_NOISELESS 1e6 C20 CLAMP MID 1.484e-7 S10 en_p ESDn ESDn en_p BB_SW S11 ESDn en_p en_p ESDn BB_SW R34 en_p IN+ R_NOISELESS 10e-3 R35 ESDn IN- R_NOISELESS 10e-3 R48 MID N050 R_NOISELESS 1e6 G1 MID N050 VSENSE MID 1e-6 C14 N050 MID 7.4e-15 Rx N061 N060 R_NOISELESS 1.65e4 Rdummy N061 MID R_NOISELESS 1.65e3 G_Zo MID N053 CL_CLAMP N061 172 Rdc1 N053 MID R_NOISELESS 1 R49 N053 N054 R_NOISELESS 1e5 R50 N054 MID R_NOISELESS 1.266e3 G4 MID N057 N054 MID 80 C15 N054 N053 1.592e-6 R51 N057 MID R_NOISELESS 1 C16 N067 MID 1.929e-10 R54 N067 N058 R_NOISELESS 10e3 R55 N058 N057 R_NOISELESS 1.547e6 C23 N007 N006 1.516e-12 G_adjust1 MID N006 en_p MID 4.75e-4 Rsrc1 N006 MID R_NOISELESS 1 R56 N007 MID R_NOISELESS 2.104e5 R57 N007 N006 R_NOISELESS 1e8 G5 MID N008 N007 MID 1 Rsrc2 N008 MID R_NOISELESS 1 R61 N009 N008 R_NOISELESS 1e4 C25 N009 N008 1.516e-8 R62 N009 MID R_NOISELESS 2.104e1 G6 MID N012 N009 MID 4.762e2 Rsrc3 N012 MID R_NOISELESS 1 C26 N011 N010 3.745e-10 G_adjust2 MID N010 VEE_B MID 1.588e-1 Rsrc4 N010 MID R_NOISELESS 1 R63 N011 MID R_NOISELESS 6.296e2 R64 N011 N010 R_NOISELESS 1e8 G7 MID N014 N011 MID 1 Rsrc5 N014 MID R_NOISELESS 1 C27 N003 N004 2.792e-12 G_adjust3 MID N004 VCC_B MID 3.772e-4 Rsrc6 N004 MID R_NOISELESS 1 R65 N003 MID R_NOISELESS 2.658e5 R66 N003 N004 R_NOISELESS 1e8 G10 MID N002 N003 MID 1 Rsrc7 N002 MID R_NOISELESS 1 R67 N001 N002 R_NOISELESS 1e4 C28 N001 N002 2.792e-8 R68 N001 MID R_NOISELESS 2.658e1 G11 MID N005 N001 MID 3.772e2 Rsrc8 N005 MID R_NOISELESS 1 Xe_n N065 MID VNSE G12 MID N066 N065 N069 1 R69 N066 N069 R_NOISELESS 1e6 R70 N066 N069 R_NOISELESS 11.786e3 C29 N066 N069 6.75e-12 R71 N069 N070 R_NOISELESS 15e3 C30 N070 MID 106e-12 Rpd N070 MID R_NOISELESS 1e9 E2 en_p en_n N066 MID 1 G13 MID N055 N058 MID 1 R72 N055 MID R_NOISELESS 1 R73 N056 N055 R_NOISELESS 1e4 R74 MID N056 R_NOISELESS 5 C21 N056 N055 3.183e-13 XVCCS_LIM_ZO N056 MID MID N060 VCCS_LIM_ZO R76 MID N060 R_NOISELESS 1 G14 MID N032 N031 MID 1 G18 MID N035 N036 MID 1 R77 MID N032 R_NOISELESS 1 R78 MID N035 R_NOISELESS 1 .ends OPA171 * .subckt CLAMP_AMP_HI VC+ VC- VIN COM VO+ VO- .param G=10 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)10e-3 | V(4,1)>10e-3),1,0)} .ends OL_SENSE * .subckt FEMT 1 2 .param FLWF=1e-3 .param NLFF=1 .param NVRF=1 .param GLFF={PWR(FLWF,0.25)*NLFF/1164} .param RNVF={1.184*PWR(NVRF,2)} .model DVNF D KF={PWR(FLWF,0.5)/1e11} IS=1.0e-16 I1 0 7 10e-3 I2 0 8 10e-3 D1 7 0 DVNF D2 8 0 DVNF E1 3 6 7 8 {GLFF} R1 3 0 1e9 R2 3 0 1e9 R3 3 6 1e9 E2 6 4 5 0 10 R4 5 0 {RNVF} R5 5 0 {RNVF} R6 3 4 1e9 R7 4 0 1e9 G1 1 2 3 4 1e-6 .ends FEMT * .subckt VCCS_EXT_LIM VIN+ VIN- IOUT- IOUT+ VP+ VP- .param Gain = 1 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))} .ends VCCS_EXT_LIM * .subckt VCCS_LIM_1 VC+ VC- IOUT+ IOUT- .param Gain = 1e-4 .param Ipos = .5 .param Ineg = -.5 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_1 * .subckt VCCS_LIM_2 VC+ VC- IOUT+ IOUT- .param Gain = 3.40e-2 .param Ipos = 0.224 .param Ineg = -0.224 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_2 * .subckt VCCS_LIM_3 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 100e-3 .param Ineg = -100e-3 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_3 * .subckt VCCS_LIM_4 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 200e-3 .param Ineg = -200e-3 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_4 * .subckt VCCS_LIM_CLAWn VC+ VC- IOUT+ IOUT- G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} = +(0, 1e-5) +(3.38, 3.1e-5) +(3.66, 3.2e-5) +(3.87, 7.8e-5) +(6.67, 5.64e-4) +(8, 8.48e-4) +(15, 2.23e-3) +(35, 6.3e-3) .ends VCCS_LIM_CLAWn * .subckt VCCS_LIM_IQ VC+ VC- IOUT+ IOUT- .param Gain = 1e-3 G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )} .ends VCCS_LIM_IQ * .subckt VNSE 1 2 .param FLW=20 .param NLF=45 .param NVR=14 .param GLF={PWR(FLW,0.25)*NLF/1164} .param RNV={1.184*PWR(NVR,2)} .model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16 I1 0 7 10E-3 I2 0 8 10E-3 D1 7 0 DVN D2 8 0 DVN E1 3 6 7 8 {GLF} R1 3 0 1E9 R2 3 0 1E9 R3 3 6 1E9 E2 6 4 5 0 10 R4 5 0 {RNV} R5 5 0 {RNV} R6 3 4 1E9 R7 4 0 1E9 E3 1 2 3 4 1 .ends VNSE * .subckt CLAMP_AMP_LO VC+ VC- VIN COM VO+ VO- .param G=1 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)