From 8843fd178992f82ea96478fe87cba80209af2ad8 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Wed, 18 Dec 2019 16:35:32 +0530
Subject: restored OMEdit code, trigger for rename_project

---
 src/frontEnd/Application.py     | 51 ++++++++++++++++++++++++++++++++++++++---
 src/frontEnd/ProjectExplorer.py |  2 ++
 2 files changed, 50 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 4f77a321..8973501d 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: Application.py
 #
 #         USAGE: ---
@@ -11,10 +10,13 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Wednesday 21 January 2015
-#      REVISION:  ---
+#       CREATED: Tuesday 24 Feb 2015 
+#      REVISION: Wednesday 18 Dec 2019
 # =========================================================================
+
+
 import pathmagic  # noqa
 from PyQt4 import QtGui, QtCore
 from configuration.Appconfig import Appconfig
@@ -437,6 +439,49 @@ class Application(QtGui.QMainWindow):
                 self.modelicaNetlist = os.path.join(
                     self.projDir, self.projName + ".mo")
 
+                """
+                try:
+                    # Creating a command for Ngspice to Modelica converter
+                    self.cmd1 = "
+                        python3 ../ngspicetoModelica/NgspicetoModelica.py "\
+                            +self.ngspiceNetlist
+                    self.obj_workThread1 = Worker.WorkerThread(self.cmd1)
+                    self.obj_workThread1.start()
+                    if self.obj_validation.validateTool("OMEdit"):
+                        # Creating command to run OMEdit
+                        self.cmd2 = "OMEdit "+self.modelicaNetlist
+                        self.obj_workThread2 = Worker.WorkerThread(self.cmd2)
+                        self.obj_workThread2.start()
+                    else:
+                        self.msg = QtGui.QMessageBox()
+                        self.msgContent = "There was an error while
+                            opening OMEdit.<br/>\
+                        Please make sure OpenModelica is installed in your\
+                            system. <br/>\
+                        To install it on Linux : Go to\
+                            <a href=https://www.openmodelica.org/download/\
+                                download-linux>OpenModelica Linux</a> and  \
+                                    install nigthly build release.<br/>\
+                        To install it on Windows : Go to\
+                         <a href=https://www.openmodelica.org/download/\
+                        download-windows>OpenModelica Windows</a>\
+                         and install latest version.<br/>"
+                        self.msg.setTextFormat(QtCore.Qt.RichText)
+                        self.msg.setText(self.msgContent)
+                        self.msg.setWindowTitle("Missing OpenModelica")
+                        self.obj_appconfig.print_info(self.msgContent)
+                        self.msg.exec_()
+                
+                except Exception as e:
+                    self.msg = QtGui.QErrorMessage()
+                    self.msg.showMessage(
+                        'Unable to convert NgSpice netlist to\
+                            Modelica netlist :'+str(e))
+                    self.msg.setWindowTitle(
+                        "Ngspice to Modelica conversion error")
+                    self.obj_appconfig.print_error(str(e))
+                """
+
                 self.obj_Mainview.obj_dockarea.modelicaEditor(self.projDir)
 
             else:
diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py
index 4627d294..09e756af 100644
--- a/src/frontEnd/ProjectExplorer.py
+++ b/src/frontEnd/ProjectExplorer.py
@@ -101,6 +101,8 @@ class ProjectExplorer(QtGui.QWidget):
 
         menu = QtGui.QMenu()
         if level == 0:
+            renameProject = menu.addAction(self.tr("Rename Project"))
+            renameProject.triggered.connect(self.renameProject)
             deleteproject = menu.addAction(self.tr("Remove Project"))
             deleteproject.triggered.connect(self.removeProject)
             refreshproject = menu.addAction(self.tr("Refresh"))
-- 
cgit 


From 44489a55fbe8bfa02e2b5707e265121132dce8dd Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Wed, 18 Dec 2019 16:36:06 +0530
Subject: changed debug statement

---
 src/configuration/Appconfig.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py
index 38a55595..2ab8743e 100644
--- a/src/configuration/Appconfig.py
+++ b/src/configuration/Appconfig.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: Appconfig.py
 #
 #         USAGE: ---
@@ -11,9 +10,10 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Wednesday 04 February 2015
-#      REVISION:  ---
+#       CREATED: Tuesday 24 Feb 2015 
+#      REVISION: Wednesday 18 Dec 2019
 # =========================================================================
 
 
@@ -64,7 +64,7 @@ class Appconfig(QtGui.QWidget):
     try:
         modelica_map_json = parser_esim.get('eSim', 'MODELICA_MAP_JSON')
     except BaseException:
-        print("Cannot access eSim in parser")
+        print("Cannot access Modelica's map_json path --- .esim folder")
 
     try:
         project_explorer = json.load(open(dictPath))
-- 
cgit 


From 08d4a0336550a0e610709970a0c5d366e109fe82 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Wed, 18 Dec 2019 16:36:50 +0530
Subject: removed appending dock windows to current_project

---
 src/frontEnd/DockArea.py | 44 +++++++++++++++++++++-----------------------
 1 file changed, 21 insertions(+), 23 deletions(-)

(limited to 'src')

diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py
index 0aa8ff17..db706fa7 100644
--- a/src/frontEnd/DockArea.py
+++ b/src/frontEnd/DockArea.py
@@ -14,8 +14,6 @@ dockList = ['Welcome']
 count = 1
 dock = {}
 
-
-#
 class DockArea(QtGui.QMainWindow):
     """
     This class contains function for designing UI of all the editors
@@ -76,9 +74,9 @@ class DockArea(QtGui.QMainWindow):
 
         dock['Tips-' + str(count)].raise_()
 
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['Tips-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['Tips-' + str(count)])
         count = count + 1
 
     def plottingEditor(self):
@@ -106,9 +104,9 @@ class DockArea(QtGui.QMainWindow):
         dock['Plotting-' + str(count)].setFocus()
         dock['Plotting-' + str(count)].raise_()
 
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['Plotting-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['Plotting-' + str(count)])
         count = count + 1
 
     def ngspiceEditor(self, projDir):
@@ -145,9 +143,9 @@ class DockArea(QtGui.QMainWindow):
         dock['NgSpice-' + str(count)].setVisible(True)
         dock['NgSpice-' + str(count)].setFocus()
         dock['NgSpice-' + str(count)].raise_()
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['NgSpice-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['NgSpice-' + str(count)])
         count = count + 1
 
     def modelEditor(self):
@@ -180,9 +178,9 @@ class DockArea(QtGui.QMainWindow):
         dock['Model Editor-' + str(count)].setFocus()
         dock['Model Editor-' + str(count)].raise_()
 
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['Model Editor-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['Model Editor-' + str(count)])
         count = count + 1
 
     def kicadToNgspiceEditor(self, clarg1, clarg2=None):
@@ -215,9 +213,9 @@ class DockArea(QtGui.QMainWindow):
         dock['kicadToNgspice-' + str(count)].setFocus()
         dock['kicadToNgspice-' + str(count)].raise_()
 
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['kicadToNgspice-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['kicadToNgspice-' + str(count)])
         count = count + 1
 
     def subcircuiteditor(self):
@@ -246,9 +244,9 @@ class DockArea(QtGui.QMainWindow):
         dock['Subcircuit-' + str(count)].setFocus()
         dock['Subcircuit-' + str(count)].raise_()
 
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['Subcircuit-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['Subcircuit-' + str(count)])
         count = count + 1
 
     def usermanual(self):
@@ -302,9 +300,9 @@ class DockArea(QtGui.QMainWindow):
         .QWidget { border-radius: 15px; border: 1px solid gray;\
             padding: 5px; width: 200px; height: 150px;  } \
         ")
-        temp = self.obj_appconfig.current_project['ProjectName']
-        self.obj_appconfig.dock_dict[temp].append(
-            dock['Modelica-' + str(count)])
+        # temp = self.obj_appconfig.current_project['ProjectName']
+        # self.obj_appconfig.dock_dict[temp].append(
+        #     dock['Modelica-' + str(count)])
 
         count = count + 1
 
-- 
cgit 


From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 15:16:35 +0530
Subject: common code for Win and Linux, merged py2 changes

---
 src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib    |  154 +-
 src/SubcircuitLibrary/2bitmul/2bitmul.cir          |   34 +-
 src/SubcircuitLibrary/2bitmul/2bitmul.cir.out      |   62 +-
 src/SubcircuitLibrary/2bitmul/2bitmul.pro          |  148 +-
 src/SubcircuitLibrary/2bitmul/2bitmul.sch          |  568 +++---
 src/SubcircuitLibrary/2bitmul/2bitmul.sub          |   48 +-
 src/SubcircuitLibrary/3_and/3_and-cache.lib        |  122 +-
 src/SubcircuitLibrary/3_and/3_and.cir              |   26 +-
 src/SubcircuitLibrary/3_and/3_and.cir.out          |   40 +-
 src/SubcircuitLibrary/3_and/3_and.pro              |   88 +-
 src/SubcircuitLibrary/3_and/3_and.sch              |  260 +--
 src/SubcircuitLibrary/3_and/3_and.sub              |   26 +-
 src/SubcircuitLibrary/4002/4002-cache.lib          |   82 +
 src/SubcircuitLibrary/4002/4002.cir                |   17 +
 src/SubcircuitLibrary/4002/4002.cir.out            |   36 +
 src/SubcircuitLibrary/4002/4002.pro                |   44 +
 src/SubcircuitLibrary/4002/4002.sch                |  315 +++
 src/SubcircuitLibrary/4002/4002.sub                |   30 +
 .../4002/4002_Previous_Values.xml                  |    1 +
 src/SubcircuitLibrary/4002/analysis                |    1 +
 src/SubcircuitLibrary/4012/4012-cache.lib          |   75 +
 src/SubcircuitLibrary/4012/4012.cir                |   19 +
 src/SubcircuitLibrary/4012/4012.cir.out            |   44 +
 src/SubcircuitLibrary/4012/4012.pro                |   44 +
 src/SubcircuitLibrary/4012/4012.sch                |  342 ++++
 src/SubcircuitLibrary/4012/4012.sub                |   38 +
 .../4012/4012_Previous_Values.xml                  |    1 +
 src/SubcircuitLibrary/4012/analysis                |    1 +
 src/SubcircuitLibrary/4017/4017-cache.lib          |   79 +
 src/SubcircuitLibrary/4017/4017.cir                |   26 +
 src/SubcircuitLibrary/4017/4017.cir.out            |   72 +
 src/SubcircuitLibrary/4017/4017.pro                |   72 +
 src/SubcircuitLibrary/4017/4017.sch                |  580 ++++++
 src/SubcircuitLibrary/4017/4017.sub                |   66 +
 .../4017/4017_Previous_Values.xml                  |    1 +
 src/SubcircuitLibrary/4017/D.lib                   |   11 +
 src/SubcircuitLibrary/4017/analysis                |    1 +
 src/SubcircuitLibrary/4023/3_and-cache.lib         |   61 +
 src/SubcircuitLibrary/4023/3_and.cir               |   13 +
 src/SubcircuitLibrary/4023/3_and.cir.out           |   20 +
 src/SubcircuitLibrary/4023/3_and.pro               |   44 +
 src/SubcircuitLibrary/4023/3_and.sch               |  130 ++
 src/SubcircuitLibrary/4023/3_and.sub               |   14 +
 .../4023/3_and_Previous_Values.xml                 |    1 +
 src/SubcircuitLibrary/4023/4023-cache.lib          |   76 +
 src/SubcircuitLibrary/4023/4023.cir                |   17 +
 src/SubcircuitLibrary/4023/4023.cir.out            |   28 +
 src/SubcircuitLibrary/4023/4023.pro                |   44 +
 src/SubcircuitLibrary/4023/4023.sch                |  309 +++
 src/SubcircuitLibrary/4023/4023.sub                |   22 +
 .../4023/4023_Previous_Values.xml                  |    1 +
 src/SubcircuitLibrary/4023/analysis                |    1 +
 src/SubcircuitLibrary/4028/4028-cache.lib          |   94 +
 src/SubcircuitLibrary/4028/4028.cir                |   32 +
 src/SubcircuitLibrary/4028/4028.cir.out            |   96 +
 src/SubcircuitLibrary/4028/4028.pro                |   43 +
 src/SubcircuitLibrary/4028/4028.sch                |  628 ++++++
 src/SubcircuitLibrary/4028/4028.sub                |   90 +
 .../4028/4028_Previous_Values.xml                  |    1 +
 src/SubcircuitLibrary/4028/analysis                |    1 +
 src/SubcircuitLibrary/4073/3_and-cache.lib         |  122 +-
 src/SubcircuitLibrary/4073/3_and.cir               |   26 +-
 src/SubcircuitLibrary/4073/3_and.cir.out           |   40 +-
 src/SubcircuitLibrary/4073/3_and.pro               |   88 +-
 src/SubcircuitLibrary/4073/3_and.sch               |  260 +--
 src/SubcircuitLibrary/4073/3_and.sub               |   26 +-
 src/SubcircuitLibrary/4073/4073-cache.lib          |  124 +-
 src/SubcircuitLibrary/4073/4073.cir                |   28 +-
 src/SubcircuitLibrary/4073/4073.cir.out            |   32 +-
 src/SubcircuitLibrary/4073/4073.pro                |   86 +-
 src/SubcircuitLibrary/4073/4073.sch                |  526 ++---
 src/SubcircuitLibrary/4073/4073.sub                |   18 +-
 src/SubcircuitLibrary/4_OR/4_OR-cache.lib          |  126 +-
 src/SubcircuitLibrary/4_OR/4_OR.cir                |   28 +-
 src/SubcircuitLibrary/4_OR/4_OR.cir.out            |   48 +-
 src/SubcircuitLibrary/4_OR/4_OR.pro                |   90 +-
 src/SubcircuitLibrary/4_OR/4_OR.sch                |  300 +--
 src/SubcircuitLibrary/4_OR/4_OR.sub                |   34 +-
 src/SubcircuitLibrary/4_and/3_and-cache.lib        |  122 +-
 src/SubcircuitLibrary/4_and/3_and.cir              |   26 +-
 src/SubcircuitLibrary/4_and/3_and.cir.out          |   40 +-
 src/SubcircuitLibrary/4_and/3_and.pro              |   88 +-
 src/SubcircuitLibrary/4_and/3_and.sch              |  260 +--
 src/SubcircuitLibrary/4_and/3_and.sub              |   26 +-
 src/SubcircuitLibrary/4_and/4_and-cache.lib        |  158 +-
 src/SubcircuitLibrary/4_and/4_and-rescue.lib       |   44 +-
 src/SubcircuitLibrary/4_and/4_and.cir              |   26 +-
 src/SubcircuitLibrary/4_and/4_and.cir.out          |   36 +-
 src/SubcircuitLibrary/4_and/4_and.pro              |  116 +-
 src/SubcircuitLibrary/4_and/4_and.sch              |  302 +--
 src/SubcircuitLibrary/4_and/4_and.sub              |   22 +-
 src/SubcircuitLibrary/4to16_demux/3_and-cache.lib  |  122 +-
 src/SubcircuitLibrary/4to16_demux/3_and.cir        |   26 +-
 src/SubcircuitLibrary/4to16_demux/3_and.cir.out    |   40 +-
 src/SubcircuitLibrary/4to16_demux/3_and.pro        |   88 +-
 src/SubcircuitLibrary/4to16_demux/3_and.sch        |  260 +--
 src/SubcircuitLibrary/4to16_demux/3_and.sub        |   26 +-
 src/SubcircuitLibrary/4to16_demux/5_and-cache.lib  |  158 +-
 src/SubcircuitLibrary/4to16_demux/5_and.cir        |   28 +-
 src/SubcircuitLibrary/4to16_demux/5_and.cir.out    |   44 +-
 src/SubcircuitLibrary/4to16_demux/5_and.pro        |  100 +-
 src/SubcircuitLibrary/4to16_demux/5_and.sch        |  342 ++--
 src/SubcircuitLibrary/4to16_demux/5_and.sub        |   30 +-
 src/SubcircuitLibrary/556/556-cache.lib            |   64 +
 src/SubcircuitLibrary/556/556.cir                  |   13 +
 src/SubcircuitLibrary/556/556.cir.out              |   15 +
 src/SubcircuitLibrary/556/556.pro                  |   72 +
 src/SubcircuitLibrary/556/556.sch                  |  275 +++
 src/SubcircuitLibrary/556/556.sub                  |    9 +
 src/SubcircuitLibrary/556/556_Previous_Values.xml  |    1 +
 src/SubcircuitLibrary/5_and/3_and-cache.lib        |  122 +-
 src/SubcircuitLibrary/5_and/3_and.cir              |   26 +-
 src/SubcircuitLibrary/5_and/3_and.cir.out          |   40 +-
 src/SubcircuitLibrary/5_and/3_and.pro              |   88 +-
 src/SubcircuitLibrary/5_and/3_and.sch              |  260 +--
 src/SubcircuitLibrary/5_and/3_and.sub              |   26 +-
 src/SubcircuitLibrary/5_and/5_and-cache.lib        |  158 +-
 src/SubcircuitLibrary/5_and/5_and.cir              |   28 +-
 src/SubcircuitLibrary/5_and/5_and.cir.out          |   44 +-
 src/SubcircuitLibrary/5_and/5_and.pro              |  100 +-
 src/SubcircuitLibrary/5_and/5_and.sch              |  342 ++--
 src/SubcircuitLibrary/5_and/5_and.sub              |   30 +-
 src/SubcircuitLibrary/74153/3_and-cache.lib        |  122 +-
 src/SubcircuitLibrary/74153/3_and.cir              |   26 +-
 src/SubcircuitLibrary/74153/3_and.cir.out          |   40 +-
 src/SubcircuitLibrary/74153/3_and.pro              |  102 +-
 src/SubcircuitLibrary/74153/3_and.sch              |  251 ++-
 src/SubcircuitLibrary/74153/3_and.sub              |   26 +-
 src/SubcircuitLibrary/74153/4_OR-cache.lib         |  126 +-
 src/SubcircuitLibrary/74153/4_OR.cir               |   28 +-
 src/SubcircuitLibrary/74153/4_OR.cir.out           |   48 +-
 src/SubcircuitLibrary/74153/4_OR.pro               |   90 +-
 src/SubcircuitLibrary/74153/4_OR.sch               |  300 +--
 src/SubcircuitLibrary/74153/4_OR.sub               |   34 +-
 .../74153/4_OR_Previous_Values.xml                 |    2 +-
 src/SubcircuitLibrary/74153/4_and-cache.lib        |  158 +-
 src/SubcircuitLibrary/74153/4_and.cir              |   26 +-
 src/SubcircuitLibrary/74153/4_and.cir.out          |   36 +-
 src/SubcircuitLibrary/74153/4_and.pro              |  115 +-
 src/SubcircuitLibrary/74153/4_and.sch              |  290 ++-
 src/SubcircuitLibrary/74153/4_and.sub              |   22 +-
 src/SubcircuitLibrary/74153/74153-cache.lib        |   46 +-
 src/SubcircuitLibrary/74153/74153.cir              |   34 +-
 src/SubcircuitLibrary/74153/74153.cir.out          |   42 +-
 src/SubcircuitLibrary/74153/74153.pro              |   40 +-
 src/SubcircuitLibrary/74153/74153.sch              |  218 +--
 src/SubcircuitLibrary/74153/74153.sub              |   40 +-
 .../74153/74153_Previous_Values.xml                |    2 +-
 src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib  |  188 +-
 src/SubcircuitLibrary/74153/Dual4to1MUX.cir        |   90 +-
 src/SubcircuitLibrary/74153/Dual4to1MUX.sch        | 1628 ++++++++--------
 src/SubcircuitLibrary/74153/analysis               |    2 +-
 src/SubcircuitLibrary/74157/3_and-cache.lib        |  122 +-
 src/SubcircuitLibrary/74157/3_and.cir              |   26 +-
 src/SubcircuitLibrary/74157/3_and.cir.out          |   40 +-
 src/SubcircuitLibrary/74157/3_and.pro              |  102 +-
 src/SubcircuitLibrary/74157/3_and.sch              |  251 ++-
 src/SubcircuitLibrary/74157/3_and.sub              |   26 +-
 src/SubcircuitLibrary/74157/74157-cache.lib        |   16 +-
 src/SubcircuitLibrary/74157/74157.cir              |   34 +-
 src/SubcircuitLibrary/74157/74157.cir.out          |   44 +-
 src/SubcircuitLibrary/74157/74157.pro              |   39 +-
 src/SubcircuitLibrary/74157/74157.sch              |  467 +++--
 src/SubcircuitLibrary/74157/74157.sub              |   44 +-
 .../74157/74157_Previous_Values.xml                |    2 +-
 src/SubcircuitLibrary/7485/3_and-cache.lib         |  122 +-
 src/SubcircuitLibrary/7485/3_and.cir               |   26 +-
 src/SubcircuitLibrary/7485/3_and.cir.out           |   40 +-
 src/SubcircuitLibrary/7485/3_and.pro               |  102 +-
 src/SubcircuitLibrary/7485/3_and.sch               |  251 ++-
 src/SubcircuitLibrary/7485/3_and.sub               |   26 +-
 src/SubcircuitLibrary/7485/4_and-cache.lib         |  158 +-
 src/SubcircuitLibrary/7485/4_and.cir               |   26 +-
 src/SubcircuitLibrary/7485/4_and.cir.out           |   36 +-
 src/SubcircuitLibrary/7485/4_and.pro               |  115 +-
 src/SubcircuitLibrary/7485/4_and.sch               |  290 ++-
 src/SubcircuitLibrary/7485/4_and.sub               |   22 +-
 src/SubcircuitLibrary/7485/5_and-cache.lib         |  158 +-
 src/SubcircuitLibrary/7485/5_and.cir               |   28 +-
 src/SubcircuitLibrary/7485/5_and.cir.out           |   44 +-
 src/SubcircuitLibrary/7485/5_and.pro               |  100 +-
 src/SubcircuitLibrary/7485/5_and.sch               |  329 ++--
 src/SubcircuitLibrary/7485/5_and.sub               |   30 +-
 src/SubcircuitLibrary/7485/7485-cache.lib          |  112 +-
 src/SubcircuitLibrary/7485/7485.cir                |   58 +-
 src/SubcircuitLibrary/7485/7485.cir.out            |   84 +-
 src/SubcircuitLibrary/7485/7485.pro                |   39 +-
 src/SubcircuitLibrary/7485/7485.sch                |  542 +++---
 src/SubcircuitLibrary/7485/7485.sub                |   84 +-
 .../7485/7485_Previous_Values.xml                  |    2 +-
 src/SubcircuitLibrary/7485/7485mod-cache.lib       |  350 ++--
 src/SubcircuitLibrary/7485/7485mod.sch             | 2014 ++++++++++----------
 src/SubcircuitLibrary/7485/c_gate-cache.lib        |  190 +-
 src/SubcircuitLibrary/7485/c_gate.cir              |   38 +-
 src/SubcircuitLibrary/7485/c_gate.cir.out          |   84 +-
 src/SubcircuitLibrary/7485/c_gate.pro              |  114 +-
 src/SubcircuitLibrary/7485/c_gate.sch              |  492 ++---
 src/SubcircuitLibrary/7485/c_gate.sub              |   70 +-
 src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib    |  146 ++
 src/SubcircuitLibrary/INVCMOS/INVCMOS.cir          |   15 +
 src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out      |   18 +
 src/SubcircuitLibrary/INVCMOS/INVCMOS.pro          |   73 +
 src/SubcircuitLibrary/INVCMOS/INVCMOS.sch          |  189 ++
 src/SubcircuitLibrary/INVCMOS/INVCMOS.sub          |   12 +
 .../INVCMOS/INVCMOS_Previous_Values.xml            |    1 +
 src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib       |   13 +
 src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib       |   11 +
 src/SubcircuitLibrary/INVCMOS/analysis             |    1 +
 src/SubcircuitLibrary/LM7812/LM7812-cache.lib      |  135 ++
 src/SubcircuitLibrary/LM7812/LM7812-rescue.lib     |   42 +
 src/SubcircuitLibrary/LM7812/LM7812.cir            |   51 +
 src/SubcircuitLibrary/LM7812/LM7812.cir.out        |   60 +
 src/SubcircuitLibrary/LM7812/LM7812.pro            |   46 +
 src/SubcircuitLibrary/LM7812/LM7812.sch            |  758 ++++++++
 src/SubcircuitLibrary/LM7812/LM7812.sub            |   54 +
 .../LM7812/LM7812_Previous_Values.xml              |    1 +
 src/SubcircuitLibrary/LM7812/NPN.lib               |    4 +
 src/SubcircuitLibrary/LM7812/PNP.lib               |    4 +
 src/SubcircuitLibrary/LM7812/Q_PNP.lib             |    1 +
 src/SubcircuitLibrary/LM7812/analysis              |    1 +
 .../full_adder/full_adder-cache.lib                |   61 +
 src/SubcircuitLibrary/full_adder/full_adder.pro    |   12 +-
 .../full_adder/half_adder-cache.lib                |   63 +
 src/SubcircuitLibrary/full_adder/half_adder.pro    |   12 +-
 src/SubcircuitLibrary/full_sub/full_sub-cache.lib  |  158 +-
 src/SubcircuitLibrary/full_sub/full_sub-rescue.lib |   40 +-
 src/SubcircuitLibrary/full_sub/full_sub.cir        |   28 +-
 src/SubcircuitLibrary/full_sub/full_sub.cir.out    |   38 +-
 src/SubcircuitLibrary/full_sub/full_sub.pro        |  148 +-
 src/SubcircuitLibrary/full_sub/full_sub.sch        |  422 ++--
 src/SubcircuitLibrary/full_sub/full_sub.sub        |   24 +-
 src/SubcircuitLibrary/full_sub/half_sub.cir.out    |   48 +-
 src/SubcircuitLibrary/full_sub/half_sub.sub        |   34 +-
 .../half_adder/half_adder-cache.lib                |   63 +
 src/SubcircuitLibrary/half_adder/half_adder.pro    |   12 +-
 src/SubcircuitLibrary/half_sub/half_sub.cir.out    |   48 +-
 src/SubcircuitLibrary/half_sub/half_sub.sub        |   34 +-
 src/SubcircuitLibrary/lm555n/NPN.lib               |    4 +
 src/SubcircuitLibrary/lm555n/analysis              |    2 +-
 src/SubcircuitLibrary/lm555n/lm555n-cache.lib      |  280 ++-
 src/SubcircuitLibrary/lm555n/lm555n-rescue.lib     |   37 +-
 src/SubcircuitLibrary/lm555n/lm555n.cir            |   44 +-
 src/SubcircuitLibrary/lm555n/lm555n.cir.out        |   11 +-
 src/SubcircuitLibrary/lm555n/lm555n.pro            |   15 +-
 src/SubcircuitLibrary/lm555n/lm555n.sch            |  613 +++---
 src/SubcircuitLibrary/lm555n/lm555n.sub            |    8 +-
 src/SubcircuitLibrary/lm555n/npn_1.lib             |   29 +
 src/SubcircuitLibrary/lm7805/NPN.lib               |    4 +
 src/SubcircuitLibrary/lm7805/PNP.lib               |    4 +
 src/SubcircuitLibrary/lm7805/Q_PNP.lib             |    1 +
 src/SubcircuitLibrary/lm7805/analysis              |    1 +
 src/SubcircuitLibrary/lm7805/lm7805-cache.lib      |  136 ++
 src/SubcircuitLibrary/lm7805/lm7805.cir            |   51 +
 src/SubcircuitLibrary/lm7805/lm7805.cir.out        |   60 +
 src/SubcircuitLibrary/lm7805/lm7805.pro            |   45 +
 src/SubcircuitLibrary/lm7805/lm7805.sch            |  757 ++++++++
 src/SubcircuitLibrary/lm7805/lm7805.sub            |   54 +
 .../lm7805/lm7805_Previous_Values.xml              |    1 +
 src/SubcircuitLibrary/lm_741/NPN.lib               |    4 +
 src/SubcircuitLibrary/lm_741/PNP.lib               |    4 +
 src/SubcircuitLibrary/lm_741/analysis              |    1 +
 src/SubcircuitLibrary/lm_741/lm_741-cache.lib      |  119 ++
 src/SubcircuitLibrary/lm_741/lm_741.cir            |   43 +
 src/SubcircuitLibrary/lm_741/lm_741.cir.out        |   46 +
 src/SubcircuitLibrary/lm_741/lm_741.pro            |   45 +
 src/SubcircuitLibrary/lm_741/lm_741.sch            |  697 +++++++
 src/SubcircuitLibrary/lm_741/lm_741.sub            |   40 +
 .../lm_741/lm_741_Previous_Values.xml              |    1 +
 src/SubcircuitLibrary/lm_741/npn_1.lib             |   29 +
 src/SubcircuitLibrary/lm_741/pnp_1.lib             |   29 +
 src/SubcircuitLibrary/scr/D.lib                    |   20 +
 src/SubcircuitLibrary/scr/PowerDiode.lib           |   21 +-
 src/SubcircuitLibrary/scr/scr-cache.lib            |   54 +-
 src/SubcircuitLibrary/scr/scr-rescue.lib           |   39 +
 src/SubcircuitLibrary/scr/scr.pro                  |   81 +-
 src/SubcircuitLibrary/scr/scr.sch                  |    9 +-
 src/SubcircuitLibrary/ua741/ua741.pro              |    2 +-
 src/SubcircuitLibrary/ujt/analysis                 |    2 +-
 src/SubcircuitLibrary/ujt/emitter.lib              |   15 +-
 src/SubcircuitLibrary/ujt/plot_data_i.txt          |   67 -
 src/SubcircuitLibrary/ujt/plot_data_v.txt          |  203 --
 src/SubcircuitLibrary/ujt/ujt-cache.lib            |   17 +-
 src/SubcircuitLibrary/ujt/ujt.cir                  |   18 +-
 src/SubcircuitLibrary/ujt/ujt.cir.out              |   20 +-
 src/SubcircuitLibrary/ujt/ujt.sch                  |  138 +-
 src/SubcircuitLibrary/ujt/ujt.sub                  |   18 +-
 src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml  |    2 +-
 src/browser/Welcome.py                             |    5 +-
 src/browser/pages/welcome.html                     |    2 +-
 src/configuration/Appconfig.py                     |   36 +-
 src/configuration/browser/UserManual.py            |   20 -
 src/deviceModelLibrary/Diode/D.lib                 |    3 +-
 src/deviceModelLibrary/Diode/LED.lib               |    2 +
 src/deviceModelLibrary/Diode/LED.xml               |    1 +
 src/deviceModelLibrary/Diode/PowerDiode.lib        |   21 +-
 src/deviceModelLibrary/Diode/ZenerD1N750.lib       |    4 +-
 src/deviceModelLibrary/IGBT/NIGBT.lib              |   12 +-
 src/deviceModelLibrary/IGBT/PIGBT.lib              |   11 +-
 src/deviceModelLibrary/JFET/NJF.lib                |    5 +-
 src/deviceModelLibrary/JFET/PJF.lib                |    6 +-
 src/deviceModelLibrary/MOS/NMOS-0.5um.lib          |    7 +-
 src/deviceModelLibrary/MOS/NMOS-180nm.lib          |   14 +-
 src/deviceModelLibrary/MOS/NMOS-5um.lib            |    4 +-
 src/deviceModelLibrary/MOS/PMOS-0.5um.lib          |    7 +-
 src/deviceModelLibrary/MOS/PMOS-180nm.lib          |   12 +-
 src/deviceModelLibrary/MOS/PMOS-5um.lib            |    4 +-
 src/deviceModelLibrary/Misc/CORE.lib               |   10 +-
 src/deviceModelLibrary/Templates/CORE.lib          |   10 +-
 src/deviceModelLibrary/Templates/D.lib             |    3 +-
 src/deviceModelLibrary/Templates/NIGBT.lib         |   11 +-
 src/deviceModelLibrary/Templates/NJF.lib           |    5 +-
 src/deviceModelLibrary/Templates/NMOS-0.5um.lib    |    7 +-
 src/deviceModelLibrary/Templates/NMOS-180nm.lib    |   14 +-
 src/deviceModelLibrary/Templates/NMOS-5um.lib      |    4 +-
 src/deviceModelLibrary/Templates/NPN.lib           |    5 +-
 src/deviceModelLibrary/Templates/PIGBT.lib         |   11 +-
 src/deviceModelLibrary/Templates/PJF.lib           |    6 +-
 src/deviceModelLibrary/Templates/PMOS-0.5um.lib    |    7 +-
 src/deviceModelLibrary/Templates/PMOS-180nm.lib    |   12 +-
 src/deviceModelLibrary/Templates/PMOS-5um.lib      |    4 +-
 src/deviceModelLibrary/Templates/PNP.lib           |    5 +-
 src/deviceModelLibrary/Transistor/BC547B.lib       |    1 +
 src/deviceModelLibrary/Transistor/BC547B.xml       |    1 +
 src/deviceModelLibrary/Transistor/NPN.lib          |    5 +-
 src/deviceModelLibrary/Transistor/NPN.xml          |   34 +-
 src/deviceModelLibrary/Transistor/PNP.lib          |    5 +-
 .../User Libraries/userDiode.lib                   |   21 +-
 src/frontEnd/Application.py                        |  432 +++--
 src/frontEnd/DockArea.py                           |   73 +-
 src/frontEnd/ProjectExplorer.py                    |   90 +-
 src/frontEnd/Workspace.py                          |   17 +-
 src/frontEnd/pathmagic.py                          |    1 +
 src/kicadtoNgspice/Analysis.py                     |  104 +-
 src/kicadtoNgspice/Convert.py                      |   52 +-
 src/kicadtoNgspice/DeviceModel.py                  |   42 +-
 src/kicadtoNgspice/KicadtoNgspice.py               |   96 +-
 src/kicadtoNgspice/Model.py                        |    6 -
 src/kicadtoNgspice/Processing.py                   |  108 +-
 src/kicadtoNgspice/Source.py                       |   11 +-
 src/kicadtoNgspice/SubcircuitTab.py                |   16 +-
 src/kicadtoNgspice/TrackWidget.py                  |   10 +-
 src/modelEditor/ModelEditor.py                     |   28 +-
 src/modelParamXML/Analog/gain.xml                  |    2 +-
 src/modelParamXML/Nghdl/.gitignore                 |    4 +
 src/modelParamXML/Nghdl/inverter.xml               |    1 -
 src/modelParamXML/Nghdl/myxor.xml                  |    1 -
 src/ngspiceSimulation/pythonPlotting.py            |   45 +-
 src/ngspicetoModelica/ModelicaUI.py                |    7 +-
 src/projManagement/Kicad.py                        |   64 +-
 src/projManagement/Validation.py                   |  104 +-
 src/projManagement/Worker.py                       |   22 +-
 src/projManagement/newProject.py                   |   24 +-
 src/projManagement/openProject.py                  |   18 +-
 src/subcircuit/convertSub.py                       |   14 +-
 src/subcircuit/newSub.py                           |   22 +-
 src/subcircuit/uploadSub.py                        |   13 +-
 src/supportFiles/fp-lib-table                      |   92 +
 src/supportFiles/fp-lib-table-online               |   88 +
 358 files changed, 20310 insertions(+), 11622 deletions(-)
 create mode 100644 src/SubcircuitLibrary/4002/4002-cache.lib
 create mode 100644 src/SubcircuitLibrary/4002/4002.cir
 create mode 100644 src/SubcircuitLibrary/4002/4002.cir.out
 create mode 100644 src/SubcircuitLibrary/4002/4002.pro
 create mode 100644 src/SubcircuitLibrary/4002/4002.sch
 create mode 100644 src/SubcircuitLibrary/4002/4002.sub
 create mode 100644 src/SubcircuitLibrary/4002/4002_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4002/analysis
 create mode 100644 src/SubcircuitLibrary/4012/4012-cache.lib
 create mode 100644 src/SubcircuitLibrary/4012/4012.cir
 create mode 100644 src/SubcircuitLibrary/4012/4012.cir.out
 create mode 100644 src/SubcircuitLibrary/4012/4012.pro
 create mode 100644 src/SubcircuitLibrary/4012/4012.sch
 create mode 100644 src/SubcircuitLibrary/4012/4012.sub
 create mode 100644 src/SubcircuitLibrary/4012/4012_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4012/analysis
 create mode 100644 src/SubcircuitLibrary/4017/4017-cache.lib
 create mode 100644 src/SubcircuitLibrary/4017/4017.cir
 create mode 100644 src/SubcircuitLibrary/4017/4017.cir.out
 create mode 100644 src/SubcircuitLibrary/4017/4017.pro
 create mode 100644 src/SubcircuitLibrary/4017/4017.sch
 create mode 100644 src/SubcircuitLibrary/4017/4017.sub
 create mode 100644 src/SubcircuitLibrary/4017/4017_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4017/D.lib
 create mode 100644 src/SubcircuitLibrary/4017/analysis
 create mode 100644 src/SubcircuitLibrary/4023/3_and-cache.lib
 create mode 100644 src/SubcircuitLibrary/4023/3_and.cir
 create mode 100644 src/SubcircuitLibrary/4023/3_and.cir.out
 create mode 100644 src/SubcircuitLibrary/4023/3_and.pro
 create mode 100644 src/SubcircuitLibrary/4023/3_and.sch
 create mode 100644 src/SubcircuitLibrary/4023/3_and.sub
 create mode 100644 src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4023/4023-cache.lib
 create mode 100644 src/SubcircuitLibrary/4023/4023.cir
 create mode 100644 src/SubcircuitLibrary/4023/4023.cir.out
 create mode 100644 src/SubcircuitLibrary/4023/4023.pro
 create mode 100644 src/SubcircuitLibrary/4023/4023.sch
 create mode 100644 src/SubcircuitLibrary/4023/4023.sub
 create mode 100644 src/SubcircuitLibrary/4023/4023_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4023/analysis
 create mode 100644 src/SubcircuitLibrary/4028/4028-cache.lib
 create mode 100644 src/SubcircuitLibrary/4028/4028.cir
 create mode 100644 src/SubcircuitLibrary/4028/4028.cir.out
 create mode 100644 src/SubcircuitLibrary/4028/4028.pro
 create mode 100644 src/SubcircuitLibrary/4028/4028.sch
 create mode 100644 src/SubcircuitLibrary/4028/4028.sub
 create mode 100644 src/SubcircuitLibrary/4028/4028_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/4028/analysis
 create mode 100644 src/SubcircuitLibrary/556/556-cache.lib
 create mode 100644 src/SubcircuitLibrary/556/556.cir
 create mode 100644 src/SubcircuitLibrary/556/556.cir.out
 create mode 100644 src/SubcircuitLibrary/556/556.pro
 create mode 100644 src/SubcircuitLibrary/556/556.sch
 create mode 100644 src/SubcircuitLibrary/556/556.sub
 create mode 100644 src/SubcircuitLibrary/556/556_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS.pro
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS.sch
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS.sub
 create mode 100644 src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib
 create mode 100644 src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib
 create mode 100644 src/SubcircuitLibrary/INVCMOS/analysis
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812-cache.lib
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812-rescue.lib
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812.cir
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812.cir.out
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812.pro
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812.sch
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812.sub
 create mode 100644 src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/LM7812/NPN.lib
 create mode 100644 src/SubcircuitLibrary/LM7812/PNP.lib
 create mode 100644 src/SubcircuitLibrary/LM7812/Q_PNP.lib
 create mode 100644 src/SubcircuitLibrary/LM7812/analysis
 create mode 100644 src/SubcircuitLibrary/full_adder/full_adder-cache.lib
 create mode 100644 src/SubcircuitLibrary/full_adder/half_adder-cache.lib
 create mode 100644 src/SubcircuitLibrary/half_adder/half_adder-cache.lib
 create mode 100644 src/SubcircuitLibrary/lm555n/NPN.lib
 create mode 100644 src/SubcircuitLibrary/lm555n/npn_1.lib
 create mode 100644 src/SubcircuitLibrary/lm7805/NPN.lib
 create mode 100644 src/SubcircuitLibrary/lm7805/PNP.lib
 create mode 100644 src/SubcircuitLibrary/lm7805/Q_PNP.lib
 create mode 100644 src/SubcircuitLibrary/lm7805/analysis
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805-cache.lib
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805.cir
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805.cir.out
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805.pro
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805.sch
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805.sub
 create mode 100644 src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/lm_741/NPN.lib
 create mode 100644 src/SubcircuitLibrary/lm_741/PNP.lib
 create mode 100644 src/SubcircuitLibrary/lm_741/analysis
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741-cache.lib
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741.cir
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741.cir.out
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741.pro
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741.sch
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741.sub
 create mode 100644 src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml
 create mode 100644 src/SubcircuitLibrary/lm_741/npn_1.lib
 create mode 100644 src/SubcircuitLibrary/lm_741/pnp_1.lib
 create mode 100644 src/SubcircuitLibrary/scr/D.lib
 create mode 100644 src/SubcircuitLibrary/scr/scr-rescue.lib
 delete mode 100644 src/configuration/browser/UserManual.py
 create mode 100644 src/deviceModelLibrary/Diode/LED.lib
 create mode 100644 src/deviceModelLibrary/Diode/LED.xml
 create mode 100644 src/deviceModelLibrary/Transistor/BC547B.lib
 create mode 100644 src/deviceModelLibrary/Transistor/BC547B.xml
 create mode 100644 src/modelParamXML/Nghdl/.gitignore
 delete mode 100644 src/modelParamXML/Nghdl/inverter.xml
 delete mode 100644 src/modelParamXML/Nghdl/myxor.xml
 create mode 100644 src/supportFiles/fp-lib-table
 create mode 100644 src/supportFiles/fp-lib-table-online

(limited to 'src')

diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
index 9d70ade9..e16831e4 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
@@ -1,77 +1,77 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
index 08e3ccc8..0f4deb6c 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
@@ -1,17 +1,17 @@
-* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
-U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
-U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
-X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
-X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
+U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
+U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
+U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
+X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
+X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
index 351629fd..71766bd8 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
@@ -1,31 +1,31 @@
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
+
+.include half_adder.sub
+* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
+x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
+x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
index 944ec056..eafbfb80 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
@@ -1,74 +1,74 @@
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-ModuleTextSizeV=1.000000000000
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-
+update=03/07/19 09:55:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
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+ModuleTextSizeH=1.000000000000
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+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
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+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
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+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
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+LibName38=eSim_Plot
+LibName39=eSim_PSpice
+LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
+
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
index 2629beec..0ba61912 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
@@ -1,284 +1,284 @@
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+	8150 2350 7450 2350
+Wire Wire Line
+	7450 2100 7450 2500
+Wire Wire Line
+	6950 2500 6950 2350
+Wire Wire Line
+	6950 2350 6400 2350
+Wire Wire Line
+	6400 2350 6400 2500
+Wire Wire Line
+	8250 1100 8250 2500
+Wire Wire Line
+	8250 2250 7050 2250
+Wire Wire Line
+	7050 2250 7050 2500
+Wire Wire Line
+	7550 2150 7550 2500
+Wire Wire Line
+	7550 2450 6500 2450
+Wire Wire Line
+	6500 2450 6500 2500
+$Comp
+L half_adder X2
+U 1 1 5C7FC23A
+P 7200 3350
+F 0 "X2" H 8100 3850 60  0000 C CNN
+F 1 "half_adder" H 8100 3750 60  0000 C CNN
+F 2 "" H 7200 3350 60  0000 C CNN
+F 3 "" H 7200 3350 60  0000 C CNN
+	1    7200 3350
+	0    1    1    0   
+$EndComp
+$Comp
+L half_adder X1
+U 1 1 5C7FC324
+P 6050 3350
+F 0 "X1" H 6950 3850 60  0000 C CNN
+F 1 "half_adder" H 6950 3750 60  0000 C CNN
+F 2 "" H 6050 3350 60  0000 C CNN
+F 3 "" H 6050 3350 60  0000 C CNN
+	1    6050 3350
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	7500 3400 7900 3400
+Wire Wire Line
+	7900 3400 7900 3650
+Wire Wire Line
+	7000 3400 7300 3400
+Wire Wire Line
+	7300 3400 7300 3650
+Wire Wire Line
+	7300 4800 7050 4800
+Wire Wire Line
+	7050 4800 7050 3600
+Wire Wire Line
+	7050 3600 6750 3600
+Wire Wire Line
+	6750 3600 6750 3650
+Wire Wire Line
+	6450 3400 6450 3650
+Wire Wire Line
+	6450 3650 6150 3650
+$Comp
+L PORT U1
+U 5 1 5C7FC4F8
+P 8200 5300
+F 0 "U1" H 8250 5400 30  0000 C CNN
+F 1 "PORT" H 8200 5300 30  0000 C CNN
+F 2 "" H 8200 5300 60  0000 C CNN
+F 3 "" H 8200 5300 60  0000 C CNN
+	5    8200 5300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C7FC5D7
+P 7300 5300
+F 0 "U1" H 7350 5400 30  0000 C CNN
+F 1 "PORT" H 7300 5300 30  0000 C CNN
+F 2 "" H 7300 5300 60  0000 C CNN
+F 3 "" H 7300 5300 60  0000 C CNN
+	6    7300 5300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C7FC641
+P 6750 5150
+F 0 "U1" H 6800 5250 30  0000 C CNN
+F 1 "PORT" H 6750 5150 30  0000 C CNN
+F 2 "" H 6750 5150 60  0000 C CNN
+F 3 "" H 6750 5150 60  0000 C CNN
+	7    6750 5150
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5C7FC698
+P 6150 5250
+F 0 "U1" H 6200 5350 30  0000 C CNN
+F 1 "PORT" H 6150 5250 30  0000 C CNN
+F 2 "" H 6150 5250 60  0000 C CNN
+F 3 "" H 6150 5250 60  0000 C CNN
+	8    6150 5250
+	0    -1   -1   0   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C7FC6EC
+P 8250 850
+F 0 "U1" H 8300 950 30  0000 C CNN
+F 1 "PORT" H 8250 850 30  0000 C CNN
+F 2 "" H 8250 850 60  0000 C CNN
+F 3 "" H 8250 850 60  0000 C CNN
+	1    8250 850 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C7FC815
+P 7900 850
+F 0 "U1" H 7950 950 30  0000 C CNN
+F 1 "PORT" H 7900 850 30  0000 C CNN
+F 2 "" H 7900 850 60  0000 C CNN
+F 3 "" H 7900 850 60  0000 C CNN
+	2    7900 850 
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C7FC857
+P 7550 850
+F 0 "U1" H 7600 950 30  0000 C CNN
+F 1 "PORT" H 7550 850 30  0000 C CNN
+F 2 "" H 7550 850 60  0000 C CNN
+F 3 "" H 7550 850 60  0000 C CNN
+	3    7550 850 
+	0    1    1    0   
+$EndComp
+Connection ~ 8250 2250
+Wire Wire Line
+	7900 1100 7900 2150
+Wire Wire Line
+	7900 2150 7550 2150
+Connection ~ 7550 2450
+Wire Wire Line
+	7550 1100 7550 2100
+Wire Wire Line
+	7550 2100 7450 2100
+Connection ~ 7450 2350
+Wire Wire Line
+	7200 1050 7200 2100
+Wire Wire Line
+	7200 2100 6800 2100
+Wire Wire Line
+	6800 2100 6800 2350
+Connection ~ 6800 2350
+Wire Wire Line
+	8200 3400 8200 5050
+$Comp
+L PORT U1
+U 4 1 5C7FC898
+P 7200 800
+F 0 "U1" H 7250 900 30  0000 C CNN
+F 1 "PORT" H 7200 800 30  0000 C CNN
+F 2 "" H 7200 800 60  0000 C CNN
+F 3 "" H 7200 800 60  0000 C CNN
+	4    7200 800 
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	7300 5050 7300 4850
+Wire Wire Line
+	7300 4850 7900 4850
+Wire Wire Line
+	7900 4850 7900 4800
+Wire Wire Line
+	6750 4800 6750 4900
+Wire Wire Line
+	6150 4800 6150 5000
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
index ce0d022d..e77495a6 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
@@ -1,25 +1,25 @@
-* Subcircuit 2bitmul
-.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 2bitmul
+.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
+* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
+.include half_adder.sub
+* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
+x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
+x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 2bitmul
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/3_and/3_and-cache.lib
+++ b/src/SubcircuitLibrary/3_and/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/3_and/3_and.cir
+++ b/src/SubcircuitLibrary/3_and/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/3_and/3_and.cir.out
+++ b/src/SubcircuitLibrary/3_and/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/3_and/3_and.pro
+++ b/src/SubcircuitLibrary/3_and/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/3_and/3_and.sch
+++ b/src/SubcircuitLibrary/3_and/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
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-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
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-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
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+LIBS:valves
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+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
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+LIBS:eSim_Power
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+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+$Comp
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+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
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+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
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+F 3 "" H 6900 2850 60  0000 C CNN
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+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/3_and/3_and.sub
+++ b/src/SubcircuitLibrary/3_and/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib
new file mode 100644
index 00000000..677411a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002-cache.lib
@@ -0,0 +1,82 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir
new file mode 100644
index 00000000..5d5c1ed7
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.cir
@@ -0,0 +1,17 @@
+* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or		
+U3  Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
+U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or		
+U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or		
+U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor		
+
+.end
diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out
new file mode 100644
index 00000000..e9cc6862
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.cir.out
@@ -0,0 +1,36 @@
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro
new file mode 100644
index 00000000..225ef82a
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.pro
@@ -0,0 +1,44 @@
+update=05/31/19 09:35:41
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+LibName11=power
diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch
new file mode 100644
index 00000000..545f46fe
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.sch
@@ -0,0 +1,315 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+F 3 "" H 4750 2900 60  0000 C CNN
+	1    4750 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5CEE0629
+P 4750 3450
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+F 2 "" H 4750 3450 60  0000 C CNN
+F 3 "" H 4750 3450 60  0000 C CNN
+	1    4750 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0663
+P 6000 3100
+F 0 "U6" H 6000 3100 60  0000 C CNN
+F 1 "d_nor" H 6050 3200 60  0000 C CNN
+F 2 "" H 6000 3100 60  0000 C CNN
+F 3 "" H 6000 3100 60  0000 C CNN
+	1    6000 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5200 2850 5400 2850
+Wire Wire Line
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+	5400 3000 5550 3000
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+Wire Wire Line
+	5650 5800 6050 5800
+Wire Wire Line
+	5650 6000 6050 6000
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+NoConn ~ 5650 5550
+NoConn ~ 5650 5800
+NoConn ~ 5650 6000
+$Comp
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+U 2 1 5CEE1C41
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+F 2 "" H 3850 2800 60  0000 C CNN
+F 3 "" H 3850 2800 60  0000 C CNN
+	2    3850 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE22EE
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+F 2 "" H 3900 3050 60  0000 C CNN
+F 3 "" H 3900 3050 60  0000 C CNN
+	3    3900 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE2322
+P 3900 3250
+F 0 "U1" H 3950 3350 30  0000 C CNN
+F 1 "PORT" H 3900 3250 30  0000 C CNN
+F 2 "" H 3900 3250 60  0000 C CNN
+F 3 "" H 3900 3250 60  0000 C CNN
+	5    3900 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE2351
+P 3900 3550
+F 0 "U1" H 3950 3650 30  0000 C CNN
+F 1 "PORT" H 3900 3550 30  0000 C CNN
+F 2 "" H 3900 3550 60  0000 C CNN
+F 3 "" H 3900 3550 60  0000 C CNN
+	4    3900 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE2387
+P 6950 3050
+F 0 "U1" H 7000 3150 30  0000 C CNN
+F 1 "PORT" H 6950 3050 30  0000 C CNN
+F 2 "" H 6950 3050 60  0000 C CNN
+F 3 "" H 6950 3050 60  0000 C CNN
+	1    6950 3050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4100 2800 4300 2800
+Wire Wire Line
+	4150 3050 4150 2900
+Wire Wire Line
+	4150 2900 4300 2900
+Wire Wire Line
+	4150 3250 4300 3250
+Wire Wire Line
+	4300 3250 4300 3350
+Wire Wire Line
+	4150 3550 4150 3450
+Wire Wire Line
+	4150 3450 4300 3450
+Wire Wire Line
+	6700 3050 6450 3050
+$Comp
+L d_or U4
+U 1 1 5CEE4ED7
+P 4900 4100
+F 0 "U4" H 4900 4100 60  0000 C CNN
+F 1 "d_or" H 4900 4200 60  0000 C CNN
+F 2 "" H 4900 4100 60  0000 C CNN
+F 3 "" H 4900 4100 60  0000 C CNN
+	1    4900 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U5
+U 1 1 5CEE4EDD
+P 4900 4650
+F 0 "U5" H 4900 4650 60  0000 C CNN
+F 1 "d_or" H 4900 4750 60  0000 C CNN
+F 2 "" H 4900 4650 60  0000 C CNN
+F 3 "" H 4900 4650 60  0000 C CNN
+	1    4900 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CEE4EE3
+P 6150 4300
+F 0 "U7" H 6150 4300 60  0000 C CNN
+F 1 "d_nor" H 6200 4400 60  0000 C CNN
+F 2 "" H 6150 4300 60  0000 C CNN
+F 3 "" H 6150 4300 60  0000 C CNN
+	1    6150 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5350 4050 5550 4050
+Wire Wire Line
+	5550 4050 5550 4200
+Wire Wire Line
+	5550 4200 5700 4200
+Wire Wire Line
+	5350 4600 5550 4600
+Wire Wire Line
+	5550 4600 5550 4300
+Wire Wire Line
+	5550 4300 5700 4300
+$Comp
+L PORT U1
+U 9 1 5CEE4EEF
+P 4000 4000
+F 0 "U1" H 4050 4100 30  0000 C CNN
+F 1 "PORT" H 4000 4000 30  0000 C CNN
+F 2 "" H 4000 4000 60  0000 C CNN
+F 3 "" H 4000 4000 60  0000 C CNN
+	9    4000 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE4EF5
+P 4050 4250
+F 0 "U1" H 4100 4350 30  0000 C CNN
+F 1 "PORT" H 4050 4250 30  0000 C CNN
+F 2 "" H 4050 4250 60  0000 C CNN
+F 3 "" H 4050 4250 60  0000 C CNN
+	10   4050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE4EFB
+P 4050 4450
+F 0 "U1" H 4100 4550 30  0000 C CNN
+F 1 "PORT" H 4050 4450 30  0000 C CNN
+F 2 "" H 4050 4450 60  0000 C CNN
+F 3 "" H 4050 4450 60  0000 C CNN
+	11   4050 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE4F01
+P 4050 4750
+F 0 "U1" H 4100 4850 30  0000 C CNN
+F 1 "PORT" H 4050 4750 30  0000 C CNN
+F 2 "" H 4050 4750 60  0000 C CNN
+F 3 "" H 4050 4750 60  0000 C CNN
+	12   4050 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE4F07
+P 7100 4250
+F 0 "U1" H 7150 4350 30  0000 C CNN
+F 1 "PORT" H 7100 4250 30  0000 C CNN
+F 2 "" H 7100 4250 60  0000 C CNN
+F 3 "" H 7100 4250 60  0000 C CNN
+	13   7100 4250
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4250 4000 4450 4000
+Wire Wire Line
+	4300 4250 4300 4100
+Wire Wire Line
+	4300 4100 4450 4100
+Wire Wire Line
+	4300 4450 4450 4450
+Wire Wire Line
+	4450 4450 4450 4550
+Wire Wire Line
+	4300 4750 4300 4650
+Wire Wire Line
+	4300 4650 4450 4650
+Wire Wire Line
+	6850 4250 6600 4250
+$Comp
+L PORT U1
+U 6 1 5CEE51A5
+P 6300 5350
+F 0 "U1" H 6350 5450 30  0000 C CNN
+F 1 "PORT" H 6300 5350 30  0000 C CNN
+F 2 "" H 6300 5350 60  0000 C CNN
+F 3 "" H 6300 5350 60  0000 C CNN
+	6    6300 5350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE522C
+P 6300 5550
+F 0 "U1" H 6350 5650 30  0000 C CNN
+F 1 "PORT" H 6300 5550 30  0000 C CNN
+F 2 "" H 6300 5550 60  0000 C CNN
+F 3 "" H 6300 5550 60  0000 C CNN
+	7    6300 5550
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5276
+P 6300 5800
+F 0 "U1" H 6350 5900 30  0000 C CNN
+F 1 "PORT" H 6300 5800 30  0000 C CNN
+F 2 "" H 6300 5800 60  0000 C CNN
+F 3 "" H 6300 5800 60  0000 C CNN
+	8    6300 5800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE52C5
+P 6300 6000
+F 0 "U1" H 6350 6100 30  0000 C CNN
+F 1 "PORT" H 6300 6000 30  0000 C CNN
+F 2 "" H 6300 6000 60  0000 C CNN
+F 3 "" H 6300 6000 60  0000 C CNN
+	14   6300 6000
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub
new file mode 100644
index 00000000..b9726625
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.sub
@@ -0,0 +1,30 @@
+* Subcircuit 4002
+.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4002
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
new file mode 100644
index 00000000..75360e5e
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/4012-cache.lib b/src/SubcircuitLibrary/4012/4012-cache.lib
new file mode 100644
index 00000000..ea0d2d70
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4012/4012.cir b/src/SubcircuitLibrary/4012/4012.cir
new file mode 100644
index 00000000..a88a9da4
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012.cir
@@ -0,0 +1,19 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8  Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter		
+U9  Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and		
+U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and		
+U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and		
+U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and		
+U3  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and		
+U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and		
+
+.end
diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out
new file mode 100644
index 00000000..c43dda8c
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012.cir.out
@@ -0,0 +1,44 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8  net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9  net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4012/4012.pro b/src/SubcircuitLibrary/4012/4012.pro
new file mode 100644
index 00000000..0f76f4bb
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012.pro
@@ -0,0 +1,44 @@
+update=06/01/19 13:10:32
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_User
+LibName11=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4012/4012.sch b/src/SubcircuitLibrary/4012/4012.sch
new file mode 100644
index 00000000..b3320871
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012.sch
@@ -0,0 +1,342 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	3350 2600 2550 2600
+Wire Wire Line
+	3350 2700 3150 2700
+Wire Wire Line
+	3150 2700 3150 2850
+Wire Wire Line
+	3150 2850 2550 2850
+Wire Wire Line
+	3350 3200 3150 3200
+Wire Wire Line
+	3150 3200 3150 3100
+Wire Wire Line
+	3150 3100 2550 3100
+Wire Wire Line
+	3350 3300 2550 3300
+Wire Wire Line
+	5200 2950 5500 2950
+$Comp
+L d_inverter U8
+U 1 1 5CEE55AB
+P 5800 2950
+F 0 "U8" H 5800 2850 60  0000 C CNN
+F 1 "d_inverter" H 5800 3100 60  0000 C CNN
+F 2 "" H 5850 2900 60  0000 C CNN
+F 3 "" H 5850 2900 60  0000 C CNN
+	1    5800 2950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6100 2950 6500 2950
+Wire Wire Line
+	3400 3950 2600 3950
+Wire Wire Line
+	3400 4050 3200 4050
+Wire Wire Line
+	3200 4050 3200 4200
+Wire Wire Line
+	3200 4200 2600 4200
+Wire Wire Line
+	3400 4550 3200 4550
+Wire Wire Line
+	3200 4550 3200 4450
+Wire Wire Line
+	3200 4450 2600 4450
+Wire Wire Line
+	3400 4650 2600 4650
+Wire Wire Line
+	5250 4300 5550 4300
+$Comp
+L d_inverter U9
+U 1 1 5CEE5715
+P 5850 4300
+F 0 "U9" H 5850 4200 60  0000 C CNN
+F 1 "d_inverter" H 5850 4450 60  0000 C CNN
+F 2 "" H 5900 4250 60  0000 C CNN
+F 3 "" H 5900 4250 60  0000 C CNN
+	1    5850 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6150 4300 6550 4300
+$Comp
+L PORT U1
+U 2 1 5CEE57D6
+P 2300 2600
+F 0 "U1" H 2350 2700 30  0000 C CNN
+F 1 "PORT" H 2300 2600 30  0000 C CNN
+F 2 "" H 2300 2600 60  0000 C CNN
+F 3 "" H 2300 2600 60  0000 C CNN
+	2    2300 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE587B
+P 2300 2850
+F 0 "U1" H 2350 2950 30  0000 C CNN
+F 1 "PORT" H 2300 2850 30  0000 C CNN
+F 2 "" H 2300 2850 60  0000 C CNN
+F 3 "" H 2300 2850 60  0000 C CNN
+	3    2300 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE58AF
+P 2300 3100
+F 0 "U1" H 2350 3200 30  0000 C CNN
+F 1 "PORT" H 2300 3100 30  0000 C CNN
+F 2 "" H 2300 3100 60  0000 C CNN
+F 3 "" H 2300 3100 60  0000 C CNN
+	4    2300 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE58E6
+P 6800 4300
+F 0 "U1" H 6850 4400 30  0000 C CNN
+F 1 "PORT" H 6800 4300 30  0000 C CNN
+F 2 "" H 6800 4300 60  0000 C CNN
+F 3 "" H 6800 4300 60  0000 C CNN
+	13   6800 4300
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE5922
+P 2300 3300
+AR Path="/5CEE58E6" Ref="U1"  Part="1" 
+AR Path="/5CEE5922" Ref="U1"  Part="5" 
+F 0 "U1" H 2350 3400 30  0000 C CNN
+F 1 "PORT" H 2300 3300 30  0000 C CNN
+F 2 "" H 2300 3300 60  0000 C CNN
+F 3 "" H 2300 3300 60  0000 C CNN
+	5    2300 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CEE596F
+P 2350 3950
+AR Path="/5CEE5922" Ref="U1"  Part="5" 
+AR Path="/5CEE596F" Ref="U1"  Part="9" 
+F 0 "U1" H 2400 4050 30  0000 C CNN
+F 1 "PORT" H 2350 3950 30  0000 C CNN
+F 2 "" H 2350 3950 60  0000 C CNN
+F 3 "" H 2350 3950 60  0000 C CNN
+	9    2350 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE59AF
+P 2350 4200
+AR Path="/5CEE596F" Ref="U1"  Part="6" 
+AR Path="/5CEE59AF" Ref="U1"  Part="10" 
+F 0 "U1" H 2400 4300 30  0000 C CNN
+F 1 "PORT" H 2350 4200 30  0000 C CNN
+F 2 "" H 2350 4200 60  0000 C CNN
+F 3 "" H 2350 4200 60  0000 C CNN
+	10   2350 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE59F6
+P 2350 4450
+AR Path="/5CEE59AF" Ref="U1"  Part="7" 
+AR Path="/5CEE59F6" Ref="U1"  Part="11" 
+F 0 "U1" H 2400 4550 30  0000 C CNN
+F 1 "PORT" H 2350 4450 30  0000 C CNN
+F 2 "" H 2350 4450 60  0000 C CNN
+F 3 "" H 2350 4450 60  0000 C CNN
+	11   2350 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE5A6A
+P 2350 4650
+AR Path="/5CEE59F6" Ref="U1"  Part="8" 
+AR Path="/5CEE5A6A" Ref="U1"  Part="12" 
+F 0 "U1" H 2400 4750 30  0000 C CNN
+F 1 "PORT" H 2350 4650 30  0000 C CNN
+F 2 "" H 2350 4650 60  0000 C CNN
+F 3 "" H 2350 4650 60  0000 C CNN
+	12   2350 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE5BF8
+P 6750 2950
+AR Path="/5CEE5A6A" Ref="U1"  Part="9" 
+AR Path="/5CEE5BF8" Ref="U1"  Part="1" 
+F 0 "U1" H 6800 3050 30  0000 C CNN
+F 1 "PORT" H 6750 2950 30  0000 C CNN
+F 2 "" H 6750 2950 60  0000 C CNN
+F 3 "" H 6750 2950 60  0000 C CNN
+	1    6750 2950
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CEE5C72
+P 7850 1450
+F 0 "U1" H 7900 1550 30  0000 C CNN
+F 1 "PORT" H 7850 1450 30  0000 C CNN
+F 2 "" H 7850 1450 60  0000 C CNN
+F 3 "" H 7850 1450 60  0000 C CNN
+	6    7850 1450
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE5D23
+P 7850 1700
+F 0 "U1" H 7900 1800 30  0000 C CNN
+F 1 "PORT" H 7850 1700 30  0000 C CNN
+F 2 "" H 7850 1700 60  0000 C CNN
+F 3 "" H 7850 1700 60  0000 C CNN
+	7    7850 1700
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE5D75
+P 7850 1950
+F 0 "U1" H 7900 2050 30  0000 C CNN
+F 1 "PORT" H 7850 1950 30  0000 C CNN
+F 2 "" H 7850 1950 60  0000 C CNN
+F 3 "" H 7850 1950 60  0000 C CNN
+	14   7850 1950
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5DCA
+P 7850 2250
+F 0 "U1" H 7900 2350 30  0000 C CNN
+F 1 "PORT" H 7850 2250 30  0000 C CNN
+F 2 "" H 7850 2250 60  0000 C CNN
+F 3 "" H 7850 2250 60  0000 C CNN
+	8    7850 2250
+	-1   0    0    1   
+$EndComp
+NoConn ~ 7600 1450
+NoConn ~ 7600 1700
+NoConn ~ 7600 1950
+NoConn ~ 7600 2250
+$Comp
+L d_and U4
+U 1 1 5CEE56F6
+P 3850 4050
+F 0 "U4" H 3850 4050 60  0000 C CNN
+F 1 "d_and" H 3900 4150 60  0000 C CNN
+F 2 "" H 3850 4050 60  0000 C CNN
+F 3 "" H 3850 4050 60  0000 C CNN
+	1    3850 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5CEE56FC
+P 3850 4650
+F 0 "U5" H 3850 4650 60  0000 C CNN
+F 1 "d_and" H 3900 4750 60  0000 C CNN
+F 2 "" H 3850 4650 60  0000 C CNN
+F 3 "" H 3850 4650 60  0000 C CNN
+	1    3850 4650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4350 4600 4300 4600
+Wire Wire Line
+	4350 4350 4350 4600
+Wire Wire Line
+	4350 4000 4350 4250
+Wire Wire Line
+	4300 4000 4350 4000
+$Comp
+L d_and U7
+U 1 1 5CEE5702
+P 4800 4350
+F 0 "U7" H 4800 4350 60  0000 C CNN
+F 1 "d_and" H 4850 4450 60  0000 C CNN
+F 2 "" H 4800 4350 60  0000 C CNN
+F 3 "" H 4800 4350 60  0000 C CNN
+	1    4800 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4250 2650 4300 2650
+Wire Wire Line
+	4300 3250 4250 3250
+Wire Wire Line
+	4300 2650 4300 2900
+Wire Wire Line
+	4300 3000 4300 3250
+$Comp
+L d_and U6
+U 1 1 5CEE5432
+P 4750 3000
+F 0 "U6" H 4750 3000 60  0000 C CNN
+F 1 "d_and" H 4800 3100 60  0000 C CNN
+F 2 "" H 4750 3000 60  0000 C CNN
+F 3 "" H 4750 3000 60  0000 C CNN
+	1    4750 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5CEE540C
+P 3800 3300
+F 0 "U3" H 3800 3300 60  0000 C CNN
+F 1 "d_and" H 3850 3400 60  0000 C CNN
+F 2 "" H 3800 3300 60  0000 C CNN
+F 3 "" H 3800 3300 60  0000 C CNN
+	1    3800 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5CEE53DC
+P 3800 2700
+F 0 "U2" H 3800 2700 60  0000 C CNN
+F 1 "d_and" H 3850 2800 60  0000 C CNN
+F 2 "" H 3800 2700 60  0000 C CNN
+F 3 "" H 3800 2700 60  0000 C CNN
+	1    3800 2700
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4012/4012.sub b/src/SubcircuitLibrary/4012/4012.sub
new file mode 100644
index 00000000..65263f03
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012.sub
@@ -0,0 +1,38 @@
+* Subcircuit 4012
+.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+* u8  net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9  net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4012
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml
new file mode 100644
index 00000000..4e7e73b2
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/analysis b/src/SubcircuitLibrary/4012/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4012/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib
new file mode 100644
index 00000000..efa6746f
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir
new file mode 100644
index 00000000..67ac9971
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.cir
@@ -0,0 +1,26 @@
+* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff		
+U11  Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff		
+U15  Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff		
+U19  Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff		
+U22  Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and		
+U3  Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and		
+U4  Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and		
+U5  Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and		
+U6  Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and		
+U8  Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and		
+U9  Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and		
+
+.end
diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out
new file mode 100644
index 00000000..e3a384c5
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.cir.out
@@ -0,0 +1,72 @@
+* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
+
+* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
+* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
+* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
+* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
+* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
+* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
+* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
+* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
+* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
+* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
+a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
+a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
+a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
+a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
+a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
+a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
+a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
+a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
+a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
+a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
+a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
+a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
+a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 5e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro
new file mode 100644
index 00000000..8cdecd6c
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.pro
@@ -0,0 +1,72 @@
+update=Fri Jun 14 10:14:54 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+
diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch
new file mode 100644
index 00000000..05549a32
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.sch
@@ -0,0 +1,580 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:4017-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+$Comp
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+	1    4000 1850
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+$Comp
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+$EndComp
+$Comp
+L d_and U12
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+F 0 "U12" H 7100 1850 60  0000 C CNN
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+F 2 "" H 7100 1850 60  0000 C CNN
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+	1    7100 1850
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+$EndComp
+$Comp
+L d_and U13
+U 1 1 5C8A12F5
+P 7800 1850
+F 0 "U13" H 7800 1850 60  0000 C CNN
+F 1 "d_and" H 7850 1950 60  0000 C CNN
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+	1    7800 1850
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diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub
new file mode 100644
index 00000000..2e27ab61
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017.sub
@@ -0,0 +1,66 @@
+* Subcircuit 4017
+.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
+* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
+* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
+* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
+* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
+* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
+* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
+* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
+* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
+* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
+* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
+* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
+a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
+a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
+a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
+a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
+a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
+a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
+a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
+a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
+a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
+a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
+a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
+a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
+a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4017
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
new file mode 100644
index 00000000..9dfd97a3
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib
new file mode 100644
index 00000000..adbdfb35
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/D.lib
@@ -0,0 +1,11 @@
+.MODEL 1N4148 D(
++  Vj=1
++  Cjo=1.700E-12
++  Rs=4.755E-01
++  Is=2.495E-09
++  M=1.959E-01
++  N=1.679E+00
++  Bv=1.000E+02
++  tt=3.030E-09
++  Ibv=1.000E-04
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis
new file mode 100644
index 00000000..40bd9d97
--- /dev/null
+++ b/src/SubcircuitLibrary/4017/analysis
@@ -0,0 +1 @@
+.tran 5e-03 100e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro
new file mode 100644
index 00000000..76df4655
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and.pro
@@ -0,0 +1,44 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch
new file mode 100644
index 00000000..d6ac89f9
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib
new file mode 100644
index 00000000..c989d8c7
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0  -150 200  200 200 N
+P 3 0 1 0  -150 200  -150 -100  200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir
new file mode 100644
index 00000000..6aad9b84
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023.cir
@@ -0,0 +1,17 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X3  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and		
+U4  Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+X2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U3  Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter		
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter		
+
+.end
diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out
new file mode 100644
index 00000000..7f48d16f
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023.cir.out
@@ -0,0 +1,28 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro
new file mode 100644
index 00000000..5a5ce355
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023.pro
@@ -0,0 +1,44 @@
+update=05/31/19 15:32:35
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch
new file mode 100644
index 00000000..57dd7868
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023.sch
@@ -0,0 +1,309 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X3
+U 1 1 5CF0FA82
+P 4800 2500
+F 0 "X3" H 4900 2450 60  0000 C CNN
+F 1 "3_and" H 4950 2650 60  0000 C CNN
+F 2 "" H 4800 2500 60  0000 C CNN
+F 3 "" H 4800 2500 60  0000 C CNN
+	1    4800 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF0FB13
+P 6150 2450
+F 0 "U4" H 6150 2350 60  0000 C CNN
+F 1 "d_inverter" H 6150 2600 60  0000 C CNN
+F 2 "" H 6200 2400 60  0000 C CNN
+F 3 "" H 6200 2400 60  0000 C CNN
+	1    6150 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF0FB34
+P 3100 1950
+F 0 "U1" H 3150 2050 30  0000 C CNN
+F 1 "PORT" H 3100 1950 30  0000 C CNN
+F 2 "" H 3100 1950 60  0000 C CNN
+F 3 "" H 3100 1950 60  0000 C CNN
+	11   3100 1950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF0FB90
+P 3100 2350
+F 0 "U1" H 3150 2450 30  0000 C CNN
+F 1 "PORT" H 3100 2350 30  0000 C CNN
+F 2 "" H 3100 2350 60  0000 C CNN
+F 3 "" H 3100 2350 60  0000 C CNN
+	12   3100 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF0FBB8
+P 3100 2750
+F 0 "U1" H 3150 2850 30  0000 C CNN
+F 1 "PORT" H 3100 2750 30  0000 C CNN
+F 2 "" H 3100 2750 60  0000 C CNN
+F 3 "" H 3100 2750 60  0000 C CNN
+	13   3100 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF0FBED
+P 7800 2450
+F 0 "U1" H 7850 2550 30  0000 C CNN
+F 1 "PORT" H 7800 2450 30  0000 C CNN
+F 2 "" H 7800 2450 60  0000 C CNN
+F 3 "" H 7800 2450 60  0000 C CNN
+	10   7800 2450
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7550 2450 6450 2450
+Wire Wire Line
+	5850 2450 5300 2450
+Wire Wire Line
+	4450 2350 4450 1950
+Wire Wire Line
+	4450 1950 3350 1950
+Wire Wire Line
+	4450 2450 4100 2450
+Wire Wire Line
+	4100 2450 4100 2350
+Wire Wire Line
+	4100 2350 3350 2350
+Wire Wire Line
+	3350 2750 3950 2750
+Wire Wire Line
+	3950 2750 3950 2550
+Wire Wire Line
+	3950 2550 4450 2550
+$Comp
+L 3_and X2
+U 1 1 5CF0FF35
+P 4700 3800
+F 0 "X2" H 4800 3750 60  0000 C CNN
+F 1 "3_and" H 4850 3950 60  0000 C CNN
+F 2 "" H 4700 3800 60  0000 C CNN
+F 3 "" H 4700 3800 60  0000 C CNN
+	1    4700 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF0FF3B
+P 6050 3750
+F 0 "U3" H 6050 3650 60  0000 C CNN
+F 1 "d_inverter" H 6050 3900 60  0000 C CNN
+F 2 "" H 6100 3700 60  0000 C CNN
+F 3 "" H 6100 3700 60  0000 C CNN
+	1    6050 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF0FF41
+P 3000 3250
+F 0 "U1" H 3050 3350 30  0000 C CNN
+F 1 "PORT" H 3000 3250 30  0000 C CNN
+F 2 "" H 3000 3250 60  0000 C CNN
+F 3 "" H 3000 3250 60  0000 C CNN
+	4    3000 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CF0FF47
+P 3000 3650
+F 0 "U1" H 3050 3750 30  0000 C CNN
+F 1 "PORT" H 3000 3650 30  0000 C CNN
+F 2 "" H 3000 3650 60  0000 C CNN
+F 3 "" H 3000 3650 60  0000 C CNN
+	5    3000 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF0FF4D
+P 3000 4050
+F 0 "U1" H 3050 4150 30  0000 C CNN
+F 1 "PORT" H 3000 4050 30  0000 C CNN
+F 2 "" H 3000 4050 60  0000 C CNN
+F 3 "" H 3000 4050 60  0000 C CNN
+	3    3000 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF0FF53
+P 7700 3750
+F 0 "U1" H 7750 3850 30  0000 C CNN
+F 1 "PORT" H 7700 3750 30  0000 C CNN
+F 2 "" H 7700 3750 60  0000 C CNN
+F 3 "" H 7700 3750 60  0000 C CNN
+	6    7700 3750
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7450 3750 6350 3750
+Wire Wire Line
+	5750 3750 5200 3750
+Wire Wire Line
+	4350 3650 4350 3250
+Wire Wire Line
+	4350 3250 3250 3250
+Wire Wire Line
+	4350 3750 4000 3750
+Wire Wire Line
+	4000 3750 4000 3650
+Wire Wire Line
+	4000 3650 3250 3650
+Wire Wire Line
+	3250 4050 3850 4050
+Wire Wire Line
+	3850 4050 3850 3850
+Wire Wire Line
+	3850 3850 4350 3850
+$Comp
+L 3_and X1
+U 1 1 5CF100B9
+P 4650 5100
+F 0 "X1" H 4750 5050 60  0000 C CNN
+F 1 "3_and" H 4800 5250 60  0000 C CNN
+F 2 "" H 4650 5100 60  0000 C CNN
+F 3 "" H 4650 5100 60  0000 C CNN
+	1    4650 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF100BF
+P 6000 5050
+F 0 "U2" H 6000 4950 60  0000 C CNN
+F 1 "d_inverter" H 6000 5200 60  0000 C CNN
+F 2 "" H 6050 5000 60  0000 C CNN
+F 3 "" H 6050 5000 60  0000 C CNN
+	1    6000 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF100C5
+P 2950 4550
+F 0 "U1" H 3000 4650 30  0000 C CNN
+F 1 "PORT" H 2950 4550 30  0000 C CNN
+F 2 "" H 2950 4550 60  0000 C CNN
+F 3 "" H 2950 4550 60  0000 C CNN
+	1    2950 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF100CB
+P 2950 4950
+F 0 "U1" H 3000 5050 30  0000 C CNN
+F 1 "PORT" H 2950 4950 30  0000 C CNN
+F 2 "" H 2950 4950 60  0000 C CNN
+F 3 "" H 2950 4950 60  0000 C CNN
+	2    2950 4950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CF100D1
+P 2950 5350
+F 0 "U1" H 3000 5450 30  0000 C CNN
+F 1 "PORT" H 2950 5350 30  0000 C CNN
+F 2 "" H 2950 5350 60  0000 C CNN
+F 3 "" H 2950 5350 60  0000 C CNN
+	8    2950 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF100D7
+P 7650 5050
+F 0 "U1" H 7700 5150 30  0000 C CNN
+F 1 "PORT" H 7650 5050 30  0000 C CNN
+F 2 "" H 7650 5050 60  0000 C CNN
+F 3 "" H 7650 5050 60  0000 C CNN
+	9    7650 5050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7400 5050 6300 5050
+Wire Wire Line
+	5700 5050 5150 5050
+Wire Wire Line
+	4300 4950 4300 4550
+Wire Wire Line
+	4300 4550 3200 4550
+Wire Wire Line
+	4300 5050 3950 5050
+Wire Wire Line
+	3950 5050 3950 4950
+Wire Wire Line
+	3950 4950 3200 4950
+Wire Wire Line
+	3200 5350 3800 5350
+Wire Wire Line
+	3800 5350 3800 5150
+Wire Wire Line
+	3800 5150 4300 5150
+$Comp
+L PORT U1
+U 7 1 5CF101BF
+P 9950 3350
+F 0 "U1" H 10000 3450 30  0000 C CNN
+F 1 "PORT" H 9950 3350 30  0000 C CNN
+F 2 "" H 9950 3350 60  0000 C CNN
+F 3 "" H 9950 3350 60  0000 C CNN
+	7    9950 3350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF1025C
+P 9950 3900
+F 0 "U1" H 10000 4000 30  0000 C CNN
+F 1 "PORT" H 9950 3900 30  0000 C CNN
+F 2 "" H 9950 3900 60  0000 C CNN
+F 3 "" H 9950 3900 60  0000 C CNN
+	14   9950 3900
+	-1   0    0    1   
+$EndComp
+NoConn ~ 9700 3350
+NoConn ~ 9700 3900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub
new file mode 100644
index 00000000..b953da2e
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023.sub
@@ -0,0 +1,22 @@
+* Subcircuit 4023
+.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4023
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
new file mode 100644
index 00000000..ad900de2
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4023/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/4028-cache.lib b/src/SubcircuitLibrary/4028/4028-cache.lib
new file mode 100644
index 00000000..5b7e8ebd
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4028/4028.cir b/src/SubcircuitLibrary/4028/4028.cir
new file mode 100644
index 00000000..ff25eb55
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028.cir
@@ -0,0 +1,32 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9  Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor		
+U10  Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor		
+U11  Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor		
+U12  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor		
+U6  Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor		
+U7  Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor		
+U8  Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor		
+U2  Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter		
+U3  Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter		
+U4  Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter		
+U5  Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter		
+U15  Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and		
+U16  Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and		
+U17  Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and		
+U18  Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and		
+U19  Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and		
+U20  Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and		
+U21  Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and		
+U13  Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and		
+U14  Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT		
+U22  Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and		
+
+.end
diff --git a/src/SubcircuitLibrary/4028/4028.cir.out b/src/SubcircuitLibrary/4028/4028.cir.out
new file mode 100644
index 00000000..882115b7
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028.cir.out
@@ -0,0 +1,96 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+
+* u9  net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10  net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12  net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6  net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7  net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8  net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2  net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3  net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4  net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15  net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17  net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19  net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20  net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21  net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+* u22  net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4028/4028.pro b/src/SubcircuitLibrary/4028/4028.pro
new file mode 100644
index 00000000..a63207b3
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:43:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/src/SubcircuitLibrary/4028/4028.sch b/src/SubcircuitLibrary/4028/4028.sch
new file mode 100644
index 00000000..373a95e6
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028.sch
@@ -0,0 +1,628 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Wire Wire Line
+	7050 3150 7750 3150
+Wire Wire Line
+	7700 3600 7050 3600
+Wire Wire Line
+	7050 4000 7700 4000
+Wire Wire Line
+	7650 4400 7050 4400
+Wire Wire Line
+	7000 4850 7650 4850
+Wire Wire Line
+	7650 5300 7000 5300
+$Comp
+L d_and U22
+U 1 1 5CF14904
+P 6550 5800
+F 0 "U22" H 6550 5800 60  0000 C CNN
+F 1 "d_and" H 6600 5900 60  0000 C CNN
+F 2 "" H 6550 5800 60  0000 C CNN
+F 3 "" H 6550 5800 60  0000 C CNN
+	1    6550 5800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4200 1950 4600 1950
+Wire Wire Line
+	4600 1750 4600 5250
+Wire Wire Line
+	4600 1750 6150 1750
+Wire Wire Line
+	4600 5250 6100 5250
+Connection ~ 4600 1950
+Wire Wire Line
+	6100 5800 5900 5800
+Wire Wire Line
+	5900 5800 5900 5350
+Wire Wire Line
+	5900 5350 6100 5350
+Wire Wire Line
+	5850 4900 6100 4900
+Wire Wire Line
+	5850 3650 5850 4900
+Wire Wire Line
+	5850 4450 6150 4450
+Wire Wire Line
+	5850 4050 6150 4050
+Connection ~ 5850 4450
+Wire Wire Line
+	5850 3650 6150 3650
+Connection ~ 5850 4050
+Wire Wire Line
+	5050 3200 6150 3200
+Wire Wire Line
+	5850 1850 5850 3200
+Wire Wire Line
+	5850 2800 6150 2800
+Wire Wire Line
+	5850 2350 6150 2350
+Connection ~ 5850 2800
+Wire Wire Line
+	5850 1850 6150 1850
+Connection ~ 5850 2350
+Wire Wire Line
+	4200 2450 4700 2450
+Wire Wire Line
+	4700 2250 4700 5700
+Wire Wire Line
+	4700 2250 6150 2250
+Wire Wire Line
+	4200 3000 4800 3000
+Wire Wire Line
+	4800 2700 4800 4350
+Wire Wire Line
+	4800 2700 6150 2700
+Wire Wire Line
+	4700 5700 6100 5700
+Connection ~ 4700 2450
+Wire Wire Line
+	6150 3550 4600 3550
+Connection ~ 4600 3550
+Wire Wire Line
+	6150 3950 4700 3950
+Connection ~ 4700 3950
+Wire Wire Line
+	4800 4350 6150 4350
+Connection ~ 4800 3000
+Wire Wire Line
+	4200 3500 4900 3500
+Wire Wire Line
+	4900 3100 4900 4800
+Wire Wire Line
+	4900 3100 6150 3100
+Wire Wire Line
+	4900 4800 6100 4800
+Connection ~ 4900 3500
+Wire Wire Line
+	4200 4100 5050 4100
+Wire Wire Line
+	5050 4100 5050 3200
+Connection ~ 5850 3200
+Wire Wire Line
+	4150 4700 5850 4700
+Connection ~ 5850 4700
+Wire Wire Line
+	4150 5200 4500 5200
+Wire Wire Line
+	4500 5200 4500 5550
+Wire Wire Line
+	4500 5550 5900 5550
+Connection ~ 5900 5550
+$Comp
+L PORT U1
+U 5 1 5CF1563E
+P 7950 5750
+F 0 "U1" H 8000 5850 30  0000 C CNN
+F 1 "PORT" H 7950 5750 30  0000 C CNN
+F 2 "" H 7950 5750 60  0000 C CNN
+F 3 "" H 7950 5750 60  0000 C CNN
+	5    7950 5750
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7700 5750 7000 5750
+$Comp
+L PORT U1
+U 8 1 5CF15953
+P 9550 4800
+F 0 "U1" H 9600 4900 30  0000 C CNN
+F 1 "PORT" H 9550 4800 30  0000 C CNN
+F 2 "" H 9550 4800 60  0000 C CNN
+F 3 "" H 9550 4800 60  0000 C CNN
+	8    9550 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 16 1 5CF15A07
+P 9550 5250
+F 0 "U1" H 9600 5350 30  0000 C CNN
+F 1 "PORT" H 9550 5250 30  0000 C CNN
+F 2 "" H 9550 5250 60  0000 C CNN
+F 3 "" H 9550 5250 60  0000 C CNN
+	16   9550 5250
+	-1   0    0    1   
+$EndComp
+NoConn ~ 9300 4800
+NoConn ~ 9300 5250
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4028/4028.sub b/src/SubcircuitLibrary/4028/4028.sub
new file mode 100644
index 00000000..828e0b67
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028.sub
@@ -0,0 +1,90 @@
+* Subcircuit 4028
+.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+* u9  net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10  net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12  net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6  net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7  net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8  net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2  net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3  net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4  net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15  net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17  net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19  net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20  net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21  net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u22  net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4028
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml
new file mode 100644
index 00000000..189fb200
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/analysis b/src/SubcircuitLibrary/4028/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4028/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/4073/3_and-cache.lib
+++ b/src/SubcircuitLibrary/4073/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/4073/3_and.cir
+++ b/src/SubcircuitLibrary/4073/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/4073/3_and.cir.out
+++ b/src/SubcircuitLibrary/4073/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/4073/3_and.pro
+++ b/src/SubcircuitLibrary/4073/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/4073/3_and.sch
+++ b/src/SubcircuitLibrary/4073/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/4073/3_and.sub
+++ b/src/SubcircuitLibrary/4073/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib
index e316d596..4ee605a2 100644
--- a/src/SubcircuitLibrary/4073/4073-cache.lib
+++ b/src/SubcircuitLibrary/4073/4073-cache.lib
@@ -1,62 +1,62 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0  -150 200  200 200 N
-P 3 0 1 0  -150 200  -150 -100  200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0  -150 200  200 200 N
+P 3 0 1 0  -150 200  -150 -100  200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir
index 7afe79fe..e159f055 100644
--- a/src/SubcircuitLibrary/4073/4073.cir
+++ b/src/SubcircuitLibrary/4073/4073.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-X3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and		
-X2  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+X3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and		
+X2  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and		
+
+.end
diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out
index d22d0923..b25337cd 100644
--- a/src/SubcircuitLibrary/4073/4073.cir.out
+++ b/src/SubcircuitLibrary/4073/4073.cir.out
@@ -1,16 +1,16 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro
index 7ed8e96e..94cd9bd4 100644
--- a/src/SubcircuitLibrary/4073/4073.pro
+++ b/src/SubcircuitLibrary/4073/4073.pro
@@ -1,43 +1,43 @@
-update=05/31/19 16:37:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
+update=05/31/19 16:37:06
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch
index ff6d873a..045208e6 100644
--- a/src/SubcircuitLibrary/4073/4073.sch
+++ b/src/SubcircuitLibrary/4073/4073.sch
@@ -1,263 +1,263 @@
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-LIBS:eSim_Subckt
-LIBS:eSim_User
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+	7    7500 4100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11A8A
+P 7550 4600
+F 0 "U1" H 7600 4700 30  0000 C CNN
+F 1 "PORT" H 7550 4600 30  0000 C CNN
+F 2 "" H 7550 4600 60  0000 C CNN
+F 3 "" H 7550 4600 60  0000 C CNN
+	14   7550 4600
+	-1   0    0    1   
+$EndComp
+NoConn ~ 7250 4100
+NoConn ~ 7300 4600
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub
index b10679cc..15208169 100644
--- a/src/SubcircuitLibrary/4073/4073.sub
+++ b/src/SubcircuitLibrary/4073/4073.sub
@@ -1,10 +1,10 @@
-* Subcircuit 4073
-.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-* Control Statements
-
+* Subcircuit 4073
+.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+* Control Statements
+
 .ends 4073
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
index a3c1c972..155f5e60 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
+++ b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
@@ -1,63 +1,63 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir
index 7adbf177..b338b7b5 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir
+++ b/src/SubcircuitLibrary/4_OR/4_OR.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
+U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
+U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
index 4388b975..adb6b01b 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out
+++ b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
@@ -1,24 +1,24 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro
index 1e19b3a7..9daf26bc 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.pro
+++ b/src/SubcircuitLibrary/4_OR/4_OR.pro
@@ -1,45 +1,45 @@
-update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch
index 2f28896c..11896865 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.sch
+++ b/src/SubcircuitLibrary/4_OR/4_OR.sch
@@ -1,150 +1,150 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60  0000 C CNN
-F 1 "d_or" H 4300 3050 60  0000 C CNN
-F 2 "" H 4300 2950 60  0000 C CNN
-F 3 "" H 4300 2950 60  0000 C CNN
-	1    4300 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60  0000 C CNN
-F 1 "d_or" H 4300 3450 60  0000 C CNN
-F 2 "" H 4300 3350 60  0000 C CNN
-F 3 "" H 4300 3350 60  0000 C CNN
-	1    4300 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60  0000 C CNN
-F 1 "d_or" H 5250 3250 60  0000 C CNN
-F 2 "" H 5250 3150 60  0000 C CNN
-F 3 "" H 5250 3150 60  0000 C CNN
-	1    5250 3150
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4800 3050 4800 2900
-Wire Wire Line
-	4800 2900 4750 2900
-Wire Wire Line
-	4800 3150 4800 3300
-Wire Wire Line
-	4800 3300 4750 3300
-Wire Wire Line
-	3350 2850 3850 2850
-Wire Wire Line
-	3850 2950 3600 2950
-Wire Wire Line
-	3850 3250 3350 3250
-Wire Wire Line
-	3600 2950 3600 3000
-Wire Wire Line
-	3600 3000 3350 3000
-Wire Wire Line
-	3850 3350 3850 3400
-Wire Wire Line
-	3850 3400 3350 3400
-Wire Wire Line
-	5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
-F 1 "PORT" H 3100 2850 30  0000 C CNN
-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	1    3100 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
-P 3100 3000
-F 0 "U1" H 3150 3100 30  0000 C CNN
-F 1 "PORT" H 3100 3000 30  0000 C CNN
-F 2 "" H 3100 3000 60  0000 C CNN
-F 3 "" H 3100 3000 60  0000 C CNN
-	2    3100 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30  0000 C CNN
-F 1 "PORT" H 3100 3250 30  0000 C CNN
-F 2 "" H 3100 3250 60  0000 C CNN
-F 3 "" H 3100 3250 60  0000 C CNN
-	3    3100 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30  0000 C CNN
-F 1 "PORT" H 3100 3400 30  0000 C CNN
-F 2 "" H 3100 3400 60  0000 C CNN
-F 3 "" H 3100 3400 60  0000 C CNN
-	4    3100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30  0000 C CNN
-F 1 "PORT" H 6450 3100 30  0000 C CNN
-F 2 "" H 6450 3100 60  0000 C CNN
-F 3 "" H 6450 3100 60  0000 C CNN
-	5    6450 3100
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2850 0    60   ~ 12
-in1
-Text Notes 3450 3000 0    60   ~ 12
-in2
-Text Notes 3450 3250 0    60   ~ 12
-in3
-Text Notes 3450 3400 0    60   ~ 12
-in4
-Text Notes 5800 3100 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60  0000 C CNN
+F 1 "d_or" H 4300 3050 60  0000 C CNN
+F 2 "" H 4300 2950 60  0000 C CNN
+F 3 "" H 4300 2950 60  0000 C CNN
+	1    4300 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60  0000 C CNN
+F 1 "d_or" H 4300 3450 60  0000 C CNN
+F 2 "" H 4300 3350 60  0000 C CNN
+F 3 "" H 4300 3350 60  0000 C CNN
+	1    4300 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60  0000 C CNN
+F 1 "d_or" H 5250 3250 60  0000 C CNN
+F 2 "" H 5250 3150 60  0000 C CNN
+F 3 "" H 5250 3150 60  0000 C CNN
+	1    5250 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4800 3050 4800 2900
+Wire Wire Line
+	4800 2900 4750 2900
+Wire Wire Line
+	4800 3150 4800 3300
+Wire Wire Line
+	4800 3300 4750 3300
+Wire Wire Line
+	3350 2850 3850 2850
+Wire Wire Line
+	3850 2950 3600 2950
+Wire Wire Line
+	3850 3250 3350 3250
+Wire Wire Line
+	3600 2950 3600 3000
+Wire Wire Line
+	3600 3000 3350 3000
+Wire Wire Line
+	3850 3350 3850 3400
+Wire Wire Line
+	3850 3400 3350 3400
+Wire Wire Line
+	5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30  0000 C CNN
+F 1 "PORT" H 3100 2850 30  0000 C CNN
+F 2 "" H 3100 2850 60  0000 C CNN
+F 3 "" H 3100 2850 60  0000 C CNN
+	1    3100 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30  0000 C CNN
+F 1 "PORT" H 3100 3000 30  0000 C CNN
+F 2 "" H 3100 3000 60  0000 C CNN
+F 3 "" H 3100 3000 60  0000 C CNN
+	2    3100 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30  0000 C CNN
+F 1 "PORT" H 3100 3250 30  0000 C CNN
+F 2 "" H 3100 3250 60  0000 C CNN
+F 3 "" H 3100 3250 60  0000 C CNN
+	3    3100 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30  0000 C CNN
+F 1 "PORT" H 3100 3400 30  0000 C CNN
+F 2 "" H 3100 3400 60  0000 C CNN
+F 3 "" H 3100 3400 60  0000 C CNN
+	4    3100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30  0000 C CNN
+F 1 "PORT" H 6450 3100 30  0000 C CNN
+F 2 "" H 6450 3100 60  0000 C CNN
+F 3 "" H 6450 3100 60  0000 C CNN
+	5    6450 3100
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2850 0    60   ~ 12
+in1
+Text Notes 3450 3000 0    60   ~ 12
+in2
+Text Notes 3450 3250 0    60   ~ 12
+in3
+Text Notes 3450 3400 0    60   ~ 12
+in4
+Text Notes 5800 3100 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub
index 53fc8b33..d1fd3a24 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.sub
+++ b/src/SubcircuitLibrary/4_OR/4_OR.sub
@@ -1,18 +1,18 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/4_and/3_and-cache.lib
+++ b/src/SubcircuitLibrary/4_and/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/4_and/3_and.cir
+++ b/src/SubcircuitLibrary/4_and/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/4_and/3_and.cir.out
+++ b/src/SubcircuitLibrary/4_and/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/4_and/3_and.pro
+++ b/src/SubcircuitLibrary/4_and/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/4_and/3_and.sch
+++ b/src/SubcircuitLibrary/4_and/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/4_and/3_and.sub
+++ b/src/SubcircuitLibrary/4_and/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib
index cb84d8f2..60f1a83d 100644
--- a/src/SubcircuitLibrary/4_and/4_and-cache.lib
+++ b/src/SubcircuitLibrary/4_and/4_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib
index 6b2c17f7..e3833051 100644
--- a/src/SubcircuitLibrary/4_and/4_and-rescue.lib
+++ b/src/SubcircuitLibrary/4_and/4_and-rescue.lib
@@ -1,22 +1,22 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir
index 35e46097..fdf2e107 100644
--- a/src/SubcircuitLibrary/4_and/4_and.cir
+++ b/src/SubcircuitLibrary/4_and/4_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out
index 6e35b18a..f40e5bc6 100644
--- a/src/SubcircuitLibrary/4_and/4_and.cir.out
+++ b/src/SubcircuitLibrary/4_and/4_and.cir.out
@@ -1,18 +1,18 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro
index 814ad76a..9c0be79e 100644
--- a/src/SubcircuitLibrary/4_and/4_and.pro
+++ b/src/SubcircuitLibrary/4_and/4_and.pro
@@ -1,58 +1,58 @@
-update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=06/01/19 15:08:42
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch
index 2d8296d4..f5e8febd 100644
--- a/src/SubcircuitLibrary/4_and/4_and.sch
+++ b/src/SubcircuitLibrary/4_and/4_and.sch
@@ -1,151 +1,151 @@
-EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60  0000 C CNN
-F 1 "3_and" H 4650 4000 60  0000 C CNN
-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60  0000 C CNN
-F 1 "d_and" H 5500 3500 60  0000 C CNN
-F 2 "" H 5450 3400 60  0000 C CNN
-F 3 "" H 5450 3400 60  0000 C CNN
-	1    5450 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5000 3100 5000 3300
-Wire Wire Line
-	4150 3000 4150 2700
-Wire Wire Line
-	4150 2700 3200 2700
-Wire Wire Line
-	4150 3100 4000 3100
-Wire Wire Line
-	4000 3100 4000 3000
-Wire Wire Line
-	4000 3000 3200 3000
-Wire Wire Line
-	4150 3200 4150 3300
-Wire Wire Line
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-$Comp
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-in4
-Text Notes 6150 3350 0    60   ~ 12
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-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Date ""
+Rev ""
+Comp ""
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+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
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+F 1 "3_and" H 4650 4000 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$Comp
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+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30  0000 C CNN
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+F 2 "" H 3000 3550 60  0000 C CNN
+F 3 "" H 3000 3550 60  0000 C CNN
+	4    3000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30  0000 C CNN
+F 1 "PORT" H 6750 3350 30  0000 C CNN
+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
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+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub
index bf20b628..8663f37e 100644
--- a/src/SubcircuitLibrary/4_and/4_and.sub
+++ b/src/SubcircuitLibrary/4_and/4_and.sub
@@ -1,12 +1,12 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib
+++ b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and.cir
+++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out
+++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and.pro
+++ b/src/SubcircuitLibrary/4to16_demux/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and.sch
+++ b/src/SubcircuitLibrary/4to16_demux/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
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-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
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-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
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-$EndComp
-$Comp
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-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
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-Wire Wire Line
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-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/4to16_demux/3_and.sub
+++ b/src/SubcircuitLibrary/4to16_demux/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib
index 4cf915be..ac396288 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib
+++ b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir
index ca1199bd..6a05b9b5 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and.cir
+++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out
index 20d3f8a5..6a6b126a 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out
+++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out
@@ -1,22 +1,22 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro
index a9d6304f..7a2f090e 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and.pro
+++ b/src/SubcircuitLibrary/4to16_demux/5_and.pro
@@ -1,50 +1,50 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=06/01/19 11:31:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_PSpice
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
+LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch
index 0d86cdec..e9eb58ee 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and.sch
+++ b/src/SubcircuitLibrary/4to16_demux/5_and.sch
@@ -1,171 +1,171 @@
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-$EndSCHEMATC
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+LIBS:cypress
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+LIBS:opto
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+LIBS:contrib
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+LIBS:eSim_Devices
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diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub
index 9d929fcb..35b10e17 100644
--- a/src/SubcircuitLibrary/4to16_demux/5_and.sub
+++ b/src/SubcircuitLibrary/4to16_demux/5_and.sub
@@ -1,16 +1,16 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/556/556-cache.lib b/src/SubcircuitLibrary/556/556-cache.lib
new file mode 100644
index 00000000..75d610da
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556-cache.lib
@@ -0,0 +1,64 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# LM555N
+#
+DEF LM555N X 0 40 Y Y 1 F N
+F0 "X" 0 -50 60 H V C CNN
+F1 "LM555N" 0 100 60 H V C CNN
+F2 "" -50 0 60 H V C CNN
+F3 "" -50 0 60 H V C CNN
+DRAW
+S 350 -400 -350 400 0 1 0 N
+X GND 1 0 -600 200 U 50 50 1 1 W
+X TR 2 -550 250 200 R 50 50 1 1 I
+X Q 3 550 250 200 L 50 50 1 1 O
+X R 4 -550 -250 200 R 50 50 1 1 I I
+X CV 5 -550 0 200 R 50 50 1 1 I
+X THR 6 550 -250 200 L 50 50 1 1 I
+X DIS 7 550 0 200 L 50 50 1 1 I
+X VCC 8 0 600 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/556/556.cir b/src/SubcircuitLibrary/556/556.cir
new file mode 100644
index 00000000..48baa73e
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556.cir
@@ -0,0 +1,13 @@
+* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N		
+X2  Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/556/556.cir.out b/src/SubcircuitLibrary/556/556.cir.out
new file mode 100644
index 00000000..c74aab7c
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556.cir.out
@@ -0,0 +1,15 @@
+* c:\esim\esim\src\subcircuitlibrary\556\556.cir
+
+.include lm555n.sub
+x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n
+x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/556/556.pro b/src/SubcircuitLibrary/556/556.pro
new file mode 100644
index 00000000..a165313d
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556.pro
@@ -0,0 +1,72 @@
+update=03/18/19 18:13:51
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=regul
+LibName6=74xx
+LibName7=cmos4000
+LibName8=adc-dac
+LibName9=memory
+LibName10=xilinx
+LibName11=microcontrollers
+LibName12=dsp
+LibName13=microchip
+LibName14=analog_switches
+LibName15=motorola
+LibName16=texas
+LibName17=intel
+LibName18=audio
+LibName19=interface
+LibName20=digital-audio
+LibName21=philips
+LibName22=display
+LibName23=cypress
+LibName24=siliconi
+LibName25=opto
+LibName26=atmel
+LibName27=contrib
+LibName28=valves
+LibName29=eSim_User
+LibName30=eSim_Subckt
+LibName31=eSim_Sources
+LibName32=eSim_PSpice
+LibName33=eSim_Power
+LibName34=eSim_Plot
+LibName35=eSim_Miscellaneous
+LibName36=eSim_Hybrid
+LibName37=eSim_Digital
+LibName38=eSim_Devices
+LibName39=eSim_Analog
diff --git a/src/SubcircuitLibrary/556/556.sch b/src/SubcircuitLibrary/556/556.sch
new file mode 100644
index 00000000..af4e1bc9
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556.sch
@@ -0,0 +1,275 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:eSim_Sources
+LIBS:eSim_PSpice
+LIBS:eSim_Power
+LIBS:eSim_Plot
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Hybrid
+LIBS:eSim_Digital
+LIBS:eSim_Devices
+LIBS:eSim_Analog
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L LM555N X1
+U 1 1 5C8F9298
+P 4150 3850
+F 0 "X1" H 4150 3800 60  0000 C CNN
+F 1 "LM555N" H 4150 3950 60  0000 C CNN
+F 2 "" H 4100 3850 60  0000 C CNN
+F 3 "" H 4100 3850 60  0000 C CNN
+	1    4150 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L LM555N X2
+U 1 1 5C8F92E5
+P 7100 3850
+F 0 "X2" H 7100 3800 60  0000 C CNN
+F 1 "LM555N" H 7100 3950 60  0000 C CNN
+F 2 "" H 7050 3850 60  0000 C CNN
+F 3 "" H 7050 3850 60  0000 C CNN
+	1    7100 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 3250 4150 3000
+Wire Wire Line
+	4150 3000 7100 3000
+Wire Wire Line
+	4150 4450 4150 4650
+Wire Wire Line
+	4150 4650 7100 4650
+$Comp
+L PORT U1
+U 14 1 5C8F93E6
+P 4650 2600
+F 0 "U1" H 4700 2700 30  0000 C CNN
+F 1 "PORT" H 4650 2600 30  0000 C CNN
+F 2 "" H 4650 2600 60  0000 C CNN
+F 3 "" H 4650 2600 60  0000 C CNN
+	14   4650 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4900 2600 5000 2600
+Wire Wire Line
+	5000 2600 5000 3000
+Connection ~ 5000 3000
+$Comp
+L PORT U1
+U 6 1 5C8F94B6
+P 3050 3600
+F 0 "U1" H 3100 3700 30  0000 C CNN
+F 1 "PORT" H 3050 3600 30  0000 C CNN
+F 2 "" H 3050 3600 60  0000 C CNN
+F 3 "" H 3050 3600 60  0000 C CNN
+	6    3050 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C8F95C0
+P 3050 3850
+F 0 "U1" H 3100 3950 30  0000 C CNN
+F 1 "PORT" H 3050 3850 30  0000 C CNN
+F 2 "" H 3050 3850 60  0000 C CNN
+F 3 "" H 3050 3850 60  0000 C CNN
+	3    3050 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C8F95E7
+P 3050 4100
+F 0 "U1" H 3100 4200 30  0000 C CNN
+F 1 "PORT" H 3050 4100 30  0000 C CNN
+F 2 "" H 3050 4100 60  0000 C CNN
+F 3 "" H 3050 4100 60  0000 C CNN
+	4    3050 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7100 3000 7100 3250
+Wire Wire Line
+	7100 4650 7100 4450
+$Comp
+L PORT U1
+U 8 1 5C8F9C35
+P 6000 3600
+F 0 "U1" H 6050 3700 30  0000 C CNN
+F 1 "PORT" H 6000 3600 30  0000 C CNN
+F 2 "" H 6000 3600 60  0000 C CNN
+F 3 "" H 6000 3600 60  0000 C CNN
+	8    6000 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5C8F9C3B
+P 6000 3850
+F 0 "U1" H 6050 3950 30  0000 C CNN
+F 1 "PORT" H 6000 3850 30  0000 C CNN
+F 2 "" H 6000 3850 60  0000 C CNN
+F 3 "" H 6000 3850 60  0000 C CNN
+	11   6000 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C8F9C41
+P 6000 4100
+F 0 "U1" H 6050 4200 30  0000 C CNN
+F 1 "PORT" H 6000 4100 30  0000 C CNN
+F 2 "" H 6000 4100 60  0000 C CNN
+F 3 "" H 6000 4100 60  0000 C CNN
+	10   6000 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C8F9D22
+P 5200 4100
+F 0 "U1" H 5250 4200 30  0000 C CNN
+F 1 "PORT" H 5200 4100 30  0000 C CNN
+F 2 "" H 5200 4100 60  0000 C CNN
+F 3 "" H 5200 4100 60  0000 C CNN
+	2    5200 4100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C8F9D28
+P 5200 3850
+F 0 "U1" H 5250 3950 30  0000 C CNN
+F 1 "PORT" H 5200 3850 30  0000 C CNN
+F 2 "" H 5200 3850 60  0000 C CNN
+F 3 "" H 5200 3850 60  0000 C CNN
+	1    5200 3850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C8F9D2E
+P 5200 3600
+F 0 "U1" H 5250 3700 30  0000 C CNN
+F 1 "PORT" H 5200 3600 30  0000 C CNN
+F 2 "" H 5200 3600 60  0000 C CNN
+F 3 "" H 5200 3600 60  0000 C CNN
+	5    5200 3600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5C8FA0FA
+P 8250 4100
+F 0 "U1" H 8300 4200 30  0000 C CNN
+F 1 "PORT" H 8250 4100 30  0000 C CNN
+F 2 "" H 8250 4100 60  0000 C CNN
+F 3 "" H 8250 4100 60  0000 C CNN
+	12   8250 4100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5C8FA100
+P 8250 3850
+F 0 "U1" H 8300 3950 30  0000 C CNN
+F 1 "PORT" H 8250 3850 30  0000 C CNN
+F 2 "" H 8250 3850 60  0000 C CNN
+F 3 "" H 8250 3850 60  0000 C CNN
+	13   8250 3850
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C8FA106
+P 8250 3600
+F 0 "U1" H 8300 3700 30  0000 C CNN
+F 1 "PORT" H 8250 3600 30  0000 C CNN
+F 2 "" H 8250 3600 60  0000 C CNN
+F 3 "" H 8250 3600 60  0000 C CNN
+	9    8250 3600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C8FA319
+P 4950 5050
+F 0 "U1" H 5000 5150 30  0000 C CNN
+F 1 "PORT" H 4950 5050 30  0000 C CNN
+F 2 "" H 4950 5050 60  0000 C CNN
+F 3 "" H 4950 5050 60  0000 C CNN
+	7    4950 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5200 5050 5200 4650
+Connection ~ 5200 4650
+Wire Wire Line
+	3300 3600 3600 3600
+Wire Wire Line
+	3300 3850 3600 3850
+Wire Wire Line
+	3300 4100 3600 4100
+Wire Wire Line
+	4700 3600 4950 3600
+Wire Wire Line
+	4700 3850 4950 3850
+Wire Wire Line
+	4700 4100 4950 4100
+Wire Wire Line
+	6250 3600 6550 3600
+Wire Wire Line
+	6250 3850 6550 3850
+Wire Wire Line
+	6250 4100 6550 4100
+Wire Wire Line
+	8000 3600 7650 3600
+Wire Wire Line
+	8000 3850 7650 3850
+Wire Wire Line
+	8000 4100 7650 4100
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/556/556.sub b/src/SubcircuitLibrary/556/556.sub
new file mode 100644
index 00000000..a370b703
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556.sub
@@ -0,0 +1,9 @@
+* Subcircuit 556
+.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\esim\esim\src\subcircuitlibrary\556\556.cir
+.include lm555n.sub
+x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n
+x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n
+* Control Statements
+
+.ends 556
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/556/556_Previous_Values.xml b/src/SubcircuitLibrary/556/556_Previous_Values.xml
new file mode 100644
index 00000000..c025c2d1
--- /dev/null
+++ b/src/SubcircuitLibrary/556/556_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/5_and/3_and-cache.lib
+++ b/src/SubcircuitLibrary/5_and/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/5_and/3_and.cir
+++ b/src/SubcircuitLibrary/5_and/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/5_and/3_and.cir.out
+++ b/src/SubcircuitLibrary/5_and/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro
index 0fdf4d25..76df4655 100644
--- a/src/SubcircuitLibrary/5_and/3_and.pro
+++ b/src/SubcircuitLibrary/5_and/3_and.pro
@@ -1,44 +1,44 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch
index c853bf49..d6ac89f9 100644
--- a/src/SubcircuitLibrary/5_and/3_and.sch
+++ b/src/SubcircuitLibrary/5_and/3_and.sch
@@ -1,130 +1,130 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
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-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
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-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/5_and/3_and.sub
+++ b/src/SubcircuitLibrary/5_and/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib
index 4cf915be..ac396288 100644
--- a/src/SubcircuitLibrary/5_and/5_and-cache.lib
+++ b/src/SubcircuitLibrary/5_and/5_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir
index ca1199bd..6a05b9b5 100644
--- a/src/SubcircuitLibrary/5_and/5_and.cir
+++ b/src/SubcircuitLibrary/5_and/5_and.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out
index 20d3f8a5..6a6b126a 100644
--- a/src/SubcircuitLibrary/5_and/5_and.cir.out
+++ b/src/SubcircuitLibrary/5_and/5_and.cir.out
@@ -1,22 +1,22 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro
index a9d6304f..7a2f090e 100644
--- a/src/SubcircuitLibrary/5_and/5_and.pro
+++ b/src/SubcircuitLibrary/5_and/5_and.pro
@@ -1,50 +1,50 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=06/01/19 11:31:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_PSpice
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
+LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch
index 0d86cdec..e9eb58ee 100644
--- a/src/SubcircuitLibrary/5_and/5_and.sch
+++ b/src/SubcircuitLibrary/5_and/5_and.sch
@@ -1,171 +1,171 @@
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-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:cypress
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+LIBS:opto
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+LIBS:contrib
+LIBS:valves
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+LIBS:eSim_Devices
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diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub
index 9d929fcb..35b10e17 100644
--- a/src/SubcircuitLibrary/5_and/5_and.sub
+++ b/src/SubcircuitLibrary/5_and/5_and.sub
@@ -1,16 +1,16 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/74153/3_and-cache.lib
+++ b/src/SubcircuitLibrary/74153/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/74153/3_and.cir
+++ b/src/SubcircuitLibrary/74153/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/74153/3_and.cir.out
+++ b/src/SubcircuitLibrary/74153/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro
index 0fdf4d25..2c9ac554 100644
--- a/src/SubcircuitLibrary/74153/3_and.pro
+++ b/src/SubcircuitLibrary/74153/3_and.pro
@@ -1,44 +1,58 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch
index c853bf49..86be0215 100644
--- a/src/SubcircuitLibrary/74153/3_and.sch
+++ b/src/SubcircuitLibrary/74153/3_and.sch
@@ -1,130 +1,121 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
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-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/74153/3_and.sub
+++ b/src/SubcircuitLibrary/74153/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib
index a3c1c972..155f5e60 100644
--- a/src/SubcircuitLibrary/74153/4_OR-cache.lib
+++ b/src/SubcircuitLibrary/74153/4_OR-cache.lib
@@ -1,63 +1,63 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir
index 7adbf177..b338b7b5 100644
--- a/src/SubcircuitLibrary/74153/4_OR.cir
+++ b/src/SubcircuitLibrary/74153/4_OR.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
+U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
+U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out
index 4388b975..adb6b01b 100644
--- a/src/SubcircuitLibrary/74153/4_OR.cir.out
+++ b/src/SubcircuitLibrary/74153/4_OR.cir.out
@@ -1,24 +1,24 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro
index 1e19b3a7..2c258cec 100644
--- a/src/SubcircuitLibrary/74153/4_OR.pro
+++ b/src/SubcircuitLibrary/74153/4_OR.pro
@@ -1,45 +1,45 @@
-update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
+update=03/28/19 22:43:48
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch
index 2f28896c..11896865 100644
--- a/src/SubcircuitLibrary/74153/4_OR.sch
+++ b/src/SubcircuitLibrary/74153/4_OR.sch
@@ -1,150 +1,150 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
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-F 0 "U2" H 4300 2950 60  0000 C CNN
-F 1 "d_or" H 4300 3050 60  0000 C CNN
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-F 3 "" H 4300 2950 60  0000 C CNN
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-	5700 3100 6200 3100
-$Comp
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-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
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-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	1    3100 2850
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-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
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-F 2 "" H 3100 3000 60  0000 C CNN
-F 3 "" H 3100 3000 60  0000 C CNN
-	2    3100 3000
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-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
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-F 2 "" H 3100 3250 60  0000 C CNN
-F 3 "" H 3100 3250 60  0000 C CNN
-	3    3100 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30  0000 C CNN
-F 1 "PORT" H 3100 3400 30  0000 C CNN
-F 2 "" H 3100 3400 60  0000 C CNN
-F 3 "" H 3100 3400 60  0000 C CNN
-	4    3100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30  0000 C CNN
-F 1 "PORT" H 6450 3100 30  0000 C CNN
-F 2 "" H 6450 3100 60  0000 C CNN
-F 3 "" H 6450 3100 60  0000 C CNN
-	5    6450 3100
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2850 0    60   ~ 12
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-Text Notes 3450 3250 0    60   ~ 12
-in3
-Text Notes 3450 3400 0    60   ~ 12
-in4
-Text Notes 5800 3100 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60  0000 C CNN
+F 1 "d_or" H 4300 3050 60  0000 C CNN
+F 2 "" H 4300 2950 60  0000 C CNN
+F 3 "" H 4300 2950 60  0000 C CNN
+	1    4300 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60  0000 C CNN
+F 1 "d_or" H 4300 3450 60  0000 C CNN
+F 2 "" H 4300 3350 60  0000 C CNN
+F 3 "" H 4300 3350 60  0000 C CNN
+	1    4300 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60  0000 C CNN
+F 1 "d_or" H 5250 3250 60  0000 C CNN
+F 2 "" H 5250 3150 60  0000 C CNN
+F 3 "" H 5250 3150 60  0000 C CNN
+	1    5250 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4800 3050 4800 2900
+Wire Wire Line
+	4800 2900 4750 2900
+Wire Wire Line
+	4800 3150 4800 3300
+Wire Wire Line
+	4800 3300 4750 3300
+Wire Wire Line
+	3350 2850 3850 2850
+Wire Wire Line
+	3850 2950 3600 2950
+Wire Wire Line
+	3850 3250 3350 3250
+Wire Wire Line
+	3600 2950 3600 3000
+Wire Wire Line
+	3600 3000 3350 3000
+Wire Wire Line
+	3850 3350 3850 3400
+Wire Wire Line
+	3850 3400 3350 3400
+Wire Wire Line
+	5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30  0000 C CNN
+F 1 "PORT" H 3100 2850 30  0000 C CNN
+F 2 "" H 3100 2850 60  0000 C CNN
+F 3 "" H 3100 2850 60  0000 C CNN
+	1    3100 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30  0000 C CNN
+F 1 "PORT" H 3100 3000 30  0000 C CNN
+F 2 "" H 3100 3000 60  0000 C CNN
+F 3 "" H 3100 3000 60  0000 C CNN
+	2    3100 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30  0000 C CNN
+F 1 "PORT" H 3100 3250 30  0000 C CNN
+F 2 "" H 3100 3250 60  0000 C CNN
+F 3 "" H 3100 3250 60  0000 C CNN
+	3    3100 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30  0000 C CNN
+F 1 "PORT" H 3100 3400 30  0000 C CNN
+F 2 "" H 3100 3400 60  0000 C CNN
+F 3 "" H 3100 3400 60  0000 C CNN
+	4    3100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30  0000 C CNN
+F 1 "PORT" H 6450 3100 30  0000 C CNN
+F 2 "" H 6450 3100 60  0000 C CNN
+F 3 "" H 6450 3100 60  0000 C CNN
+	5    6450 3100
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2850 0    60   ~ 12
+in1
+Text Notes 3450 3000 0    60   ~ 12
+in2
+Text Notes 3450 3250 0    60   ~ 12
+in3
+Text Notes 3450 3400 0    60   ~ 12
+in4
+Text Notes 5800 3100 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub
index 53fc8b33..d1fd3a24 100644
--- a/src/SubcircuitLibrary/74153/4_OR.sub
+++ b/src/SubcircuitLibrary/74153/4_OR.sub
@@ -1,18 +1,18 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml
index 0683d9eb..23698d37 100644
--- a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml
+++ b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib
index cb84d8f2..ac396288 100644
--- a/src/SubcircuitLibrary/74153/4_and-cache.lib
+++ b/src/SubcircuitLibrary/74153/4_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir
index 35e46097..50d490fa 100644
--- a/src/SubcircuitLibrary/74153/4_and.cir
+++ b/src/SubcircuitLibrary/74153/4_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out
index 6e35b18a..f40e5bc6 100644
--- a/src/SubcircuitLibrary/74153/4_and.cir.out
+++ b/src/SubcircuitLibrary/74153/4_and.cir.out
@@ -1,18 +1,18 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro
index 814ad76a..6eb77fff 100644
--- a/src/SubcircuitLibrary/74153/4_and.pro
+++ b/src/SubcircuitLibrary/74153/4_and.pro
@@ -1,58 +1,57 @@
-update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=03/26/19 18:58:33
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=texas
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch
index 2d8296d4..883458e1 100644
--- a/src/SubcircuitLibrary/74153/4_and.sch
+++ b/src/SubcircuitLibrary/74153/4_and.sch
@@ -1,151 +1,139 @@
-EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60  0000 C CNN
-F 1 "3_and" H 4650 4000 60  0000 C CNN
-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60  0000 C CNN
-F 1 "d_and" H 5500 3500 60  0000 C CNN
-F 2 "" H 5450 3400 60  0000 C CNN
-F 3 "" H 5450 3400 60  0000 C CNN
-	1    5450 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
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-	4000 3100 4000 3000
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-	4000 3000 3200 3000
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-	4150 3200 4150 3300
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-	4150 3300 3250 3300
-Wire Wire Line
-	5000 3400 5000 3550
-Wire Wire Line
-	5000 3550 3250 3550
-Wire Wire Line
-	5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30  0000 C CNN
-F 1 "PORT" H 2950 2700 30  0000 C CNN
-F 2 "" H 2950 2700 60  0000 C CNN
-F 3 "" H 2950 2700 60  0000 C CNN
-	1    2950 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30  0000 C CNN
-F 1 "PORT" H 2950 3000 30  0000 C CNN
-F 2 "" H 2950 3000 60  0000 C CNN
-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30  0000 C CNN
-F 1 "PORT" H 3000 3300 30  0000 C CNN
-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30  0000 C CNN
-F 1 "PORT" H 3000 3550 30  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	4    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30  0000 C CNN
-F 1 "PORT" H 6750 3350 30  0000 C CNN
-F 2 "" H 6750 3350 60  0000 C CNN
-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2650 0    60   ~ 12
-in1
-Text Notes 3450 2950 0    60   ~ 12
-in2
-Text Notes 3500 3300 0    60   ~ 12
-in3
-Text Notes 3500 3550 0    60   ~ 12
-in4
-Text Notes 6150 3350 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60  0000 C CNN
+F 1 "3_and" H 4650 4000 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60  0000 C CNN
+F 1 "d_and" H 5500 3500 60  0000 C CNN
+F 2 "" H 5450 3400 60  0000 C CNN
+F 3 "" H 5450 3400 60  0000 C CNN
+	1    5450 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 3100 5000 3300
+Wire Wire Line
+	4150 3000 4150 2700
+Wire Wire Line
+	4150 2700 3200 2700
+Wire Wire Line
+	4150 3100 4000 3100
+Wire Wire Line
+	4000 3100 4000 3000
+Wire Wire Line
+	4000 3000 3200 3000
+Wire Wire Line
+	4150 3200 4150 3300
+Wire Wire Line
+	4150 3300 3250 3300
+Wire Wire Line
+	5000 3400 5000 3550
+Wire Wire Line
+	5000 3550 3250 3550
+Wire Wire Line
+	5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30  0000 C CNN
+F 1 "PORT" H 2950 2700 30  0000 C CNN
+F 2 "" H 2950 2700 60  0000 C CNN
+F 3 "" H 2950 2700 60  0000 C CNN
+	1    2950 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30  0000 C CNN
+F 1 "PORT" H 2950 3000 30  0000 C CNN
+F 2 "" H 2950 3000 60  0000 C CNN
+F 3 "" H 2950 3000 60  0000 C CNN
+	2    2950 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30  0000 C CNN
+F 1 "PORT" H 3000 3300 30  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30  0000 C CNN
+F 1 "PORT" H 3000 3550 30  0000 C CNN
+F 2 "" H 3000 3550 60  0000 C CNN
+F 3 "" H 3000 3550 60  0000 C CNN
+	4    3000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30  0000 C CNN
+F 1 "PORT" H 6750 3350 30  0000 C CNN
+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub
index bf20b628..8663f37e 100644
--- a/src/SubcircuitLibrary/74153/4_and.sub
+++ b/src/SubcircuitLibrary/74153/4_and.sub
@@ -1,12 +1,12 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib
index 4f81c933..1e85854e 100644
--- a/src/SubcircuitLibrary/74153/74153-cache.lib
+++ b/src/SubcircuitLibrary/74153/74153-cache.lib
@@ -4,40 +4,40 @@ EESchema-LIBRARY Version 2.3
 # 4_OR
 #
 DEF 4_OR X 0 40 Y Y 1 F N
-F0 "X" 150 -100 60 H V C CNN
-F1 "4_OR" 150 100 60 H V C CNN
+F0 "X" 3900 3050 60 H V C CNN
+F1 "4_OR" 3900 3250 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
-A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
-A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
-A -30 -99 393 627 146 0 1 0 N 150 250 350 0
-P 2 0 1 0 -200 -250 150 -250 N
-P 2 0 1 0 -200 250 150 250 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X in4 4 -350 -150 200 R 50 50 1 1 I
-X out 5 550 0 200 L 50 50 1 1 O
+A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900
+A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150
+A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150
+P 2 0 1 0  3550 2900  3900 2900 N
+P 2 0 1 0  3550 3400  3900 3400 N
+X in1 1 3400 3300 200 R 50 50 1 1 I
+X in2 2 3400 3200 200 R 50 50 1 1 I
+X in3 3 3400 3100 200 R 50 50 1 1 I
+X in4 4 3400 3000 200 R 50 50 1 1 I
+X out 5 4300 3150 200 L 50 50 1 1 O
 ENDDRAW
 ENDDEF
 #
 # 4_and
 #
 DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 50 -50 60 H V C CNN
-F1 "4_and" 100 100 60 H V C CNN
+F0 "X" 1500 1050 60 H V C CNN
+F1 "4_and" 1550 1200 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
-A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
-P 2 0 1 0 -200 200 150 200 N
-P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
-X in1 1 -400 150 200 R 50 50 1 1 I
-X in2 2 -400 50 200 R 50 50 1 1 I
-X in3 3 -400 -50 200 R 50 50 1 1 I
-X in4 4 -400 -150 200 R 50 50 1 1 I
-X out 5 500 0 200 L 50 50 1 1 O
+A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
+P 2 0 1 0  1250 1300  1600 1300 N
+P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
+X in1 1 1050 1250 200 R 50 50 1 1 I
+X in2 2 1050 1150 200 R 50 50 1 1 I
+X in3 3 1050 1050 200 R 50 50 1 1 I
+X in4 4 1050 950 200 R 50 50 1 1 I
+X out 5 1950 1100 200 L 50 50 1 1 O
 ENDDRAW
 ENDDEF
 #
@@ -89,7 +89,7 @@ F1 "d_inverter" 0 150 60 H V C CNN
 F2 "" 50 -50 60 H V C CNN
 F3 "" 50 -50 60 H V C CNN
 DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
 X ~ 1 -300 0 200 R 50 50 1 1 I
 X ~ 2 300 0 200 L 50 50 1 1 O I
 ENDDRAW
diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir
index 955b30b1..b20e6858 100644
--- a/src/SubcircuitLibrary/74153/74153.cir
+++ b/src/SubcircuitLibrary/74153/74153.cir
@@ -1,25 +1,25 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74153/74153.cir
+* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir
 
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 26 15:19:41 2019
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
 * Sheet Name: /
-U2  Net-_U1-Pad14_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT		
-U35  Net-_U1-Pad1_ Net-_U35-Pad2_ d_inverter		
-U34  Net-_U1-Pad15_ Net-_U34-Pad2_ d_inverter		
-X8  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and		
-X9  Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and		
-X4  Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and		
-X10  Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and		
-X5  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad10_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and		
-X6  Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad11_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and		
-X3  Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad12_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and		
-X7  Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad13_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and		
-X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad9_ 4_OR		
-X2  Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad7_ 4_OR		
+U2  Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+U35  Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter		
+U34  Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter		
+X8  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and		
+X9  Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and		
+X4  Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and		
+X10  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and		
+X5  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and		
+X6  Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and		
+X3  Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and		
+X7  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and		
+X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR		
+X2  Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR		
 
 .end
diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out
index 93b8fdd1..c95e5ad9 100644
--- a/src/SubcircuitLibrary/74153/74153.cir.out
+++ b/src/SubcircuitLibrary/74153/74153.cir.out
@@ -1,26 +1,26 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir
+* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir
 
 .include 4_and.sub
 .include 4_OR.sub
-* u2  net-_u1-pad14_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-* u35  net-_u1-pad1_ net-_u35-pad2_ d_inverter
-* u34  net-_u1-pad15_ net-_u34-pad2_ d_inverter
-x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and
-x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and
-x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and
-x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and
-x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and
-x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and
-x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and
-x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR
-x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR
-a1 net-_u1-pad14_ net-_u2-pad2_ u2
-a2 net-_u1-pad2_ net-_u3-pad2_ u3
-a3 net-_u1-pad1_ net-_u35-pad2_ u35
-a4 net-_u1-pad15_ net-_u34-pad2_ u34
+* u2  net-_u1-pad12_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u35  net-_u1-pad5_ net-_u35-pad2_ d_inverter
+* u34  net-_u1-pad10_ net-_u34-pad2_ d_inverter
+x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and
+x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and
+x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and
+x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and
+x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and
+x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and
+x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and
+x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR
+x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR
+a1 net-_u1-pad12_ net-_u2-pad2_ u2
+a2 net-_u1-pad11_ net-_u3-pad2_ u3
+a3 net-_u1-pad5_ net-_u35-pad2_ u35
+a4 net-_u1-pad10_ net-_u34-pad2_ u34
 * Schematic Name: d_inverter, NgSpice Name: d_inverter
 .model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
 * Schematic Name: d_inverter, NgSpice Name: d_inverter
@@ -29,7 +29,7 @@ a4 net-_u1-pad15_ net-_u34-pad2_ u34
 .model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
 * Schematic Name: d_inverter, NgSpice Name: d_inverter
 .model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-03 0e-00 0e-03
+.tran 0e-00 0e-00 0e-00
 
 * Control Statements 
 .control
diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro
index 78440d11..ed8b8bf2 100644
--- a/src/SubcircuitLibrary/74153/74153.pro
+++ b/src/SubcircuitLibrary/74153/74153.pro
@@ -1,4 +1,4 @@
-update=Tue Jun 25 16:51:16 2019
+update=03/28/19 23:27:36
 version=1
 last_client=eeschema
 [general]
@@ -29,15 +29,31 @@ version=1
 NetIExt=net
 [eeschema]
 version=1
-LibDir=../../../kicadSchematicLibrary
+LibDir=
 [eeschema/libraries]
-LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
+LibName1=power
+LibName2=device
+LibName3=texas
+LibName4=intel
+LibName5=audio
+LibName6=interface
+LibName7=digital-audio
+LibName8=philips
+LibName9=display
+LibName10=cypress
+LibName11=siliconi
+LibName12=opto
+LibName13=atmel
+LibName14=contrib
+LibName15=valves
+LibName16=eSim_Analog
+LibName17=eSim_Devices
+LibName18=eSim_Digital
+LibName19=eSim_Hybrid
+LibName20=eSim_Miscellaneous
+LibName21=eSim_Plot
+LibName22=eSim_Power
+LibName23=eSim_PSpice
+LibName24=eSim_Sources
+LibName25=eSim_User
+LibName26=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch
index fc9b4516..e0bcf950 100644
--- a/src/SubcircuitLibrary/74153/74153.sch
+++ b/src/SubcircuitLibrary/74153/74153.sch
@@ -1,4 +1,19 @@
 EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
 LIBS:eSim_Analog
 LIBS:eSim_Devices
 LIBS:eSim_Digital
@@ -6,9 +21,10 @@ LIBS:eSim_Hybrid
 LIBS:eSim_Miscellaneous
 LIBS:eSim_Plot
 LIBS:eSim_Power
+LIBS:eSim_PSpice
 LIBS:eSim_Sources
-LIBS:eSim_Subckt
 LIBS:eSim_User
+LIBS:eSim_Subckt
 LIBS:74153-cache
 EELAYER 25 0
 EELAYER END
@@ -48,156 +64,156 @@ F 3 "" H 2750 900 60  0000 C CNN
 $EndComp
 $Comp
 L PORT U1
-U 6 1 5C93A0F9
+U 1 1 5C93A0F9
 P 1350 2050
 F 0 "U1" H 1400 2150 30  0000 C CNN
 F 1 "PORT" H 1350 2050 30  0000 C CNN
 F 2 "" H 1350 2050 60  0000 C CNN
 F 3 "" H 1350 2050 60  0000 C CNN
-	6    1350 2050
+	1    1350 2050
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 10 1 5C93A174
+U 6 1 5C93A174
 P 1350 4700
 F 0 "U1" H 1400 4800 30  0000 C CNN
 F 1 "PORT" H 1350 4700 30  0000 C CNN
 F 2 "" H 1350 4700 60  0000 C CNN
 F 3 "" H 1350 4700 60  0000 C CNN
-	10   1350 4700
+	6    1350 4700
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 5 1 5C93AA3C
+U 2 1 5C93AA3C
 P 1350 2600
 F 0 "U1" H 1400 2700 30  0000 C CNN
 F 1 "PORT" H 1350 2600 30  0000 C CNN
 F 2 "" H 1350 2600 60  0000 C CNN
 F 3 "" H 1350 2600 60  0000 C CNN
-	5    1350 2600
+	2    1350 2600
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 4 1 5C93AACB
+U 3 1 5C93AACB
 P 1350 3200
 F 0 "U1" H 1400 3300 30  0000 C CNN
 F 1 "PORT" H 1350 3200 30  0000 C CNN
 F 2 "" H 1350 3200 60  0000 C CNN
 F 3 "" H 1350 3200 60  0000 C CNN
-	4    1350 3200
+	3    1350 3200
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 3 1 5C93AB5F
+U 4 1 5C93AB5F
 P 1350 3700
 F 0 "U1" H 1400 3800 30  0000 C CNN
 F 1 "PORT" H 1350 3700 30  0000 C CNN
 F 2 "" H 1350 3700 60  0000 C CNN
 F 3 "" H 1350 3700 60  0000 C CNN
-	3    1350 3700
+	4    1350 3700
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 11 1 5C93AD97
+U 7 1 5C93AD97
 P 1350 5250
 F 0 "U1" H 1400 5350 30  0000 C CNN
 F 1 "PORT" H 1350 5250 30  0000 C CNN
 F 2 "" H 1350 5250 60  0000 C CNN
 F 3 "" H 1350 5250 60  0000 C CNN
-	11   1350 5250
+	7    1350 5250
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 12 1 5C93ADFC
+U 8 1 5C93ADFC
 P 1350 5850
 F 0 "U1" H 1400 5950 30  0000 C CNN
 F 1 "PORT" H 1350 5850 30  0000 C CNN
 F 2 "" H 1350 5850 60  0000 C CNN
 F 3 "" H 1350 5850 60  0000 C CNN
-	12   1350 5850
+	8    1350 5850
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 13 1 5C93AE63
+U 9 1 5C93AE63
 P 1350 6350
 F 0 "U1" H 1400 6450 30  0000 C CNN
 F 1 "PORT" H 1350 6350 30  0000 C CNN
 F 2 "" H 1350 6350 60  0000 C CNN
 F 3 "" H 1350 6350 60  0000 C CNN
-	13   1350 6350
+	9    1350 6350
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 $EndComp
 $Comp
 L PORT U1
-U 1 1 5C93AECA
+U 5 1 5C93AECA
 P 1350 3950
 F 0 "U1" H 1400 4050 30  0000 C CNN
 F 1 "PORT" H 1350 3950 30  0000 C CNN
 F 2 "" H 1350 3950 60  0000 C CNN
 F 3 "" H 1350 3950 60  0000 C CNN
-	1    1350 3950
+	5    1350 3950
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 $EndComp
 $Comp
 L PORT U1
-U 15 1 5C93AF79
+U 10 1 5C93AF79
 P 1350 6600
 F 0 "U1" H 1400 6700 30  0000 C CNN
 F 1 "PORT" H 1350 6600 30  0000 C CNN
 F 2 "" H 1350 6600 60  0000 C CNN
 F 3 "" H 1350 6600 60  0000 C CNN
-	15   1350 6600
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 $EndComp
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 L PORT U1
-U 2 1 5C93B10A
+U 11 1 5C93B10A
 P 1550 950
 F 0 "U1" H 1600 1050 30  0000 C CNN
 F 1 "PORT" H 1550 950 30  0000 C CNN
 F 2 "" H 1550 950 60  0000 C CNN
 F 3 "" H 1550 950 60  0000 C CNN
-	2    1550 950 
+	11   1550 950 
 	1    0    0    -1  
 $EndComp
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 L PORT U1
-U 14 1 5C93B179
+U 12 1 5C93B179
 P 1550 1350
 F 0 "U1" H 1600 1450 30  0000 C CNN
 F 1 "PORT" H 1550 1350 30  0000 C CNN
 F 2 "" H 1550 1350 60  0000 C CNN
 F 3 "" H 1550 1350 60  0000 C CNN
-	14   1550 1350
+	12   1550 1350
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 7 1 5C93B567
+U 13 1 5C93B567
 P 7850 2600
 F 0 "U1" H 7900 2700 30  0000 C CNN
 F 1 "PORT" H 7850 2600 30  0000 C CNN
 F 2 "" H 7850 2600 60  0000 C CNN
 F 3 "" H 7850 2600 60  0000 C CNN
-	7    7850 2600
+	13   7850 2600
 	-1   0    0    1   
 $EndComp
 $Comp
 L PORT U1
-U 9 1 5C93B5DA
+U 14 1 5C93B5DA
 P 7900 5250
 F 0 "U1" H 7950 5350 30  0000 C CNN
 F 1 "PORT" H 7900 5250 30  0000 C CNN
 F 2 "" H 7900 5250 60  0000 C CNN
 F 3 "" H 7900 5250 60  0000 C CNN
-	9    7900 5250
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 	-1   0    0    1   
 $EndComp
 $Comp
@@ -253,89 +269,89 @@ YB
 $Comp
 L 4_and X8
 U 1 1 5C9D0C22
-P 4200 1950
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-F 1 "4_and" H 4300 2050 60  0000 C CNN
-F 2 "" H 4200 1950 60  0000 C CNN
-F 3 "" H 4200 1950 60  0000 C CNN
-	1    4200 1950
+P 2750 3050
+F 0 "X8" H 4250 4100 60  0000 C CNN
+F 1 "4_and" H 4300 4250 60  0000 C CNN
+F 2 "" H 2750 3050 60  0000 C CNN
+F 3 "" H 2750 3050 60  0000 C CNN
+	1    2750 3050
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X9
 U 1 1 5C9D0CA2
-P 4200 2500
-F 0 "X9" H 4250 2500 60  0000 C CNN
-F 1 "4_and" H 4300 2600 60  0000 C CNN
-F 2 "" H 4200 2500 60  0000 C CNN
-F 3 "" H 4200 2500 60  0000 C CNN
-	1    4200 2500
+P 2750 3600
+F 0 "X9" H 4250 4650 60  0000 C CNN
+F 1 "4_and" H 4300 4800 60  0000 C CNN
+F 2 "" H 2750 3600 60  0000 C CNN
+F 3 "" H 2750 3600 60  0000 C CNN
+	1    2750 3600
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X4
 U 1 1 5C9D0D16
-P 4150 3100
-F 0 "X4" H 4200 3100 60  0000 C CNN
-F 1 "4_and" H 4250 3200 60  0000 C CNN
-F 2 "" H 4150 3100 60  0000 C CNN
-F 3 "" H 4150 3100 60  0000 C CNN
-	1    4150 3100
+P 2700 4200
+F 0 "X4" H 4200 5250 60  0000 C CNN
+F 1 "4_and" H 4250 5400 60  0000 C CNN
+F 2 "" H 2700 4200 60  0000 C CNN
+F 3 "" H 2700 4200 60  0000 C CNN
+	1    2700 4200
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X10
 U 1 1 5C9D0D93
-P 4200 3600
-F 0 "X10" H 4250 3600 60  0000 C CNN
-F 1 "4_and" H 4300 3700 60  0000 C CNN
-F 2 "" H 4200 3600 60  0000 C CNN
-F 3 "" H 4200 3600 60  0000 C CNN
-	1    4200 3600
+P 2750 4700
+F 0 "X10" H 4250 5750 60  0000 C CNN
+F 1 "4_and" H 4300 5900 60  0000 C CNN
+F 2 "" H 2750 4700 60  0000 C CNN
+F 3 "" H 2750 4700 60  0000 C CNN
+	1    2750 4700
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X5
 U 1 1 5C9D182A
-P 4150 4600
-F 0 "X5" H 4200 4600 60  0000 C CNN
-F 1 "4_and" H 4250 4700 60  0000 C CNN
-F 2 "" H 4150 4600 60  0000 C CNN
-F 3 "" H 4150 4600 60  0000 C CNN
-	1    4150 4600
+P 2700 5700
+F 0 "X5" H 4200 6750 60  0000 C CNN
+F 1 "4_and" H 4250 6900 60  0000 C CNN
+F 2 "" H 2700 5700 60  0000 C CNN
+F 3 "" H 2700 5700 60  0000 C CNN
+	1    2700 5700
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X6
 U 1 1 5C9D1830
-P 4150 5150
-F 0 "X6" H 4200 5150 60  0000 C CNN
-F 1 "4_and" H 4250 5250 60  0000 C CNN
-F 2 "" H 4150 5150 60  0000 C CNN
-F 3 "" H 4150 5150 60  0000 C CNN
-	1    4150 5150
+P 2700 6250
+F 0 "X6" H 4200 7300 60  0000 C CNN
+F 1 "4_and" H 4250 7450 60  0000 C CNN
+F 2 "" H 2700 6250 60  0000 C CNN
+F 3 "" H 2700 6250 60  0000 C CNN
+	1    2700 6250
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X3
 U 1 1 5C9D1836
-P 4100 5750
-F 0 "X3" H 4150 5750 60  0000 C CNN
-F 1 "4_and" H 4200 5850 60  0000 C CNN
-F 2 "" H 4100 5750 60  0000 C CNN
-F 3 "" H 4100 5750 60  0000 C CNN
-	1    4100 5750
+P 2650 6850
+F 0 "X3" H 4150 7900 60  0000 C CNN
+F 1 "4_and" H 4200 8050 60  0000 C CNN
+F 2 "" H 2650 6850 60  0000 C CNN
+F 3 "" H 2650 6850 60  0000 C CNN
+	1    2650 6850
 	1    0    0    -1  
 $EndComp
 $Comp
 L 4_and X7
 U 1 1 5C9D183C
-P 4150 6250
-F 0 "X7" H 4200 6250 60  0000 C CNN
-F 1 "4_and" H 4250 6350 60  0000 C CNN
-F 2 "" H 4150 6250 60  0000 C CNN
-F 3 "" H 4150 6250 60  0000 C CNN
-	1    4150 6250
+P 2700 7350
+F 0 "X7" H 4200 8400 60  0000 C CNN
+F 1 "4_and" H 4250 8550 60  0000 C CNN
+F 2 "" H 2700 7350 60  0000 C CNN
+F 3 "" H 2700 7350 60  0000 C CNN
+	1    2700 7350
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
@@ -498,12 +514,12 @@ Wire Wire Line
 $Comp
 L 4_OR X1
 U 1 1 5C9D22F7
-P 5900 5250
-F 0 "X1" H 6000 5250 60  0000 C CNN
-F 1 "4_OR" H 6050 5350 60  0000 C CNN
-F 2 "" H 5900 5250 60  0000 C CNN
-F 3 "" H 5900 5250 60  0000 C CNN
-	1    5900 5250
+P 2150 8400
+F 0 "X1" H 6050 11450 60  0000 C CNN
+F 1 "4_OR" H 6050 11650 60  0000 C CNN
+F 2 "" H 2150 8400 60  0000 C CNN
+F 3 "" H 2150 8400 60  0000 C CNN
+	1    2150 8400
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
@@ -525,12 +541,12 @@ Wire Wire Line
 $Comp
 L 4_OR X2
 U 1 1 5C9D28DE
-P 6000 2600
-F 0 "X2" H 6100 2600 60  0000 C CNN
-F 1 "4_OR" H 6150 2700 60  0000 C CNN
-F 2 "" H 6000 2600 60  0000 C CNN
-F 3 "" H 6000 2600 60  0000 C CNN
-	1    6000 2600
+P 2250 5750
+F 0 "X2" H 6150 8800 60  0000 C CNN
+F 1 "4_OR" H 6150 9000 60  0000 C CNN
+F 2 "" H 2250 5750 60  0000 C CNN
+F 3 "" H 2250 5750 60  0000 C CNN
+	1    2250 5750
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
@@ -549,28 +565,4 @@ Wire Wire Line
 	4700 3600 4700 2750
 Wire Wire Line
 	4700 2750 5650 2750
-$Comp
-L PORT U1
-U 16 1 5D11F8AE
-P 7450 1200
-F 0 "U1" H 7500 1300 30  0000 C CNN
-F 1 "PORT" H 7450 1200 30  0000 C CNN
-F 2 "" H 7450 1200 60  0000 C CNN
-F 3 "" H 7450 1200 60  0000 C CNN
-	16   7450 1200
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5D11F97A
-P 7400 1550
-F 0 "U1" H 7450 1650 30  0000 C CNN
-F 1 "PORT" H 7400 1550 30  0000 C CNN
-F 2 "" H 7400 1550 60  0000 C CNN
-F 3 "" H 7400 1550 60  0000 C CNN
-	8    7400 1550
-	-1   0    0    1   
-$EndComp
-NoConn ~ 7200 1200
-NoConn ~ 7150 1550
 $EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub
index 0bbdea00..6e00261f 100644
--- a/src/SubcircuitLibrary/74153/74153.sub
+++ b/src/SubcircuitLibrary/74153/74153.sub
@@ -1,26 +1,26 @@
 * Subcircuit 74153
-.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir
+.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir
 .include 4_and.sub
 .include 4_OR.sub
-* u2  net-_u1-pad14_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u35  net-_u1-pad1_ net-_u35-pad2_ d_inverter
-* u34  net-_u1-pad15_ net-_u34-pad2_ d_inverter
-x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and
-x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and
-x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and
-x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and
-x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and
-x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and
-x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and
-x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR
-x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR
-a1 net-_u1-pad14_ net-_u2-pad2_ u2
-a2 net-_u1-pad2_ net-_u3-pad2_ u3
-a3 net-_u1-pad1_ net-_u35-pad2_ u35
-a4 net-_u1-pad15_ net-_u34-pad2_ u34
+* u2  net-_u1-pad12_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad11_ net-_u3-pad2_ d_inverter
+* u35  net-_u1-pad5_ net-_u35-pad2_ d_inverter
+* u34  net-_u1-pad10_ net-_u34-pad2_ d_inverter
+x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and
+x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and
+x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and
+x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and
+x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and
+x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and
+x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and
+x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and
+x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR
+x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR
+a1 net-_u1-pad12_ net-_u2-pad2_ u2
+a2 net-_u1-pad11_ net-_u3-pad2_ u3
+a3 net-_u1-pad5_ net-_u35-pad2_ u35
+a4 net-_u1-pad10_ net-_u34-pad2_ u34
 * Schematic Name: d_inverter, NgSpice Name: d_inverter
 .model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
 * Schematic Name: d_inverter, NgSpice Name: d_inverter
diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml
index 028f2d75..ea70e6f3 100644
--- a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml
+++ b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR</field></x2><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x9><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x10><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
+<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib
index 32c8b38f..10496d63 100644
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib
+++ b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib
@@ -1,94 +1,94 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir
index 5dddad23..583c4a00 100644
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir
+++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir
@@ -1,45 +1,45 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U14  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and		
-U25  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and		
-U5  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and		
-U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and		
-U7  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and		
-U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and		
-U18  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and		
-U24  Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and		
-U28  Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or		
-U29  Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or		
-U32  Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or		
-U2  Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter		
-U3  Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter		
-U15  Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and		
-U6  Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and		
-U8  Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and		
-U4  Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and		
-U16  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and		
-U27  Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and		
-U10  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and		
-U22  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and		
-U12  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and		
-U23  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and		
-U19  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and		
-U26  Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and		
-U30  Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or		
-U31  Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or		
-U33  Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or		
-U17  Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and		
-U11  Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
-U13  Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
-U9  Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-U34  Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter		
-U35  Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U14  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and		
+U25  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and		
+U5  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and		
+U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and		
+U7  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and		
+U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and		
+U18  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and		
+U24  Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and		
+U28  Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or		
+U29  Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or		
+U32  Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or		
+U2  Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter		
+U3  Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter		
+U15  Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and		
+U6  Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and		
+U8  Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and		
+U4  Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and		
+U16  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and		
+U27  Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and		
+U10  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and		
+U22  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and		
+U12  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and		
+U23  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and		
+U19  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and		
+U26  Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and		
+U30  Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or		
+U31  Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or		
+U33  Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or		
+U17  Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and		
+U11  Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
+U13  Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
+U9  Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+U34  Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter		
+U35  Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter		
+
+.end
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch
index bb19bb7d..340b1a31 100644
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch
+++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch
@@ -1,814 +1,814 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:74153-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-F 2 "" H 1350 3950 60  0000 C CNN
-F 3 "" H 1350 3950 60  0000 C CNN
-	5    1350 3950
-	1    0    0    -1  
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-P 1350 6600
-F 0 "U1" H 1400 6700 30  0000 C CNN
-F 1 "PORT" H 1350 6600 30  0000 C CNN
-F 2 "" H 1350 6600 60  0000 C CNN
-F 3 "" H 1350 6600 60  0000 C CNN
-	10   1350 6600
-	1    0    0    -1  
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-P 1550 950
-F 0 "U1" H 1600 1050 30  0000 C CNN
-F 1 "PORT" H 1550 950 30  0000 C CNN
-F 2 "" H 1550 950 60  0000 C CNN
-F 3 "" H 1550 950 60  0000 C CNN
-	11   1550 950 
-	1    0    0    -1  
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-P 1550 1350
-F 0 "U1" H 1600 1450 30  0000 C CNN
-F 1 "PORT" H 1550 1350 30  0000 C CNN
-F 2 "" H 1550 1350 60  0000 C CNN
-F 3 "" H 1550 1350 60  0000 C CNN
-	12   1550 1350
-	1    0    0    -1  
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-Wire Wire Line
-	7300 5250 7650 5250
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-U 13 1 5C93B567
-P 7850 2600
-F 0 "U1" H 7900 2700 30  0000 C CNN
-F 1 "PORT" H 7850 2600 30  0000 C CNN
-F 2 "" H 7850 2600 60  0000 C CNN
-F 3 "" H 7850 2600 60  0000 C CNN
-	13   7850 2600
-	-1   0    0    1   
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-P 7900 5250
-F 0 "U1" H 7950 5350 30  0000 C CNN
-F 1 "PORT" H 7900 5250 30  0000 C CNN
-F 2 "" H 7900 5250 60  0000 C CNN
-F 3 "" H 7900 5250 60  0000 C CNN
-	14   7900 5250
-	-1   0    0    1   
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-Wire Wire Line
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-Wire Wire Line
-	3400 5000 2300 5000
-Connection ~ 2300 5000
-Wire Wire Line
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-Wire Wire Line
-	2200 5700 3350 5700
-Wire Wire Line
-	2200 6200 3350 6200
-Connection ~ 2200 5700
-Wire Wire Line
-	2300 6100 3350 6100
-Wire Wire Line
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-Connection ~ 3200 2450
-Wire Wire Line
-	3400 2350 2300 2350
-Connection ~ 2300 2350
-Wire Wire Line
-	3350 3050 2200 3050
-Connection ~ 2200 3050
-Wire Wire Line
-	3350 2950 3100 2950
-Connection ~ 3100 2950
-Wire Wire Line
-	3350 3450 2300 3450
-Wire Wire Line
-	2300 3450 2300 3400
-Connection ~ 2300 3400
-Wire Wire Line
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-Connection ~ 2200 3550
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-L d_inverter U34
-U 1 1 5C95C9D0
-P 2650 3950
-F 0 "U34" H 2650 3850 60  0000 C CNN
-F 1 "d_inverter" H 2650 4100 60  0000 C CNN
-F 2 "" H 2700 3900 60  0000 C CNN
-F 3 "" H 2700 3900 60  0000 C CNN
-	1    2650 3950
-	1    0    0    -1  
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-L d_inverter U35
-U 1 1 5C95CD17
-P 2700 6600
-F 0 "U35" H 2700 6500 60  0000 C CNN
-F 1 "d_inverter" H 2700 6750 60  0000 C CNN
-F 2 "" H 2750 6550 60  0000 C CNN
-F 3 "" H 2750 6550 60  0000 C CNN
-	1    2700 6600
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
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+LIBS:device
+LIBS:texas
+LIBS:intel
+LIBS:audio
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+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
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+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
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+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
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+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
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+Comment2 ""
+Comment3 ""
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+$EndDescr
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+P 3850 2450
+F 0 "U14" H 3850 2450 60  0000 C CNN
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+F 2 "" H 3850 2450 60  0000 C CNN
+F 3 "" H 3850 2450 60  0000 C CNN
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+F 2 "" H 4850 2600 60  0000 C CNN
+F 3 "" H 4850 2600 60  0000 C CNN
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+F 2 "" H 3800 3050 60  0000 C CNN
+F 3 "" H 3800 3050 60  0000 C CNN
+	1    3800 3050
+	1    0    0    -1  
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+L d_and U20
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+F 0 "U20" H 4800 3200 60  0000 C CNN
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+F 2 "" H 4800 3200 60  0000 C CNN
+F 3 "" H 4800 3200 60  0000 C CNN
+	1    4800 3200
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+F 2 "" H 3800 3550 60  0000 C CNN
+F 3 "" H 3800 3550 60  0000 C CNN
+	1    3800 3550
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+F 2 "" H 4800 3700 60  0000 C CNN
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+F 2 "" H 3950 1900 60  0000 C CNN
+F 3 "" H 3950 1900 60  0000 C CNN
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+F 2 "" H 4850 2150 60  0000 C CNN
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+F 2 "" H 5900 2550 60  0000 C CNN
+F 3 "" H 5900 2550 60  0000 C CNN
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+F 2 "" H 5900 2800 60  0000 C CNN
+F 3 "" H 5900 2800 60  0000 C CNN
+	1    5900 2800
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+F 2 "" H 6850 2650 60  0000 C CNN
+F 3 "" H 6850 2650 60  0000 C CNN
+	1    6850 2650
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+$EndComp
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+	4400 2500 4400 2400
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+L d_inverter U2
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+F 2 "" H 2700 1300 60  0000 C CNN
+F 3 "" H 2700 1300 60  0000 C CNN
+	1    2650 1350
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+L d_inverter U3
+U 1 1 5C93798D
+P 2700 950
+F 0 "U3" H 2700 850 60  0000 C CNN
+F 1 "d_inverter" H 2700 1100 60  0000 C CNN
+F 2 "" H 2750 900 60  0000 C CNN
+F 3 "" H 2750 900 60  0000 C CNN
+	1    2700 950 
+	1    0    0    -1  
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	1800 950  2400 950 
+Wire Wire Line
+	1800 1350 2350 1350
+Wire Wire Line
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+Connection ~ 2200 950 
+Wire Wire Line
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+L d_and U15
+U 1 1 5C937C96
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+F 0 "U15" H 3850 2700 60  0000 C CNN
+F 1 "d_and" H 3900 2800 60  0000 C CNN
+F 2 "" H 3850 2700 60  0000 C CNN
+F 3 "" H 3850 2700 60  0000 C CNN
+	1    3850 2700
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+F 0 "U6" H 3800 3300 60  0000 C CNN
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+F 2 "" H 3800 3300 60  0000 C CNN
+F 3 "" H 3800 3300 60  0000 C CNN
+	1    3800 3300
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+F 0 "U8" H 3800 3800 60  0000 C CNN
+F 1 "d_and" H 3850 3900 60  0000 C CNN
+F 2 "" H 3800 3800 60  0000 C CNN
+F 3 "" H 3800 3800 60  0000 C CNN
+	1    3800 3800
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+L d_and U4
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+F 2 "" H 3800 2150 60  0000 C CNN
+F 3 "" H 3800 2150 60  0000 C CNN
+	1    3800 2150
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+Wire Wire Line
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+Wire Wire Line
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+	3350 2050 1600 2050
+Wire Wire Line
+	3000 3950 3000 3800
+Wire Wire Line
+	2950 3950 3000 3950
+Wire Wire Line
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+L d_and U16
+U 1 1 5C9388D0
+P 3850 5100
+F 0 "U16" H 3850 5100 60  0000 C CNN
+F 1 "d_and" H 3900 5200 60  0000 C CNN
+F 2 "" H 3850 5100 60  0000 C CNN
+F 3 "" H 3850 5100 60  0000 C CNN
+	1    3850 5100
+	1    0    0    -1  
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+L d_and U27
+U 1 1 5C9388D6
+P 4850 5250
+F 0 "U27" H 4850 5250 60  0000 C CNN
+F 1 "d_and" H 4900 5350 60  0000 C CNN
+F 2 "" H 4850 5250 60  0000 C CNN
+F 3 "" H 4850 5250 60  0000 C CNN
+	1    4850 5250
+	1    0    0    -1  
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+L d_and U10
+U 1 1 5C9388DC
+P 3800 5700
+F 0 "U10" H 3800 5700 60  0000 C CNN
+F 1 "d_and" H 3850 5800 60  0000 C CNN
+F 2 "" H 3800 5700 60  0000 C CNN
+F 3 "" H 3800 5700 60  0000 C CNN
+	1    3800 5700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U22
+U 1 1 5C9388E2
+P 4800 5850
+F 0 "U22" H 4800 5850 60  0000 C CNN
+F 1 "d_and" H 4850 5950 60  0000 C CNN
+F 2 "" H 4800 5850 60  0000 C CNN
+F 3 "" H 4800 5850 60  0000 C CNN
+	1    4800 5850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U12
+U 1 1 5C9388E8
+P 3800 6200
+F 0 "U12" H 3800 6200 60  0000 C CNN
+F 1 "d_and" H 3850 6300 60  0000 C CNN
+F 2 "" H 3800 6200 60  0000 C CNN
+F 3 "" H 3800 6200 60  0000 C CNN
+	1    3800 6200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U23
+U 1 1 5C9388EE
+P 4800 6350
+F 0 "U23" H 4800 6350 60  0000 C CNN
+F 1 "d_and" H 4850 6450 60  0000 C CNN
+F 2 "" H 4800 6350 60  0000 C CNN
+F 3 "" H 4800 6350 60  0000 C CNN
+	1    4800 6350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5C9388F4
+P 3950 4550
+F 0 "U19" H 3950 4550 60  0000 C CNN
+F 1 "d_and" H 4000 4650 60  0000 C CNN
+F 2 "" H 3950 4550 60  0000 C CNN
+F 3 "" H 3950 4550 60  0000 C CNN
+	1    3950 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U26
+U 1 1 5C9388FA
+P 4850 4800
+F 0 "U26" H 4850 4800 60  0000 C CNN
+F 1 "d_and" H 4900 4900 60  0000 C CNN
+F 2 "" H 4850 4800 60  0000 C CNN
+F 3 "" H 4850 4800 60  0000 C CNN
+	1    4850 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U30
+U 1 1 5C938900
+P 5900 5200
+F 0 "U30" H 5900 5200 60  0000 C CNN
+F 1 "d_or" H 5900 5300 60  0000 C CNN
+F 2 "" H 5900 5200 60  0000 C CNN
+F 3 "" H 5900 5200 60  0000 C CNN
+	1    5900 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U31
+U 1 1 5C938906
+P 5900 5450
+F 0 "U31" H 5900 5450 60  0000 C CNN
+F 1 "d_or" H 5900 5550 60  0000 C CNN
+F 2 "" H 5900 5450 60  0000 C CNN
+F 3 "" H 5900 5450 60  0000 C CNN
+	1    5900 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U33
+U 1 1 5C93890C
+P 6850 5300
+F 0 "U33" H 6850 5300 60  0000 C CNN
+F 1 "d_or" H 6850 5400 60  0000 C CNN
+F 2 "" H 6850 5300 60  0000 C CNN
+F 3 "" H 6850 5300 60  0000 C CNN
+	1    6850 5300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+L d_and U17
+U 1 1 5C938937
+P 3850 5350
+F 0 "U17" H 3850 5350 60  0000 C CNN
+F 1 "d_and" H 3900 5450 60  0000 C CNN
+F 2 "" H 3850 5350 60  0000 C CNN
+F 3 "" H 3850 5350 60  0000 C CNN
+	1    3850 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U11
+U 1 1 5C93893D
+P 3800 5950
+F 0 "U11" H 3800 5950 60  0000 C CNN
+F 1 "d_and" H 3850 6050 60  0000 C CNN
+F 2 "" H 3800 5950 60  0000 C CNN
+F 3 "" H 3800 5950 60  0000 C CNN
+	1    3800 5950
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+$EndComp
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+L d_and U13
+U 1 1 5C938943
+P 3800 6450
+F 0 "U13" H 3800 6450 60  0000 C CNN
+F 1 "d_and" H 3850 6550 60  0000 C CNN
+F 2 "" H 3800 6450 60  0000 C CNN
+F 3 "" H 3800 6450 60  0000 C CNN
+	1    3800 6450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U9
+U 1 1 5C938949
+P 3800 4800
+F 0 "U9" H 3800 4800 60  0000 C CNN
+F 1 "d_and" H 3850 4900 60  0000 C CNN
+F 2 "" H 3800 4800 60  0000 C CNN
+F 3 "" H 3800 4800 60  0000 C CNN
+	1    3800 4800
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+L PORT U1
+U 1 1 5C93A0F9
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+F 0 "U1" H 1400 2150 30  0000 C CNN
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+L PORT U1
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+F 0 "U1" H 1400 4800 30  0000 C CNN
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+F 3 "" H 1350 4700 60  0000 C CNN
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+L PORT U1
+U 2 1 5C93AA3C
+P 1350 2600
+F 0 "U1" H 1400 2700 30  0000 C CNN
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+F 2 "" H 1350 2600 60  0000 C CNN
+F 3 "" H 1350 2600 60  0000 C CNN
+	2    1350 2600
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+$Comp
+L PORT U1
+U 3 1 5C93AACB
+P 1350 3200
+F 0 "U1" H 1400 3300 30  0000 C CNN
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+F 2 "" H 1350 3200 60  0000 C CNN
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+F 3 "" H 1350 3700 60  0000 C CNN
+	4    1350 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+F 1 "PORT" H 1350 5250 30  0000 C CNN
+F 2 "" H 1350 5250 60  0000 C CNN
+F 3 "" H 1350 5250 60  0000 C CNN
+	7    1350 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+F 0 "U1" H 1400 5950 30  0000 C CNN
+F 1 "PORT" H 1350 5850 30  0000 C CNN
+F 2 "" H 1350 5850 60  0000 C CNN
+F 3 "" H 1350 5850 60  0000 C CNN
+	8    1350 5850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C93AE63
+P 1350 6350
+F 0 "U1" H 1400 6450 30  0000 C CNN
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+F 2 "" H 1350 6350 60  0000 C CNN
+F 3 "" H 1350 6350 60  0000 C CNN
+	9    1350 6350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C93AECA
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+F 0 "U1" H 1400 4050 30  0000 C CNN
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+F 3 "" H 1350 3950 60  0000 C CNN
+	5    1350 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C93AF79
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+F 0 "U1" H 1400 6700 30  0000 C CNN
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+F 3 "" H 1350 6600 60  0000 C CNN
+	10   1350 6600
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+$Comp
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+F 3 "" H 1550 950 60  0000 C CNN
+	11   1550 950 
+	1    0    0    -1  
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+F 2 "" H 1550 1350 60  0000 C CNN
+F 3 "" H 1550 1350 60  0000 C CNN
+	12   1550 1350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+F 1 "PORT" H 7850 2600 30  0000 C CNN
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+F 3 "" H 7850 2600 60  0000 C CNN
+	13   7850 2600
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+$Comp
+L PORT U1
+U 14 1 5C93B5DA
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+F 0 "U1" H 7950 5350 30  0000 C CNN
+F 1 "PORT" H 7900 5250 30  0000 C CNN
+F 2 "" H 7900 5250 60  0000 C CNN
+F 3 "" H 7900 5250 60  0000 C CNN
+	14   7900 5250
+	-1   0    0    1   
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+$Comp
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+F 3 "" H 2700 3900 60  0000 C CNN
+	1    2650 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U35
+U 1 1 5C95CD17
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+F 0 "U35" H 2700 6500 60  0000 C CNN
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+F 2 "" H 2750 6550 60  0000 C CNN
+F 3 "" H 2750 6550 60  0000 C CNN
+	1    2700 6600
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis
index 655d30ed..ebd5c0a9 100644
--- a/src/SubcircuitLibrary/74153/analysis
+++ b/src/SubcircuitLibrary/74153/analysis
@@ -1 +1 @@
-.tran 0e-03 0e-00 0e-03
\ No newline at end of file
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/74157/3_and-cache.lib
+++ b/src/SubcircuitLibrary/74157/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/74157/3_and.cir
+++ b/src/SubcircuitLibrary/74157/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/74157/3_and.cir.out
+++ b/src/SubcircuitLibrary/74157/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro
index 0fdf4d25..2c9ac554 100644
--- a/src/SubcircuitLibrary/74157/3_and.pro
+++ b/src/SubcircuitLibrary/74157/3_and.pro
@@ -1,44 +1,58 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch
index c853bf49..86be0215 100644
--- a/src/SubcircuitLibrary/74157/3_and.sch
+++ b/src/SubcircuitLibrary/74157/3_and.sch
@@ -1,130 +1,121 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/74157/3_and.sub
+++ b/src/SubcircuitLibrary/74157/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib
index d72d1628..de171255 100644
--- a/src/SubcircuitLibrary/74157/74157-cache.lib
+++ b/src/SubcircuitLibrary/74157/74157-cache.lib
@@ -1,17 +1,17 @@
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
-# 3_and-RESCUE-74157
+# 3_and
 #
-DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N
+DEF 3_and X 0 40 Y Y 1 F N
 F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
 A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
 X in1 1 450 500 200 R 50 50 1 1 I
 X in2 2 450 400 200 R 50 50 1 1 I
 X in3 3 450 300 200 R 50 50 1 1 I
@@ -67,7 +67,7 @@ F1 "d_inverter" 0 150 60 H V C CNN
 F2 "" 50 -50 60 H V C CNN
 F3 "" 50 -50 60 H V C CNN
 DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
 X ~ 1 -300 0 200 R 50 50 1 1 I
 X ~ 2 300 0 200 L 50 50 1 1 O I
 ENDDRAW
@@ -84,8 +84,8 @@ DRAW
 A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
 A -25 -124 325 574 323 0 1 0 N 150 150 250 50
 A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
 X IN1 1 -450 100 215 R 50 50 1 1 I
 X IN2 2 -450 0 215 R 50 50 1 1 I
 X OUT 3 450 50 200 L 50 50 1 1 O
diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir
index cfd1c0e9..6920161c 100644
--- a/src/SubcircuitLibrary/74157/74157.cir
+++ b/src/SubcircuitLibrary/74157/74157.cir
@@ -1,25 +1,25 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74157/74157.cir
+* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir
 
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 20:50:36 2019
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
 * Sheet Name: /
-U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad4_ d_or		
-U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad7_ d_or		
-U22  Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad9_ d_or		
-U23  Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad12_ d_or		
-U3  Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT		
-U2  Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter		
-X2  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad1_ 3_and		
-X3  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U21-Pad1_ 3_and		
-X4  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U22-Pad1_ 3_and		
-X5  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U23-Pad1_ 3_and		
-X6  Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U20-Pad2_ 3_and		
-X7  Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad2_ 3_and		
-X1  Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad10_ Net-_U22-Pad2_ 3_and		
-X8  Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ Net-_U23-Pad2_ 3_and		
+U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or		
+U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or		
+U22  Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or		
+U23  Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or		
+U3  Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+U2  Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter		
+X2  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and		
+X3  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and		
+X4  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and		
+X5  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and		
+X6  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and		
+X7  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and		
+X1  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and		
+X8  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and		
 
 .end
diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out
index b9a19223..3a11a42d 100644
--- a/src/SubcircuitLibrary/74157/74157.cir.out
+++ b/src/SubcircuitLibrary/74157/74157.cir.out
@@ -1,27 +1,27 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir
+* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
 
 .include 3_and.sub
-* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or
-* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or
-* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or
-* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or
-* u3  net-_u1-pad1_ net-_u3-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-* u2  net-_u1-pad15_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23
-a5 net-_u1-pad1_ net-_u3-pad2_ u3
-a6 net-_u1-pad15_ net-_u2-pad2_ u2
+* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
+* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
+* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
+* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
+* u3  net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u2  net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
+x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
+x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
+x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
+x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
+x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
+x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
+x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
+a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
+a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
+a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
+a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
+a5 net-_u1-pad10_ net-_u3-pad2_ u3
+a6 net-_u1-pad9_ net-_u2-pad2_ u2
 * Schematic Name: d_or, NgSpice Name: d_or
 .model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
 * Schematic Name: d_or, NgSpice Name: d_or
diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro
index 4042e1e9..fcbb1fc8 100644
--- a/src/SubcircuitLibrary/74157/74157.pro
+++ b/src/SubcircuitLibrary/74157/74157.pro
@@ -1,4 +1,4 @@
-update=Tue Jun 25 20:59:09 2019
+update=03/28/19 22:30:06
 version=1
 last_client=eeschema
 [general]
@@ -29,16 +29,29 @@ version=1
 NetIExt=net
 [eeschema]
 version=1
-LibDir=../../../kicadSchematicLibrary
+LibDir=
 [eeschema/libraries]
-LibName1=74157-rescue
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
+LibName1=power
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_User
+LibName24=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch
index c7c64ece..7fd3609e 100644
--- a/src/SubcircuitLibrary/74157/74157.sch
+++ b/src/SubcircuitLibrary/74157/74157.sch
@@ -1,5 +1,17 @@
 EESchema Schematic File Version 2
-LIBS:74157-rescue
+LIBS:power
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
 LIBS:eSim_Analog
 LIBS:eSim_Devices
 LIBS:eSim_Digital
@@ -7,9 +19,10 @@ LIBS:eSim_Hybrid
 LIBS:eSim_Miscellaneous
 LIBS:eSim_Plot
 LIBS:eSim_Power
+LIBS:eSim_PSpice
 LIBS:eSim_Sources
-LIBS:eSim_Subckt
 LIBS:eSim_User
+LIBS:eSim_Subckt
 LIBS:74157-cache
 EELAYER 25 0
 EELAYER END
@@ -25,6 +38,34 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
+Wire Wire Line
+	1650 1850 2750 1850
+Wire Wire Line
+	2750 3350 1650 3350
+Wire Wire Line
+	2750 3050 2750 3350
+Wire Wire Line
+	2800 4050 1650 4050
+Wire Wire Line
+	2800 3550 2800 4050
+Wire Wire Line
+	2200 2150 2200 4350
+Wire Wire Line
+	2200 2150 1650 2150
+Wire Wire Line
+	2150 2900 2150 4850
+Wire Wire Line
+	2150 2900 1650 2900
+Wire Wire Line
+	2100 3600 2100 5300
+Wire Wire Line
+	2100 3600 1650 3600
+Wire Wire Line
+	2050 4300 2050 5800
+Wire Wire Line
+	1650 4300 2050 4300
+Wire Wire Line
+	2200 5500 2200 6250
 $Comp
 L d_or U20
 U 1 1 5C95E06C
@@ -69,6 +110,62 @@ F 3 "" H 6650 4750 60  0000 C CNN
 	1    6650 4750
 	1    0    0    -1  
 $EndComp
+Wire Wire Line
+	6200 3200 5950 3200
+Wire Wire Line
+	5950 3200 5950 2000
+Wire Wire Line
+	5950 2000 4750 2000
+Wire Wire Line
+	6200 3700 5850 3700
+Wire Wire Line
+	5850 3700 5850 2500
+Wire Wire Line
+	5850 2500 4750 2500
+Wire Wire Line
+	6200 4150 5750 4150
+Wire Wire Line
+	5750 4150 5750 2950
+Wire Wire Line
+	5750 2950 4750 2950
+Wire Wire Line
+	6200 4650 5650 4650
+Wire Wire Line
+	5650 4650 5650 3450
+Wire Wire Line
+	5650 3450 4750 3450
+Wire Wire Line
+	4750 4250 5450 4250
+Wire Wire Line
+	5450 4250 5450 3300
+Wire Wire Line
+	5450 3300 6200 3300
+Wire Wire Line
+	4750 4750 5550 4750
+Wire Wire Line
+	5550 4750 5550 3800
+Wire Wire Line
+	5550 3800 6200 3800
+Wire Wire Line
+	4700 5200 5600 5200
+Wire Wire Line
+	5600 5200 5600 4250
+Wire Wire Line
+	5600 4250 6200 4250
+Wire Wire Line
+	4750 5700 5700 5700
+Wire Wire Line
+	5700 5700 5700 4750
+Wire Wire Line
+	5700 4750 6200 4750
+Wire Wire Line
+	7100 3250 8300 3250
+Wire Wire Line
+	7100 3750 8300 3750
+Wire Wire Line
+	7100 4200 8300 4200
+Wire Wire Line
+	7100 4700 8250 4700
 $Comp
 L d_inverter U3
 U 1 1 5C95E74D
@@ -80,154 +177,168 @@ F 3 "" H 2800 6200 60  0000 C CNN
 	1    2750 6250
 	1    0    0    -1  
 $EndComp
+Wire Wire Line
+	1700 6250 2450 6250
+Connection ~ 2200 6250
 $Comp
 L PORT U1
-U 2 1 5C95E920
+U 1 1 5C95E920
 P 1400 1850
 F 0 "U1" H 1450 1950 30  0000 C CNN
 F 1 "PORT" H 1400 1850 30  0000 C CNN
 F 2 "" H 1400 1850 60  0000 C CNN
 F 3 "" H 1400 1850 60  0000 C CNN
-	2    1400 1850
+	1    1400 1850
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 3 1 5C95E9CF
+U 2 1 5C95E9CF
 P 1400 2150
 F 0 "U1" H 1450 2250 30  0000 C CNN
 F 1 "PORT" H 1400 2150 30  0000 C CNN
 F 2 "" H 1400 2150 60  0000 C CNN
 F 3 "" H 1400 2150 60  0000 C CNN
-	3    1400 2150
+	2    1400 2150
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 11 1 5C95EA28
+U 3 1 5C95EA28
+P 1400 2700
+F 0 "U1" H 1450 2800 30  0000 C CNN
+F 1 "PORT" H 1400 2700 30  0000 C CNN
+F 2 "" H 1400 2700 60  0000 C CNN
+F 3 "" H 1400 2700 60  0000 C CNN
+	3    1400 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C95EA9C
+P 1400 2900
+F 0 "U1" H 1450 3000 30  0000 C CNN
+F 1 "PORT" H 1400 2900 30  0000 C CNN
+F 2 "" H 1400 2900 60  0000 C CNN
+F 3 "" H 1400 2900 60  0000 C CNN
+	4    1400 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C95EAFD
 P 1400 3350
 F 0 "U1" H 1450 3450 30  0000 C CNN
 F 1 "PORT" H 1400 3350 30  0000 C CNN
 F 2 "" H 1400 3350 60  0000 C CNN
 F 3 "" H 1400 3350 60  0000 C CNN
-	11   1400 3350
+	5    1400 3350
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 10 1 5C95EA9C
+U 6 1 5C95EB63
 P 1400 3600
 F 0 "U1" H 1450 3700 30  0000 C CNN
 F 1 "PORT" H 1400 3600 30  0000 C CNN
 F 2 "" H 1400 3600 60  0000 C CNN
 F 3 "" H 1400 3600 60  0000 C CNN
-	10   1400 3600
+	6    1400 3600
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 5 1 5C95EAFD
-P 1400 2650
-F 0 "U1" H 1450 2750 30  0000 C CNN
-F 1 "PORT" H 1400 2650 30  0000 C CNN
-F 2 "" H 1400 2650 60  0000 C CNN
-F 3 "" H 1400 2650 60  0000 C CNN
-	5    1400 2650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C95EB63
-P 1400 2900
-F 0 "U1" H 1450 3000 30  0000 C CNN
-F 1 "PORT" H 1400 2900 30  0000 C CNN
-F 2 "" H 1400 2900 60  0000 C CNN
-F 3 "" H 1400 2900 60  0000 C CNN
-	6    1400 2900
+U 7 1 5C95EBC8
+P 1400 4050
+F 0 "U1" H 1450 4150 30  0000 C CNN
+F 1 "PORT" H 1400 4050 30  0000 C CNN
+F 2 "" H 1400 4050 60  0000 C CNN
+F 3 "" H 1400 4050 60  0000 C CNN
+	7    1400 4050
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 13 1 5C95EC38
+U 8 1 5C95EC38
 P 1400 4300
 F 0 "U1" H 1450 4400 30  0000 C CNN
 F 1 "PORT" H 1400 4300 30  0000 C CNN
 F 2 "" H 1400 4300 60  0000 C CNN
 F 3 "" H 1400 4300 60  0000 C CNN
-	13   1400 4300
+	8    1400 4300
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 1 1 5C95ECA1
+U 10 1 5C95ECA1
 P 1450 6250
 F 0 "U1" H 1500 6350 30  0000 C CNN
 F 1 "PORT" H 1450 6250 30  0000 C CNN
 F 2 "" H 1450 6250 60  0000 C CNN
 F 3 "" H 1450 6250 60  0000 C CNN
-	1    1450 6250
+	10   1450 6250
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 15 1 5C95ED51
+U 9 1 5C95ED51
 P 1400 6650
 F 0 "U1" H 1450 6750 30  0000 C CNN
 F 1 "PORT" H 1400 6650 30  0000 C CNN
 F 2 "" H 1400 6650 60  0000 C CNN
 F 3 "" H 1400 6650 60  0000 C CNN
-	15   1400 6650
+	9    1400 6650
 	1    0    0    -1  
 $EndComp
 $Comp
 L PORT U1
-U 4 1 5C95EDCC
+U 12 1 5C95EDCC
 P 8550 3250
 F 0 "U1" H 8600 3350 30  0000 C CNN
 F 1 "PORT" H 8550 3250 30  0000 C CNN
 F 2 "" H 8550 3250 60  0000 C CNN
 F 3 "" H 8550 3250 60  0000 C CNN
-	4    8550 3250
+	12   8550 3250
 	-1   0    0    1   
 $EndComp
 $Comp
 L PORT U1
-U 7 1 5C95EEA6
+U 13 1 5C95EEA6
 P 8550 3750
 F 0 "U1" H 8600 3850 30  0000 C CNN
 F 1 "PORT" H 8550 3750 30  0000 C CNN
 F 2 "" H 8550 3750 60  0000 C CNN
 F 3 "" H 8550 3750 60  0000 C CNN
-	7    8550 3750
+	13   8550 3750
 	-1   0    0    1   
 $EndComp
 $Comp
 L PORT U1
-U 9 1 5C95EF2D
+U 14 1 5C95EF2D
 P 8550 4200
 F 0 "U1" H 8600 4300 30  0000 C CNN
 F 1 "PORT" H 8550 4200 30  0000 C CNN
 F 2 "" H 8550 4200 60  0000 C CNN
 F 3 "" H 8550 4200 60  0000 C CNN
-	9    8550 4200
+	14   8550 4200
 	-1   0    0    1   
 $EndComp
 $Comp
 L PORT U1
-U 12 1 5C95EFB5
+U 11 1 5C95EFB5
 P 8500 4700
 F 0 "U1" H 8550 4800 30  0000 C CNN
 F 1 "PORT" H 8500 4700 30  0000 C CNN
 F 2 "" H 8500 4700 60  0000 C CNN
 F 3 "" H 8500 4700 60  0000 C CNN
-	12   8500 4700
+	11   8500 4700
 	-1   0    0    1   
 $EndComp
 Text Notes 1950 1800 0    60   ~ 12
 A0\n
 Text Notes 1950 2100 0    60   ~ 12
 A1
-Text Notes 1900 2600 0    60   ~ 12
+Text Notes 1900 2650 0    60   ~ 12
 B0
 Text Notes 1900 2900 0    60   ~ 12
 B1\n
@@ -254,6 +365,10 @@ F 3 "" H 2700 6600 60  0000 C CNN
 	1    2650 6650
 	1    0    0    -1  
 $EndComp
+Wire Wire Line
+	3400 6650 2950 6650
+Wire Wire Line
+	1650 6650 2350 6650
 Text Notes 7850 3200 0    60   ~ 12
 YA
 Text Notes 7850 3700 0    60   ~ 12
@@ -262,8 +377,69 @@ Text Notes 7850 4200 2    60   ~ 12
 YC
 Text Notes 7800 4700 0    60   ~ 12
 YD
+Wire Wire Line
+	3450 2000 3900 2000
+Wire Wire Line
+	3450 2000 3450 5700
+Wire Wire Line
+	3450 2500 3900 2500
+Wire Wire Line
+	3450 2950 3900 2950
+Connection ~ 3450 2500
+Wire Wire Line
+	3450 3450 3900 3450
+Connection ~ 3450 2950
+Wire Wire Line
+	3450 4250 3900 4250
+Connection ~ 3450 3450
+Wire Wire Line
+	3450 4750 3900 4750
+Connection ~ 3450 4250
+Wire Wire Line
+	3450 5200 3850 5200
+Connection ~ 3450 4750
+Wire Wire Line
+	3400 5700 3900 5700
+Connection ~ 3450 5200
+Wire Wire Line
+	3300 5600 3900 5600
+Wire Wire Line
+	3300 4150 3300 5600
+Wire Wire Line
+	3300 5100 3850 5100
+Wire Wire Line
+	3300 4650 3900 4650
+Connection ~ 3300 5100
+Wire Wire Line
+	3300 4150 3900 4150
+Connection ~ 3300 4650
+Wire Wire Line
+	3250 3350 3900 3350
+Wire Wire Line
+	3250 1900 3250 3350
+Wire Wire Line
+	3250 2850 3900 2850
+Wire Wire Line
+	3250 2400 3900 2400
+Connection ~ 3250 2850
+Wire Wire Line
+	3250 1900 3900 1900
+Connection ~ 3250 2400
+Wire Wire Line
+	3250 3000 3100 3000
+Wire Wire Line
+	3100 3000 3100 6250
+Wire Wire Line
+	3100 6250 3050 6250
+Connection ~ 3250 3000
+Wire Wire Line
+	3300 5500 2200 5500
+Connection ~ 3300 5500
+Wire Wire Line
+	3400 6650 3400 5700
+Connection ~ 3450 5700
 $Comp
-L 3_and-RESCUE-74157 X2
+L 3_and X2
 U 1 1 5C9D0110
 P 3450 2400
 F 0 "X2" H 4350 2700 60  0000 C CNN
@@ -274,7 +450,7 @@ F 3 "" H 3450 2400 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X3
+L 3_and X3
 U 1 1 5C9D01B8
 P 3450 2900
 F 0 "X3" H 4350 3200 60  0000 C CNN
@@ -285,7 +461,7 @@ F 3 "" H 3450 2900 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X4
+L 3_and X4
 U 1 1 5C9D0222
 P 3450 3350
 F 0 "X4" H 4350 3650 60  0000 C CNN
@@ -296,7 +472,7 @@ F 3 "" H 3450 3350 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X5
+L 3_and X5
 U 1 1 5C9D0289
 P 3450 3850
 F 0 "X5" H 4350 4150 60  0000 C CNN
@@ -307,7 +483,7 @@ F 3 "" H 3450 3850 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X6
+L 3_and X6
 U 1 1 5C9D0361
 P 3450 4650
 F 0 "X6" H 4350 4950 60  0000 C CNN
@@ -318,7 +494,7 @@ F 3 "" H 3450 4650 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X7
+L 3_and X7
 U 1 1 5C9D0367
 P 3450 5150
 F 0 "X7" H 4350 5450 60  0000 C CNN
@@ -329,7 +505,7 @@ F 3 "" H 3450 5150 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X1
+L 3_and X1
 U 1 1 5C9D036D
 P 3400 5600
 F 0 "X1" H 4300 5900 60  0000 C CNN
@@ -340,7 +516,7 @@ F 3 "" H 3400 5600 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L 3_and-RESCUE-74157 X8
+L 3_and X8
 U 1 1 5C9D0373
 P 3450 6100
 F 0 "X8" H 4350 6400 60  0000 C CNN
@@ -350,180 +526,6 @@ F 3 "" H 3450 6100 60  0000 C CNN
 	1    3450 6100
 	1    0    0    -1  
 $EndComp
-$Comp
-L PORT U1
-U 8 1 5D123D14
-P 8450 1500
-F 0 "U1" H 8500 1600 30  0000 C CNN
-F 1 "PORT" H 8450 1500 30  0000 C CNN
-F 2 "" H 8450 1500 60  0000 C CNN
-F 3 "" H 8450 1500 60  0000 C CNN
-	8    8450 1500
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 16 1 5D123E38
-P 8450 1850
-F 0 "U1" H 8500 1950 30  0000 C CNN
-F 1 "PORT" H 8450 1850 30  0000 C CNN
-F 2 "" H 8450 1850 60  0000 C CNN
-F 3 "" H 8450 1850 60  0000 C CNN
-	16   8450 1850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	1650 1850 2750 1850
-Wire Wire Line
-	2750 3350 1650 3350
-Wire Wire Line
-	2750 3050 2750 3350
-Wire Wire Line
-	2800 4050 1650 4050
-Wire Wire Line
-	2800 3550 2800 4050
-Wire Wire Line
-	2200 2150 2200 4350
-Wire Wire Line
-	2200 2150 1650 2150
-Wire Wire Line
-	2150 2900 2150 4850
-Wire Wire Line
-	2150 2900 1650 2900
-Wire Wire Line
-	2100 3600 2100 5300
-Wire Wire Line
-	2100 3600 1650 3600
-Wire Wire Line
-	2050 4300 2050 5800
-Wire Wire Line
-	1650 4300 2050 4300
-Wire Wire Line
-	2200 5500 2200 6250
-Wire Wire Line
-	6200 3200 5950 3200
-Wire Wire Line
-	5950 3200 5950 2000
-Wire Wire Line
-	5950 2000 4750 2000
-Wire Wire Line
-	6200 3700 5850 3700
-Wire Wire Line
-	5850 3700 5850 2500
-Wire Wire Line
-	5850 2500 4750 2500
-Wire Wire Line
-	6200 4150 5750 4150
-Wire Wire Line
-	5750 4150 5750 2950
-Wire Wire Line
-	5750 2950 4750 2950
-Wire Wire Line
-	6200 4650 5650 4650
-Wire Wire Line
-	5650 4650 5650 3450
-Wire Wire Line
-	5650 3450 4750 3450
-Wire Wire Line
-	4750 4250 5450 4250
-Wire Wire Line
-	5450 4250 5450 3300
-Wire Wire Line
-	5450 3300 6200 3300
-Wire Wire Line
-	4750 4750 5550 4750
-Wire Wire Line
-	5550 4750 5550 3800
-Wire Wire Line
-	5550 3800 6200 3800
-Wire Wire Line
-	4700 5200 5600 5200
-Wire Wire Line
-	5600 5200 5600 4250
-Wire Wire Line
-	5600 4250 6200 4250
-Wire Wire Line
-	4750 5700 5700 5700
-Wire Wire Line
-	5700 5700 5700 4750
-Wire Wire Line
-	5700 4750 6200 4750
-Wire Wire Line
-	7100 3250 8300 3250
-Wire Wire Line
-	7100 3750 8300 3750
-Wire Wire Line
-	7100 4200 8300 4200
-Wire Wire Line
-	7100 4700 8250 4700
-Wire Wire Line
-	1700 6250 2450 6250
-Connection ~ 2200 6250
-Wire Wire Line
-	3400 6650 2950 6650
-Wire Wire Line
-	1650 6650 2350 6650
-Wire Wire Line
-	3450 2000 3900 2000
-Wire Wire Line
-	3450 2000 3450 5700
-Wire Wire Line
-	3450 2500 3900 2500
-Wire Wire Line
-	3450 2950 3900 2950
-Connection ~ 3450 2500
-Wire Wire Line
-	3450 3450 3900 3450
-Connection ~ 3450 2950
-Wire Wire Line
-	3450 4250 3900 4250
-Connection ~ 3450 3450
-Wire Wire Line
-	3450 4750 3900 4750
-Connection ~ 3450 4250
-Wire Wire Line
-	3450 5200 3850 5200
-Connection ~ 3450 4750
-Wire Wire Line
-	3400 5700 3900 5700
-Connection ~ 3450 5200
-Wire Wire Line
-	3300 5600 3900 5600
-Wire Wire Line
-	3300 4150 3300 5600
-Wire Wire Line
-	3300 5100 3850 5100
-Wire Wire Line
-	3300 4650 3900 4650
-Connection ~ 3300 5100
-Wire Wire Line
-	3300 4150 3900 4150
-Connection ~ 3300 4650
-Wire Wire Line
-	3250 3350 3900 3350
-Wire Wire Line
-	3250 1900 3250 3350
-Wire Wire Line
-	3250 2850 3900 2850
-Wire Wire Line
-	3250 2400 3900 2400
-Connection ~ 3250 2850
-Wire Wire Line
-	3250 1900 3900 1900
-Connection ~ 3250 2400
-Wire Wire Line
-	3250 3000 3100 3000
-Wire Wire Line
-	3100 3000 3100 6250
-Wire Wire Line
-	3100 6250 3050 6250
-Connection ~ 3250 3000
-Wire Wire Line
-	3300 5500 2200 5500
-Connection ~ 3300 5500
-Wire Wire Line
-	3400 6650 3400 5700
-Connection ~ 3450 5700
 Wire Wire Line
 	3900 2100 2750 2100
 Wire Wire Line
@@ -531,7 +533,7 @@ Wire Wire Line
 Wire Wire Line
 	3900 2600 1650 2600
 Wire Wire Line
-	1650 2600 1650 2650
+	1650 2600 1650 2700
 Wire Wire Line
 	3900 3050 2750 3050
 Wire Wire Line
@@ -544,17 +546,4 @@ Wire Wire Line
 	2100 5300 3850 5300
 Wire Wire Line
 	2050 5800 3900 5800
-$Comp
-L PORT U1
-U 14 1 5C95EBC8
-P 1400 4050
-F 0 "U1" H 1450 4150 30  0000 C CNN
-F 1 "PORT" H 1400 4050 30  0000 C CNN
-F 2 "" H 1400 4050 60  0000 C CNN
-F 3 "" H 1400 4050 60  0000 C CNN
-	14   1400 4050
-	1    0    0    -1  
-$EndComp
-NoConn ~ 8200 1500
-NoConn ~ 8200 1850
 $EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub
index 54897c26..545741f5 100644
--- a/src/SubcircuitLibrary/74157/74157.sub
+++ b/src/SubcircuitLibrary/74157/74157.sub
@@ -1,27 +1,27 @@
 * Subcircuit 74157
-.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir
+.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
 .include 3_and.sub
-* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or
-* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or
-* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or
-* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or
-* u3  net-_u1-pad1_ net-_u3-pad2_ d_inverter
-* u2  net-_u1-pad15_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23
-a5 net-_u1-pad1_ net-_u3-pad2_ u3
-a6 net-_u1-pad15_ net-_u2-pad2_ u2
+* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
+* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
+* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
+* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
+* u3  net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u2  net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
+x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
+x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
+x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
+x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
+x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
+x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
+x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
+a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
+a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
+a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
+a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
+a5 net-_u1-pad10_ net-_u3-pad2_ u3
+a6 net-_u1-pad9_ net-_u2-pad2_ u2
 * Schematic Name: d_or, NgSpice Name: d_or
 .model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
 * Schematic Name: d_or, NgSpice Name: d_or
diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
index 6fa26ea2..85f14960 100644
--- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
+++ b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x8><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
+<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/7485/3_and-cache.lib
+++ b/src/SubcircuitLibrary/7485/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/7485/3_and.cir
+++ b/src/SubcircuitLibrary/7485/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/7485/3_and.cir.out
+++ b/src/SubcircuitLibrary/7485/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro
index 0fdf4d25..2c9ac554 100644
--- a/src/SubcircuitLibrary/7485/3_and.pro
+++ b/src/SubcircuitLibrary/7485/3_and.pro
@@ -1,44 +1,58 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch
index c853bf49..86be0215 100644
--- a/src/SubcircuitLibrary/7485/3_and.sch
+++ b/src/SubcircuitLibrary/7485/3_and.sch
@@ -1,130 +1,121 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/7485/3_and.sub
+++ b/src/SubcircuitLibrary/7485/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib
index cb84d8f2..ac396288 100644
--- a/src/SubcircuitLibrary/7485/4_and-cache.lib
+++ b/src/SubcircuitLibrary/7485/4_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir
index 35e46097..50d490fa 100644
--- a/src/SubcircuitLibrary/7485/4_and.cir
+++ b/src/SubcircuitLibrary/7485/4_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out
index 6e35b18a..f40e5bc6 100644
--- a/src/SubcircuitLibrary/7485/4_and.cir.out
+++ b/src/SubcircuitLibrary/7485/4_and.cir.out
@@ -1,18 +1,18 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro
index 814ad76a..6eb77fff 100644
--- a/src/SubcircuitLibrary/7485/4_and.pro
+++ b/src/SubcircuitLibrary/7485/4_and.pro
@@ -1,58 +1,57 @@
-update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
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-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
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-LibName8=display
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-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
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-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
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-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=03/26/19 18:58:33
+version=1
+last_client=eeschema
+[general]
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+[pcbnew]
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+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=texas
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch
index 2d8296d4..883458e1 100644
--- a/src/SubcircuitLibrary/7485/4_and.sch
+++ b/src/SubcircuitLibrary/7485/4_and.sch
@@ -1,151 +1,139 @@
-EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
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-$EndComp
-$Comp
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-$Comp
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-$Comp
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-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
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-$EndComp
-$Comp
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-U 3 1 5C9A2A0D
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-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
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-F 1 "PORT" H 3000 3550 30  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	4    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
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-F 1 "PORT" H 6750 3350 30  0000 C CNN
-F 2 "" H 6750 3350 60  0000 C CNN
-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
-	-1   0    0    1   
-$EndComp
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-Text Notes 3500 3300 0    60   ~ 12
-in3
-Text Notes 3500 3550 0    60   ~ 12
-in4
-Text Notes 6150 3350 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
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+P 3700 3500
+F 0 "X1" H 4600 3800 60  0000 C CNN
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+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
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+F 2 "" H 5450 3400 60  0000 C CNN
+F 3 "" H 5450 3400 60  0000 C CNN
+	1    5450 3400
+	1    0    0    -1  
+$EndComp
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+$Comp
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+$Comp
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+	2    2950 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+P 3000 3300
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+F 1 "PORT" H 3000 3300 30  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
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+	4    3000 3550
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+$EndComp
+$Comp
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+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub
index bf20b628..8663f37e 100644
--- a/src/SubcircuitLibrary/7485/4_and.sub
+++ b/src/SubcircuitLibrary/7485/4_and.sub
@@ -1,12 +1,12 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib
index 4cf915be..ac396288 100644
--- a/src/SubcircuitLibrary/7485/5_and-cache.lib
+++ b/src/SubcircuitLibrary/7485/5_and-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir
index ca1199bd..6a05b9b5 100644
--- a/src/SubcircuitLibrary/7485/5_and.cir
+++ b/src/SubcircuitLibrary/7485/5_and.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out
index 20d3f8a5..6a6b126a 100644
--- a/src/SubcircuitLibrary/7485/5_and.cir.out
+++ b/src/SubcircuitLibrary/7485/5_and.cir.out
@@ -1,22 +1,22 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro
index a9d6304f..c82e4e6d 100644
--- a/src/SubcircuitLibrary/7485/5_and.pro
+++ b/src/SubcircuitLibrary/7485/5_and.pro
@@ -1,50 +1,50 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=03/26/19 18:50:27
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_PSpice
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
+LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch
index 0d86cdec..da927b09 100644
--- a/src/SubcircuitLibrary/7485/5_and.sch
+++ b/src/SubcircuitLibrary/7485/5_and.sch
@@ -1,171 +1,158 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60  0000 C CNN
-F 1 "3_and" H 4750 3850 60  0000 C CNN
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-	6000 3150 6500 3150
-$Comp
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-F 1 "PORT" H 3350 2700 30  0000 C CNN
-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
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-$Comp
-L PORT U1
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-$EndComp
-$Comp
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-U 3 1 5C9A28D9
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-$Comp
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-U 4 1 5C9A28FF
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-F 2 "" H 3350 3300 60  0000 C CNN
-F 3 "" H 3350 3300 60  0000 C CNN
-	4    3350 3300
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-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
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-F 2 "" H 3350 3500 60  0000 C CNN
-F 3 "" H 3350 3500 60  0000 C CNN
-	5    3350 3500
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-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30  0000 C CNN
-F 1 "PORT" H 6750 3150 30  0000 C CNN
-F 2 "" H 6750 3150 60  0000 C CNN
-F 3 "" H 6750 3150 60  0000 C CNN
-	6    6750 3150
-	-1   0    0    1   
-$EndComp
-Text Notes 3800 2700 0    60   ~ 12
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-Text Notes 3800 3100 0    60   ~ 12
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-in4
-Text Notes 3800 3500 0    60   ~ 12
-in5
-Text Notes 6150 3150 0    60   ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
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+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
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+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
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+F 0 "U1" H 3400 3000 30  0000 C CNN
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+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
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+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
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+$Comp
+L PORT U1
+U 4 1 5C9A28FF
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+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
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+$EndComp
+$Comp
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+U 6 1 5C9A2958
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+F 1 "PORT" H 6750 3150 30  0000 C CNN
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diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub
index 9d929fcb..35b10e17 100644
--- a/src/SubcircuitLibrary/7485/5_and.sub
+++ b/src/SubcircuitLibrary/7485/5_and.sub
@@ -1,16 +1,16 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib
index eb9a059e..6edb5033 100644
--- a/src/SubcircuitLibrary/7485/7485-cache.lib
+++ b/src/SubcircuitLibrary/7485/7485-cache.lib
@@ -4,80 +4,57 @@ EESchema-LIBRARY Version 2.3
 # 3_and
 #
 DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0 -150 200 200 200 N
-P 3 0 1 0 -150 200 -150 -100 200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
 ENDDRAW
 ENDDEF
 #
 # 4_and
 #
 DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 50 -50 60 H V C CNN
-F1 "4_and" 100 100 60 H V C CNN
+F0 "X" 1500 1050 60 H V C CNN
+F1 "4_and" 1550 1200 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
-A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
-P 2 0 1 0 -200 200 150 200 N
-P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
-X in1 1 -400 150 200 R 50 50 1 1 I
-X in2 2 -400 50 200 R 50 50 1 1 I
-X in3 3 -400 -50 200 R 50 50 1 1 I
-X in4 4 -400 -150 200 R 50 50 1 1 I
-X out 5 500 0 200 L 50 50 1 1 O
+A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
+P 2 0 1 0  1250 1300  1600 1300 N
+P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
+X in1 1 1050 1250 200 R 50 50 1 1 I
+X in2 2 1050 1150 200 R 50 50 1 1 I
+X in3 3 1050 1050 200 R 50 50 1 1 I
+X in4 4 1050 950 200 R 50 50 1 1 I
+X out 5 1950 1100 200 L 50 50 1 1 O
 ENDDRAW
 ENDDEF
 #
 # 5_and
 #
 DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
+F0 "X" 1350 800 60 H V C CNN
+F1 "5_and" 1400 1050 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 5_nor
-#
-DEF 5_nor X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_nor" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-T 0 50 400 60 0 0 0 name~is~c_gate Normal 0 C C
-T 0 50 450 60 0 0 0 subcircuit~file Normal 0 C C
-A 150 0 316 716 -716 0 1 0 N 250 300 250 -300
-P 2 0 1 0 -300 300 250 300 N
-P 4 0 1 0 -300 300 -300 -300 200 -300 250 -300 N
-X in1 1 -500 250 200 R 50 50 1 1 I I
-X in2 2 -500 150 200 R 50 50 1 1 I I
-X in3 3 -500 50 200 R 50 50 1 1 I I
-X in4 4 -500 -50 200 R 50 50 1 1 I I
-X in5 5 -500 -150 200 R 50 50 1 1 I I
-X in6 6 -500 -250 200 R 50 50 1 1 I I
-X out 7 650 0 200 L 50 50 1 1 O
+A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
+P 2 0 1 0  1050 1150  1450 1150 N
+P 3 0 1 0  1050 1150  1050 650  1450 650 N
+X in1 1 850 1100 200 R 50 50 1 1 I
+X in2 2 850 1000 200 R 50 50 1 1 I
+X in3 3 850 900 200 R 50 50 1 1 I
+X in4 4 850 800 200 R 50 50 1 1 I
+X in5 5 850 700 200 R 50 50 1 1 I
+X out 6 1850 900 200 L 50 50 1 1 O
 ENDDRAW
 ENDDEF
 #
@@ -121,6 +98,27 @@ X ~ 26 250 0 100 L 30 30 26 1 B
 ENDDRAW
 ENDDEF
 #
+# c_gate
+#
+DEF c_gate X 0 40 Y Y 1 F N
+F0 "X" 5900 4450 60 H V C CNN
+F1 "c_gate" 5950 4700 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
+P 2 0 1 0  5550 4850  6100 4850 N
+P 4 0 1 0  5550 4850  5550 4250  6050 4250  6100 4250 N
+X in1 1 5350 4800 200 R 50 50 1 1 I I
+X in2 2 5350 4700 200 R 50 50 1 1 I I
+X in3 3 5350 4600 200 R 50 50 1 1 I I
+X in4 4 5350 4500 200 R 50 50 1 1 I I
+X in5 5 5350 4400 200 R 50 50 1 1 I I
+X in6 6 5350 4300 200 R 50 50 1 1 I I
+X out 7 6500 4550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
 # d_and
 #
 DEF d_and U 0 40 Y Y 1 F N
@@ -131,7 +129,7 @@ F3 "" 0 0 60 H V C CNN
 DRAW
 A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
 A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
 X IN1 1 -450 100 200 R 50 50 1 1 I
 X IN2 2 -450 0 200 R 50 50 1 1 I
 X OUT 3 450 50 200 L 50 50 1 1 O
@@ -148,7 +146,7 @@ F3 "" 0 0 60 H V C CNN
 DRAW
 A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
 A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
 X IN1 1 -450 100 200 R 50 50 1 1 I
 X IN2 2 -450 0 200 R 50 50 1 1 I
 X OUT 3 450 50 200 L 50 50 1 1 O I
@@ -166,8 +164,8 @@ DRAW
 A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
 A -25 -124 325 574 323 0 1 0 N 150 150 250 50
 A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
 X IN1 1 -450 100 215 R 50 50 1 1 I
 X IN2 2 -450 0 215 R 50 50 1 1 I
 X OUT 3 450 50 200 L 50 50 1 1 O I
diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir
index 87188910..e15a357f 100644
--- a/src/SubcircuitLibrary/7485/7485.cir
+++ b/src/SubcircuitLibrary/7485/7485.cir
@@ -1,42 +1,42 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/7485/7485.cir
+* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir
 
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:22:51 2019
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
 * Sheet Name: /
-U6  Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and		
-U2  Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U18-Pad2_ d_nand		
-U7  Net-_U18-Pad2_ Net-_U1-Pad1_ Net-_U14-Pad2_ d_and		
+U6  Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand		
+U7  Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and		
 U14  Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor		
-U19  Net-_U1-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and		
-U18  Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and		
-U8  Net-_U1-Pad13_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and		
-U3  Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U3-Pad3_ d_nand		
-U9  Net-_U3-Pad3_ Net-_U1-Pad14_ Net-_U15-Pad2_ d_and		
+U19  Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and		
+X12  Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and		
+X7  Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and		
+X9  Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and		
+X10  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and		
+X11  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and		
+X13  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and		
+U18  Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and		
+X8  Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and		
+X3  Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and		
+X6  Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and		
+X5  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and		
+X4  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and		
+U8  Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and		
+U3  Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand		
+U9  Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and		
 U15  Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor		
 U12  Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and		
-U5  Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U12-Pad2_ d_nand		
-U13  Net-_U12-Pad2_ Net-_U1-Pad9_ Net-_U13-Pad3_ d_and		
+U5  Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand		
+U13  Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and		
 U17  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor		
-U10  Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
-U4  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nand		
-U11  Net-_U10-Pad2_ Net-_U1-Pad11_ Net-_U11-Pad3_ d_and		
+U10  Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
+U4  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand		
+U11  Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and		
 U16  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT		
-X7  Net-_U1-Pad14_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad2_ 3_and		
-X8  Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X12-Pad3_ 4_and		
-X3  Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U1-Pad12_ Net-_X1-Pad4_ 4_and		
-X2  Net-_U14-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad13_ Net-_X1-Pad5_ 3_and		
-X6  Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad10_ Net-_X1-Pad3_ 5_and		
-X5  Net-_U1-Pad4_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad2_ 5_and		
-X4  Net-_U1-Pad3_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad1_ 5_and		
-X11  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X11-Pad6_ 5_and		
-X10  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X10-Pad6_ 5_and		
-X9  Net-_U1-Pad9_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X12-Pad4_ 5_and		
-X13  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad6_ 5_and		
-X12  Net-_U19-Pad3_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_X12-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad5_ 5_nor		
-X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad7_ 5_nor		
+X2  Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate		
+X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
 
 .end
diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out
index 76e4fe6d..afc7b865 100644
--- a/src/SubcircuitLibrary/7485/7485.cir.out
+++ b/src/SubcircuitLibrary/7485/7485.cir.out
@@ -1,58 +1,58 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir
+* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir
 
-.include 5_nor.sub
 .include 4_and.sub
 .include 3_and.sub
 .include 5_and.sub
-* u6  net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and
-* u2  net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand
-* u7  net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and
+.include c_gate.sub
+* u6  net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand
+* u7  net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and
 * u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
-* u19  net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and
-* u18  net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u8  net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and
-* u3  net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand
-* u9  net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and
+* u19  net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and
+x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and
+x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and
+x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and
+x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and
+x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and
+x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and
+* u18  net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and
+x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and
+x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and
+x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and
+x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and
+x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and
+* u8  net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and
+* u3  net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand
+* u9  net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and
 * u15  net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
 * u12  net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and
-* u5  net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand
-* u13  net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and
+* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand
+* u13  net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and
 * u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor
-* u10  net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u4  net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand
-* u11  net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and
+* u10  net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u4  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand
+* u11  net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and
 * u16  net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and
-x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and
-x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and
-x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and
-x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and
-x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and
-x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and
-x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and
-x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and
-x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and
-x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and
-x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor
-a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6
-a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2
-a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7
+x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate
+x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6
+a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2
+a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7
 a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
-a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19
-a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8
-a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3
-a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9
+a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8
+a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3
+a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9
 a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
 a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12
-a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5
-a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13
+a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5
+a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13
 a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
-a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4
-a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11
+a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4
+a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11
 a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
 * Schematic Name: d_and, NgSpice Name: d_and
 .model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro
index fee23d1f..8fb4abb4 100644
--- a/src/SubcircuitLibrary/7485/7485.pro
+++ b/src/SubcircuitLibrary/7485/7485.pro
@@ -1,4 +1,4 @@
-update=Tue Jun 25 23:21:38 2019
+update=03/26/19 19:27:48
 version=1
 last_client=eeschema
 [general]
@@ -29,15 +29,30 @@ version=1
 NetIExt=net
 [eeschema]
 version=1
-LibDir=../../../kicadSchematicLibrary
+LibDir=
 [eeschema/libraries]
-LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-LibName10=eSim_Subckt
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_User
+LibName25=eSim_Subckt
diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch
index 32175173..0db5f0d6 100644
--- a/src/SubcircuitLibrary/7485/7485.sch
+++ b/src/SubcircuitLibrary/7485/7485.sch
@@ -1,4 +1,18 @@
 EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
 LIBS:eSim_Analog
 LIBS:eSim_Devices
 LIBS:eSim_Digital
@@ -6,6 +20,7 @@ LIBS:eSim_Hybrid
 LIBS:eSim_Miscellaneous
 LIBS:eSim_Plot
 LIBS:eSim_Power
+LIBS:eSim_PSpice
 LIBS:eSim_Sources
 LIBS:eSim_User
 LIBS:eSim_Subckt
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+F 3 "" H 5450 2750 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
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+F 2 "" H 5650 3050 60  0000 C CNN
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+	1    5650 3600
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+	1    5650 4150
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+F 3 "" H 7550 4850 60  0000 C CNN
+	1    7550 4850
+	1    0    0    -1  
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 L d_and U18
 U 1 1 5C9A32FD
 P 6350 6900
@@ -91,6 +172,61 @@ F 3 "" H 6350 6900 60  0000 C CNN
 	1    0    0    1   
 $EndComp
 $Comp
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+F 3 "" H 5500 6250 60  0000 C CNN
+	1    5500 6250
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+F 2 "" H 4900 5150 60  0000 C CNN
+F 3 "" H 4900 5150 60  0000 C CNN
+	1    4900 5150
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+$EndComp
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+F 2 "" H 5100 4850 60  0000 C CNN
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+	1    5100 4850
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+F 1 "5_and" H 6500 5350 60  0000 C CNN
+F 2 "" H 5100 4300 60  0000 C CNN
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+	1    5100 4300
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 P 3250 2600
@@ -222,20 +358,56 @@ F 3 "" H 4300 3950 60  0000 C CNN
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+	1    3050 6600
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+F 1 "c_gate" H 8800 14700 60  0000 C CNN
+F 2 "" H 2850 10000 60  0000 C CNN
+F 3 "" H 2850 10000 60  0000 C CNN
+	1    2850 10000
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 P 950 3900
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 F 2 "" H 950 3900 60  0000 C CNN
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 L PORT U1
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 F 2 "" H 1000 5300 60  0000 C CNN
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 L PORT U1
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 F 1 "PORT" H 800 3150 30  0000 C CNN
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 L PORT U1
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 L PORT U1
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-	1    6400 5200
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-F 3 "" H 6950 3250 60  0000 C CNN
-	1    6950 3250
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diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub
index 63ea7f3b..5a45c57c 100644
--- a/src/SubcircuitLibrary/7485/7485.sub
+++ b/src/SubcircuitLibrary/7485/7485.sub
@@ -1,58 +1,58 @@
 * Subcircuit 7485
-.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir
-.include 5_nor.sub
+.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir
 .include 4_and.sub
 .include 3_and.sub
 .include 5_and.sub
-* u6  net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and
-* u2  net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand
-* u7  net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and
+.include c_gate.sub
+* u6  net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand
+* u7  net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and
 * u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
-* u19  net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and
-* u18  net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u8  net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and
-* u3  net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand
-* u9  net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and
+* u19  net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and
+x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and
+x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and
+x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and
+x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and
+x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and
+x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and
+* u18  net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and
+x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and
+x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and
+x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and
+x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and
+x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and
+* u8  net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and
+* u3  net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand
+* u9  net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and
 * u15  net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
 * u12  net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and
-* u5  net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand
-* u13  net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and
+* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand
+* u13  net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and
 * u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor
-* u10  net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u4  net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand
-* u11  net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and
+* u10  net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u4  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand
+* u11  net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and
 * u16  net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor
-x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and
-x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and
-x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and
-x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and
-x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and
-x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and
-x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and
-x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and
-x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and
-x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and
-x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and
-x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor
-a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6
-a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2
-a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7
+x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate
+x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate
+a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6
+a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2
+a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7
 a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
-a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19
-a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8
-a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3
-a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9
+a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8
+a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3
+a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9
 a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
 a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12
-a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5
-a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13
+a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5
+a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13
 a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
-a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4
-a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11
+a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4
+a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11
 a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
 * Schematic Name: d_and, NgSpice Name: d_and
 .model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml
index 124a0047..6d8f93b6 100644
--- a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml
+++ b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x1><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x9><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x12><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x13><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
+<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib
index f1f7990e..6edb5033 100644
--- a/src/SubcircuitLibrary/7485/7485mod-cache.lib
+++ b/src/SubcircuitLibrary/7485/7485mod-cache.lib
@@ -1,175 +1,175 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0  1250 1300  1600 1300 N
-P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0  1050 1150  1450 1150 N
-P 3 0 1 0  1050 1150  1050 650  1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# c_gate
-#
-DEF c_gate X 0 40 Y Y 1 F N
-F0 "X" 5900 4450 60 H V C CNN
-F1 "c_gate" 5950 4700 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
-P 2 0 1 0  5550 4850  6100 4850 N
-P 4 0 1 0  5550 4850  5550 4250  6050 4250  6100 4250 N
-X in1 1 5350 4800 200 R 50 50 1 1 I I
-X in2 2 5350 4700 200 R 50 50 1 1 I I
-X in3 3 5350 4600 200 R 50 50 1 1 I I
-X in4 4 5350 4500 200 R 50 50 1 1 I I
-X in5 5 5350 4400 200 R 50 50 1 1 I I
-X in6 6 5350 4300 200 R 50 50 1 1 I I
-X out 7 6500 4550 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_nand
-#
-DEF d_nand U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nand" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 1500 1050 60 H V C CNN
+F1 "4_and" 1550 1200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
+P 2 0 1 0  1250 1300  1600 1300 N
+P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
+X in1 1 1050 1250 200 R 50 50 1 1 I
+X in2 2 1050 1150 200 R 50 50 1 1 I
+X in3 3 1050 1050 200 R 50 50 1 1 I
+X in4 4 1050 950 200 R 50 50 1 1 I
+X out 5 1950 1100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 1350 800 60 H V C CNN
+F1 "5_and" 1400 1050 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
+P 2 0 1 0  1050 1150  1450 1150 N
+P 3 0 1 0  1050 1150  1050 650  1450 650 N
+X in1 1 850 1100 200 R 50 50 1 1 I
+X in2 2 850 1000 200 R 50 50 1 1 I
+X in3 3 850 900 200 R 50 50 1 1 I
+X in4 4 850 800 200 R 50 50 1 1 I
+X in5 5 850 700 200 R 50 50 1 1 I
+X out 6 1850 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# c_gate
+#
+DEF c_gate X 0 40 Y Y 1 F N
+F0 "X" 5900 4450 60 H V C CNN
+F1 "c_gate" 5950 4700 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
+P 2 0 1 0  5550 4850  6100 4850 N
+P 4 0 1 0  5550 4850  5550 4250  6050 4250  6100 4250 N
+X in1 1 5350 4800 200 R 50 50 1 1 I I
+X in2 2 5350 4700 200 R 50 50 1 1 I I
+X in3 3 5350 4600 200 R 50 50 1 1 I I
+X in4 4 5350 4500 200 R 50 50 1 1 I I
+X in5 5 5350 4400 200 R 50 50 1 1 I I
+X in6 6 5350 4300 200 R 50 50 1 1 I I
+X out 7 6500 4550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch
index 9114b802..f7e537ad 100644
--- a/src/SubcircuitLibrary/7485/7485mod.sch
+++ b/src/SubcircuitLibrary/7485/7485mod.sch
@@ -1,1007 +1,1007 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
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-P 950 3900
-F 0 "U1" H 1000 4000 30  0000 C CNN
-F 1 "PORT" H 950 3900 30  0000 C CNN
-F 2 "" H 950 3900 60  0000 C CNN
-F 3 "" H 950 3900 60  0000 C CNN
-	8    950  3900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C9A8D2C
-P 950 4100
-F 0 "U1" H 1000 4200 30  0000 C CNN
-F 1 "PORT" H 950 4100 30  0000 C CNN
-F 2 "" H 950 4100 60  0000 C CNN
-F 3 "" H 950 4100 60  0000 C CNN
-	9    950  4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C9A8DBD
-P 1000 5100
-F 0 "U1" H 1050 5200 30  0000 C CNN
-F 1 "PORT" H 1000 5100 30  0000 C CNN
-F 2 "" H 1000 5100 60  0000 C CNN
-F 3 "" H 1000 5100 60  0000 C CNN
-	10   1000 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C9A8E65
-P 1000 5300
-F 0 "U1" H 1050 5400 30  0000 C CNN
-F 1 "PORT" H 1000 5300 30  0000 C CNN
-F 2 "" H 1000 5300 60  0000 C CNN
-F 3 "" H 1000 5300 60  0000 C CNN
-	11   1000 5300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A8EEE
-P 800 3150
-F 0 "U1" H 850 3250 30  0000 C CNN
-F 1 "PORT" H 800 3150 30  0000 C CNN
-F 2 "" H 800 3150 60  0000 C CNN
-F 3 "" H 800 3150 60  0000 C CNN
-	1    800  3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A8F9C
-P 800 3400
-F 0 "U1" H 850 3500 30  0000 C CNN
-F 1 "PORT" H 800 3400 30  0000 C CNN
-F 2 "" H 800 3400 60  0000 C CNN
-F 3 "" H 800 3400 60  0000 C CNN
-	2    800  3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A9031
-P 800 3600
-F 0 "U1" H 850 3700 30  0000 C CNN
-F 1 "PORT" H 800 3600 30  0000 C CNN
-F 2 "" H 800 3600 60  0000 C CNN
-F 3 "" H 800 3600 60  0000 C CNN
-	3    800  3600
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1050 3250 1050 3150
-Wire Wire Line
-	1050 3550 1050 3600
-Wire Wire Line
-	1350 4000 1350 4100
-Wire Wire Line
-	1350 4100 1200 4100
-Wire Wire Line
-	9550 2050 9850 2050
-Wire Wire Line
-	9400 3950 9850 3950
-Wire Wire Line
-	9350 5450 9900 5450
-$Comp
-L PORT U1
-U 12 1 5C9A9B26
-P 10100 2050
-F 0 "U1" H 10150 2150 30  0000 C CNN
-F 1 "PORT" H 10100 2050 30  0000 C CNN
-F 2 "" H 10100 2050 60  0000 C CNN
-F 3 "" H 10100 2050 60  0000 C CNN
-	12   10100 2050
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C9A9BCA
-P 10100 3950
-F 0 "U1" H 10150 4050 30  0000 C CNN
-F 1 "PORT" H 10100 3950 30  0000 C CNN
-F 2 "" H 10100 3950 60  0000 C CNN
-F 3 "" H 10100 3950 60  0000 C CNN
-	13   10100 3950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C9A9CA0
-P 10150 5450
-F 0 "U1" H 10200 5550 30  0000 C CNN
-F 1 "PORT" H 10150 5450 30  0000 C CNN
-F 2 "" H 10150 5450 60  0000 C CNN
-F 3 "" H 10150 5450 60  0000 C CNN
-	14   10150 5450
-	-1   0    0    1   
-$EndComp
-Text Notes 9650 2000 0    60   ~ 12
-A>B
-Text Notes 9600 3900 0    60   ~ 12
-A=B\n
-Text Notes 9600 5400 0    60   ~ 12
-A<B\n
-Text Notes 1250 5100 0    60   ~ 12
-A0
-Text Notes 1200 5400 0    60   ~ 12
-B0
-Text Notes 1300 3900 2    60   ~ 12
-A1
-Text Notes 1300 4200 2    60   ~ 12
-B1
-Text Notes 1250 3250 2    60   ~ 12
-A<B
-Text Notes 1250 3400 2    60   ~ 12
-A=B
-Text Notes 1250 3550 2    60   ~ 12
-A>B
-Text Notes 1350 2750 2    60   ~ 12
-A2
-Text Notes 1350 2950 2    60   ~ 12
-B2
-Text Notes 1300 1350 2    60   ~ 12
-A3
-Text Notes 1300 1550 2    60   ~ 12
-B3
-Wire Wire Line
-	8200 5600 7450 5600
-Wire Wire Line
-	7450 5600 7450 6050
-Wire Wire Line
-	7450 6050 6900 6050
-Wire Wire Line
-	6800 6650 6800 6300
-Wire Wire Line
-	6800 6300 6900 6300
-Wire Wire Line
-	6900 6300 6900 6050
-Wire Notes Line
-	500  3000 1350 3000
-Wire Notes Line
-	1350 3000 1350 3750
-Wire Notes Line
-	1350 3750 500  3750
-Wire Notes Line
-	500  3750 500  3000
-Text Notes 600  3000 3    60   ~ 12
-Cascading Inputs
-Wire Notes Line
-	9500 1550 9500 6050
-Wire Notes Line
-	9500 6050 10550 6050
-Wire Notes Line
-	10550 6050 10550 1550
-Wire Notes Line
-	10550 1550 9500 1550
-Text Notes 9900 3400 0    60   ~ 12
-Outputs
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:7485-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U6
+U 1 1 5C9A2432
+P 3150 1200
+F 0 "U6" H 3150 1200 60  0000 C CNN
+F 1 "d_and" H 3200 1300 60  0000 C CNN
+F 2 "" H 3150 1200 60  0000 C CNN
+F 3 "" H 3150 1200 60  0000 C CNN
+	1    3150 1200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U2
+U 1 1 5C9A246F
+P 2100 1450
+F 0 "U2" H 2100 1450 60  0000 C CNN
+F 1 "d_nand" H 2150 1550 60  0000 C CNN
+F 2 "" H 2100 1450 60  0000 C CNN
+F 3 "" H 2100 1450 60  0000 C CNN
+	1    2100 1450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U7
+U 1 1 5C9A24BA
+P 3150 1600
+F 0 "U7" H 3150 1600 60  0000 C CNN
+F 1 "d_and" H 3200 1700 60  0000 C CNN
+F 2 "" H 3150 1600 60  0000 C CNN
+F 3 "" H 3150 1600 60  0000 C CNN
+	1    3150 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 5C9A252F
+P 4050 1400
+F 0 "U14" H 4050 1400 60  0000 C CNN
+F 1 "d_nor" H 4100 1500 60  0000 C CNN
+F 2 "" H 4050 1400 60  0000 C CNN
+F 3 "" H 4050 1400 60  0000 C CNN
+	1    4050 1400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5C9A2580
+P 6900 1000
+F 0 "U19" H 6900 1000 60  0000 C CNN
+F 1 "d_and" H 6950 1100 60  0000 C CNN
+F 2 "" H 6900 1000 60  0000 C CNN
+F 3 "" H 6900 1000 60  0000 C CNN
+	1    6900 1000
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X12
+U 1 1 5C9A2DC4
+P 6050 1650
+F 0 "X12" H 6950 1950 60  0000 C CNN
+F 1 "3_and" H 7000 2150 60  0000 C CNN
+F 2 "" H 6050 1650 60  0000 C CNN
+F 3 "" H 6050 1650 60  0000 C CNN
+	1    6050 1650
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 5C9A2EB7
+P 5450 2750
+F 0 "X7" H 6950 3800 60  0000 C CNN
+F 1 "4_and" H 7000 3950 60  0000 C CNN
+F 2 "" H 5450 2750 60  0000 C CNN
+F 3 "" H 5450 2750 60  0000 C CNN
+	1    5450 2750
+	1    0    0    -1  
+$EndComp
+$Comp
+L 5_and X9
+U 1 1 5C9A2F2E
+P 5650 3050
+F 0 "X9" H 7000 3850 60  0000 C CNN
+F 1 "5_and" H 7050 4100 60  0000 C CNN
+F 2 "" H 5650 3050 60  0000 C CNN
+F 3 "" H 5650 3050 60  0000 C CNN
+	1    5650 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L 5_and X10
+U 1 1 5C9A2F95
+P 5650 3600
+F 0 "X10" H 7000 4400 60  0000 C CNN
+F 1 "5_and" H 7050 4650 60  0000 C CNN
+F 2 "" H 5650 3600 60  0000 C CNN
+F 3 "" H 5650 3600 60  0000 C CNN
+	1    5650 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L 5_and X11
+U 1 1 5C9A3164
+P 5650 4150
+F 0 "X11" H 7000 4950 60  0000 C CNN
+F 1 "5_and" H 7050 5200 60  0000 C CNN
+F 2 "" H 5650 4150 60  0000 C CNN
+F 3 "" H 5650 4150 60  0000 C CNN
+	1    5650 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L 5_and X13
+U 1 1 5C9A31B3
+P 7550 4850
+F 0 "X13" H 8900 5650 60  0000 C CNN
+F 1 "5_and" H 8950 5900 60  0000 C CNN
+F 2 "" H 7550 4850 60  0000 C CNN
+F 3 "" H 7550 4850 60  0000 C CNN
+	1    7550 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5C9A32FD
+P 6350 6900
+F 0 "U18" H 6350 6900 60  0000 C CNN
+F 1 "d_and" H 6400 7000 60  0000 C CNN
+F 2 "" H 6350 6900 60  0000 C CNN
+F 3 "" H 6350 6900 60  0000 C CNN
+	1    6350 6900
+	1    0    0    1   
+$EndComp
+$Comp
+L 3_and X8
+U 1 1 5C9A3303
+P 5500 6250
+F 0 "X8" H 6400 6550 60  0000 C CNN
+F 1 "3_and" H 6450 6750 60  0000 C CNN
+F 2 "" H 5500 6250 60  0000 C CNN
+F 3 "" H 5500 6250 60  0000 C CNN
+	1    5500 6250
+	1    0    0    1   
+$EndComp
+$Comp
+L 4_and X3
+U 1 1 5C9A3309
+P 4900 5150
+F 0 "X3" H 6400 6200 60  0000 C CNN
+F 1 "4_and" H 6450 6350 60  0000 C CNN
+F 2 "" H 4900 5150 60  0000 C CNN
+F 3 "" H 4900 5150 60  0000 C CNN
+	1    4900 5150
+	1    0    0    1   
+$EndComp
+$Comp
+L 5_and X6
+U 1 1 5C9A330F
+P 5100 4850
+F 0 "X6" H 6450 5650 60  0000 C CNN
+F 1 "5_and" H 6500 5900 60  0000 C CNN
+F 2 "" H 5100 4850 60  0000 C CNN
+F 3 "" H 5100 4850 60  0000 C CNN
+	1    5100 4850
+	1    0    0    1   
+$EndComp
+$Comp
+L 5_and X5
+U 1 1 5C9A3315
+P 5100 4300
+F 0 "X5" H 6450 5100 60  0000 C CNN
+F 1 "5_and" H 6500 5350 60  0000 C CNN
+F 2 "" H 5100 4300 60  0000 C CNN
+F 3 "" H 5100 4300 60  0000 C CNN
+	1    5100 4300
+	1    0    0    1   
+$EndComp
+$Comp
+L 5_and X4
+U 1 1 5C9A331B
+P 5100 3750
+F 0 "X4" H 6450 4550 60  0000 C CNN
+F 1 "5_and" H 6500 4800 60  0000 C CNN
+F 2 "" H 5100 3750 60  0000 C CNN
+F 3 "" H 5100 3750 60  0000 C CNN
+	1    5100 3750
+	1    0    0    1   
+$EndComp
+$Comp
+L d_and U8
+U 1 1 5C9A39D8
+P 3250 2600
+F 0 "U8" H 3250 2600 60  0000 C CNN
+F 1 "d_and" H 3300 2700 60  0000 C CNN
+F 2 "" H 3250 2600 60  0000 C CNN
+F 3 "" H 3250 2600 60  0000 C CNN
+	1    3250 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U3
+U 1 1 5C9A39DE
+P 2200 2850
+F 0 "U3" H 2200 2850 60  0000 C CNN
+F 1 "d_nand" H 2250 2950 60  0000 C CNN
+F 2 "" H 2200 2850 60  0000 C CNN
+F 3 "" H 2200 2850 60  0000 C CNN
+	1    2200 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U9
+U 1 1 5C9A39E4
+P 3250 3000
+F 0 "U9" H 3250 3000 60  0000 C CNN
+F 1 "d_and" H 3300 3100 60  0000 C CNN
+F 2 "" H 3250 3000 60  0000 C CNN
+F 3 "" H 3250 3000 60  0000 C CNN
+	1    3250 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 5C9A39EA
+P 4150 2800
+F 0 "U15" H 4150 2800 60  0000 C CNN
+F 1 "d_nor" H 4200 2900 60  0000 C CNN
+F 2 "" H 4150 2800 60  0000 C CNN
+F 3 "" H 4150 2800 60  0000 C CNN
+	1    4150 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U12
+U 1 1 5C9A3B56
+P 3600 4950
+F 0 "U12" H 3600 4950 60  0000 C CNN
+F 1 "d_and" H 3650 5050 60  0000 C CNN
+F 2 "" H 3600 4950 60  0000 C CNN
+F 3 "" H 3600 4950 60  0000 C CNN
+	1    3600 4950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 5C9A3B5C
+P 2550 5200
+F 0 "U5" H 2550 5200 60  0000 C CNN
+F 1 "d_nand" H 2600 5300 60  0000 C CNN
+F 2 "" H 2550 5200 60  0000 C CNN
+F 3 "" H 2550 5200 60  0000 C CNN
+	1    2550 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5C9A3B62
+P 3600 5350
+F 0 "U13" H 3600 5350 60  0000 C CNN
+F 1 "d_and" H 3650 5450 60  0000 C CNN
+F 2 "" H 3600 5350 60  0000 C CNN
+F 3 "" H 3600 5350 60  0000 C CNN
+	1    3600 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 5C9A3B68
+P 4500 5150
+F 0 "U17" H 4500 5150 60  0000 C CNN
+F 1 "d_nor" H 4550 5250 60  0000 C CNN
+F 2 "" H 4500 5150 60  0000 C CNN
+F 3 "" H 4500 5150 60  0000 C CNN
+	1    4500 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U10
+U 1 1 5C9A3C6D
+P 3400 3750
+F 0 "U10" H 3400 3750 60  0000 C CNN
+F 1 "d_and" H 3450 3850 60  0000 C CNN
+F 2 "" H 3400 3750 60  0000 C CNN
+F 3 "" H 3400 3750 60  0000 C CNN
+	1    3400 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 5C9A3C73
+P 2350 4000
+F 0 "U4" H 2350 4000 60  0000 C CNN
+F 1 "d_nand" H 2400 4100 60  0000 C CNN
+F 2 "" H 2350 4000 60  0000 C CNN
+F 3 "" H 2350 4000 60  0000 C CNN
+	1    2350 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U11
+U 1 1 5C9A3C79
+P 3400 4150
+F 0 "U11" H 3400 4150 60  0000 C CNN
+F 1 "d_and" H 3450 4250 60  0000 C CNN
+F 2 "" H 3400 4150 60  0000 C CNN
+F 3 "" H 3400 4150 60  0000 C CNN
+	1    3400 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 5C9A3C7F
+P 4300 3950
+F 0 "U16" H 4300 3950 60  0000 C CNN
+F 1 "d_nor" H 4350 4050 60  0000 C CNN
+F 2 "" H 4300 3950 60  0000 C CNN
+F 3 "" H 4300 3950 60  0000 C CNN
+	1    4300 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L c_gate X2
+U 1 1 5C9A4498
+P 3050 6600
+F 0 "X2" H 3100 6650 60  0000 C CNN
+F 1 "c_gate" H 9000 11300 60  0000 C CNN
+F 2 "" H 3050 6600 60  0000 C CNN
+F 3 "" H 3050 6600 60  0000 C CNN
+	1    3050 6600
+	1    0    0    -1  
+$EndComp
+$Comp
+L c_gate X1
+U 1 1 5C9A465F
+P 2850 10000
+F 0 "X1" H 2900 10050 60  0000 C CNN
+F 1 "c_gate" H 8800 14700 60  0000 C CNN
+F 2 "" H 2850 10000 60  0000 C CNN
+F 3 "" H 2850 10000 60  0000 C CNN
+	1    2850 10000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3600 1300 3600 1150
+Wire Wire Line
+	3600 1400 3600 1550
+Wire Wire Line
+	2700 1000 2700 4700
+Wire Wire Line
+	2700 1600 1550 1600
+Wire Wire Line
+	1550 1600 1550 1450
+Wire Wire Line
+	1100 1450 1650 1450
+Wire Wire Line
+	1100 1350 1650 1350
+Wire Wire Line
+	1550 1350 1550 1100
+Wire Wire Line
+	1550 1100 2700 1100
+Wire Wire Line
+	2550 1400 2700 1400
+Connection ~ 2700 1400
+Connection ~ 1550 1350
+Connection ~ 1550 1450
+Wire Wire Line
+	3700 2700 3700 2550
+Wire Wire Line
+	3700 2800 3700 2950
+Wire Wire Line
+	2800 2000 2800 4600
+Wire Wire Line
+	2800 3000 1650 3000
+Wire Wire Line
+	1650 3000 1650 2850
+Wire Wire Line
+	1200 2850 1750 2850
+Wire Wire Line
+	1200 2750 1750 2750
+Wire Wire Line
+	1650 2750 1650 2500
+Wire Wire Line
+	1650 2500 2800 2500
+Wire Wire Line
+	2650 2800 2800 2800
+Connection ~ 2800 2800
+Connection ~ 1650 2750
+Connection ~ 1650 2850
+Wire Wire Line
+	4050 5050 4050 4900
+Wire Wire Line
+	4050 5150 4050 5300
+Wire Wire Line
+	3150 4950 3150 5850
+Wire Wire Line
+	3150 5350 2000 5350
+Wire Wire Line
+	2000 5350 2000 5200
+Wire Wire Line
+	1250 5200 2100 5200
+Wire Wire Line
+	1250 5100 2100 5100
+Wire Wire Line
+	2000 5100 2000 4850
+Wire Wire Line
+	2000 4850 3150 4850
+Wire Wire Line
+	3000 5150 3150 5150
+Connection ~ 3150 5150
+Connection ~ 2000 5100
+Connection ~ 2000 5200
+Wire Wire Line
+	3850 3850 3850 3700
+Wire Wire Line
+	3850 3950 3850 4100
+Wire Wire Line
+	2950 3200 2950 4350
+Wire Wire Line
+	2950 4150 1800 4150
+Wire Wire Line
+	1800 4150 1800 4000
+Wire Wire Line
+	1350 4000 1900 4000
+Wire Wire Line
+	1200 3900 1900 3900
+Wire Wire Line
+	1800 3900 1800 3650
+Wire Wire Line
+	1800 3650 2950 3650
+Wire Wire Line
+	2800 3950 2950 3950
+Connection ~ 2950 3950
+Connection ~ 1800 3900
+Connection ~ 1800 4000
+Wire Wire Line
+	1400 1350 1400 7000
+Wire Wire Line
+	1400 7000 5900 7000
+Connection ~ 1400 1350
+Wire Wire Line
+	1250 5200 1250 5300
+Wire Wire Line
+	5900 6900 2900 6900
+Wire Wire Line
+	2900 6900 2900 4700
+Wire Wire Line
+	2900 4700 2700 4700
+Connection ~ 2700 1500
+Wire Wire Line
+	5950 6750 1450 6750
+Wire Wire Line
+	1450 6750 1450 2750
+Connection ~ 1450 2750
+Wire Wire Line
+	5950 6650 2950 6650
+Wire Wire Line
+	2950 6650 2950 4600
+Wire Wire Line
+	2950 4600 2800 4600
+Connection ~ 2800 2900
+Wire Wire Line
+	5100 6550 5950 6550
+Wire Wire Line
+	5100 1350 5100 6550
+Wire Wire Line
+	4500 1350 6500 1350
+Wire Wire Line
+	1500 1450 1500 900 
+Wire Wire Line
+	1500 900  6450 900 
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+Wire Wire Line
+	2700 1000 6450 1000
+Connection ~ 2700 1200
+Wire Wire Line
+	6500 1150 4500 1150
+Wire Wire Line
+	4500 1150 4500 1900
+Wire Wire Line
+	4500 1900 1600 1900
+Wire Wire Line
+	1600 1900 1600 2850
+Connection ~ 1600 2850
+Wire Wire Line
+	6500 1250 4550 1250
+Wire Wire Line
+	4550 1250 4550 2000
+Wire Wire Line
+	4550 2000 2800 2000
+Connection ~ 2800 2600
+Connection ~ 5100 1350
+Wire Wire Line
+	6500 1500 4600 1500
+Wire Wire Line
+	4600 1500 4600 2100
+Wire Wire Line
+	4600 2100 1750 2100
+Wire Wire Line
+	1750 2100 1750 4000
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+Wire Wire Line
+	6500 1600 4650 1600
+Wire Wire Line
+	4650 1600 4650 3200
+Wire Wire Line
+	4650 3200 2950 3200
+Connection ~ 2950 3750
+Wire Wire Line
+	6500 1700 5100 1700
+Connection ~ 5100 1700
+Wire Wire Line
+	6500 1800 5250 1800
+Wire Wire Line
+	5250 1800 5250 6100
+Wire Wire Line
+	5250 2750 4600 2750
+Wire Wire Line
+	6500 1950 1500 1950
+Wire Wire Line
+	1500 1950 1500 5200
+Connection ~ 1500 5200
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+	6500 2050 4950 2050
+Wire Wire Line
+	4950 2050 4950 4300
+Wire Wire Line
+	4950 4300 3150 4300
+Wire Wire Line
+	3150 4300 3150 5000
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+Wire Wire Line
+	6500 2150 5100 2150
+Connection ~ 5100 2150
+Wire Wire Line
+	6500 2250 5250 2250
+Connection ~ 5250 2250
+Wire Wire Line
+	6500 2350 5350 2350
+Wire Wire Line
+	5350 2350 5350 5550
+Wire Wire Line
+	5350 3900 4750 3900
+Wire Wire Line
+	6500 2500 5100 2500
+Connection ~ 5100 2500
+Wire Wire Line
+	6500 2600 5250 2600
+Connection ~ 5250 2600
+Wire Wire Line
+	6500 2700 5350 2700
+Connection ~ 5350 2700
+Wire Wire Line
+	6500 2800 5450 2800
+Wire Wire Line
+	5450 2800 5450 5100
+Wire Wire Line
+	4950 5100 5950 5100
+Wire Wire Line
+	6500 2900 5550 2900
+Wire Wire Line
+	5550 2900 5550 3250
+Wire Wire Line
+	5550 3250 1050 3250
+Wire Wire Line
+	6500 3050 5100 3050
+Connection ~ 5100 3050
+Wire Wire Line
+	5250 3150 6500 3150
+Connection ~ 5250 2750
+Wire Wire Line
+	6500 3250 5700 3250
+Wire Wire Line
+	5700 3250 5700 3200
+Wire Wire Line
+	5700 3200 5350 3200
+Connection ~ 5350 3200
+Wire Wire Line
+	6500 3350 5450 3350
+Connection ~ 5450 3350
+Wire Wire Line
+	4800 3450 6500 3450
+Wire Wire Line
+	4800 3450 4800 3400
+Wire Wire Line
+	4800 3400 1050 3400
+Wire Wire Line
+	5950 3450 5950 4450
+Connection ~ 5950 3450
+Wire Wire Line
+	5950 4550 5450 4550
+Connection ~ 5450 4550
+Wire Wire Line
+	5350 4650 5950 4650
+Connection ~ 5350 3900
+Wire Wire Line
+	5250 4750 5950 4750
+Connection ~ 5250 3150
+Wire Wire Line
+	5950 4850 5100 4850
+Connection ~ 5100 4850
+Wire Wire Line
+	5950 5400 5100 5400
+Connection ~ 5100 5400
+Wire Wire Line
+	5950 5750 5100 5750
+Connection ~ 5100 5750
+Wire Wire Line
+	5950 5000 4800 5000
+Wire Wire Line
+	4800 5000 4800 3550
+Wire Wire Line
+	4800 3550 1050 3550
+Connection ~ 5450 5100
+Wire Wire Line
+	5350 5200 5950 5200
+Connection ~ 5350 4650
+Wire Wire Line
+	5250 5300 5950 5300
+Connection ~ 5250 4750
+Wire Wire Line
+	5950 5950 1800 5950
+Wire Wire Line
+	1800 5950 1800 5100
+Connection ~ 1800 5100
+Wire Wire Line
+	5950 6400 1600 6400
+Wire Wire Line
+	1600 6400 1600 3900
+Connection ~ 1600 3900
+Wire Wire Line
+	5950 6300 5100 6300
+Connection ~ 5100 6300
+Wire Wire Line
+	5350 5550 5950 5550
+Connection ~ 5350 5200
+Wire Wire Line
+	5250 5650 5950 5650
+Connection ~ 5250 5300
+Wire Wire Line
+	3150 5850 5950 5850
+Connection ~ 3150 5250
+Wire Wire Line
+	5250 6100 5950 6100
+Connection ~ 5250 5650
+Wire Wire Line
+	5950 6200 3000 6200
+Wire Wire Line
+	3000 6200 3000 4350
+Wire Wire Line
+	3000 4350 2950 4350
+Connection ~ 2950 4050
+Wire Wire Line
+	8400 3950 5950 3950
+Connection ~ 5950 3950
+Wire Wire Line
+	8400 3750 5100 3750
+Connection ~ 5100 3750
+Wire Wire Line
+	8400 3850 5250 3850
+Connection ~ 5250 3850
+Wire Wire Line
+	8400 4050 5350 4050
+Connection ~ 5350 4050
+Wire Wire Line
+	8400 4150 5450 4150
+Connection ~ 5450 4150
+Wire Wire Line
+	8400 1800 8400 950 
+Wire Wire Line
+	8400 950  7350 950 
+Wire Wire Line
+	8400 1900 8200 1900
+Wire Wire Line
+	8200 1900 8200 1250
+Wire Wire Line
+	8200 1250 7350 1250
+Wire Wire Line
+	8400 2000 8050 2000
+Wire Wire Line
+	8050 2000 8050 1650
+Wire Wire Line
+	8050 1650 7400 1650
+Wire Wire Line
+	7500 2150 7800 2150
+Wire Wire Line
+	7800 2150 7800 2100
+Wire Wire Line
+	7800 2100 8400 2100
+Wire Wire Line
+	8400 2200 7900 2200
+Wire Wire Line
+	7900 2200 7900 2700
+Wire Wire Line
+	7900 2700 7500 2700
+Wire Wire Line
+	7500 3250 8050 3250
+Wire Wire Line
+	8050 3250 8050 2300
+Wire Wire Line
+	8050 2300 8400 2300
+Wire Wire Line
+	8200 5200 8200 4650
+Wire Wire Line
+	8200 4650 6950 4650
+Wire Wire Line
+	8200 5300 8050 5300
+Wire Wire Line
+	8050 5300 8050 5200
+Wire Wire Line
+	8050 5200 6950 5200
+Wire Wire Line
+	8200 5400 7250 5400
+Wire Wire Line
+	7250 5400 7250 5750
+Wire Wire Line
+	7250 5750 6950 5750
+Wire Wire Line
+	6850 6250 6850 5850
+Wire Wire Line
+	6850 5850 7350 5850
+Wire Wire Line
+	7350 5850 7350 5500
+Wire Wire Line
+	7350 5500 8200 5500
+Wire Wire Line
+	6800 6950 6950 6950
+Wire Wire Line
+	6950 6950 6950 6200
+Wire Wire Line
+	6950 6200 7950 6200
+Wire Wire Line
+	7950 6200 7950 5700
+Wire Wire Line
+	7950 5700 8200 5700
+$Comp
+L PORT U1
+U 4 1 5C9A8539
+P 850 1350
+F 0 "U1" H 900 1450 30  0000 C CNN
+F 1 "PORT" H 850 1350 30  0000 C CNN
+F 2 "" H 850 1350 60  0000 C CNN
+F 3 "" H 850 1350 60  0000 C CNN
+	4    850  1350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A8668
+P 850 1550
+F 0 "U1" H 900 1650 30  0000 C CNN
+F 1 "PORT" H 850 1550 30  0000 C CNN
+F 2 "" H 850 1550 60  0000 C CNN
+F 3 "" H 850 1550 60  0000 C CNN
+	5    850  1550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1100 1550 1100 1450
+$Comp
+L PORT U1
+U 6 1 5C9A8815
+P 950 2650
+F 0 "U1" H 1000 2750 30  0000 C CNN
+F 1 "PORT" H 950 2650 30  0000 C CNN
+F 2 "" H 950 2650 60  0000 C CNN
+F 3 "" H 950 2650 60  0000 C CNN
+	6    950  2650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1200 2650 1200 2750
+$Comp
+L PORT U1
+U 7 1 5C9A8B82
+P 950 2850
+F 0 "U1" H 1000 2950 30  0000 C CNN
+F 1 "PORT" H 950 2850 30  0000 C CNN
+F 2 "" H 950 2850 60  0000 C CNN
+F 3 "" H 950 2850 60  0000 C CNN
+	7    950  2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5C9A8C46
+P 950 3900
+F 0 "U1" H 1000 4000 30  0000 C CNN
+F 1 "PORT" H 950 3900 30  0000 C CNN
+F 2 "" H 950 3900 60  0000 C CNN
+F 3 "" H 950 3900 60  0000 C CNN
+	8    950  3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5C9A8D2C
+P 950 4100
+F 0 "U1" H 1000 4200 30  0000 C CNN
+F 1 "PORT" H 950 4100 30  0000 C CNN
+F 2 "" H 950 4100 60  0000 C CNN
+F 3 "" H 950 4100 60  0000 C CNN
+	9    950  4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5C9A8DBD
+P 1000 5100
+F 0 "U1" H 1050 5200 30  0000 C CNN
+F 1 "PORT" H 1000 5100 30  0000 C CNN
+F 2 "" H 1000 5100 60  0000 C CNN
+F 3 "" H 1000 5100 60  0000 C CNN
+	10   1000 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5C9A8E65
+P 1000 5300
+F 0 "U1" H 1050 5400 30  0000 C CNN
+F 1 "PORT" H 1000 5300 30  0000 C CNN
+F 2 "" H 1000 5300 60  0000 C CNN
+F 3 "" H 1000 5300 60  0000 C CNN
+	11   1000 5300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A8EEE
+P 800 3150
+F 0 "U1" H 850 3250 30  0000 C CNN
+F 1 "PORT" H 800 3150 30  0000 C CNN
+F 2 "" H 800 3150 60  0000 C CNN
+F 3 "" H 800 3150 60  0000 C CNN
+	1    800  3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A8F9C
+P 800 3400
+F 0 "U1" H 850 3500 30  0000 C CNN
+F 1 "PORT" H 800 3400 30  0000 C CNN
+F 2 "" H 800 3400 60  0000 C CNN
+F 3 "" H 800 3400 60  0000 C CNN
+	2    800  3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A9031
+P 800 3600
+F 0 "U1" H 850 3700 30  0000 C CNN
+F 1 "PORT" H 800 3600 30  0000 C CNN
+F 2 "" H 800 3600 60  0000 C CNN
+F 3 "" H 800 3600 60  0000 C CNN
+	3    800  3600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1050 3250 1050 3150
+Wire Wire Line
+	1050 3550 1050 3600
+Wire Wire Line
+	1350 4000 1350 4100
+Wire Wire Line
+	1350 4100 1200 4100
+Wire Wire Line
+	9550 2050 9850 2050
+Wire Wire Line
+	9400 3950 9850 3950
+Wire Wire Line
+	9350 5450 9900 5450
+$Comp
+L PORT U1
+U 12 1 5C9A9B26
+P 10100 2050
+F 0 "U1" H 10150 2150 30  0000 C CNN
+F 1 "PORT" H 10100 2050 30  0000 C CNN
+F 2 "" H 10100 2050 60  0000 C CNN
+F 3 "" H 10100 2050 60  0000 C CNN
+	12   10100 2050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5C9A9BCA
+P 10100 3950
+F 0 "U1" H 10150 4050 30  0000 C CNN
+F 1 "PORT" H 10100 3950 30  0000 C CNN
+F 2 "" H 10100 3950 60  0000 C CNN
+F 3 "" H 10100 3950 60  0000 C CNN
+	13   10100 3950
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5C9A9CA0
+P 10150 5450
+F 0 "U1" H 10200 5550 30  0000 C CNN
+F 1 "PORT" H 10150 5450 30  0000 C CNN
+F 2 "" H 10150 5450 60  0000 C CNN
+F 3 "" H 10150 5450 60  0000 C CNN
+	14   10150 5450
+	-1   0    0    1   
+$EndComp
+Text Notes 9650 2000 0    60   ~ 12
+A>B
+Text Notes 9600 3900 0    60   ~ 12
+A=B\n
+Text Notes 9600 5400 0    60   ~ 12
+A<B\n
+Text Notes 1250 5100 0    60   ~ 12
+A0
+Text Notes 1200 5400 0    60   ~ 12
+B0
+Text Notes 1300 3900 2    60   ~ 12
+A1
+Text Notes 1300 4200 2    60   ~ 12
+B1
+Text Notes 1250 3250 2    60   ~ 12
+A<B
+Text Notes 1250 3400 2    60   ~ 12
+A=B
+Text Notes 1250 3550 2    60   ~ 12
+A>B
+Text Notes 1350 2750 2    60   ~ 12
+A2
+Text Notes 1350 2950 2    60   ~ 12
+B2
+Text Notes 1300 1350 2    60   ~ 12
+A3
+Text Notes 1300 1550 2    60   ~ 12
+B3
+Wire Wire Line
+	8200 5600 7450 5600
+Wire Wire Line
+	7450 5600 7450 6050
+Wire Wire Line
+	7450 6050 6900 6050
+Wire Wire Line
+	6800 6650 6800 6300
+Wire Wire Line
+	6800 6300 6900 6300
+Wire Wire Line
+	6900 6300 6900 6050
+Wire Notes Line
+	500  3000 1350 3000
+Wire Notes Line
+	1350 3000 1350 3750
+Wire Notes Line
+	1350 3750 500  3750
+Wire Notes Line
+	500  3750 500  3000
+Text Notes 600  3000 3    60   ~ 12
+Cascading Inputs
+Wire Notes Line
+	9500 1550 9500 6050
+Wire Notes Line
+	9500 6050 10550 6050
+Wire Notes Line
+	10550 6050 10550 1550
+Wire Notes Line
+	10550 1550 9500 1550
+Text Notes 9900 3400 0    60   ~ 12
+Outputs
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib
index e83bf18b..05fb44d7 100644
--- a/src/SubcircuitLibrary/7485/c_gate-cache.lib
+++ b/src/SubcircuitLibrary/7485/c_gate-cache.lib
@@ -1,95 +1,95 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0  1050 1150  1450 1150 N
-P 3 0 1 0  1050 1150  1050 650  1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 1350 800 60 H V C CNN
+F1 "5_and" 1400 1050 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
+P 2 0 1 0  1050 1150  1450 1150 N
+P 3 0 1 0  1050 1150  1050 650  1450 650 N
+X in1 1 850 1100 200 R 50 50 1 1 I
+X in2 2 850 1000 200 R 50 50 1 1 I
+X in3 3 850 900 200 R 50 50 1 1 I
+X in4 4 850 800 200 R 50 50 1 1 I
+X in5 5 850 700 200 R 50 50 1 1 I
+X out 6 1850 900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir
index 865e4229..1ac12515 100644
--- a/src/SubcircuitLibrary/7485/c_gate.cir
+++ b/src/SubcircuitLibrary/7485/c_gate.cir
@@ -1,19 +1,19 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and		
-U8  Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
-U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter		
-U6  Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter		
-U7  Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and		
+U8  Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and		
+U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
+U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
+U5  Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter		
+U6  Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter		
+U7  Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out
index 249e9b8f..db7bb2f8 100644
--- a/src/SubcircuitLibrary/7485/c_gate.cir.out
+++ b/src/SubcircuitLibrary/7485/c_gate.cir.out
@@ -1,42 +1,42 @@
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro
index 0ac5f7d7..f0743529 100644
--- a/src/SubcircuitLibrary/7485/c_gate.pro
+++ b/src/SubcircuitLibrary/7485/c_gate.pro
@@ -1,57 +1,57 @@
-update=03/26/19 19:06:59
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-[general]
-version=1
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-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
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-LibName2=intel
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-LibName5=digital-audio
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-LibName9=siliconi
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-LibName11=atmel
-LibName12=contrib
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-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
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-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
+update=03/26/19 19:06:59
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=texas
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch
index 8205ff7f..5d960c8d 100644
--- a/src/SubcircuitLibrary/7485/c_gate.sch
+++ b/src/SubcircuitLibrary/7485/c_gate.sch
@@ -1,246 +1,246 @@
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-LIBS:texas
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-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
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-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:c_gate-cache
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+$Comp
+L PORT U1
+U 5 1 5C9A3052
+P 1800 3150
+F 0 "U1" H 1850 3250 30  0000 C CNN
+F 1 "PORT" H 1800 3150 30  0000 C CNN
+F 2 "" H 1800 3150 60  0000 C CNN
+F 3 "" H 1800 3150 60  0000 C CNN
+	5    1800 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A308D
+P 1800 3300
+F 0 "U1" H 1850 3400 30  0000 C CNN
+F 1 "PORT" H 1800 3300 30  0000 C CNN
+F 2 "" H 1800 3300 60  0000 C CNN
+F 3 "" H 1800 3300 60  0000 C CNN
+	6    1800 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5C9A30DD
+P 7200 3250
+F 0 "U1" H 7250 3350 30  0000 C CNN
+F 1 "PORT" H 7200 3250 30  0000 C CNN
+F 2 "" H 7200 3250 60  0000 C CNN
+F 3 "" H 7200 3250 60  0000 C CNN
+	7    7200 3250
+	-1   0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub
index e7138794..c6eaa478 100644
--- a/src/SubcircuitLibrary/7485/c_gate.sub
+++ b/src/SubcircuitLibrary/7485/c_gate.sub
@@ -1,36 +1,36 @@
-* Subcircuit c_gate
-.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit c_gate
+.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends c_gate
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib
new file mode 100644
index 00000000..cc25b0c9
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib
@@ -0,0 +1,146 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
new file mode 100644
index 00000000..44f1df81
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
@@ -0,0 +1,15 @@
+* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_M1-Pad2_ Net-_C1-Pad1_ PORT		
+M1  Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
+M2  Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P		
+v1  Net-_M2-Pad1_ GND 5		
+C1  Net-_C1-Pad1_ GND 1u		
+
+.end
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out
new file mode 100644
index 00000000..cb2b6641
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out
@@ -0,0 +1,18 @@
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+* u1  net-_m1-pad2_ net-_c1-pad1_ port
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1  net-_m2-pad1_ gnd 5
+c1  net-_c1-pad1_ gnd 1u
+.tran 0e-03 0e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro
new file mode 100644
index 00000000..b3f410b6
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro
@@ -0,0 +1,73 @@
+update=Sun Aug 25 15:54:56 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_User
+LibName37=eSim_Plot
+LibName38=eSim_PSpice
+LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
+
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch
new file mode 100644
index 00000000..13a7fc09
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch
@@ -0,0 +1,189 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:eSim_Subckt
+LIBS:INVCMOS-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "29 apr 2015"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	5900 4000 5900 4150
+Connection ~ 5800 2450
+Connection ~ 5800 4150
+Wire Wire Line
+	5900 4150 5800 4150
+Connection ~ 5050 3350
+Wire Wire Line
+	4000 3350 5050 3350
+Wire Wire Line
+	5050 3850 5500 3850
+Wire Wire Line
+	5050 2700 5050 3850
+Wire Wire Line
+	5050 2700 5500 2700
+Wire Wire Line
+	5800 3650 5800 2900
+Wire Wire Line
+	5800 2500 5800 2300
+Connection ~ 4200 3350
+$Comp
+L PORT U1
+U 1 1 5D6263BC
+P 3750 3350
+F 0 "U1" H 3800 3450 30  0000 C CNN
+F 1 "PORT" H 3750 3350 30  0000 C CNN
+F 2 "" H 3750 3350 60  0000 C CNN
+F 3 "" H 3750 3350 60  0000 C CNN
+	1    3750 3350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 3250 5800 3250
+Connection ~ 5800 3250
+Wire Wire Line
+	5800 4050 5800 4550
+$Comp
+L eSim_MOS_N M1
+U 1 1 5D6265DB
+P 5600 3650
+F 0 "M1" H 5600 3500 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5700 3600 50  0000 R CNN
+F 2 "" H 5900 3350 29  0000 C CNN
+F 3 "" H 5700 3450 60  0000 C CNN
+	1    5600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 5D626659
+P 5650 2700
+F 0 "M2" H 5600 2750 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5700 2850 50  0000 R CNN
+F 2 "" H 5900 2800 29  0000 C CNN
+F 3 "" H 5700 2700 60  0000 C CNN
+	1    5650 2700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5900 2850 6050 2850
+Wire Wire Line
+	6050 2850 6050 2450
+Wire Wire Line
+	6050 2450 5800 2450
+Connection ~ 6000 3250
+Connection ~ 5800 4300
+$Comp
+L GND #PWR1
+U 1 1 5D626C59
+P 5800 4550
+F 0 "#PWR1" H 5800 4300 50  0001 C CNN
+F 1 "GND" H 5800 4400 50  0000 C CNN
+F 2 "" H 5800 4550 50  0001 C CNN
+F 3 "" H 5800 4550 50  0001 C CNN
+	1    5800 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v1
+U 1 1 5D626C7F
+P 6250 2300
+F 0 "v1" H 6050 2400 60  0000 C CNN
+F 1 "5" H 6050 2250 60  0000 C CNN
+F 2 "R1" H 5950 2300 60  0000 C CNN
+F 3 "" H 6250 2300 60  0000 C CNN
+	1    6250 2300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L GND #PWR2
+U 1 1 5D626CF6
+P 6850 2300
+F 0 "#PWR2" H 6850 2050 50  0001 C CNN
+F 1 "GND" H 6850 2150 50  0000 C CNN
+F 2 "" H 6850 2300 50  0001 C CNN
+F 3 "" H 6850 2300 50  0001 C CNN
+	1    6850 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6850 2300 6700 2300
+$Comp
+L PORT U1
+U 2 1 5D626DCB
+P 6300 3250
+F 0 "U1" H 6350 3350 30  0000 C CNN
+F 1 "PORT" H 6300 3250 30  0000 C CNN
+F 2 "" H 6300 3250 60  0000 C CNN
+F 3 "" H 6300 3250 60  0000 C CNN
+	2    6300 3250
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 5D62796C
+P 6050 3850
+F 0 "C1" H 6075 3950 50  0000 L CNN
+F 1 "1u" H 6075 3750 50  0000 L CNN
+F 2 "" H 6088 3700 30  0000 C CNN
+F 3 "" H 6050 3850 60  0000 C CNN
+	1    6050 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 3700 6050 3400
+Wire Wire Line
+	6050 3400 6000 3400
+Wire Wire Line
+	6000 3400 6000 3250
+Wire Wire Line
+	6050 4000 6050 4300
+Wire Wire Line
+	6050 4300 5800 4300
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub
new file mode 100644
index 00000000..2319995c
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub
@@ -0,0 +1,12 @@
+* Subcircuit INVCMOS
+.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ 
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1  net-_m2-pad1_ gnd 5
+c1  net-_c1-pad1_ gnd 1u
+* Control Statements
+
+.ends INVCMOS
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml
new file mode 100644
index 00000000..e5bb98c7
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/SubcircuitLibrary/INVCMOS/analysis b/src/SubcircuitLibrary/INVCMOS/analysis
new file mode 100644
index 00000000..334c5333
--- /dev/null
+++ b/src/SubcircuitLibrary/INVCMOS/analysis
@@ -0,0 +1 @@
+.tran 0e-03 0e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib
new file mode 100644
index 00000000..c02b3211
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib
@@ -0,0 +1,135 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN-RESCUE-LM7812
+#
+DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP-RESCUE-LM7812
+#
+DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib
new file mode 100644
index 00000000..e6cfa7d6
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib
@@ -0,0 +1,42 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# eSim_NPN-RESCUE-LM7812
+#
+DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP-RESCUE-LM7812
+#
+DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir b/src/SubcircuitLibrary/LM7812/LM7812.cir
new file mode 100644
index 00000000..3f0d3adf
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812.cir
@@ -0,0 +1,51 @@
+* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1  Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k		
+R2  Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500		
+R3  Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k		
+R4  Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k		
+U1  Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R5  Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500		
+Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+Q4  Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN		
+R6  Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k		
+Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R7  Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k		
+Q6  Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN		
+R10  Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k		
+Q7  Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN		
+Q8  Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN		
+Q12  Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
+R12  Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k		
+R9  Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k		
+Q5  Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP		
+Q9  Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP		
+R8  Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100		
+R11  Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50		
+Q10  Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+Q11  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN		
+Q13  Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN		
+R13  Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
+R14  Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k		
+Q14  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP		
+Q15  Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN		
+R17  Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k		
+R16  Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k		
+R15  Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k		
+U2  Net-_Q15-Pad2_ Net-_R15-Pad2_ zener		
+Q16  Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN		
+Q17  Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN		
+R18  Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200		
+R20  Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3		
+R19  Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240		
+U3  Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir.out b/src/SubcircuitLibrary/LM7812/LM7812.cir.out
new file mode 100644
index 00000000..73404965
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812.cir.out
@@ -0,0 +1,60 @@
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir
+
+.include PNP.lib
+.include NPN.lib
+r1  net-_q16-pad1_ net-_q1-pad2_ 100k
+r2  net-_q16-pad1_ net-_q1-pad1_ 500
+r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
+* u1  net-_q10-pad3_ net-_q1-pad2_ zener
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r5  net-_q10-pad2_ net-_q10-pad3_ 500
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
+r6  net-_q2-pad3_ net-_q3-pad1_ 1k
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
+r7  net-_q3-pad2_ net-_q10-pad3_ 6k
+q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
+r10  net-_q6-pad3_ net-_q10-pad3_ 1k
+q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r12  net-_q12-pad3_ net-_q2-pad3_ 6k
+r9  net-_q2-pad3_ net-_c1-pad2_ 20k
+q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
+q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
+r8  net-_q16-pad1_ net-_q5-pad3_ 100
+r11  net-_q16-pad1_ net-_q9-pad3_ 50
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
+r13  net-_q11-pad3_ net-_q10-pad3_ 6k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+r14  net-_q10-pad1_ net-_c1-pad1_ 6k
+q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
+q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
+r17  net-_q12-pad2_ net-_q10-pad3_ 5k
+r16  net-_q12-pad1_ net-_q12-pad2_ 10.38k
+r15  net-_q16-pad1_ net-_r15-pad2_ 10k
+* u2  net-_q15-pad2_ net-_r15-pad2_ zener
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r18  net-_q16-pad3_ net-_q12-pad1_ 200
+r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
+r19  net-_q17-pad3_ net-_q15-pad2_ 240
+* u3  net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port
+a1 net-_q10-pad3_ net-_q1-pad2_ u1
+a2 net-_q15-pad2_ net-_r15-pad2_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.pro b/src/SubcircuitLibrary/LM7812/LM7812.pro
new file mode 100644
index 00000000..12d08139
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812.pro
@@ -0,0 +1,46 @@
+update=Mon Aug 26 14:09:03 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=LM7812-rescue
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
+
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sch b/src/SubcircuitLibrary/LM7812/LM7812.sch
new file mode 100644
index 00000000..ca95c2ca
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812.sch
@@ -0,0 +1,758 @@
+EESchema Schematic File Version 2
+LIBS:LM7812-rescue
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:LM7812-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+$EndComp
+$Comp
+L eSim_NPN-RESCUE-LM7812 Q17
+U 1 1 5CE4942E
+P 7300 1950
+F 0 "Q17" H 7200 2000 50  0000 R CNN
+F 1 "eSim_NPN" H 7250 2100 50  0000 R CNN
+F 2 "" H 7500 2050 29  0000 C CNN
+F 3 "" H 7300 1950 60  0000 C CNN
+	1    7300 1950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6650 1800 6650 2300
+Wire Wire Line
+	6650 1950 7100 1950
+Wire Wire Line
+	7400 1050 7400 1750
+Connection ~ 5850 1050
+Wire Wire Line
+	6650 1400 6650 1050
+Connection ~ 6650 1050
+$Comp
+L R R18
+U 1 1 5CE498BA
+P 6650 2450
+F 0 "R18" V 6730 2450 50  0000 C CNN
+F 1 "200" V 6650 2450 50  0000 C CNN
+F 2 "" V 6580 2450 50  0001 C CNN
+F 3 "" H 6650 2450 50  0001 C CNN
+	1    6650 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R20
+U 1 1 5CE4999A
+P 7400 2450
+F 0 "R20" V 7480 2450 50  0000 C CNN
+F 1 "0.3" V 7400 2450 50  0000 C CNN
+F 2 "" V 7330 2450 50  0001 C CNN
+F 3 "" H 7400 2450 50  0001 C CNN
+	1    7400 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R19
+U 1 1 5CE49AF5
+P 7000 2250
+F 0 "R19" V 7080 2250 50  0000 C CNN
+F 1 "240" V 7000 2250 50  0000 C CNN
+F 2 "" V 6930 2250 50  0001 C CNN
+F 3 "" H 7000 2250 50  0001 C CNN
+	1    7000 2250
+	0    1    1    0   
+$EndComp
+Connection ~ 6650 1950
+Wire Wire Line
+	5850 2250 6850 2250
+Connection ~ 5850 2150
+Wire Wire Line
+	7400 2150 7400 2300
+Wire Wire Line
+	7150 2250 7400 2250
+Connection ~ 7400 2250
+Wire Wire Line
+	6100 2600 6100 2650
+Wire Wire Line
+	6100 2650 7400 2650
+Wire Wire Line
+	7400 2650 7400 2600
+Connection ~ 6050 2600
+Wire Wire Line
+	6650 2600 6650 2650
+Connection ~ 6650 2650
+$Comp
+L PORT U3
+U 1 1 5CE4AAF6
+P 8050 1050
+F 0 "U3" H 8100 1150 30  0000 C CNN
+F 1 "PORT" H 8050 1050 30  0000 C CNN
+F 2 "" H 8050 1050 60  0000 C CNN
+F 3 "" H 8050 1050 60  0000 C CNN
+	1    8050 1050
+	-1   0    0    1   
+$EndComp
+Connection ~ 7400 1050
+$Comp
+L PORT U3
+U 3 1 5CE4B13E
+P 7700 3000
+F 0 "U3" H 7750 3100 30  0000 C CNN
+F 1 "PORT" H 7700 3000 30  0000 C CNN
+F 2 "" H 7700 3000 60  0000 C CNN
+F 3 "" H 7700 3000 60  0000 C CNN
+	3    7700 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U3
+U 2 1 5CE4B701
+P 6650 5300
+F 0 "U3" H 6700 5400 30  0000 C CNN
+F 1 "PORT" H 6650 5300 30  0000 C CNN
+F 2 "" H 6650 5300 60  0000 C CNN
+F 3 "" H 6650 5300 60  0000 C CNN
+	2    6650 5300
+	-1   0    0    1   
+$EndComp
+Connection ~ 6050 5300
+Wire Wire Line
+	6350 1600 5950 1600
+Wire Wire Line
+	5950 1600 5950 1550
+Wire Wire Line
+	5950 1550 5000 1550
+Wire Wire Line
+	5000 1550 5000 1950
+Connection ~ 5000 1950
+Wire Wire Line
+	7300 2650 7300 3000
+Wire Wire Line
+	7300 3000 7450 3000
+Connection ~ 7300 2650
+Connection ~ 2500 5200
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sub b/src/SubcircuitLibrary/LM7812/LM7812.sub
new file mode 100644
index 00000000..0dd95154
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812.sub
@@ -0,0 +1,54 @@
+* Subcircuit LM7812
+.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ 
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir
+.include PNP.lib
+.include NPN.lib
+r1  net-_q16-pad1_ net-_q1-pad2_ 100k
+r2  net-_q16-pad1_ net-_q1-pad1_ 500
+r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
+* u1  net-_q10-pad3_ net-_q1-pad2_ zener
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r5  net-_q10-pad2_ net-_q10-pad3_ 500
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
+r6  net-_q2-pad3_ net-_q3-pad1_ 1k
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
+r7  net-_q3-pad2_ net-_q10-pad3_ 6k
+q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
+r10  net-_q6-pad3_ net-_q10-pad3_ 1k
+q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r12  net-_q12-pad3_ net-_q2-pad3_ 6k
+r9  net-_q2-pad3_ net-_c1-pad2_ 20k
+q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
+q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
+r8  net-_q16-pad1_ net-_q5-pad3_ 100
+r11  net-_q16-pad1_ net-_q9-pad3_ 50
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
+r13  net-_q11-pad3_ net-_q10-pad3_ 6k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+r14  net-_q10-pad1_ net-_c1-pad1_ 6k
+q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
+q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
+r17  net-_q12-pad2_ net-_q10-pad3_ 5k
+r16  net-_q12-pad1_ net-_q12-pad2_ 10.38k
+r15  net-_q16-pad1_ net-_r15-pad2_ 10k
+* u2  net-_q15-pad2_ net-_r15-pad2_ zener
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r18  net-_q16-pad3_ net-_q12-pad1_ 200
+r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
+r19  net-_q17-pad3_ net-_q15-pad2_ 240
+a1 net-_q10-pad3_ net-_q1-pad2_ u1
+a2 net-_q15-pad2_ net-_r15-pad2_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
+* Control Statements
+
+.ends LM7812
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml
new file mode 100644
index 00000000..263f360c
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/NPN.lib b/src/SubcircuitLibrary/LM7812/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/LM7812/PNP.lib b/src/SubcircuitLibrary/LM7812/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/LM7812/Q_PNP.lib b/src/SubcircuitLibrary/LM7812/Q_PNP.lib
new file mode 100644
index 00000000..154ed2d8
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/Q_PNP.lib
@@ -0,0 +1 @@
+.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/analysis b/src/SubcircuitLibrary/LM7812/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/LM7812/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
new file mode 100644
index 00000000..623a7f41
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro
index 0bd0d5af..c0db0775 100644
--- a/src/SubcircuitLibrary/full_adder/full_adder.pro
+++ b/src/SubcircuitLibrary/full_adder/full_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
 LibName28=atmel
 LibName29=contrib
 LibName30=valves
-LibName31=eSim_Analog
-LibName32=eSim_Devices
-LibName33=eSim_Digital
-LibName34=eSim_Hybrid
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
new file mode 100644
index 00000000..68785220
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  150 -50  -200 -50 N
+P 2 0 1 0  150 150  -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro
index 30094fb9..695ae0f6 100644
--- a/src/SubcircuitLibrary/full_adder/half_adder.pro
+++ b/src/SubcircuitLibrary/full_adder/half_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
 LibName28=atmel
 LibName29=contrib
 LibName30=valves
-LibName31=eSim_Analog
-LibName32=eSim_Devices
-LibName33=eSim_Digital
-LibName34=eSim_Hybrid
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
index f874f5e2..6949ac1a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
+++ b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
@@ -1,79 +1,79 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_sub
-#
-DEF half_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 300 300 -300 0 1 0 N
-X A 1 -500 200 200 R 50 50 1 1 I
-X B 2 -500 -100 200 R 50 50 1 1 I
-X D 3 500 150 200 L 50 50 1 1 O
-X BORROW 4 500 -100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_sub
+#
+DEF half_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "half_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 300 300 -300 0 1 0 N
+X A 1 -500 200 200 R 50 50 1 1 I
+X B 2 -500 -100 200 R 50 50 1 1 I
+X D 3 500 150 200 L 50 50 1 1 O
+X BORROW 4 500 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
index 416747ef..803b5ece 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
+++ b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
@@ -1,20 +1,20 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# half_sub-RESCUE-full_sub
-#
-DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -1450 850 1550 -1050 0 1 0 N
-X A 1 -1100 850 200 R 50 50 1 1 I
-X B 2 -350 850 200 R 50 50 1 1 I
-X D 3 -800 -1050 200 L 50 50 1 1 O
-X BORROW 4 0 -1050 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# half_sub-RESCUE-full_sub
+#
+DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -1450 850 1550 -1050 0 1 0 N
+X A 1 -1100 850 200 R 50 50 1 1 I
+X B 2 -350 850 200 R 50 50 1 1 I
+X D 3 -800 -1050 200 L 50 50 1 1 O
+X BORROW 4 0 -1050 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir
index 7d6f198f..67359421 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir
+++ b/src/SubcircuitLibrary/full_sub/full_sub.cir
@@ -1,14 +1,14 @@
-* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or		
-U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT		
-X1  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub		
-X2  Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub		
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or		
+U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT		
+X1  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub		
+X2  Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub		
+
+.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out
index e310dcd0..5e58cc0a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out
+++ b/src/SubcircuitLibrary/full_sub/full_sub.cir.out
@@ -1,19 +1,19 @@
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+
+.include half_sub.sub
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro
index 3336e88e..1a0c3543 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.pro
+++ b/src/SubcircuitLibrary/full_sub/full_sub.pro
@@ -1,74 +1,74 @@
-update=03/07/19 10:55:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=full_sub-rescue
-LibName2=adc-dac
-LibName3=memory
-LibName4=xilinx
-LibName5=microcontrollers
-LibName6=dsp
-LibName7=microchip
-LibName8=analog_switches
-LibName9=motorola
-LibName10=texas
-LibName11=intel
-LibName12=audio
-LibName13=interface
-LibName14=digital-audio
-LibName15=philips
-LibName16=display
-LibName17=cypress
-LibName18=siliconi
-LibName19=opto
-LibName20=atmel
-LibName21=contrib
-LibName22=power
-LibName23=device
-LibName24=transistors
-LibName25=conn
-LibName26=linear
-LibName27=regul
-LibName28=74xx
-LibName29=cmos4000
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Power
-LibName36=eSim_Sources
-LibName37=eSim_Subckt
-LibName38=eSim_User
-LibName39=eSim_Plot
-LibName40=eSim_PSpice
-
+update=03/07/19 10:55:03
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=full_sub-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=device
+LibName24=transistors
+LibName25=conn
+LibName26=linear
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_User
+LibName39=eSim_Plot
+LibName40=eSim_PSpice
+
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch
index ed8ac50d..99ca85e5 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.sch
+++ b/src/SubcircuitLibrary/full_sub/full_sub.sch
@@ -1,211 +1,211 @@
-EESchema Schematic File Version 2
-LIBS:full_sub-rescue
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:full_sub-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-Date ""
-Rev ""
-Comp ""
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-Comment4 ""
-$EndDescr
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-U 1 1 5C80A4E8
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-F 1 "PORT" H 1200 3450 30  0000 C CNN
-F 2 "" H 1200 3450 60  0000 C CNN
-F 3 "" H 1200 3450 60  0000 C CNN
-	1    1200 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 2 1 5C80A51E
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-F 2 "" H 1200 3650 60  0000 C CNN
-F 3 "" H 1200 3650 60  0000 C CNN
-	2    1200 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 3 1 5C80A54E
-P 3800 5100
-F 0 "U5" H 3850 5200 30  0000 C CNN
-F 1 "PORT" H 3800 5100 30  0000 C CNN
-F 2 "" H 3800 5100 60  0000 C CNN
-F 3 "" H 3800 5100 60  0000 C CNN
-	3    3800 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 5 1 5C80A828
-P 11000 4800
-F 0 "U5" H 11050 4900 30  0000 C CNN
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-F 2 "" H 11000 4800 60  0000 C CNN
-F 3 "" H 11000 4800 60  0000 C CNN
-	5    11000 4800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 4 1 5C80AB2A
-P 11000 4950
-F 0 "U5" H 11050 5050 30  0000 C CNN
-F 1 "PORT" H 11000 4950 30  0000 C CNN
-F 2 "" H 11000 4950 60  0000 C CNN
-F 3 "" H 11000 4950 60  0000 C CNN
-	4    11000 4950
-	-1   0    0    1   
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-U 1 1 5C80AC4D
-P 3800 3450
-F 0 "X1" H 3800 3450 60  0000 C CNN
-F 1 "half_sub" H 3800 3450 60  0000 C CNN
-F 2 "" H 3800 3450 60  0001 C CNN
-F 3 "" H 3800 3450 60  0001 C CNN
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-U 1 1 5C80AD72
-P 7300 5150
-F 0 "X2" H 7300 5150 60  0000 C CNN
-F 1 "half_sub" H 7300 5150 60  0000 C CNN
-F 2 "" H 7300 5150 60  0001 C CNN
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+EESchema Schematic File Version 2
+LIBS:full_sub-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:full_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U3
+U 1 1 5C80734A
+P 9350 4050
+F 0 "U3" H 9350 4050 60  0000 C CNN
+F 1 "d_or" H 9350 4150 60  0000 C CNN
+F 2 "" H 9350 4050 60  0000 C CNN
+F 3 "" H 9350 4050 60  0000 C CNN
+	1    9350 4050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 3600 5800 3600
+Wire Wire Line
+	4650 2800 8600 2800
+Wire Wire Line
+	8600 2800 8600 3950
+Wire Wire Line
+	8600 3950 8900 3950
+Wire Wire Line
+	8100 4450 8650 4450
+Wire Wire Line
+	8650 4450 8650 4050
+Wire Wire Line
+	8650 4050 8900 4050
+Wire Wire Line
+	2800 3450 2800 3250
+Wire Wire Line
+	2800 3250 3300 3250
+Wire Wire Line
+	1450 3550 3300 3550
+Wire Wire Line
+	4050 5100 5200 5100
+Wire Wire Line
+	5800 3600 5800 5250
+Wire Wire Line
+	8250 5250 9350 5250
+Wire Wire Line
+	9350 5250 9350 4900
+Wire Wire Line
+	9350 4900 10750 4900
+Wire Wire Line
+	9800 4000 9800 4600
+Wire Wire Line
+	9800 4600 9550 4600
+Wire Wire Line
+	9550 4600 9550 4800
+Wire Wire Line
+	9550 4800 10750 4800
+$Comp
+L PORT U5
+U 1 1 5C80A4E8
+P 1200 3450
+F 0 "U5" H 1250 3550 30  0000 C CNN
+F 1 "PORT" H 1200 3450 30  0000 C CNN
+F 2 "" H 1200 3450 60  0000 C CNN
+F 3 "" H 1200 3450 60  0000 C CNN
+	1    1200 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 2 1 5C80A51E
+P 1200 3650
+F 0 "U5" H 1250 3750 30  0000 C CNN
+F 1 "PORT" H 1200 3650 30  0000 C CNN
+F 2 "" H 1200 3650 60  0000 C CNN
+F 3 "" H 1200 3650 60  0000 C CNN
+	2    1200 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 3 1 5C80A54E
+P 3800 5100
+F 0 "U5" H 3850 5200 30  0000 C CNN
+F 1 "PORT" H 3800 5100 30  0000 C CNN
+F 2 "" H 3800 5100 60  0000 C CNN
+F 3 "" H 3800 5100 60  0000 C CNN
+	3    3800 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 5 1 5C80A828
+P 11000 4800
+F 0 "U5" H 11050 4900 30  0000 C CNN
+F 1 "PORT" H 11000 4800 30  0000 C CNN
+F 2 "" H 11000 4800 60  0000 C CNN
+F 3 "" H 11000 4800 60  0000 C CNN
+	5    11000 4800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U5
+U 4 1 5C80AB2A
+P 11000 4950
+F 0 "U5" H 11050 5050 30  0000 C CNN
+F 1 "PORT" H 11000 4950 30  0000 C CNN
+F 2 "" H 11000 4950 60  0000 C CNN
+F 3 "" H 11000 4950 60  0000 C CNN
+	4    11000 4950
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1450 3450 2800 3450
+Wire Wire Line
+	1450 3650 1450 3550
+Wire Wire Line
+	10750 4900 10750 4950
+$Comp
+L half_sub X1
+U 1 1 5C80AC4D
+P 3800 3450
+F 0 "X1" H 3800 3450 60  0000 C CNN
+F 1 "half_sub" H 3800 3450 60  0000 C CNN
+F 2 "" H 3800 3450 60  0001 C CNN
+F 3 "" H 3800 3450 60  0001 C CNN
+	1    3800 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4300 3550 4650 3550
+Wire Wire Line
+	4650 3550 4650 2800
+Wire Wire Line
+	4300 3300 4850 3300
+Wire Wire Line
+	4850 3300 4850 3600
+$Comp
+L half_sub X2
+U 1 1 5C80AD72
+P 7300 5150
+F 0 "X2" H 7300 5150 60  0000 C CNN
+F 1 "half_sub" H 7300 5150 60  0000 C CNN
+F 2 "" H 7300 5150 60  0001 C CNN
+F 3 "" H 7300 5150 60  0001 C CNN
+	1    7300 5150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5800 5250 6800 5250
+Wire Wire Line
+	5200 5100 5200 4950
+Wire Wire Line
+	5200 4950 6800 4950
+Wire Wire Line
+	7800 5000 8250 5000
+Wire Wire Line
+	8250 5000 8250 5250
+Wire Wire Line
+	7800 5250 8100 5250
+Wire Wire Line
+	8100 5250 8100 4450
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub
index ec5698b5..9c9dcc5a 100644
--- a/src/SubcircuitLibrary/full_sub/full_sub.sub
+++ b/src/SubcircuitLibrary/full_sub/full_sub.sub
@@ -1,13 +1,13 @@
-* Subcircuit full_sub
-.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit full_sub
+.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+.include half_sub.sub
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends full_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out
index 95e6e2bd..91816956 100644
--- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out
+++ b/src/SubcircuitLibrary/full_sub/half_sub.cir.out
@@ -1,24 +1,24 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub
index 1931f76e..a61a3409 100644
--- a/src/SubcircuitLibrary/full_sub/half_sub.sub
+++ b/src/SubcircuitLibrary/full_sub/half_sub.sub
@@ -1,18 +1,18 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit half_sub
+.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends half_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
new file mode 100644
index 00000000..68785220
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  150 -50  -200 -50 N
+P 2 0 1 0  150 150  -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro
index 30094fb9..695ae0f6 100644
--- a/src/SubcircuitLibrary/half_adder/half_adder.pro
+++ b/src/SubcircuitLibrary/half_adder/half_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
 LibName28=atmel
 LibName29=contrib
 LibName30=valves
-LibName31=eSim_Analog
-LibName32=eSim_Devices
-LibName33=eSim_Digital
-LibName34=eSim_Hybrid
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out
index 95e6e2bd..91816956 100644
--- a/src/SubcircuitLibrary/half_sub/half_sub.cir.out
+++ b/src/SubcircuitLibrary/half_sub/half_sub.cir.out
@@ -1,24 +1,24 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub
index 1931f76e..a61a3409 100644
--- a/src/SubcircuitLibrary/half_sub/half_sub.sub
+++ b/src/SubcircuitLibrary/half_sub/half_sub.sub
@@ -1,18 +1,18 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit half_sub
+.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
+* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends half_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/NPN.lib b/src/SubcircuitLibrary/lm555n/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis
index 31bc5ccd..a0953567 100644
--- a/src/SubcircuitLibrary/lm555n/analysis
+++ b/src/SubcircuitLibrary/lm555n/analysis
@@ -1 +1 @@
-.ac oct 897897 kjadsfhHz jhdsakjHz
\ No newline at end of file
+.tran 10e-03 100e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib
index 421c1147..824af11e 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib
+++ b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib
@@ -1,147 +1,26 @@
-EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:00:43 AM IST
+EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
-# ADC8
+# GND-RESCUE-lm555n
 #
-DEF ADC8 U 0 10 Y Y 8 L N
-F0 "U" -100 100 40 H V C CNN
-F1 "ADC8" 0 0 40 H V C CNN
-DRAW
-S -150 50 150 -50 0 1 0 N
-X in1 1 -300 0 150 R 25 25 1 1 I
-X out1 9 300 0 150 L 25 25 1 1 O
-X in2 2 -300 0 150 R 25 25 2 1 I
-X out2 10 300 0 150 L 25 25 2 1 O
-X in3 3 -300 0 150 R 25 25 3 1 I
-X out3 11 300 0 150 L 25 25 3 1 O
-X in4 4 -300 0 150 R 25 25 4 1 I
-X out4 12 300 0 150 L 25 25 4 1 O
-X in5 5 -300 0 150 R 25 25 5 1 I
-X out5 13 300 0 150 L 25 25 5 1 O
-X in6 6 -300 0 150 R 25 25 6 1 I
-X out6 14 300 0 150 L 25 25 6 1 O
-X in7 7 -300 0 150 R 25 25 7 1 I
-X out7 15 300 0 150 L 25 25 7 1 O
-X in8 8 -300 0 150 R 25 25 8 1 I
-X out8 16 300 0 150 L 25 25 8 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" -150 100 40 H V C CNN
-F1 "d_inverter" 100 100 40 H V C CNN
-DRAW
-P 4 0 1 0  -100 -100  -100 100  100 0  -100 -100 N
-X in 1 -250 0 150 R 25 25 1 1 I
-X out 2 250 0 150 L 25 25 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# D_SRLatch
-#
-DEF D_SRLatch U 0 40 Y Y 1 F N
-F0 "U" -200 250 60 H V C CNN
-F1 "D_SRLatch" 0 100 60 H V C CNN
-DRAW
-S -300 200 300 -200 0 1 0 N
-X S 1 -600 150 300 R 50 50 1 1 I
-X R 2 -600 -150 300 R 50 50 1 1 I
-X Enable 3 -600 0 300 R 50 50 1 1 I
-X Set 4 150 -500 300 U 50 50 1 1 I
-X Reset 5 -150 -500 300 U 50 50 1 1 I
-X Q 6 600 150 300 L 50 50 1 1 O
-X ~Q 7 600 -150 300 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# DAC8
-#
-DEF DAC8 U 0 10 Y Y 8 L N
-F0 "U" -100 100 40 H V C CNN
-F1 "DAC8" 0 0 40 H V C CNN
-DRAW
-S -150 50 150 -50 0 1 0 N
-X in1 1 -300 0 150 R 25 25 1 1 I
-X out1 9 300 0 150 L 25 25 1 1 O
-X in2 2 -300 0 150 R 25 25 2 1 I
-X out2 10 300 0 150 L 25 25 2 1 O
-X in3 3 -300 0 150 R 25 25 3 1 I
-X out3 11 300 0 150 L 25 25 3 1 O
-X in4 4 -300 0 150 R 25 25 4 1 I
-X out4 12 300 0 150 L 25 25 4 1 O
-X in5 5 -300 0 150 R 25 25 5 1 I
-X out5 13 300 0 150 L 25 25 5 1 O
-X in6 6 -300 0 150 R 25 25 6 1 I
-X out6 14 300 0 150 L 25 25 6 1 O
-X in7 7 -300 0 150 R 25 25 7 1 I
-X out7 15 300 0 150 L 25 25 7 1 O
-X in8 8 -300 0 150 R 25 25 8 1 I
-X out8 16 300 0 150 L 25 25 8 1 O
-ENDDRAW
-ENDDEF
-#
-# GND
-#
-DEF ~GND #PWR 0 0 Y Y 1 F P
+DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P
 F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND" 0 -70 30 H I C CNN
+F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
 DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
 X GND 1 0 0 0 U 30 30 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# LIMIT8
-#
-DEF LIMIT8 U 0 40 Y Y 8 F N
-F0 "U" 0 100 30 H V C CNN
-F1 "LIMIT8" 0 0 30 H V C CNN
-DRAW
-S -150 50 150 -50 0 1 0 N
-X in 1 -300 0 150 R 25 25 1 1 I
-X out 9 300 0 150 L 25 25 1 1 O
-X in 2 -300 0 150 R 25 25 2 1 I
-X out 10 300 0 150 L 25 25 2 1 O
-X in 3 -300 0 150 R 25 25 3 1 I
-X out 11 300 0 150 L 25 25 3 1 O
-X in 4 -300 0 150 R 25 25 4 1 I
-X out 12 300 0 150 L 25 25 4 1 O
-X in 5 -300 0 150 R 25 25 5 1 I
-X out 13 300 0 150 L 25 25 5 1 O
-X in 6 -300 0 150 R 25 25 6 1 I
-X out 14 300 0 150 L 25 25 6 1 O
-X in 7 -300 0 150 R 25 25 7 1 I
-X out 15 300 0 150 L 25 25 7 1 O
-X in 8 -300 0 150 R 25 25 8 1 I
-X out 16 300 0 150 L 25 25 8 1 O
-ENDDRAW
-ENDDEF
-#
-# NPN
-#
-DEF NPN Q 0 0 Y Y 1 F N
-F0 "Q" 0 -150 50 H V R CNN
-F1 "NPN" 0 150 50 H V R CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  0 0  100 100 N
-P 3 0 1 10  0 75  0 -75  0 -75 N
-P 3 0 1 0  50 -50  0 0  0 0 N
-P 3 0 1 0  90 -90  100 -100  100 -100 N
-P 5 0 1 0  90 -90  70 -30  30 -70  90 -90  90 -90 F
-X E 1 100 -200 100 U 40 40 1 1 P
-X B 2 -200 0 200 R 40 40 1 1 I
-X C 3 100 200 100 D 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
 # PORT
 #
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 0 -50 30 H V C CNN
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
 F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
 DRAW
 A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
 A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
@@ -154,26 +33,47 @@ X ~ 5 250 0 100 L 30 30 5 1 B
 X ~ 6 250 0 100 L 30 30 6 1 B
 X ~ 7 250 0 100 L 30 30 7 1 B
 X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
 ENDDRAW
 ENDDEF
 #
 # PWR_FLAG
 #
 DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 270 30 H I C CNN
-F1 "PWR_FLAG" 0 230 30 H V C CNN
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
 DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 3 0 1 0  0 0  0 100  0 100 N
-P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
 ENDDRAW
 ENDDEF
 #
-# R
+# R-RESCUE-lm555n
 #
-DEF R R 0 0 N Y 1 F N
+DEF R-RESCUE-lm555n R 0 0 N Y 1 F N
 F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
+F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
 $FPLIST
  R?
  SM0603
@@ -190,8 +90,10 @@ ENDDEF
 # VCVS
 #
 DEF VCVS E 0 40 Y Y 1 F N
-F0 "E" -200 100 50 H V C CNN
+F0 "E" 0 150 50 H V C CNN
 F1 "VCVS" -200 -50 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
 $FPLIST
  1_pin
 $ENDFPLIST
@@ -204,4 +106,100 @@ X -c 4 50 -200 100 U 35 35 1 1 P
 ENDDRAW
 ENDDEF
 #
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_srlatch
+#
+DEF d_srlatch U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_srlatch" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X S 1 -800 400 200 R 50 50 1 1 I
+X R 2 -800 -450 200 R 50 50 1 1 I
+X EN 3 -800 0 200 R 50 50 1 1 I
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# limit
+#
+DEF limit U 0 40 Y Y 1 F N
+F0 "U" 50 -50 60 H V C CNN
+F1 "limit" 50 50 60 H V C CNN
+F2 "" 0 50 60 H V C CNN
+F3 "" 0 50 60 H V C CNN
+DRAW
+C 300 0 0 0 1 0 N
+P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N
+X IN 1 -400 0 200 R 50 50 1 1 I
+X OUT 2 600 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
 #End Library
diff --git a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib
index 2ed63bd8..fffeca36 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib
+++ b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib
@@ -1,36 +1,17 @@
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
-# GND-RESCUE-lm555n
+# d_inverter-RESCUE-lm555n
 #
-DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
+DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N
+F0 "U" -150 100 40 H V C CNN
+F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
 DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# R-RESCUE-lm555n
-#
-DEF R-RESCUE-lm555n R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- R?
- SM0603
- SM0805
- R?-*
-$ENDFPLIST
-DRAW
-S -40 150 40 -150 0 1 12 N
-X ~ 1 0 250 100 D 60 60 1 1 P
-X ~ 2 0 -250 100 U 60 60 1 1 P
+P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N
+X in 1 -250 0 150 R 25 25 1 1 I
+X out 2 250 0 150 L 25 25 1 1 O I
 ENDDRAW
 ENDDEF
 #
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir
index 144b7152..682d4945 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir
@@ -1,25 +1,31 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:00:36 AM IST
+* /home/ash98/Downloads/lm555n/lm555n.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
-*Sheet Name:/
-U5  5 21 D_INVERTER		
-U6  1 4 5 21 21 8 10 D_SRLATCH		
-E2  18 0 23 14 10000		
-U4  19 20 11 12 LIMIT8		
-U3  8 10 7 9 DAC8		
-U2  11 12 6 4 1 5 ADC8		
-U1  22 14 7 6 15 16 3 13 PORT		
-R8  9 2 1500		
-Q1  22 2 3 QNOM		
-R7  18 20 25		
-R6  17 19 25		
-E1  17 0 16 15 10000		
-R4  16 15 2E6		
-R5  23 14 2E6		
-R3  23 22 5000		
-R2  15 23 5000		
-R1  13 15 5000		
+* Sheet Name: /
+E2  Net-_E2-Pad1_ GND /c /d 10000		
+U1  Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT		
+R8  Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500		
+R7  Net-_E2-Pad1_ Net-_R7-Pad2_ 25		
+R6  Net-_E1-Pad1_ Net-_R6-Pad2_ 25		
+E1  Net-_E1-Pad1_ GND /b /a 10000		
+R4  /b /a 2E6		
+R5  /c /d 2E6		
+R3  /c Net-_Q1-Pad3_ 5000		
+R2  /a /c 5000		
+R1  Net-_R1-Pad1_ /a 5000		
+U8  Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch		
+U7  Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter		
+U5  Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1		
+U4  Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1		
+U6  Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1		
+U3  Net-_R7-Pad2_ Net-_U3-Pad2_ limit		
+U2  Net-_R6-Pad2_ Net-_U2-Pad2_ limit		
+U9  Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1		
+U10  Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
 
 .end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
index f45920fd..a81070a1 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
@@ -1,5 +1,5 @@
 * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
-
+.include npn_1.lib
 * Inverter d_inverter
 * SR Latch d_srlatch
 e2  18 0 23 14 10000
@@ -8,7 +8,7 @@ e2  18 0 23 14 10000
 * Analog to Digital converter adc8
 u1  22 14 7 6 15 16 3 13 port
 r8  9 2 1500
-q1 3 2 22 qnom
+q1 3 2 22 npn_1
 r7  18 20 25
 r6  17 19 25
 e1  17 0 16 15 10000
@@ -33,3 +33,10 @@ a7 [11] [4] u2
 a8 [12] [1] u2
 a9 [6] [5] u2
 .model u2 adc_bridge(in_low=0.8 in_high=2.0 )
+
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro
index 1a966cc5..0a5408b6 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.pro
+++ b/src/SubcircuitLibrary/lm555n/lm555n.pro
@@ -1,8 +1,8 @@
-update=Thu May 19 16:58:03 2016
+update=Tue Apr  2 17:35:59 2019
 last_client=eeschema
 [eeschema]
 version=1
-LibDir=
+LibDir=/home/yogesh/FreeEDA/library
 [eeschema/libraries]
 LibName1=lm555n-rescue
 LibName2=power
@@ -44,3 +44,14 @@ LibName37=measurementSpice
 LibName38=portSpice
 LibName39=sourcesSpice
 LibName40=digitalXSpice
+LibName41=eSim_User
+LibName42=eSim_Subckt
+LibName43=eSim_Sources
+LibName44=eSim_PSpice
+LibName45=eSim_Power
+LibName46=eSim_Plot
+LibName47=eSim_Miscellaneous
+LibName48=eSim_Hybrid
+LibName49=eSim_Digital
+LibName50=eSim_Devices
+LibName51=eSim_Analog
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch
index 417063b1..28110b13 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.sch
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sch
@@ -1,4 +1,5 @@
-EESchema Schematic File Version 2  date Monday 17 December 2012 11:00:43 AM IST
+EESchema Schematic File Version 2
+LIBS:lm555n-rescue
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -10,7 +11,6 @@ LIBS:cmos4000
 LIBS:adc-dac
 LIBS:memory
 LIBS:xilinx
-LIBS:special
 LIBS:microcontrollers
 LIBS:dsp
 LIBS:microchip
@@ -29,19 +29,21 @@ LIBS:opto
 LIBS:atmel
 LIBS:contrib
 LIBS:valves
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:digitalXSpice
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:eSim_Sources
+LIBS:eSim_PSpice
+LIBS:eSim_Power
+LIBS:eSim_Plot
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Hybrid
+LIBS:eSim_Digital
+LIBS:eSim_Devices
+LIBS:eSim_Analog
 LIBS:lm555n-cache
-EELAYER 25  0
+EELAYER 25 0
 EELAYER END
-$Descr A4 11700 8267
+$Descr A4 11693 8268
 encoding utf-8
 Sheet 1 1
 Title ""
@@ -53,383 +55,464 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-$Comp
-L D_INVERTER U5
-U 1 1 50CEA9C5
-P 6700 4050
-F 0 "U5" H 6550 4150 40  0000 C CNN
-F 1 "D_INVERTER" H 6800 4150 40  0000 C CNN
-	1    6700 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L D_SRLATCH U6
-U 1 1 50CEA9AE
-P 7100 3400
-F 0 "U6" H 6900 3650 60  0000 C CNN
-F 1 "D_SRLATCH" H 7100 3500 60  0000 C CNN
-	1    7100 3400
-	1    0    0    -1  
-$EndComp
-Text Notes 5750 3050 0    60   ~ 0
+Text Notes 3700 3050 0    60   ~ 0
 IC 555
 Wire Wire Line
-	4700 3000 4900 3000
-Wire Wire Line
-	4700 4750 4700 4650
-Connection ~ 4400 3550
-Connection ~ 4400 4900
-Wire Wire Line
-	4300 4900 7700 4900
-Wire Wire Line
-	4400 4200 4400 4100
-Wire Wire Line
-	7700 4900 7700 4800
-Wire Wire Line
-	7700 3250 7850 3250
-Wire Wire Line
-	7400 4600 7100 4600
-Wire Wire Line
-	7100 4600 7100 4250
+	2650 3000 2850 3000
 Wire Wire Line
-	7700 3650 7700 3550
+	2650 4750 2650 4650
+Connection ~ 2350 3550
+Connection ~ 2350 4900
 Wire Wire Line
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 Wire Wire Line
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 $Comp
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 L PORT U1
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 L PORT U1
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 L PORT U1
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 L PORT U1
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 L PORT U1
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 L PORT U1
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 L PORT U1
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 L PORT U1
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+F 3 "" H 2000 3000 60  0001 C CNN
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 U 1 1 50AA20DA
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 U 1 1 50AA140C
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-Text Label 4850 4000 0    60   ~ 0
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 U 1 1 50AA12F7
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-	1    5650 3250
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-L R R6
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 L VCVS E1
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 $EndComp
 $Comp
-L R R4
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 U 1 1 50A9E001
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 $EndComp
 $Comp
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 	1    0    0    -1  
 $EndComp
 $Comp
-L R R2
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 U 1 1 50A9DF03
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-	1    4400 3850
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+F 3 "" H 2350 3850 60  0001 C CNN
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 	1    0    0    -1  
 $EndComp
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 U 1 1 50A9DEFE
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 	1    0    0    -1  
 $EndComp
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+L adc_bridge_1 U6
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+Wire Wire Line
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+Wire Wire Line
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+L eSim_NPN Q1
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 $EndSCHEMATC
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub
index beeefc43..b524f5c6 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.sub
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sub
@@ -1,5 +1,6 @@
 * Subcircuit lm555n
-.subckt lm555n 22 14 7 6 15 16 3 13 
+.subckt lm555n 22 14 7 6 15 16 3 13
+.include npn_1.lib 
 * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
 * Inverter d_inverter
 * SR Latch d_srlatch
@@ -8,7 +9,7 @@ e2  18 0 23 14 10000
 * Digital to Analog converter dac8
 * Analog to Digital converter adc8
 r8  9 2 1500
-q1 3 2 22 qnom
+q1 3 2 22 npn_1
 r7  18 20 25
 r6  17 19 25
 e1  17 0 16 15 10000
@@ -33,5 +34,6 @@ a7 [11] [4] u2
 a8 [12] [1] u2
 a9 [6] [5] u2
 .model u2 adc_bridge(in_low=0.8 in_high=2.0 )
+*control statements
 
-.ends lm555n
\ No newline at end of file
+.ends lm555n
diff --git a/src/SubcircuitLibrary/lm555n/npn_1.lib b/src/SubcircuitLibrary/lm555n/npn_1.lib
new file mode 100644
index 00000000..a1818ed8
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/npn_1.lib
@@ -0,0 +1,29 @@
+.model npn_1 NPN(
++ Vtf=1.7 
++ Cjc=0.5p
++ Nc=2 
++ Tr=46.91n 
++ Ne=1.307 
++ Cje=0.5p
++ Isc=0 
++ Xtb=1.5 
++ Rb=500
++ Rc=1 
++ Tf=411.1p 
++ Xti=3 
++ Ikr=0 
++ Bf=125
++ Fc=.5 
++ Ise=14.34f 
++ Br=6.092 
++ Ikf=.2847 
++ Mje=.377 
++ Mjc=.3416 
++ Vaf=74.03 
++ Vjc=.75 
++ Vje=.75 
++ Xtf=3 
++ Itf=.6 
++ Is=14.34f 
++ Eg=1.11 
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/NPN.lib b/src/SubcircuitLibrary/lm7805/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm7805/PNP.lib b/src/SubcircuitLibrary/lm7805/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/lm7805/Q_PNP.lib b/src/SubcircuitLibrary/lm7805/Q_PNP.lib
new file mode 100644
index 00000000..154ed2d8
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/Q_PNP.lib
@@ -0,0 +1 @@
+.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/analysis b/src/SubcircuitLibrary/lm7805/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib
new file mode 100644
index 00000000..aaf8454e
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib
@@ -0,0 +1,136 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir b/src/SubcircuitLibrary/lm7805/lm7805.cir
new file mode 100644
index 00000000..081b4920
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805.cir
@@ -0,0 +1,51 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1  Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k		
+R2  Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500		
+R3  Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k		
+R4  Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k		
+U1  Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R5  Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500		
+Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+Q4  Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN		
+R6  Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k		
+Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R7  Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k		
+Q6  Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN		
+R10  Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k		
+Q7  Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN		
+Q8  Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN		
+Q12  Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
+R12  Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k		
+R9  Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k		
+Q5  Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP		
+Q9  Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP		
+R8  Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100		
+R11  Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50		
+Q10  Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+Q11  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN		
+Q13  Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN		
+R13  Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
+R14  Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k		
+Q14  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP		
+Q15  Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN		
+R17  Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k		
+R16  Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k		
+R15  Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k		
+U2  Net-_Q15-Pad2_ Net-_R15-Pad2_ zener		
+Q16  Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN		
+Q17  Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN		
+R18  Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200		
+R20  Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3		
+R19  Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240		
+U3  Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir.out b/src/SubcircuitLibrary/lm7805/lm7805.cir.out
new file mode 100644
index 00000000..f122fba6
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805.cir.out
@@ -0,0 +1,60 @@
+* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir
+
+.include PNP.lib
+.include NPN.lib
+r1  net-_q16-pad1_ net-_q1-pad2_ 100k
+r2  net-_q16-pad1_ net-_q1-pad1_ 500
+r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
+* u1  net-_q10-pad3_ net-_q1-pad2_ zener
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r5  net-_q10-pad2_ net-_q10-pad3_ 500
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
+r6  net-_q2-pad3_ net-_q3-pad1_ 1k
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
+r7  net-_q3-pad2_ net-_q10-pad3_ 6k
+q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
+r10  net-_q6-pad3_ net-_q10-pad3_ 1k
+q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r12  net-_q12-pad3_ net-_q2-pad3_ 6k
+r9  net-_q2-pad3_ net-_c1-pad2_ 20k
+q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
+q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
+r8  net-_q16-pad1_ net-_q5-pad3_ 100
+r11  net-_q16-pad1_ net-_q9-pad3_ 50
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
+r13  net-_q11-pad3_ net-_q10-pad3_ 6k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+r14  net-_q10-pad1_ net-_c1-pad1_ 6k
+q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
+q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
+r17  net-_q12-pad2_ net-_q10-pad3_ 5k
+r16  net-_q12-pad1_ net-_q12-pad2_ 1.385k
+r15  net-_q16-pad1_ net-_r15-pad2_ 10k
+* u2  net-_q15-pad2_ net-_r15-pad2_ zener
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r18  net-_q16-pad3_ net-_q12-pad1_ 200
+r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
+r19  net-_q17-pad3_ net-_q15-pad2_ 240
+* u3  net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port
+a1 net-_q10-pad3_ net-_q1-pad2_ u1
+a2 net-_q15-pad2_ net-_r15-pad2_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.pro b/src/SubcircuitLibrary/lm7805/lm7805.pro
new file mode 100644
index 00000000..d410e2fa
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805.pro
@@ -0,0 +1,45 @@
+update=Mon Aug 26 14:34:23 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
+
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sch b/src/SubcircuitLibrary/lm7805/lm7805.sch
new file mode 100644
index 00000000..701d163d
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805.sch
@@ -0,0 +1,757 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:lm7805-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L R R1
+U 1 1 5CE41429
+P 1250 1600
+F 0 "R1" V 1330 1600 50  0000 C CNN
+F 1 "100k" V 1250 1600 50  0000 C CNN
+F 2 "" V 1180 1600 50  0001 C CNN
+F 3 "" H 1250 1600 50  0001 C CNN
+	1    1250 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5CE4148B
+P 1950 1600
+F 0 "R2" V 2030 1600 50  0000 C CNN
+F 1 "500" V 1950 1600 50  0000 C CNN
+F 2 "" V 1880 1600 50  0001 C CNN
+F 3 "" H 1950 1600 50  0001 C CNN
+	1    1950 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 5CE414A5
+P 1950 3050
+F 0 "R3" V 2030 3050 50  0000 C CNN
+F 1 "3.3k" V 1950 3050 50  0000 C CNN
+F 2 "" V 1880 3050 50  0001 C CNN
+F 3 "" H 1950 3050 50  0001 C CNN
+	1    1950 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R4
+U 1 1 5CE414CA
+P 1950 3750
+F 0 "R4" V 2030 3750 50  0000 C CNN
+F 1 "2.7k" V 1950 3750 50  0000 C CNN
+F 2 "" V 1880 3750 50  0001 C CNN
+F 3 "" H 1950 3750 50  0001 C CNN
+	1    1950 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L zener U1
+U 1 1 5CE414FA
+P 1250 3350
+F 0 "U1" H 1200 3250 60  0000 C CNN
+F 1 "zener" H 1250 3450 60  0000 C CNN
+F 2 "" H 1300 3350 60  0000 C CNN
+F 3 "" H 1300 3350 60  0000 C CNN
+	1    1250 3350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 5CE41586
+P 1850 2350
+F 0 "Q1" H 1750 2400 50  0000 R CNN
+F 1 "eSim_NPN" H 1800 2500 50  0000 R CNN
+F 2 "" H 2050 2450 29  0000 C CNN
+F 3 "" H 1850 2350 60  0000 C CNN
+	1    1850 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R5
+U 1 1 5CE418C5
+P 1950 4600
+F 0 "R5" V 2030 4600 50  0000 C CNN
+F 1 "500" V 1950 4600 50  0000 C CNN
+F 2 "" V 1880 4600 50  0001 C CNN
+F 3 "" H 1950 4600 50  0001 C CNN
+	1    1950 4600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1250 1750 1250 3050
+Wire Wire Line
+	1250 1450 1250 1300
+Wire Wire Line
+	1250 1300 1950 1300
+Wire Wire Line
+	1950 1300 1950 1450
+Wire Wire Line
+	1950 2150 1950 1750
+Wire Wire Line
+	1950 2550 1950 2900
+Wire Wire Line
+	1950 3200 1950 3600
+Wire Wire Line
+	1950 3900 1950 4450
+Wire Wire Line
+	1250 3550 1250 5200
+Wire Wire Line
+	1250 5200 3200 5200
+Wire Wire Line
+	1950 5200 1950 4750
+Wire Wire Line
+	1650 2350 1250 2350
+Connection ~ 1250 2350
+$Comp
+L eSim_NPN Q2
+U 1 1 5CE41D6C
+P 2650 3350
+F 0 "Q2" H 2550 3400 50  0000 R CNN
+F 1 "eSim_NPN" H 2600 3500 50  0000 R CNN
+F 2 "" H 2850 3450 29  0000 C CNN
+F 3 "" H 2650 3350 60  0000 C CNN
+	1    2650 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 5CE41E26
+P 3100 4100
+F 0 "Q4" H 3000 4150 50  0000 R CNN
+F 1 "eSim_NPN" H 3050 4250 50  0000 R CNN
+F 2 "" H 3300 4200 29  0000 C CNN
+F 3 "" H 3100 4100 60  0000 C CNN
+	1    3100 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R6
+U 1 1 5CE41EA8
+P 2750 3850
+F 0 "R6" V 2830 3850 50  0000 C CNN
+F 1 "1k" V 2750 3850 50  0000 C CNN
+F 2 "" V 2680 3850 50  0001 C CNN
+F 3 "" H 2750 3850 50  0001 C CNN
+	1    2750 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q3
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+F 0 "Q3" H 2750 4700 50  0000 R CNN
+F 1 "eSim_NPN" H 2800 4800 50  0000 R CNN
+F 2 "" H 3050 4750 29  0000 C CNN
+F 3 "" H 2850 4650 60  0000 C CNN
+	1    2850 4650
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	2750 4000 2750 4450
+Wire Wire Line
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+Connection ~ 2750 4100
+Wire Wire Line
+	3200 4300 3200 4750
+Wire Wire Line
+	3050 4650 3450 4650
+Wire Wire Line
+	2450 3350 1950 3350
+Connection ~ 1950 3350
+Wire Wire Line
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+Wire Wire Line
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+F 1 "6k" V 3200 4900 50  0000 C CNN
+F 2 "" V 3130 4900 50  0001 C CNN
+F 3 "" H 3200 4900 50  0001 C CNN
+	1    3200 4900
+	1    0    0    -1  
+$EndComp
+Connection ~ 3200 4650
+Wire Wire Line
+	3200 5050 3200 5250
+Connection ~ 1950 5200
+Wire Wire Line
+	2750 4850 2750 5200
+Connection ~ 2750 5200
+$Comp
+L eSim_NPN Q6
+U 1 1 5CE424FB
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+F 0 "Q6" H 3550 4700 50  0000 R CNN
+F 1 "eSim_NPN" H 3600 4800 50  0000 R CNN
+F 2 "" H 3850 4750 29  0000 C CNN
+F 3 "" H 3650 4650 60  0000 C CNN
+	1    3650 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R10
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+F 0 "R10" V 3830 5100 50  0000 C CNN
+F 1 "1k" V 3750 5100 50  0000 C CNN
+F 2 "" V 3680 5100 50  0001 C CNN
+F 3 "" H 3750 5100 50  0001 C CNN
+	1    3750 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3750 4850 3750 4950
+Wire Wire Line
+	3200 5250 3750 5250
+Connection ~ 3200 5200
+$Comp
+L eSim_NPN Q7
+U 1 1 5CE427DA
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+F 0 "Q7" H 3600 2800 50  0000 R CNN
+F 1 "eSim_NPN" H 3650 2900 50  0000 R CNN
+F 2 "" H 3900 2850 29  0000 C CNN
+F 3 "" H 3700 2750 60  0000 C CNN
+	1    3700 2750
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q8
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+P 3700 3400
+F 0 "Q8" H 3600 3450 50  0000 R CNN
+F 1 "eSim_NPN" H 3650 3550 50  0000 R CNN
+F 2 "" H 3900 3500 29  0000 C CNN
+F 3 "" H 3700 3400 60  0000 C CNN
+	1    3700 3400
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 5CE4293A
+P 4350 3000
+F 0 "Q12" H 4250 3050 50  0000 R CNN
+F 1 "eSim_NPN" H 4300 3150 50  0000 R CNN
+F 2 "" H 4550 3100 29  0000 C CNN
+F 3 "" H 4350 3000 60  0000 C CNN
+	1    4350 3000
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	4250 3200 4250 3400
+Wire Wire Line
+	4250 3400 3900 3400
+Wire Wire Line
+	4250 2750 4250 2800
+Wire Wire Line
+	3900 2750 4250 2750
+Connection ~ 3200 3600
+$Comp
+L R R12
+U 1 1 5CE42C4F
+P 4350 3450
+F 0 "R12" V 4430 3450 50  0000 C CNN
+F 1 "6k" V 4350 3450 50  0000 C CNN
+F 2 "" V 4280 3450 50  0001 C CNN
+F 3 "" H 4350 3450 50  0001 C CNN
+	1    4350 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4350 3300 4250 3300
+Connection ~ 4250 3300
+Wire Wire Line
+	3700 3600 4350 3600
+Wire Wire Line
+	3700 3600 3700 3650
+Wire Wire Line
+	3700 3650 3550 3650
+Wire Wire Line
+	3550 3650 3550 3600
+Connection ~ 3550 3600
+$Comp
+L R R9
+U 1 1 5CE42EA3
+P 3750 3950
+F 0 "R9" V 3830 3950 50  0000 C CNN
+F 1 "20k" V 3750 3950 50  0000 C CNN
+F 2 "" V 3680 3950 50  0001 C CNN
+F 3 "" H 3750 3950 50  0001 C CNN
+	1    3750 3950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3750 4100 3750 4450
+Wire Wire Line
+	3750 3800 3750 3600
+Connection ~ 3750 3600
+Wire Wire Line
+	2750 3150 2750 2450
+Wire Wire Line
+	2750 2450 3600 2450
+Wire Wire Line
+	3600 2450 3600 2550
+$Comp
+L eSim_PNP Q5
+U 1 1 5CE43397
+P 3450 1700
+F 0 "Q5" H 3350 1750 50  0000 R CNN
+F 1 "eSim_PNP" H 3400 1850 50  0000 R CNN
+F 2 "" H 3650 1800 29  0000 C CNN
+F 3 "" H 3450 1700 60  0000 C CNN
+	1    3450 1700
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q9
+U 1 1 5CE4353C
+P 4100 1700
+F 0 "Q9" H 4000 1750 50  0000 R CNN
+F 1 "eSim_PNP" H 4050 1850 50  0000 R CNN
+F 2 "" H 4300 1800 29  0000 C CNN
+F 3 "" H 4100 1700 60  0000 C CNN
+	1    4100 1700
+	1    0    0    1   
+$EndComp
+$Comp
+L R R8
+U 1 1 5CE435B8
+P 3350 1250
+F 0 "R8" V 3430 1250 50  0000 C CNN
+F 1 "100" V 3350 1250 50  0000 C CNN
+F 2 "" V 3280 1250 50  0001 C CNN
+F 3 "" H 3350 1250 50  0001 C CNN
+	1    3350 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R11
+U 1 1 5CE4368E
+P 4200 1250
+F 0 "R11" V 4280 1250 50  0000 C CNN
+F 1 "50" V 4200 1250 50  0000 C CNN
+F 2 "" V 4130 1250 50  0001 C CNN
+F 3 "" H 4200 1250 50  0001 C CNN
+	1    4200 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 5CE43705
+P 4100 2200
+F 0 "Q10" H 4000 2250 50  0000 R CNN
+F 1 "eSim_NPN" H 4050 2350 50  0000 R CNN
+F 2 "" H 4300 2300 29  0000 C CNN
+F 3 "" H 4100 2200 60  0000 C CNN
+	1    4100 2200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3350 1400 3350 1500
+Wire Wire Line
+	3650 1700 3900 1700
+Wire Wire Line
+	4200 1400 4200 1500
+Wire Wire Line
+	3350 1100 3350 1050
+Wire Wire Line
+	1650 1050 7800 1050
+Wire Wire Line
+	4200 1050 4200 1100
+Wire Wire Line
+	4200 1900 4200 2000
+Wire Wire Line
+	3750 1700 3750 2000
+Wire Wire Line
+	3750 2000 3350 2000
+Wire Wire Line
+	3350 1900 3350 2450
+Connection ~ 3750 1700
+Connection ~ 3350 2450
+Connection ~ 3350 2000
+Wire Wire Line
+	2300 2200 3900 2200
+Wire Wire Line
+	2300 2200 2300 4200
+Wire Wire Line
+	2300 4200 1950 4200
+Connection ~ 1950 4200
+Wire Wire Line
+	2200 2400 4200 2400
+Wire Wire Line
+	2200 2400 2200 5200
+Connection ~ 2200 5200
+$Comp
+L eSim_NPN Q11
+U 1 1 5CE4439E
+P 4300 4400
+F 0 "Q11" H 4200 4450 50  0000 R CNN
+F 1 "eSim_NPN" H 4250 4550 50  0000 R CNN
+F 2 "" H 4500 4500 29  0000 C CNN
+F 3 "" H 4300 4400 60  0000 C CNN
+	1    4300 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q13
+U 1 1 5CE44419
+P 4600 4800
+F 0 "Q13" H 4500 4850 50  0000 R CNN
+F 1 "eSim_NPN" H 4550 4950 50  0000 R CNN
+F 2 "" H 4800 4900 29  0000 C CNN
+F 3 "" H 4600 4800 60  0000 C CNN
+	1    4600 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R13
+U 1 1 5CE444B9
+P 4400 5050
+F 0 "R13" V 4480 5050 50  0000 C CNN
+F 1 "6k" V 4400 5050 50  0000 C CNN
+F 2 "" V 4330 5050 50  0001 C CNN
+F 3 "" H 4400 5050 50  0001 C CNN
+	1    4400 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 5CE4451D
+P 4050 4150
+F 0 "C1" H 4075 4250 50  0000 L CNN
+F 1 "30p" H 4075 4050 50  0000 L CNN
+F 2 "" H 4088 4000 30  0000 C CNN
+F 3 "" H 4050 4150 60  0000 C CNN
+	1    4050 4150
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4100 4400 3750 4400
+Connection ~ 3750 4400
+Wire Wire Line
+	3900 4150 3750 4150
+Connection ~ 3750 4150
+Wire Wire Line
+	4700 4150 4200 4150
+Wire Wire Line
+	4400 4150 4400 4200
+Wire Wire Line
+	4400 4600 4400 4900
+Connection ~ 4400 4800
+Wire Wire Line
+	4400 5200 4400 5300
+Wire Wire Line
+	3650 5300 6400 5300
+Wire Wire Line
+	3650 5300 3650 5250
+Connection ~ 3650 5250
+Wire Wire Line
+	4700 5300 4700 5000
+Connection ~ 4400 5300
+Wire Wire Line
+	4700 3800 4700 4600
+Connection ~ 4400 4150
+$Comp
+L R R14
+U 1 1 5CE44FFF
+P 4700 3650
+F 0 "R14" V 4780 3650 50  0000 C CNN
+F 1 "6k" V 4700 3650 50  0000 C CNN
+F 2 "" V 4630 3650 50  0001 C CNN
+F 3 "" H 4700 3650 50  0001 C CNN
+	1    4700 3650
+	1    0    0    -1  
+$EndComp
+Connection ~ 4700 4150
+$Comp
+L eSim_PNP Q14
+U 1 1 5CE45652
+P 5050 3950
+F 0 "Q14" H 4950 4000 50  0000 R CNN
+F 1 "eSim_PNP" H 5000 4100 50  0000 R CNN
+F 2 "" H 5250 4050 29  0000 C CNN
+F 3 "" H 5050 3950 60  0000 C CNN
+	1    5050 3950
+	1    0    0    1   
+$EndComp
+Wire Wire Line
+	4850 3950 4700 3950
+Connection ~ 4700 3950
+Wire Wire Line
+	4700 3500 4700 3450
+Wire Wire Line
+	4700 3450 5150 3450
+Wire Wire Line
+	5150 3450 5150 3750
+Wire Wire Line
+	5150 5300 5150 4150
+Connection ~ 4700 5300
+Wire Wire Line
+	4750 3450 4750 1950
+Wire Wire Line
+	4200 1950 5300 1950
+Connection ~ 4200 1950
+Connection ~ 4750 3450
+$Comp
+L eSim_NPN Q15
+U 1 1 5CE463AD
+P 5400 2150
+F 0 "Q15" H 5300 2200 50  0000 R CNN
+F 1 "eSim_NPN" H 5350 2300 50  0000 R CNN
+F 2 "" H 5600 2250 29  0000 C CNN
+F 3 "" H 5400 2150 60  0000 C CNN
+	1    5400 2150
+	-1   0    0    -1  
+$EndComp
+Connection ~ 4750 1950
+Wire Wire Line
+	4150 2750 4150 2600
+Wire Wire Line
+	4150 2600 6100 2600
+Wire Wire Line
+	5300 2600 5300 2350
+Connection ~ 4150 2750
+$Comp
+L R R17
+U 1 1 5CE46DDE
+P 6050 4250
+F 0 "R17" V 6130 4250 50  0000 C CNN
+F 1 "5k" V 6050 4250 50  0000 C CNN
+F 2 "" V 5980 4250 50  0001 C CNN
+F 3 "" H 6050 4250 50  0001 C CNN
+	1    6050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R16
+U 1 1 5CE46F8E
+P 6050 3050
+F 0 "R16" V 6130 3050 50  0000 C CNN
+F 1 "1.385k" V 6050 3050 50  0000 C CNN
+F 2 "" V 5980 3050 50  0001 C CNN
+F 3 "" H 6050 3050 50  0001 C CNN
+	1    6050 3050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 3200 6050 4100
+Wire Wire Line
+	6050 5300 6050 4400
+Connection ~ 5150 5300
+Wire Wire Line
+	6050 2600 6050 2900
+Connection ~ 5300 2600
+Wire Wire Line
+	4550 3000 5100 3000
+Wire Wire Line
+	5100 3000 5100 3250
+Wire Wire Line
+	5100 3250 5350 3250
+Wire Wire Line
+	5350 3250 5350 3600
+Wire Wire Line
+	5350 3600 6050 3600
+Connection ~ 6050 3600
+Wire Wire Line
+	1650 1050 1650 1300
+Connection ~ 1650 1300
+Connection ~ 3350 1050
+$Comp
+L R R15
+U 1 1 5CE47F7A
+P 5850 1300
+F 0 "R15" V 5930 1300 50  0000 C CNN
+F 1 "10k" V 5850 1300 50  0000 C CNN
+F 2 "" V 5780 1300 50  0001 C CNN
+F 3 "" H 5850 1300 50  0001 C CNN
+	1    5850 1300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5850 1050 5850 1150
+Connection ~ 4200 1050
+$Comp
+L zener U2
+U 1 1 5CE48686
+P 5850 1900
+F 0 "U2" H 5800 1800 60  0000 C CNN
+F 1 "zener" H 5850 2000 60  0000 C CNN
+F 2 "" H 5900 1900 60  0000 C CNN
+F 3 "" H 5900 1900 60  0000 C CNN
+	1    5850 1900
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	5850 1450 5850 1600
+Wire Wire Line
+	5850 2100 5850 2250
+Wire Wire Line
+	5850 2150 5600 2150
+$Comp
+L eSim_NPN Q16
+U 1 1 5CE4907A
+P 6550 1600
+F 0 "Q16" H 6450 1650 50  0000 R CNN
+F 1 "eSim_NPN" H 6500 1750 50  0000 R CNN
+F 2 "" H 6750 1700 29  0000 C CNN
+F 3 "" H 6550 1600 60  0000 C CNN
+	1    6550 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 5CE4942E
+P 7300 1950
+F 0 "Q17" H 7200 2000 50  0000 R CNN
+F 1 "eSim_NPN" H 7250 2100 50  0000 R CNN
+F 2 "" H 7500 2050 29  0000 C CNN
+F 3 "" H 7300 1950 60  0000 C CNN
+	1    7300 1950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6650 1800 6650 2300
+Wire Wire Line
+	6650 1950 7100 1950
+Wire Wire Line
+	7400 1050 7400 1750
+Connection ~ 5850 1050
+Wire Wire Line
+	6650 1400 6650 1050
+Connection ~ 6650 1050
+$Comp
+L R R18
+U 1 1 5CE498BA
+P 6650 2450
+F 0 "R18" V 6730 2450 50  0000 C CNN
+F 1 "200" V 6650 2450 50  0000 C CNN
+F 2 "" V 6580 2450 50  0001 C CNN
+F 3 "" H 6650 2450 50  0001 C CNN
+	1    6650 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R20
+U 1 1 5CE4999A
+P 7400 2450
+F 0 "R20" V 7480 2450 50  0000 C CNN
+F 1 "0.3" V 7400 2450 50  0000 C CNN
+F 2 "" V 7330 2450 50  0001 C CNN
+F 3 "" H 7400 2450 50  0001 C CNN
+	1    7400 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R19
+U 1 1 5CE49AF5
+P 7000 2250
+F 0 "R19" V 7080 2250 50  0000 C CNN
+F 1 "240" V 7000 2250 50  0000 C CNN
+F 2 "" V 6930 2250 50  0001 C CNN
+F 3 "" H 7000 2250 50  0001 C CNN
+	1    7000 2250
+	0    1    1    0   
+$EndComp
+Connection ~ 6650 1950
+Wire Wire Line
+	5850 2250 6850 2250
+Connection ~ 5850 2150
+Wire Wire Line
+	7400 2150 7400 2300
+Wire Wire Line
+	7150 2250 7400 2250
+Connection ~ 7400 2250
+Wire Wire Line
+	6100 2600 6100 2650
+Wire Wire Line
+	6100 2650 7400 2650
+Wire Wire Line
+	7400 2650 7400 2600
+Connection ~ 6050 2600
+Wire Wire Line
+	6650 2600 6650 2650
+Connection ~ 6650 2650
+$Comp
+L PORT U3
+U 1 1 5CE4AAF6
+P 8050 1050
+F 0 "U3" H 8100 1150 30  0000 C CNN
+F 1 "PORT" H 8050 1050 30  0000 C CNN
+F 2 "" H 8050 1050 60  0000 C CNN
+F 3 "" H 8050 1050 60  0000 C CNN
+	1    8050 1050
+	-1   0    0    1   
+$EndComp
+Connection ~ 7400 1050
+$Comp
+L PORT U3
+U 3 1 5CE4B13E
+P 7700 3000
+F 0 "U3" H 7750 3100 30  0000 C CNN
+F 1 "PORT" H 7700 3000 30  0000 C CNN
+F 2 "" H 7700 3000 60  0000 C CNN
+F 3 "" H 7700 3000 60  0000 C CNN
+	3    7700 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U3
+U 2 1 5CE4B701
+P 6650 5300
+F 0 "U3" H 6700 5400 30  0000 C CNN
+F 1 "PORT" H 6650 5300 30  0000 C CNN
+F 2 "" H 6650 5300 60  0000 C CNN
+F 3 "" H 6650 5300 60  0000 C CNN
+	2    6650 5300
+	-1   0    0    1   
+$EndComp
+Connection ~ 6050 5300
+Wire Wire Line
+	6350 1600 5950 1600
+Wire Wire Line
+	5950 1600 5950 1550
+Wire Wire Line
+	5950 1550 5000 1550
+Wire Wire Line
+	5000 1550 5000 1950
+Connection ~ 5000 1950
+Wire Wire Line
+	7300 2650 7300 3000
+Wire Wire Line
+	7300 3000 7450 3000
+Connection ~ 7300 2650
+Connection ~ 2500 5200
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sub b/src/SubcircuitLibrary/lm7805/lm7805.sub
new file mode 100644
index 00000000..7ee1489c
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805.sub
@@ -0,0 +1,54 @@
+* Subcircuit lm7805
+.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ 
+* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir
+.include PNP.lib
+.include NPN.lib
+r1  net-_q16-pad1_ net-_q1-pad2_ 100k
+r2  net-_q16-pad1_ net-_q1-pad1_ 500
+r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
+* u1  net-_q10-pad3_ net-_q1-pad2_ zener
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r5  net-_q10-pad2_ net-_q10-pad3_ 500
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
+r6  net-_q2-pad3_ net-_q3-pad1_ 1k
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
+r7  net-_q3-pad2_ net-_q10-pad3_ 6k
+q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
+r10  net-_q6-pad3_ net-_q10-pad3_ 1k
+q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
+q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
+r12  net-_q12-pad3_ net-_q2-pad3_ 6k
+r9  net-_q2-pad3_ net-_c1-pad2_ 20k
+q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
+q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
+r8  net-_q16-pad1_ net-_q5-pad3_ 100
+r11  net-_q16-pad1_ net-_q9-pad3_ 50
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
+r13  net-_q11-pad3_ net-_q10-pad3_ 6k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+r14  net-_q10-pad1_ net-_c1-pad1_ 6k
+q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
+q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
+r17  net-_q12-pad2_ net-_q10-pad3_ 5k
+r16  net-_q12-pad1_ net-_q12-pad2_ 1.385k
+r15  net-_q16-pad1_ net-_r15-pad2_ 10k
+* u2  net-_q15-pad2_ net-_r15-pad2_ zener
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
+r18  net-_q16-pad3_ net-_q12-pad1_ 200
+r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
+r19  net-_q17-pad3_ net-_q15-pad2_ 240
+a1 net-_q10-pad3_ net-_q1-pad2_ u1
+a2 net-_q15-pad2_ net-_r15-pad2_ u2
+* Schematic Name: zener, NgSpice Name: zener
+.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
+* Control Statements
+
+.ends lm7805
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml
new file mode 100644
index 00000000..7395bd7c
--- /dev/null
+++ b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/NPN.lib b/src/SubcircuitLibrary/lm_741/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm_741/PNP.lib b/src/SubcircuitLibrary/lm_741/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/lm_741/analysis b/src/SubcircuitLibrary/lm_741/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib
new file mode 100644
index 00000000..04e3fecd
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib
@@ -0,0 +1,119 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  25 25  100 100 N
+P 3 0 1 0  25 -25  100 -100  100 -100 N
+P 3 0 1 20  25 75  25 -75  25 -75 N
+P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  25 25  100 100 N
+P 3 0 1 0  25 -25  100 -100  100 -100 N
+P 3 0 1 20  25 75  25 -75  25 -75 N
+P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir b/src/SubcircuitLibrary/lm_741/lm_741.cir
new file mode 100644
index 00000000..4a5917ea
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741.cir
@@ -0,0 +1,43 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+Q6  Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP		
+Q5  Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP		
+Q3  Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
+Q4  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q9  Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q8  Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN		
+Q7  Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
+R1  Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k		
+R2  Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k		
+R3  Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k		
+Q12  Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
+Q13  Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
+R4  Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k		
+R11  Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k		
+Q10  Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q11  Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q14  Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
+R8  Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k		
+R7  Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
+Q16  Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN		
+Q15  Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN		
+R5  Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k		
+R6  Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50		
+Q17  Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN		
+Q18  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN		
+Q20  Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN		
+R9  Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25		
+R10  Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50		
+Q19  Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP		
+U1  Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir.out b/src/SubcircuitLibrary/lm_741/lm_741.cir.out
new file mode 100644
index 00000000..a00bd86a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741.cir.out
@@ -0,0 +1,46 @@
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1  net-_q7-pad3_ net-_q12-pad3_ 1k
+r2  net-_q3-pad3_ net-_q12-pad3_ 50k
+r3  net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4  net-_q13-pad3_ net-_q12-pad3_ 5k
+r11  net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5  net-_q15-pad2_ net-_q12-pad3_ 50k
+r6  net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9  net-_q18-pad3_ net-_q20-pad3_ 25
+r10  net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* u1  net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.pro b/src/SubcircuitLibrary/lm_741/lm_741.pro
new file mode 100644
index 00000000..cbe83f35
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741.pro
@@ -0,0 +1,45 @@
+update=Fri Jun  7 21:53:51 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sch b/src/SubcircuitLibrary/lm_741/lm_741.sch
new file mode 100644
index 00000000..b017fd2b
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741.sch
@@ -0,0 +1,697 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:lm_741-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 5CE90A7B
+P 2650 2700
+F 0 "Q1" H 2550 2750 50  0000 R CNN
+F 1 "eSim_NPN" H 2600 2850 50  0000 R CNN
+F 2 "" H 2850 2800 29  0000 C CNN
+F 3 "" H 2650 2700 60  0000 C CNN
+	1    2650 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 5CE90A7C
+P 4300 2700
+F 0 "Q2" H 4200 2750 50  0000 R CNN
+F 1 "eSim_NPN" H 4250 2850 50  0000 R CNN
+F 2 "" H 4500 2800 29  0000 C CNN
+F 3 "" H 4300 2700 60  0000 C CNN
+	1    4300 2700
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_PNP Q6
+U 1 1 5CE90A7D
+P 3000 3200
+F 0 "Q6" H 2900 3250 50  0000 R CNN
+F 1 "eSim_PNP" H 2950 3350 50  0000 R CNN
+F 2 "" H 3200 3300 29  0000 C CNN
+F 3 "" H 3000 3200 60  0000 C CNN
+	1    3000 3200
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q5
+U 1 1 5CE90A7E
+P 3950 3200
+F 0 "Q5" H 3850 3250 50  0000 R CNN
+F 1 "eSim_PNP" H 3900 3350 50  0000 R CNN
+F 2 "" H 4150 3300 29  0000 C CNN
+F 3 "" H 3950 3200 60  0000 C CNN
+	1    3950 3200
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 5CE90A7F
+P 3300 4000
+F 0 "Q3" H 3200 4050 50  0000 R CNN
+F 1 "eSim_NPN" H 3250 4150 50  0000 R CNN
+F 2 "" H 3500 4100 29  0000 C CNN
+F 3 "" H 3300 4000 60  0000 C CNN
+	1    3300 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 5CE90A80
+P 3850 2000
+F 0 "Q4" H 3750 2050 50  0000 R CNN
+F 1 "eSim_PNP" H 3800 2150 50  0000 R CNN
+F 2 "" H 4050 2100 29  0000 C CNN
+F 3 "" H 3850 2000 60  0000 C CNN
+	1    3850 2000
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q9
+U 1 1 5CE90A81
+P 5200 2000
+F 0 "Q9" H 5100 2050 50  0000 R CNN
+F 1 "eSim_PNP" H 5150 2150 50  0000 R CNN
+F 2 "" H 5400 2100 29  0000 C CNN
+F 3 "" H 5200 2000 60  0000 C CNN
+	1    5200 2000
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 5CE90A82
+P 3950 4600
+F 0 "Q8" H 3850 4650 50  0000 R CNN
+F 1 "eSim_NPN" H 3900 4750 50  0000 R CNN
+F 2 "" H 4150 4700 29  0000 C CNN
+F 3 "" H 3950 4600 60  0000 C CNN
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+F 2 "" H 6700 2050 29  0000 C CNN
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+F 2 "" H 7700 2050 29  0000 C CNN
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+F 3 "" V 7350 2650 30  0000 C CNN
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+F 1 "30p" H 6625 3100 50  0000 L CNN
+F 2 "" H 6638 3050 30  0000 C CNN
+F 3 "" H 6600 3200 60  0000 C CNN
+	1    6600 3200
+	1    0    0    -1  
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+F 2 "" H 7250 4050 29  0000 C CNN
+F 3 "" H 7050 3950 60  0000 C CNN
+	1    7050 3950
+	1    0    0    -1  
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+L eSim_NPN Q15
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+F 0 "Q15" H 7400 4350 50  0000 R CNN
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+F 2 "" H 7700 4400 29  0000 C CNN
+F 3 "" H 7500 4300 60  0000 C CNN
+	1    7500 4300
+	1    0    0    -1  
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+F 0 "R5" H 7150 5180 50  0000 C CNN
+F 1 "50k" H 7150 5100 50  0000 C CNN
+F 2 "" H 7150 5030 30  0000 C CNN
+F 3 "" V 7150 5100 30  0000 C CNN
+	1    7100 5050
+	0    1    1    0   
+$EndComp
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+U 1 1 5CE90A94
+P 7550 5050
+F 0 "R6" H 7600 5180 50  0000 C CNN
+F 1 "50" H 7600 5100 50  0000 C CNN
+F 2 "" H 7600 5030 30  0000 C CNN
+F 3 "" V 7600 5100 30  0000 C CNN
+	1    7550 5050
+	0    1    1    0   
+$EndComp
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+L eSim_NPN Q17
+U 1 1 5CE90A95
+P 6800 4700
+F 0 "Q17" H 6700 4750 50  0000 R CNN
+F 1 "eSim_NPN" H 6750 4850 50  0000 R CNN
+F 2 "" H 7000 4800 29  0000 C CNN
+F 3 "" H 6800 4700 60  0000 C CNN
+	1    6800 4700
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q18
+U 1 1 5CE90A96
+P 8800 2300
+F 0 "Q18" H 8700 2350 50  0000 R CNN
+F 1 "eSim_NPN" H 8750 2450 50  0000 R CNN
+F 2 "" H 9000 2400 29  0000 C CNN
+F 3 "" H 8800 2300 60  0000 C CNN
+	1    8800 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 5CE90A97
+P 8400 2750
+F 0 "Q20" H 8300 2800 50  0000 R CNN
+F 1 "eSim_NPN" H 8350 2900 50  0000 R CNN
+F 2 "" H 8600 2850 29  0000 C CNN
+F 3 "" H 8400 2750 60  0000 C CNN
+	1    8400 2750
+	-1   0    0    -1  
+$EndComp
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+L eSim_R R9
+U 1 1 5CE90A98
+P 8850 3000
+F 0 "R9" H 8900 3130 50  0000 C CNN
+F 1 "25" H 8900 3050 50  0000 C CNN
+F 2 "" H 8900 2980 30  0000 C CNN
+F 3 "" V 8900 3050 30  0000 C CNN
+	1    8850 3000
+	0    1    1    0   
+$EndComp
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+L eSim_R R10
+U 1 1 5CE90A99
+P 8850 3750
+F 0 "R10" H 8900 3880 50  0000 C CNN
+F 1 "50" H 8900 3800 50  0000 C CNN
+F 2 "" H 8900 3730 30  0000 C CNN
+F 3 "" V 8900 3800 30  0000 C CNN
+	1    8850 3750
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_PNP Q19
+U 1 1 5CE90A9A
+P 8800 4600
+F 0 "Q19" H 8700 4650 50  0000 R CNN
+F 1 "eSim_PNP" H 8750 4750 50  0000 R CNN
+F 2 "" H 9000 4700 29  0000 C CNN
+F 3 "" H 8800 4600 60  0000 C CNN
+	1    8800 4600
+	1    0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CE90A9B
+P 1900 1200
+F 0 "U1" H 1950 1300 30  0000 C CNN
+F 1 "PORT" H 1900 1200 30  0000 C CNN
+F 2 "" H 1900 1200 60  0000 C CNN
+F 3 "" H 1900 1200 60  0000 C CNN
+	3    1900 1200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CE90A9C
+P 4500 1050
+F 0 "U1" H 4550 1150 30  0000 C CNN
+F 1 "PORT" H 4500 1050 30  0000 C CNN
+F 2 "" H 4500 1050 60  0000 C CNN
+F 3 "" H 4500 1050 60  0000 C CNN
+	2    4500 1050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CE90A9D
+P 9750 1650
+F 0 "U1" H 9800 1750 30  0000 C CNN
+F 1 "PORT" H 9750 1650 30  0000 C CNN
+F 2 "" H 9750 1650 60  0000 C CNN
+F 3 "" H 9750 1650 60  0000 C CNN
+	7    9750 1650
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CE90A9E
+P 9750 3500
+F 0 "U1" H 9800 3600 30  0000 C CNN
+F 1 "PORT" H 9750 3500 30  0000 C CNN
+F 2 "" H 9750 3500 60  0000 C CNN
+F 3 "" H 9750 3500 60  0000 C CNN
+	6    9750 3500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CE90A9F
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+F 0 "U1" H 9750 5650 30  0000 C CNN
+F 1 "PORT" H 9700 5550 30  0000 C CNN
+F 2 "" H 9700 5550 60  0000 C CNN
+F 3 "" H 9700 5550 60  0000 C CNN
+	4    9700 5550
+	-1   0    0    1   
+$EndComp
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+Wire Wire Line
+	2750 2900 2750 2950
+Wire Wire Line
+	2750 2950 2900 2950
+Wire Wire Line
+	2900 2950 2900 3000
+Wire Wire Line
+	4200 2900 4200 2950
+Wire Wire Line
+	4200 2950 4050 2950
+Wire Wire Line
+	4050 2950 4050 3000
+Wire Wire Line
+	2900 3400 2900 4400
+Wire Wire Line
+	2900 4000 3100 4000
+Wire Wire Line
+	4200 2000 4200 2500
+Wire Wire Line
+	4200 2350 2750 2350
+Wire Wire Line
+	2750 2350 2750 2500
+Wire Wire Line
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+Connection ~ 4200 2000
+Wire Wire Line
+	3750 2200 3750 2350
+Connection ~ 3750 2350
+Wire Wire Line
+	3750 1800 3750 1650
+Wire Wire Line
+	3400 1650 7600 1650
+Wire Wire Line
+	3400 1650 3400 3800
+Wire Wire Line
+	5300 1650 5300 1800
+Connection ~ 3750 1650
+Wire Wire Line
+	5300 2200 5300 4500
+Wire Wire Line
+	5300 3500 3650 3500
+Wire Wire Line
+	3650 3500 3650 3200
+Connection ~ 3650 3200
+Connection ~ 2900 4000
+Wire Wire Line
+	4050 4400 4050 3400
+Wire Wire Line
+	3400 4200 3400 4600
+Wire Wire Line
+	3200 4600 3750 4600
+Connection ~ 3400 4600
+Wire Wire Line
+	4050 5100 4050 4800
+Wire Wire Line
+	3600 5100 3600 4600
+Connection ~ 3600 4600
+Wire Wire Line
+	2900 5100 2900 4800
+Wire Wire Line
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+Wire Wire Line
+	2900 5550 9450 5550
+Wire Wire Line
+	4050 5550 4050 5400
+Wire Wire Line
+	3600 5400 3600 5550
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+Wire Wire Line
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+Wire Wire Line
+	6400 2950 6400 4500
+Wire Wire Line
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+Wire Wire Line
+	5900 4250 5900 4700
+Connection ~ 5900 4700
+Wire Wire Line
+	5300 5100 5300 4900
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5300 3500
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	7600 3450 7400 3450
+Wire Wire Line
+	6900 3450 7100 3450
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	7600 2650 7400 2650
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7600 2450
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 6700 3950
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+Wire Wire Line
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+Wire Wire Line
+	7000 4700 7600 4700
+Connection ~ 7600 4700
+Wire Wire Line
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+Connection ~ 6700 5550
+Wire Wire Line
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+Connection ~ 7150 5550
+Wire Wire Line
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+Wire Wire Line
+	8300 2300 8300 2550
+Connection ~ 8300 2300
+Connection ~ 7600 2300
+Wire Wire Line
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+Connection ~ 8900 1650
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	8300 3350 8900 3350
+Wire Wire Line
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+Wire Wire Line
+	8900 3500 9500 3500
+Connection ~ 8900 3500
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4750 2700 4750 1050
+Wire Wire Line
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+U 5 1 5CE90AA0
+P 1850 4850
+F 0 "U1" H 1900 4950 30  0000 C CNN
+F 1 "PORT" H 1850 4850 30  0000 C CNN
+F 2 "" H 1850 4850 60  0000 C CNN
+F 3 "" H 1850 4850 60  0000 C CNN
+	5    1850 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CE90AA1
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+F 0 "U1" H 1900 5200 30  0000 C CNN
+F 1 "PORT" H 1850 5100 30  0000 C CNN
+F 2 "" H 1850 5100 60  0000 C CNN
+F 3 "" H 1850 5100 60  0000 C CNN
+	1    1850 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2100 5100 2700 5100
+Wire Wire Line
+	2700 5100 2700 5050
+Wire Wire Line
+	2700 5050 2900 5050
+Connection ~ 2900 5050
+Wire Wire Line
+	2100 4850 2550 4850
+Wire Wire Line
+	2550 4850 2550 4900
+Wire Wire Line
+	2550 4900 4050 4900
+Connection ~ 4050 4900
+$Comp
+L PORT U1
+U 8 1 5CE9368F
+P 9600 6050
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+F 1 "PORT" H 9600 6050 30  0000 C CNN
+F 2 "" H 9600 6050 60  0000 C CNN
+F 3 "" H 9600 6050 60  0000 C CNN
+	8    9600 6050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	9350 6050 9100 6050
+NoConn ~ 9100 6050
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sub b/src/SubcircuitLibrary/lm_741/lm_741.sub
new file mode 100644
index 00000000..fa8d27b1
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741.sub
@@ -0,0 +1,40 @@
+* Subcircuit lm_741
+.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1  net-_q7-pad3_ net-_q12-pad3_ 1k
+r2  net-_q3-pad3_ net-_q12-pad3_ 50k
+r3  net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4  net-_q13-pad3_ net-_q12-pad3_ 5k
+r11  net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5  net-_q15-pad2_ net-_q12-pad3_ 50k
+r6  net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9  net-_q18-pad3_ net-_q20-pad3_ 25
+r10  net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* Control Statements
+
+.ends lm_741
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml
new file mode 100644
index 00000000..b61322bb
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/npn_1.lib b/src/SubcircuitLibrary/lm_741/npn_1.lib
new file mode 100644
index 00000000..a1818ed8
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/npn_1.lib
@@ -0,0 +1,29 @@
+.model npn_1 NPN(
++ Vtf=1.7 
++ Cjc=0.5p
++ Nc=2 
++ Tr=46.91n 
++ Ne=1.307 
++ Cje=0.5p
++ Isc=0 
++ Xtb=1.5 
++ Rb=500
++ Rc=1 
++ Tf=411.1p 
++ Xti=3 
++ Ikr=0 
++ Bf=125
++ Fc=.5 
++ Ise=14.34f 
++ Br=6.092 
++ Ikf=.2847 
++ Mje=.377 
++ Mjc=.3416 
++ Vaf=74.03 
++ Vjc=.75 
++ Vje=.75 
++ Xtf=3 
++ Itf=.6 
++ Is=14.34f 
++ Eg=1.11 
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/pnp_1.lib b/src/SubcircuitLibrary/lm_741/pnp_1.lib
new file mode 100644
index 00000000..a4ee06da
--- /dev/null
+++ b/src/SubcircuitLibrary/lm_741/pnp_1.lib
@@ -0,0 +1,29 @@
+.model pnp_1 PNP(
++ Vtf=1.7 
++ Cjc=1.5p
++ Nc=2 
++ Tr=46.91n 
++ Ne=1.307 
++ Cje=0.3p
++ Isc=0 
++ Xtb=1.5 
++ Rb=250
++ Rc=1 
++ Tf=411.1p 
++ Xti=3 
++ Ikr=0 
++ Bf=25
++ Fc=.5 
++ Ise=14.34f 
++ Br=6.092 
++ Ikf=.2847 
++ Mje=.377 
++ Mjc=.3416 
++ Vaf=74.03 
++ Vjc=.75 
++ Vje=.75 
++ Xtf=3 
++ Itf=.6 
++ Is=14.34f 
++ Eg=1.11 
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib
new file mode 100644
index 00000000..ef18bb50
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/D.lib
@@ -0,0 +1,20 @@
+.MODEL D1N750 D(
++  Vj=.75
++  Nbvl=14.976
++  Cjo=175p
++  Rs=.25
++  Isr=1.859n
++  Eg=1.11
++  M=.5516
++  Nbv=1.6989
++  N=1
++  Tbv1=-21.277u
++  Bv=8.1
++  Fc=.5
++  Ikf=0
++  Nr=2
++  Ibv=20.245m
++  Is=880.5E-18
++  Xti=3
++  Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib
index d6fb6469..a2f61dce 100644
--- a/src/SubcircuitLibrary/scr/PowerDiode.lib
+++ b/src/SubcircuitLibrary/scr/PowerDiode.lib
@@ -1 +1,20 @@
-.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
+.MODEL PowerDiode D(
++ Vj=.75
++ Nbvl=14.976
++ Cjo=175p
++ Rs=.25
++ Isr=1.859n
++ Eg=1.11
++ M=.5516
++ Nbv=1.6989
++ N=1
++ Tbv1=-21.277u
++ bv=1800
++ Fc=.5
++ Ikf=0
++ Nr=2
++ Ibv=20.245m
++ Is=2.2E-15
++ Xti=3
++ Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib
index 24105a8a..0a685b80 100644
--- a/src/SubcircuitLibrary/scr/scr-cache.lib
+++ b/src/SubcircuitLibrary/scr/scr-cache.lib
@@ -6,20 +6,16 @@ EESchema-LIBRARY Version 2.3
 DEF C C 0 10 N Y 1 F N
 F0 "C" 25 100 50 H V L CNN
 F1 "C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
 $FPLIST
- C?
- C_????_*
- C_????
- SMD*_c
- Capacitor*
+ C_*
 $ENDFPLIST
 DRAW
-P 2 0 1 20  -80 -30  80 -30 N
-P 2 0 1 20  -80 30  80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -54,8 +50,8 @@ $FPLIST
  S*
 $ENDFPLIST
 DRAW
-P 2 0 1 6  50 50  50 -50 N
-P 3 0 1 0  -50 50  50 0  -50 -50 F
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
 X A 1 -200 0 150 R 40 40 1 1 P
 X K 2 200 0 150 L 40 40 1 1 P
 ENDDRAW
@@ -63,7 +59,7 @@ ENDDEF
 #
 # PORT
 #
-DEF PORT U 0 40 Y Y 8 F N
+DEF PORT U 0 40 Y Y 26 F N
 F0 "U" 50 100 30 H V C CNN
 F1 "PORT" 0 0 30 H V C CNN
 F2 "" 0 0 60 H V C CNN
@@ -80,14 +76,32 @@ X ~ 5 250 0 100 L 30 30 5 1 B
 X ~ 6 250 0 100 L 30 30 6 1 B
 X ~ 7 250 0 100 L 30 30 7 1 B
 X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
 ENDDRAW
 ENDDEF
 #
-# R
+# R-RESCUE-scr
 #
-DEF R R 0 0 N Y 1 F N
+DEF R-RESCUE-scr R 0 0 N Y 1 F N
 F0 "R" 50 130 50 H V C CNN
-F1 "R" 50 50 50 H V C CNN
+F1 "R-RESCUE-scr" 50 50 50 H V C CNN
 F2 "" 50 -20 30 H V C CNN
 F3 "" 50 50 30 V V C CNN
 $FPLIST
@@ -116,11 +130,11 @@ X ~ 1_IN 450 -100 200 U 50 20 1 1 I
 ENDDRAW
 ENDDEF
 #
-# dc
+# dc-RESCUE-scr
 #
-DEF dc v 0 40 Y Y 1 F N
+DEF dc-RESCUE-scr v 0 40 Y Y 1 F N
 F0 "v" -200 100 60 H V C CNN
-F1 "dc" -200 -50 60 H V C CNN
+F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN
 F2 "R1" -300 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
 $FPLIST
diff --git a/src/SubcircuitLibrary/scr/scr-rescue.lib b/src/SubcircuitLibrary/scr/scr-rescue.lib
new file mode 100644
index 00000000..64237b7d
--- /dev/null
+++ b/src/SubcircuitLibrary/scr/scr-rescue.lib
@@ -0,0 +1,39 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# R-RESCUE-scr
+#
+DEF R-RESCUE-scr R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R-RESCUE-scr" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc-RESCUE-scr
+#
+DEF dc-RESCUE-scr v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro
index fc4ca966..ca0df803 100644
--- a/src/SubcircuitLibrary/scr/scr.pro
+++ b/src/SubcircuitLibrary/scr/scr.pro
@@ -1,44 +1,45 @@
-update=Tue Dec  8 15:45:12 2015
-last_client=eeschema
+update=Wed Jul 31 19:51:09 2019
+last_client=kicad
 [eeschema]
 version=1
 LibDir=
 [eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Sources
-LibName7=eSim_Subckt
-LibName8=eSim_User
-LibName9=power
-LibName10=device
-LibName11=transistors
-LibName12=conn
-LibName13=linear
-LibName14=regul
-LibName15=74xx
-LibName16=cmos4000
-LibName17=adc-dac
-LibName18=memory
-LibName19=xilinx
-LibName20=special
-LibName21=microcontrollers
-LibName22=dsp
-LibName23=microchip
-LibName24=analog_switches
-LibName25=motorola
-LibName26=texas
-LibName27=intel
-LibName28=audio
-LibName29=interface
-LibName30=digital-audio
-LibName31=philips
-LibName32=display
-LibName33=cypress
-LibName34=siliconi
-LibName35=opto
-LibName36=atmel
-LibName37=contrib
-LibName38=valves
+LibName1=scr-rescue
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Sources
+LibName8=eSim_Subckt
+LibName9=eSim_User
+LibName10=power
+LibName11=device
+LibName12=transistors
+LibName13=conn
+LibName14=linear
+LibName15=regul
+LibName16=74xx
+LibName17=cmos4000
+LibName18=adc-dac
+LibName19=memory
+LibName20=xilinx
+LibName21=special
+LibName22=microcontrollers
+LibName23=dsp
+LibName24=microchip
+LibName25=analog_switches
+LibName26=motorola
+LibName27=texas
+LibName28=intel
+LibName29=audio
+LibName30=interface
+LibName31=digital-audio
+LibName32=philips
+LibName33=display
+LibName34=cypress
+LibName35=siliconi
+LibName36=opto
+LibName37=atmel
+LibName38=contrib
+LibName39=valves
diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch
index 1f23ec65..69244f56 100644
--- a/src/SubcircuitLibrary/scr/scr.sch
+++ b/src/SubcircuitLibrary/scr/scr.sch
@@ -1,4 +1,5 @@
 EESchema Schematic File Version 2
+LIBS:scr-rescue
 LIBS:eSim_Analog
 LIBS:eSim_Devices
 LIBS:eSim_Digital
@@ -182,7 +183,7 @@ F 3 "" H 3800 4350 60  0001 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L dc v1
+L dc-RESCUE-scr v1
 U 1 1 565DBF58
 P 3600 3700
 F 0 "v1" H 3400 3800 60  0000 C CNN
@@ -193,7 +194,7 @@ F 3 "" H 3600 3700 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L dc v2
+L dc-RESCUE-scr v2
 U 1 1 565DC066
 P 5550 3000
 F 0 "v2" H 5350 3100 60  0000 C CNN
@@ -217,7 +218,7 @@ $EndComp
 Wire Wire Line
 	5950 2000 6650 2000
 $Comp
-L R R1
+L R-RESCUE-scr R1
 U 1 1 5666B019
 P 3550 2950
 F 0 "R1" H 3600 3080 50  0000 C CNN
@@ -228,7 +229,7 @@ F 3 "" V 3600 3000 30  0000 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L R R2
+L R-RESCUE-scr R2
 U 1 1 5666B17A
 P 4200 5300
 F 0 "R2" H 4250 5430 50  0000 C CNN
diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro
index be9bc92c..5dbb81a5 100644
--- a/src/SubcircuitLibrary/ua741/ua741.pro
+++ b/src/SubcircuitLibrary/ua741/ua741.pro
@@ -2,7 +2,7 @@ update=Monday 17 December 2012 06:14:06 PM IST
 last_client=eeschema
 [eeschema]
 version=1
-LibDir=
+LibDir=/home/yogesh/FreeEDA/library
 NetFmt=1
 HPGLSpd=20
 HPGLDm=15
diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis
index 21dc4b94..ffc57a6b 100644
--- a/src/SubcircuitLibrary/ujt/analysis
+++ b/src/SubcircuitLibrary/ujt/analysis
@@ -1 +1 @@
-.tran 5e-06 100e-03 0e-03
\ No newline at end of file
+.tran 5e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib
index 3af759f4..3e78b1ee 100644
--- a/src/SubcircuitLibrary/ujt/emitter.lib
+++ b/src/SubcircuitLibrary/ujt/emitter.lib
@@ -1,4 +1,11 @@
-.MODEL emitter D(
-+  Is=21.3P
-+  N=1.8
-)
\ No newline at end of file
+.model emitter D(
++ Vj=1
++ Cjo=1.700E-12
++ Rs=4.755E-01
++ Is=21.3P
++ M=1.959E-01
++ N=1.8
++ Bv=1.000E+02
++ tt=3.030E-09
++ Ibv=1.000E-04
+)
diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt
index bb08d2c2..e69de29b 100644
--- a/src/SubcircuitLibrary/ujt/plot_data_i.txt
+++ b/src/SubcircuitLibrary/ujt/plot_data_i.txt
@@ -1,67 +0,0 @@
-     * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-     Transient Analysis  Sat Jun 15 16:01:36  2019
---------------------------------------------------------------------------------
-Index   time            h1#branch       vh1#branch      
---------------------------------------------------------------------------------
-0	0.000000e+00	1.936296e-124	-1.93630e-121	
-1	1.000000e-05	1.522607e-65	-1.52261e-62	
-2	2.000000e-05	1.522589e-65	-1.52259e-62	
-3	4.000000e-05	1.522545e-65	-1.52255e-62	
-4	8.000000e-05	0.000000e+00	0.000000e+00	
-5	1.600000e-04	0.000000e+00	0.000000e+00	
-6	3.200000e-04	0.000000e+00	0.000000e+00	
-7	6.400000e-04	0.000000e+00	0.000000e+00	
-8	1.280000e-03	3.035283e-65	-3.03528e-62	
-9	2.560000e-03	1.511759e-65	-1.51176e-62	
-10	4.560000e-03	0.000000e+00	0.000000e+00	
-11	6.560000e-03	0.000000e+00	0.000000e+00	
-12	8.560000e-03	0.000000e+00	0.000000e+00	
-13	1.056000e-02	0.000000e+00	0.000000e+00	
-14	1.256000e-02	0.000000e+00	0.000000e+00	
-15	1.456000e-02	0.000000e+00	0.000000e+00	
-16	1.656000e-02	0.000000e+00	0.000000e+00	
-17	1.856000e-02	0.000000e+00	0.000000e+00	
-18	2.056000e-02	0.000000e+00	0.000000e+00	
-19	2.256000e-02	0.000000e+00	0.000000e+00	
-20	2.456000e-02	0.000000e+00	0.000000e+00	
-21	2.656000e-02	0.000000e+00	0.000000e+00	
-22	2.856000e-02	0.000000e+00	0.000000e+00	
-23	3.056000e-02	0.000000e+00	0.000000e+00	
-24	3.256000e-02	0.000000e+00	0.000000e+00	
-25	3.456000e-02	0.000000e+00	0.000000e+00	
-26	3.656000e-02	0.000000e+00	0.000000e+00	
-27	3.856000e-02	0.000000e+00	0.000000e+00	
-28	4.056000e-02	0.000000e+00	0.000000e+00	
-29	4.256000e-02	0.000000e+00	0.000000e+00	
-30	4.456000e-02	0.000000e+00	0.000000e+00	
-31	4.656000e-02	0.000000e+00	0.000000e+00	
-32	4.856000e-02	0.000000e+00	0.000000e+00	
-33	5.056000e-02	0.000000e+00	0.000000e+00	
-34	5.256000e-02	0.000000e+00	0.000000e+00	
-35	5.456000e-02	0.000000e+00	0.000000e+00	
-36	5.656000e-02	0.000000e+00	0.000000e+00	
-37	5.856000e-02	0.000000e+00	0.000000e+00	
-38	6.056000e-02	0.000000e+00	0.000000e+00	
-39	6.256000e-02	0.000000e+00	0.000000e+00	
-40	6.456000e-02	0.000000e+00	0.000000e+00	
-41	6.656000e-02	0.000000e+00	0.000000e+00	
-42	6.856000e-02	0.000000e+00	0.000000e+00	
-43	7.056000e-02	0.000000e+00	0.000000e+00	
-44	7.256000e-02	0.000000e+00	0.000000e+00	
-45	7.456000e-02	0.000000e+00	0.000000e+00	
-46	7.656000e-02	0.000000e+00	0.000000e+00	
-47	7.856000e-02	0.000000e+00	0.000000e+00	
-48	8.056000e-02	0.000000e+00	0.000000e+00	
-49	8.256000e-02	0.000000e+00	0.000000e+00	
-50	8.456000e-02	0.000000e+00	0.000000e+00	
-51	8.656000e-02	0.000000e+00	0.000000e+00	
-52	8.856000e-02	0.000000e+00	0.000000e+00	
-53	9.056000e-02	0.000000e+00	0.000000e+00	
-54	9.256000e-02	0.000000e+00	0.000000e+00	
-
-Index   time            h1#branch       vh1#branch      
---------------------------------------------------------------------------------
-55	9.456000e-02	0.000000e+00	0.000000e+00	
-56	9.656000e-02	0.000000e+00	0.000000e+00	
-57	9.856000e-02	0.000000e+00	0.000000e+00	
-58	1.000000e-01	3.640960e-66	-3.64096e-63	
diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt
index 207ce5b7..e69de29b 100644
--- a/src/SubcircuitLibrary/ujt/plot_data_v.txt
+++ b/src/SubcircuitLibrary/ujt/plot_data_v.txt
@@ -1,203 +0,0 @@
-     * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-     Transient Analysis  Sat Jun 15 16:01:36  2019
---------------------------------------------------------------------------------
-Index   time            V(1)            V(2)            V(3)            
---------------------------------------------------------------------------------
-0	0.000000e+00	6.088894e-52	-2.80622e-43	-2.80622e-43	
-1	1.000000e-05	-2.51069e-46	-2.80871e-43	-2.80871e-43	
-2	2.000000e-05	-2.51068e-46	-2.80868e-43	-2.80868e-43	
-3	4.000000e-05	-2.51147e-46	-2.80860e-43	-2.80860e-43	
-4	8.000000e-05	1.691803e-50	-2.80589e-43	-2.80589e-43	
-5	1.600000e-04	-1.19543e-50	-2.80543e-43	-2.80543e-43	
-6	3.200000e-04	-2.36974e-50	-2.80438e-43	-2.80438e-43	
-7	6.400000e-04	4.520590e-52	-2.80203e-43	-2.80203e-43	
-8	1.280000e-03	-2.71395e-46	-2.79955e-43	-2.79955e-43	
-9	2.560000e-03	-3.13629e-46	-2.78870e-43	-2.78870e-43	
-10	4.560000e-03	-5.10465e-52	-2.76667e-43	-2.76667e-43	
-11	6.560000e-03	-2.20180e-52	-2.74650e-43	-2.74650e-43	
-12	8.560000e-03	2.805351e-52	-2.72507e-43	-2.72507e-43	
-13	1.056000e-02	-6.11918e-52	-2.70239e-43	-2.70239e-43	
-14	1.256000e-02	-1.35091e-52	-2.67846e-43	-2.67846e-43	
-15	1.456000e-02	6.127039e-53	-2.65331e-43	-2.65331e-43	
-16	1.656000e-02	-6.60318e-52	-2.62693e-43	-2.62693e-43	
-17	1.856000e-02	-2.70241e-52	-2.59936e-43	-2.59936e-43	
-18	2.056000e-02	6.713684e-53	-2.57059e-43	-2.57059e-43	
-19	2.256000e-02	-1.55773e-52	-2.54064e-43	-2.54064e-43	
-20	2.456000e-02	3.929090e-53	-2.50953e-43	-2.50953e-43	
-21	2.656000e-02	-5.71836e-52	-2.47727e-43	-2.47727e-43	
-22	2.856000e-02	-1.42047e-52	-2.44388e-43	-2.44388e-43	
-23	3.056000e-02	-4.85310e-52	-2.40937e-43	-2.40937e-43	
-24	3.256000e-02	3.962144e-52	-2.37377e-43	-2.37377e-43	
-25	3.456000e-02	-7.13895e-52	-2.33707e-43	-2.33707e-43	
-26	3.656000e-02	-3.25981e-52	-2.29932e-43	-2.29932e-43	
-27	3.856000e-02	-3.11521e-52	-2.26051e-43	-2.26051e-43	
-28	4.056000e-02	2.279041e-52	-2.22068e-43	-2.22068e-43	
-29	4.256000e-02	-4.09991e-52	-2.17983e-43	-2.17983e-43	
-30	4.456000e-02	6.197036e-53	-2.13800e-43	-2.13800e-43	
-31	4.656000e-02	-4.88067e-52	-2.09519e-43	-2.09519e-43	
-32	4.856000e-02	-5.64247e-52	-2.05144e-43	-2.05144e-43	
-33	5.056000e-02	-4.96151e-52	-2.00675e-43	-2.00675e-43	
-34	5.256000e-02	-4.23061e-52	-1.96115e-43	-1.96115e-43	
-35	5.456000e-02	2.057927e-52	-1.91467e-43	-1.91467e-43	
-36	5.656000e-02	-6.33244e-52	-1.86732e-43	-1.86732e-43	
-37	5.856000e-02	-3.34770e-52	-1.81913e-43	-1.81913e-43	
-38	6.056000e-02	-2.07109e-52	-1.77011e-43	-1.77011e-43	
-39	6.256000e-02	1.985474e-52	-1.72030e-43	-1.72030e-43	
-40	6.456000e-02	-2.45836e-52	-1.66972e-43	-1.66972e-43	
-41	6.656000e-02	-1.04902e-52	-1.61839e-43	-1.61839e-43	
-42	6.856000e-02	-2.43454e-52	-1.56633e-43	-1.56633e-43	
-43	7.056000e-02	-9.13597e-53	-1.51357e-43	-1.51357e-43	
-44	7.256000e-02	-2.89902e-52	-1.46013e-43	-1.46013e-43	
-45	7.456000e-02	-1.08625e-52	-1.40604e-43	-1.40604e-43	
-46	7.656000e-02	-1.19143e-52	-1.35132e-43	-1.35132e-43	
-47	7.856000e-02	-3.87284e-52	-1.29600e-43	-1.29600e-43	
-48	8.056000e-02	-1.76399e-52	-1.24011e-43	-1.24011e-43	
-49	8.256000e-02	9.167300e-53	-1.18367e-43	-1.18367e-43	
-50	8.456000e-02	-1.40774e-52	-1.12671e-43	-1.12671e-43	
-51	8.656000e-02	1.945441e-52	-1.06925e-43	-1.06925e-43	
-52	8.856000e-02	-7.42845e-53	-1.01132e-43	-1.01132e-43	
-53	9.056000e-02	-3.70259e-52	-9.52954e-44	-9.52954e-44	
-54	9.256000e-02	-5.23530e-54	-8.94171e-44	-8.94171e-44	
-
-Index   time            V(1)            V(2)            V(3)            
---------------------------------------------------------------------------------
-55	9.456000e-02	1.749423e-52	-8.35001e-44	-8.35001e-44	
-56	9.656000e-02	-1.18682e-52	-7.75471e-44	-7.75471e-44	
-57	9.856000e-02	-3.13438e-53	-7.15610e-44	-7.15610e-44	
-58	1.000000e-01	6.326077e-47	-6.71639e-44	-6.71639e-44	
-
-     * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-     Transient Analysis  Sat Jun 15 16:01:36  2019
---------------------------------------------------------------------------------
-Index   time            V(4)            V(5)            V(6)            
---------------------------------------------------------------------------------
-0	0.000000e+00	-2.80622e-43	-2.80622e-43	-1.93630e-118	
-1	1.000000e-05	-2.80871e-43	-2.80871e-43	-1.52261e-59	
-2	2.000000e-05	-2.80868e-43	-2.80868e-43	-1.52259e-59	
-3	4.000000e-05	-2.80860e-43	-2.80860e-43	-1.52255e-59	
-4	8.000000e-05	-2.80589e-43	-2.80589e-43	0.000000e+00	
-5	1.600000e-04	-2.80543e-43	-2.80543e-43	0.000000e+00	
-6	3.200000e-04	-2.80438e-43	-2.80438e-43	0.000000e+00	
-7	6.400000e-04	-2.80203e-43	-2.80203e-43	0.000000e+00	
-8	1.280000e-03	-2.79955e-43	-2.79955e-43	-3.03528e-59	
-9	2.560000e-03	-2.78870e-43	-2.78870e-43	-1.51176e-59	
-10	4.560000e-03	-2.76667e-43	-2.76667e-43	0.000000e+00	
-11	6.560000e-03	-2.74650e-43	-2.74650e-43	0.000000e+00	
-12	8.560000e-03	-2.72507e-43	-2.72507e-43	0.000000e+00	
-13	1.056000e-02	-2.70239e-43	-2.70239e-43	0.000000e+00	
-14	1.256000e-02	-2.67846e-43	-2.67846e-43	0.000000e+00	
-15	1.456000e-02	-2.65331e-43	-2.65331e-43	0.000000e+00	
-16	1.656000e-02	-2.62693e-43	-2.62693e-43	0.000000e+00	
-17	1.856000e-02	-2.59936e-43	-2.59936e-43	0.000000e+00	
-18	2.056000e-02	-2.57059e-43	-2.57059e-43	0.000000e+00	
-19	2.256000e-02	-2.54064e-43	-2.54064e-43	0.000000e+00	
-20	2.456000e-02	-2.50953e-43	-2.50953e-43	0.000000e+00	
-21	2.656000e-02	-2.47727e-43	-2.47727e-43	0.000000e+00	
-22	2.856000e-02	-2.44388e-43	-2.44388e-43	0.000000e+00	
-23	3.056000e-02	-2.40937e-43	-2.40937e-43	0.000000e+00	
-24	3.256000e-02	-2.37377e-43	-2.37377e-43	0.000000e+00	
-25	3.456000e-02	-2.33707e-43	-2.33707e-43	0.000000e+00	
-26	3.656000e-02	-2.29932e-43	-2.29932e-43	0.000000e+00	
-27	3.856000e-02	-2.26051e-43	-2.26051e-43	0.000000e+00	
-28	4.056000e-02	-2.22068e-43	-2.22068e-43	0.000000e+00	
-29	4.256000e-02	-2.17983e-43	-2.17983e-43	0.000000e+00	
-30	4.456000e-02	-2.13800e-43	-2.13800e-43	0.000000e+00	
-31	4.656000e-02	-2.09519e-43	-2.09519e-43	0.000000e+00	
-32	4.856000e-02	-2.05144e-43	-2.05144e-43	0.000000e+00	
-33	5.056000e-02	-2.00675e-43	-2.00675e-43	0.000000e+00	
-34	5.256000e-02	-1.96115e-43	-1.96115e-43	0.000000e+00	
-35	5.456000e-02	-1.91467e-43	-1.91467e-43	0.000000e+00	
-36	5.656000e-02	-1.86732e-43	-1.86732e-43	0.000000e+00	
-37	5.856000e-02	-1.81913e-43	-1.81913e-43	0.000000e+00	
-38	6.056000e-02	-1.77011e-43	-1.77011e-43	0.000000e+00	
-39	6.256000e-02	-1.72030e-43	-1.72030e-43	0.000000e+00	
-40	6.456000e-02	-1.66972e-43	-1.66972e-43	0.000000e+00	
-41	6.656000e-02	-1.61839e-43	-1.61839e-43	0.000000e+00	
-42	6.856000e-02	-1.56633e-43	-1.56633e-43	0.000000e+00	
-43	7.056000e-02	-1.51357e-43	-1.51357e-43	0.000000e+00	
-44	7.256000e-02	-1.46013e-43	-1.46013e-43	0.000000e+00	
-45	7.456000e-02	-1.40604e-43	-1.40604e-43	0.000000e+00	
-46	7.656000e-02	-1.35132e-43	-1.35132e-43	0.000000e+00	
-47	7.856000e-02	-1.29600e-43	-1.29600e-43	0.000000e+00	
-48	8.056000e-02	-1.24011e-43	-1.24011e-43	0.000000e+00	
-49	8.256000e-02	-1.18367e-43	-1.18367e-43	0.000000e+00	
-50	8.456000e-02	-1.12671e-43	-1.12671e-43	0.000000e+00	
-51	8.656000e-02	-1.06925e-43	-1.06925e-43	0.000000e+00	
-52	8.856000e-02	-1.01132e-43	-1.01132e-43	0.000000e+00	
-53	9.056000e-02	-9.52954e-44	-9.52954e-44	0.000000e+00	
-54	9.256000e-02	-8.94171e-44	-8.94171e-44	0.000000e+00	
-
-Index   time            V(4)            V(5)            V(6)            
---------------------------------------------------------------------------------
-55	9.456000e-02	-8.35001e-44	-8.35001e-44	0.000000e+00	
-56	9.656000e-02	-7.75471e-44	-7.75471e-44	0.000000e+00	
-57	9.856000e-02	-7.15610e-44	-7.15610e-44	0.000000e+00	
-58	1.000000e-01	-6.71639e-44	-6.71639e-44	-3.64096e-60	
-
-     * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-     Transient Analysis  Sat Jun 15 16:01:36  2019
---------------------------------------------------------------------------------
-Index   time            V(7)            
---------------------------------------------------------------------------------
-0	0.000000e+00	-2.80622e-43	
-1	1.000000e-05	-2.80871e-43	
-2	2.000000e-05	-2.80868e-43	
-3	4.000000e-05	-2.80860e-43	
-4	8.000000e-05	-2.80589e-43	
-5	1.600000e-04	-2.80543e-43	
-6	3.200000e-04	-2.80438e-43	
-7	6.400000e-04	-2.80203e-43	
-8	1.280000e-03	-2.79955e-43	
-9	2.560000e-03	-2.78870e-43	
-10	4.560000e-03	-2.76667e-43	
-11	6.560000e-03	-2.74650e-43	
-12	8.560000e-03	-2.72507e-43	
-13	1.056000e-02	-2.70239e-43	
-14	1.256000e-02	-2.67846e-43	
-15	1.456000e-02	-2.65331e-43	
-16	1.656000e-02	-2.62693e-43	
-17	1.856000e-02	-2.59936e-43	
-18	2.056000e-02	-2.57059e-43	
-19	2.256000e-02	-2.54064e-43	
-20	2.456000e-02	-2.50953e-43	
-21	2.656000e-02	-2.47727e-43	
-22	2.856000e-02	-2.44388e-43	
-23	3.056000e-02	-2.40937e-43	
-24	3.256000e-02	-2.37377e-43	
-25	3.456000e-02	-2.33707e-43	
-26	3.656000e-02	-2.29932e-43	
-27	3.856000e-02	-2.26051e-43	
-28	4.056000e-02	-2.22068e-43	
-29	4.256000e-02	-2.17983e-43	
-30	4.456000e-02	-2.13800e-43	
-31	4.656000e-02	-2.09519e-43	
-32	4.856000e-02	-2.05144e-43	
-33	5.056000e-02	-2.00675e-43	
-34	5.256000e-02	-1.96115e-43	
-35	5.456000e-02	-1.91467e-43	
-36	5.656000e-02	-1.86732e-43	
-37	5.856000e-02	-1.81913e-43	
-38	6.056000e-02	-1.77011e-43	
-39	6.256000e-02	-1.72030e-43	
-40	6.456000e-02	-1.66972e-43	
-41	6.656000e-02	-1.61839e-43	
-42	6.856000e-02	-1.56633e-43	
-43	7.056000e-02	-1.51357e-43	
-44	7.256000e-02	-1.46013e-43	
-45	7.456000e-02	-1.40604e-43	
-46	7.656000e-02	-1.35132e-43	
-47	7.856000e-02	-1.29600e-43	
-48	8.056000e-02	-1.24011e-43	
-49	8.256000e-02	-1.18367e-43	
-50	8.456000e-02	-1.12671e-43	
-51	8.656000e-02	-1.06925e-43	
-52	8.856000e-02	-1.01132e-43	
-53	9.056000e-02	-9.52954e-44	
-54	9.256000e-02	-8.94171e-44	
-
-Index   time            V(7)            
---------------------------------------------------------------------------------
-55	9.456000e-02	-8.35001e-44	
-56	9.656000e-02	-7.75471e-44	
-57	9.856000e-02	-7.15610e-44	
-58	1.000000e-01	-6.71639e-44	
diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib
index e6fcb32b..ff75f664 100644
--- a/src/SubcircuitLibrary/ujt/ujt-cache.lib
+++ b/src/SubcircuitLibrary/ujt/ujt-cache.lib
@@ -20,23 +20,10 @@ X -c 4 50 -200 100 U 35 35 1 1 P
 ENDDRAW
 ENDDEF
 #
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
 # NLDS
 #
-DEF NLDS B 0 40 Y Y 1 F N
-F0 "B" 0 0 60 H V C CNN
+DEF NLDS BB 0 40 Y Y 1 F N
+F0 "BB" 0 0 60 H V C CNN
 F1 "NLDS" 0 0 60 H V C CNN
 F2 "" 0 0 60 H V C CNN
 F3 "" 0 0 60 H V C CNN
diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir
index 017c4845..e0e911d7 100644
--- a/src/SubcircuitLibrary/ujt/ujt.cir
+++ b/src/SubcircuitLibrary/ujt/ujt.cir
@@ -1,18 +1,18 @@
 * /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir
 
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jun 16 10:51:40 2019
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
 
 * Sheet Name: /
-R3  GND 6 1000k		
-C1  5 7 35p		
-R1  7 2 38.15		
-R2  3 5 2.518k		
-U1  1 2 3 PORT		
-B1  5 7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)		
-D1  1 4 eSim_Diode		
-H1  6 GND 4 5 1k		
+R3  /0 /6 1000k		
+H1  /6 /0 /4 /5 1k		
+C1  /5 /7 35p		
+R1  /7 /2 38.15k		
+R2  /3 /5 2.518k		
+U1  /1 /2 /3 PORT		
+B1  /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)		
+D1  /1 /4 eSim_Diode		
 
 .end
diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out
index c3186f1c..2045c539 100644
--- a/src/SubcircuitLibrary/ujt/ujt.cir.out
+++ b/src/SubcircuitLibrary/ujt/ujt.cir.out
@@ -1,17 +1,17 @@
 * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
 
 .include emitter.lib
-r3  gnd 6 1000k
-c1  5 7 35p
-r1  7 2 38.15
-r2  3 5 2.518k
-* u1  1 2 3 port
-b1  5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
-d1 1 4 emitter
+r3  /0 /6 1000k
 * h1
-Vh1 4 5 0
-h1 6 gnd Vh1 1k
-.tran 5e-06 100e-03 0e-03
+c1  /5 /7 35p
+r1  /7 /2 38.15k
+r2  /3 /5 2.518k
+* u1  /1 /2 /3 port
+b1  /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
+d1 /1 /4 emitter
+Vh1 /4 /5 0
+h1 /6 /0 Vh1 1k
+.tran 5e-03 100e-03 0e-03
 
 * Control Statements 
 .control
diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch
index c1eb98f1..a82bddf7 100644
--- a/src/SubcircuitLibrary/ujt/ujt.sch
+++ b/src/SubcircuitLibrary/ujt/ujt.sch
@@ -28,15 +28,26 @@ $EndDescr
 $Comp
 L eSim_R R3
 U 1 1 5CF5F733
-P 7400 2850
-F 0 "R3" H 7450 2980 50  0000 C CNN
-F 1 "1000k" H 7450 2900 50  0000 C CNN
-F 2 "" H 7450 2830 30  0000 C CNN
-F 3 "" V 7450 2900 30  0000 C CNN
-	1    7400 2850
+P 6650 3400
+F 0 "R3" H 6700 3530 50  0000 C CNN
+F 1 "1000k" H 6700 3450 50  0000 C CNN
+F 2 "" H 6700 3380 30  0000 C CNN
+F 3 "" V 6700 3450 30  0000 C CNN
+	1    6650 3400
 	0    1    -1   0   
 $EndComp
 $Comp
+L CCVS H1
+U 1 1 5CF5F77B
+P 6150 3350
+F 0 "H1" H 6150 3500 50  0000 C CNN
+F 1 "1k" H 5950 3300 50  0000 C CNN
+F 2 "" H 6150 3350 60  0000 C CNN
+F 3 "" H 6150 3350 60  0000 C CNN
+	1    6150 3350
+	0    1    1    0   
+$EndComp
+$Comp
 L eSim_C C1
 U 1 1 5CF61B3A
 P 5150 4700
@@ -52,7 +63,7 @@ L eSim_R R1
 U 1 1 5CF6211F
 P 4300 4850
 F 0 "R1" H 4350 4980 50  0000 C CNN
-F 1 "38.15" H 4350 4900 50  0000 C CNN
+F 1 "38.15k" H 4350 4900 50  0000 C CNN
 F 2 "" H 4350 4830 30  0000 C CNN
 F 3 "" V 4350 4900 30  0000 C CNN
 	1    4300 4850
@@ -83,12 +94,12 @@ $EndComp
 $Comp
 L PORT U1
 U 1 1 5CF689AD
-P 5950 1200
-F 0 "U1" H 6000 1300 30  0000 C CNN
-F 1 "PORT" H 5950 1200 30  0000 C CNN
-F 2 "" H 5950 1200 60  0000 C CNN
-F 3 "" H 5950 1200 60  0000 C CNN
-	1    5950 1200
+P 5950 2200
+F 0 "U1" H 6000 2300 30  0000 C CNN
+F 1 "PORT" H 5950 2200 30  0000 C CNN
+F 2 "" H 5950 2200 60  0000 C CNN
+F 3 "" H 5950 2200 60  0000 C CNN
+	1    5950 2200
 	0    1    1    0   
 $EndComp
 $Comp
@@ -102,6 +113,16 @@ F 3 "" H 4600 3000 60  0000 C CNN
 	3    4600 3000
 	0    1    1    0   
 $EndComp
+Text Label 5600 4100 0    60   ~ 0
+5
+Text Label 5950 3150 0    60   ~ 0
+4
+Text Label 5950 2600 0    60   ~ 0
+1
+Text Label 6450 3050 0    60   ~ 0
+6
+Text Label 6450 3650 0    60   ~ 0
+0
 $Comp
 L NLDS B1
 U 1 1 5CFD2C88
@@ -113,37 +134,54 @@ F 3 "" H 5950 4800 60  0000 C CNN
 	1    5950 4800
 	1    0    0    -1  
 $EndComp
+Text Label 5350 5250 0    60   ~ 0
+7
+Text Label 4600 3450 0    60   ~ 0
+3
+Text Label 4250 4500 0    60   ~ 0
+2
 $Comp
 L eSim_Diode D1
 U 1 1 5CFF8BB7
-P 5950 1850
-F 0 "D1" H 5950 1950 50  0000 C CNN
-F 1 "eSim_Diode" H 5950 1750 50  0000 C CNN
-F 2 "" H 5950 1850 60  0000 C CNN
-F 3 "" H 5950 1850 60  0000 C CNN
-	1    5950 1850
+P 5950 2850
+F 0 "D1" H 5950 2950 50  0000 C CNN
+F 1 "eSim_Diode" H 5950 2750 50  0000 C CNN
+F 2 "" H 5950 2850 60  0000 C CNN
+F 3 "" H 5950 2850 60  0000 C CNN
+	1    5950 2850
 	0    1    1    0   
 $EndComp
 Wire Wire Line
-	6950 2500 7450 2500
+	6200 3050 6700 3050
+Wire Wire Line
+	6700 3050 6700 3200
+Wire Wire Line
+	6200 3650 6300 3650
+Wire Wire Line
+	6300 3650 6700 3650
 Wire Wire Line
-	7450 2500 7450 2650
+	5950 2450 5950 2700
 Wire Wire Line
-	6950 3100 7450 3100
+	5950 3000 5950 3300
 Wire Wire Line
-	5950 1450 5950 1700
+	5950 3400 5950 3850
 Wire Wire Line
-	5950 2000 5950 2750
+	5950 3850 5950 4100
 Wire Wire Line
-	5950 2850 5950 4450
+	5950 4100 5950 4450
 Wire Wire Line
 	5150 4100 5150 4550
 Wire Wire Line
-	4600 4100 5950 4100
+	4600 4100 5150 4100
+Wire Wire Line
+	5150 4100 5950 4100
+Connection ~ 5950 4100
 Wire Wire Line
 	5150 4850 5150 5250
 Wire Wire Line
-	4250 5250 5950 5250
+	4250 5250 5150 5250
+Wire Wire Line
+	5150 5250 5950 5250
 Wire Wire Line
 	4250 5250 4250 4950
 Wire Wire Line
@@ -157,49 +195,5 @@ Wire Wire Line
 	5950 5250 5950 5150
 Connection ~ 5150 5250
 Wire Wire Line
-	7450 3100 7450 2950
-Connection ~ 5950 4100
-$Comp
-L CCVS H1
-U 1 1 5D04A7ED
-P 6900 2800
-F 0 "H1" H 6900 2950 50  0000 C CNN
-F 1 "1k" H 6700 2750 50  0000 C CNN
-F 2 "" H 6900 2800 60  0000 C CNN
-F 3 "" H 6900 2800 60  0000 C CNN
-	1    6900 2800
-	0    1    1    0   
-$EndComp
-$Comp
-L GND #PWR01
-U 1 1 5D04C560
-P 7150 3150
-F 0 "#PWR01" H 7150 2900 50  0001 C CNN
-F 1 "GND" H 7150 3000 50  0000 C CNN
-F 2 "" H 7150 3150 50  0001 C CNN
-F 3 "" H 7150 3150 50  0001 C CNN
-	1    7150 3150
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7150 3150 7150 3100
-Connection ~ 7150 3100
-Wire Wire Line
-	5950 2750 6700 2750
-Wire Wire Line
-	6700 2850 5950 2850
-Text GLabel 5950 1550 0    60   Input ~ 0
-1
-Text GLabel 5950 2200 0    60   Input ~ 0
-4
-Text GLabel 5950 3500 0    60   Input ~ 0
-5
-Text GLabel 5700 5250 3    60   Input ~ 0
-7
-Text GLabel 4250 4550 0    60   Input ~ 0
-2
-Text GLabel 4600 3350 0    60   Input ~ 0
-3
-Text GLabel 7200 2500 1    60   Input ~ 0
-6
+	6700 3650 6700 3500
 $EndSCHEMATC
diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub
index e86745b5..2fb1db35 100644
--- a/src/SubcircuitLibrary/ujt/ujt.sub
+++ b/src/SubcircuitLibrary/ujt/ujt.sub
@@ -1,16 +1,16 @@
 * Subcircuit ujt
-.subckt ujt 1 2 3 
+.subckt ujt /1 /2 /3 
 * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
 .include emitter.lib
-r3  gnd 6 1000k
-c1  5 7 35p
-r1  7 2 38.15
-r2  3 5 2.518k
-b1  5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
-d1 1 4 emitter
+r3  /0 /6 1000k
 * h1
-Vh1 4 5 0
-h1 6 gnd Vh1 1k
+c1  /5 /7 35p
+r1  /7 /2 38.15k
+r2  /3 /5 2.518k
+b1  /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
+d1 /1 /4 emitter
+Vh1 /4 /5 0
+h1 /6 /0 Vh1 1k
 * Control Statements
 
 .ends ujt
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml
index 993933d5..4468b395 100644
--- a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml
+++ b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
+<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/browser/Welcome.py b/src/browser/Welcome.py
index f9f273df..2d91bcc9 100644
--- a/src/browser/Welcome.py
+++ b/src/browser/Welcome.py
@@ -2,7 +2,10 @@ from PyQt4 import QtGui, QtCore
 
 
 class Welcome(QtGui.QWidget):
-    """This class contains content of dock area part of initial esim Window."""
+    """
+    This class contains content of dock area part of initial esim Window.
+    It creates Welcome page of eSim.
+    """
 
     def __init__(self):
         QtGui.QWidget.__init__(self)
diff --git a/src/browser/pages/welcome.html b/src/browser/pages/welcome.html
index 3c48a85a..6c4a6d11 100644
--- a/src/browser/pages/welcome.html
+++ b/src/browser/pages/welcome.html
@@ -39,7 +39,7 @@ pre{
 <center><img src="../../../images/logo.png" alt="eSim logo" height="100" width="100"></center>
 <br/> 
 <p>
-<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>) and  Ngspice(<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>). eSim source is released under <b>GNU General Public License.</b> 
+<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>), Ngspice (<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>) and GHDL (<a href=http://ghdl.free.fr/>http://ghdl.free.fr/</a>). eSim source is released under <b>GNU General Public License.</b> 
 </p>
 <br/>
 <p>
diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py
index 2ab8743e..8a29ad72 100644
--- a/src/configuration/Appconfig.py
+++ b/src/configuration/Appconfig.py
@@ -12,11 +12,10 @@
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
 #      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Tuesday 24 Feb 2015 
-#      REVISION: Wednesday 18 Dec 2019
+#       CREATED: Tuesday 24 February 2015
+#      REVISION: Friday 14 February 2020
 # =========================================================================
 
-
 from PyQt4 import QtGui
 import os
 import json
@@ -31,7 +30,7 @@ class Appconfig(QtGui.QWidget):
     This class also contains function for
     - Printing error.
     - Showing warnings.
-    - Dispalying information.
+    - Displaying information.
     """
 
     # Home directory
@@ -42,9 +41,9 @@ class Appconfig(QtGui.QWidget):
     # Current Subcircuit detail
     current_subcircuit = {"SubcircuitName": None}
     # Workspace detail
-    workspace_text = '''eSim stores your project in a folder called a \
-    eSim-Workspace. You can choose a different workspace folder to use\
-     for this session.'''
+    workspace_text = "eSim stores your project in a folder called "
+    workspace_text += "eSim-Workspace. You can choose a different "
+    workspace_text += "workspace folder to use for this session."
     procThread_list = []
     proc_dict = {}
     # holds the pids of all external windows corresponds to the current project
@@ -63,8 +62,23 @@ class Appconfig(QtGui.QWidget):
     # Try catch added, since eSim cannot be accessed under parser for Win10
     try:
         modelica_map_json = parser_esim.get('eSim', 'MODELICA_MAP_JSON')
-    except BaseException:
-        print("Cannot access Modelica's map_json path --- .esim folder")
+    except BaseException as e:
+        print("===============================================")
+        print("Cannot access Modelica map file --- .esim folder")
+        print(str(e))
+        print("===============================================")
+
+    # Open file and read KiCad config path
+    try:
+        file = open('../supportFiles/kicad_config_path.txt', 'r')
+        kicad_path = file.read().rstrip()
+        file.close()
+    except BaseException as e:
+        kicad_path = None
+        print("===============================================")
+        print("Cannot access kicad path file --- supportFiles")
+        print(str(e))
+        print("===============================================")
 
     try:
         project_explorer = json.load(open(dictPath))
@@ -76,8 +90,8 @@ class Appconfig(QtGui.QWidget):
         super(Appconfig, self).__init__()
         # Application Details
         self._APPLICATION = 'eSim'
-        self._VERSION = 'v1.1'
-        self._AUTHOR = 'Fahim'
+        self._VERSION = 'v2.0.0'
+        self._AUTHOR = 'Fahim, Rahul'
 
         # Application geometry setting
         self._app_xpos = 100
diff --git a/src/configuration/browser/UserManual.py b/src/configuration/browser/UserManual.py
deleted file mode 100644
index 3bcfbace..00000000
--- a/src/configuration/browser/UserManual.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from PyQt4 import QtGui
-import webbrowser
-
-
-class UserManual(QtGui.QWidget):
-    """
-    This class creates Welcome page of eSim.
-    """
-
-    def __init__(self):
-        QtGui.QWidget.__init__(self)
-
-        self.vlayout = QtGui.QVBoxLayout()
-
-        self.url = "../browser/pages/User-Manual/eSim.html"
-        self.test = webbrowser.open(
-            "../browser/pages/User-Manual/eSim.html", new=2)
-
-        self.setLayout(self.vlayout)
-        self.show()
diff --git a/src/deviceModelLibrary/Diode/D.lib b/src/deviceModelLibrary/Diode/D.lib
index 974dd402..8a7fb4da 100644
--- a/src/deviceModelLibrary/Diode/D.lib
+++ b/src/deviceModelLibrary/Diode/D.lib
@@ -1 +1,2 @@
-.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
+.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/src/deviceModelLibrary/Diode/LED.lib b/src/deviceModelLibrary/Diode/LED.lib
new file mode 100644
index 00000000..000831b2
--- /dev/null
+++ b/src/deviceModelLibrary/Diode/LED.lib
@@ -0,0 +1,2 @@
+.model LED D(is=4.36625E-25 rs=3.00014 n=1.38167 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/src/deviceModelLibrary/Diode/LED.xml b/src/deviceModelLibrary/Diode/LED.xml
new file mode 100644
index 00000000..91eb9169
--- /dev/null
+++ b/src/deviceModelLibrary/Diode/LED.xml
@@ -0,0 +1 @@
+<library><model_name>D</model_name><ref_model>LED</ref_model><param><cjo>1.700E-12</cjo><rs>4.755E-01</rs><is>2.495E-09</is><m>1.959E-01</m><n>1.679E00</n><bv>1.000E02</bv><ibv>1.000E-04</ibv><tt>3.030E-09</tt><vj>1</vj></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Diode/PowerDiode.lib b/src/deviceModelLibrary/Diode/PowerDiode.lib
index d6fb6469..a2f61dce 100644
--- a/src/deviceModelLibrary/Diode/PowerDiode.lib
+++ b/src/deviceModelLibrary/Diode/PowerDiode.lib
@@ -1 +1,20 @@
-.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
+.MODEL PowerDiode D(
++ Vj=.75
++ Nbvl=14.976
++ Cjo=175p
++ Rs=.25
++ Isr=1.859n
++ Eg=1.11
++ M=.5516
++ Nbv=1.6989
++ N=1
++ Tbv1=-21.277u
++ bv=1800
++ Fc=.5
++ Ikf=0
++ Nr=2
++ Ibv=20.245m
++ Is=2.2E-15
++ Xti=3
++ Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.lib b/src/deviceModelLibrary/Diode/ZenerD1N750.lib
index ec968783..890c37fe 100644
--- a/src/deviceModelLibrary/Diode/ZenerD1N750.lib
+++ b/src/deviceModelLibrary/Diode/ZenerD1N750.lib
@@ -1 +1,3 @@
-.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m Nbvl=14.976 Tbv1=-21.277u )
+.model D1N750	D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 
++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m 
++ Nbvl=14.976 Tbv1=-21.277u) 
diff --git a/src/deviceModelLibrary/IGBT/NIGBT.lib b/src/deviceModelLibrary/IGBT/NIGBT.lib
index 67cdd9ca..86cd1b4e 100644
--- a/src/deviceModelLibrary/IGBT/NIGBT.lib
+++ b/src/deviceModelLibrary/IGBT/NIGBT.lib
@@ -1 +1,11 @@
-.MODEL IXGH40N60 NIGBT( TAU=287.56E-9 KF=.36047 AREA=37.500E-6 AGD=18.750E-6 KP=50.034 VT=4.1822 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 )
+.MODEL IXGH40N60 NIGBT(
++  TAU=287.56E-9
++  KF=.36047
++  AREA=37.500E-6
++  AGD=18.750E-6
++  KP=50.034
++  VT=4.1822
++  CGS=31.942E-9
++  COXD=53.188E-9
++  VTD=2.6570
+)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/IGBT/PIGBT.lib b/src/deviceModelLibrary/IGBT/PIGBT.lib
index ddf3c779..d4f9e814 100644
--- a/src/deviceModelLibrary/IGBT/PIGBT.lib
+++ b/src/deviceModelLibrary/IGBT/PIGBT.lib
@@ -1 +1,10 @@
-.MODEL IXGH40N60 PIGBT( TAU=287.56E-9 KP=50.034 AREA=37.500E-6 AGD=18.750E-6 VT=4.1822 KF=.36047 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 )
+.MODEL IXGH40N60 PIGBT (
++ TAU=287.56E-9
++ KP=50.034
++ AREA=37.500E-6
++ AGD=18.750E-6
++ VT=4.1822
++ KF=.36047
++ CGS=31.942E-9
++ COXD=53.188E-9
++ VTD=2.6570)
diff --git a/src/deviceModelLibrary/JFET/NJF.lib b/src/deviceModelLibrary/JFET/NJF.lib
index a9ea544f..dbb2cbae 100644
--- a/src/deviceModelLibrary/JFET/NJF.lib
+++ b/src/deviceModelLibrary/JFET/NJF.lib
@@ -1 +1,4 @@
-.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
+.model J2N3819	NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++		Af=1)
diff --git a/src/deviceModelLibrary/JFET/PJF.lib b/src/deviceModelLibrary/JFET/PJF.lib
index 95297dea..5589571d 100644
--- a/src/deviceModelLibrary/JFET/PJF.lib
+++ b/src/deviceModelLibrary/JFET/PJF.lib
@@ -1 +1,5 @@
-.model J2N3820 PJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
+.model J2N3820	PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++		Af=1)
+
diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib
index a38a9673..2e6f4635 100644
--- a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib
+++ b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib
@@ -1 +1,6 @@
-.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 NSUB=1.40E17 )
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.lib b/src/deviceModelLibrary/MOS/NMOS-180nm.lib
index bb481014..51e9b119 100644
--- a/src/deviceModelLibrary/MOS/NMOS-180nm.lib
+++ b/src/deviceModelLibrary/MOS/NMOS-180nm.lib
@@ -1 +1,13 @@
-.model CMOSN NMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3 )
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.lib b/src/deviceModelLibrary/MOS/NMOS-5um.lib
index 5260b17a..a237e1fe 100644
--- a/src/deviceModelLibrary/MOS/NMOS-5um.lib
+++ b/src/deviceModelLibrary/MOS/NMOS-5um.lib
@@ -1,3 +1,5 @@
 * 5um technology
 
-.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 Level=1 Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib
index 12ae53b8..848e8b05 100644
--- a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib
+++ b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib
@@ -1 +1,6 @@
-.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 NSUB=1.0E17 )
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.lib b/src/deviceModelLibrary/MOS/PMOS-180nm.lib
index 998d1885..032b5b95 100644
--- a/src/deviceModelLibrary/MOS/PMOS-180nm.lib
+++ b/src/deviceModelLibrary/MOS/PMOS-180nm.lib
@@ -1 +1,11 @@
-.model CMOSP PMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3 )
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.lib b/src/deviceModelLibrary/MOS/PMOS-5um.lib
index 1d808f0b..9c3ed976 100644
--- a/src/deviceModelLibrary/MOS/PMOS-5um.lib
+++ b/src/deviceModelLibrary/MOS/PMOS-5um.lib
@@ -1,3 +1,5 @@
 *5um technology
 
-.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 Level=1 Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/Misc/CORE.lib b/src/deviceModelLibrary/Misc/CORE.lib
index df7539a5..a7581029 100644
--- a/src/deviceModelLibrary/Misc/CORE.lib
+++ b/src/deviceModelLibrary/Misc/CORE.lib
@@ -1 +1,9 @@
-.MODEL K3019PL_3C8 Core( A=44.82 C=.4112 abc=123 Area=1.38 K=25.74 MS=415.2K Path=4.52 )
+.MODEL K3019PL_3C8 Core(
++  A=44.82 
++  C=.4112
++  abc=123
++  Area=1.38
++  K=25.74
++  MS=415.2K
++  Path=4.52
+)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/CORE.lib b/src/deviceModelLibrary/Templates/CORE.lib
index df7539a5..a7581029 100644
--- a/src/deviceModelLibrary/Templates/CORE.lib
+++ b/src/deviceModelLibrary/Templates/CORE.lib
@@ -1 +1,9 @@
-.MODEL K3019PL_3C8 Core( A=44.82 C=.4112 abc=123 Area=1.38 K=25.74 MS=415.2K Path=4.52 )
+.MODEL K3019PL_3C8 Core(
++  A=44.82 
++  C=.4112
++  abc=123
++  Area=1.38
++  K=25.74
++  MS=415.2K
++  Path=4.52
+)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/D.lib b/src/deviceModelLibrary/Templates/D.lib
index 974dd402..8a7fb4da 100644
--- a/src/deviceModelLibrary/Templates/D.lib
+++ b/src/deviceModelLibrary/Templates/D.lib
@@ -1 +1,2 @@
-.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
+.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/src/deviceModelLibrary/Templates/NIGBT.lib b/src/deviceModelLibrary/Templates/NIGBT.lib
index 67cdd9ca..8c09dcbc 100644
--- a/src/deviceModelLibrary/Templates/NIGBT.lib
+++ b/src/deviceModelLibrary/Templates/NIGBT.lib
@@ -1 +1,10 @@
-.MODEL IXGH40N60 NIGBT( TAU=287.56E-9 KF=.36047 AREA=37.500E-6 AGD=18.750E-6 KP=50.034 VT=4.1822 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 )
+.MODEL IXGH40N60 NIGBT (
++ TAU=287.56E-9
++ KP=50.034
++ AREA=37.500E-6
++ AGD=18.750E-6
++ VT=4.1822
++ KF=.36047
++ CGS=31.942E-9
++ COXD=53.188E-9
++ VTD=2.6570)
diff --git a/src/deviceModelLibrary/Templates/NJF.lib b/src/deviceModelLibrary/Templates/NJF.lib
index a9ea544f..dbb2cbae 100644
--- a/src/deviceModelLibrary/Templates/NJF.lib
+++ b/src/deviceModelLibrary/Templates/NJF.lib
@@ -1 +1,4 @@
-.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
+.model J2N3819	NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++		Af=1)
diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib
index a38a9673..2e6f4635 100644
--- a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib
+++ b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib
@@ -1 +1,6 @@
-.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 NSUB=1.40E17 )
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.lib b/src/deviceModelLibrary/Templates/NMOS-180nm.lib
index bb481014..51e9b119 100644
--- a/src/deviceModelLibrary/Templates/NMOS-180nm.lib
+++ b/src/deviceModelLibrary/Templates/NMOS-180nm.lib
@@ -1 +1,13 @@
-.model CMOSN NMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3 )
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.lib b/src/deviceModelLibrary/Templates/NMOS-5um.lib
index 5260b17a..a237e1fe 100644
--- a/src/deviceModelLibrary/Templates/NMOS-5um.lib
+++ b/src/deviceModelLibrary/Templates/NMOS-5um.lib
@@ -1,3 +1,5 @@
 * 5um technology
 
-.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 Level=1 Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/Templates/NPN.lib b/src/deviceModelLibrary/Templates/NPN.lib
index 382b5380..6509fe7a 100644
--- a/src/deviceModelLibrary/Templates/NPN.lib
+++ b/src/deviceModelLibrary/Templates/NPN.lib
@@ -1 +1,4 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/deviceModelLibrary/Templates/PIGBT.lib b/src/deviceModelLibrary/Templates/PIGBT.lib
index ddf3c779..d4f9e814 100644
--- a/src/deviceModelLibrary/Templates/PIGBT.lib
+++ b/src/deviceModelLibrary/Templates/PIGBT.lib
@@ -1 +1,10 @@
-.MODEL IXGH40N60 PIGBT( TAU=287.56E-9 KP=50.034 AREA=37.500E-6 AGD=18.750E-6 VT=4.1822 KF=.36047 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 )
+.MODEL IXGH40N60 PIGBT (
++ TAU=287.56E-9
++ KP=50.034
++ AREA=37.500E-6
++ AGD=18.750E-6
++ VT=4.1822
++ KF=.36047
++ CGS=31.942E-9
++ COXD=53.188E-9
++ VTD=2.6570)
diff --git a/src/deviceModelLibrary/Templates/PJF.lib b/src/deviceModelLibrary/Templates/PJF.lib
index 95297dea..5589571d 100644
--- a/src/deviceModelLibrary/Templates/PJF.lib
+++ b/src/deviceModelLibrary/Templates/PJF.lib
@@ -1 +1,5 @@
-.model J2N3820 PJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
+.model J2N3820	PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++		Af=1)
+
diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib
index 12ae53b8..848e8b05 100644
--- a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib
+++ b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib
@@ -1 +1,6 @@
-.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 NSUB=1.0E17 )
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.lib b/src/deviceModelLibrary/Templates/PMOS-180nm.lib
index 998d1885..032b5b95 100644
--- a/src/deviceModelLibrary/Templates/PMOS-180nm.lib
+++ b/src/deviceModelLibrary/Templates/PMOS-180nm.lib
@@ -1 +1,11 @@
-.model CMOSP PMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3 )
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.lib b/src/deviceModelLibrary/Templates/PMOS-5um.lib
index 1d808f0b..9c3ed976 100644
--- a/src/deviceModelLibrary/Templates/PMOS-5um.lib
+++ b/src/deviceModelLibrary/Templates/PMOS-5um.lib
@@ -1,3 +1,5 @@
 *5um technology
 
-.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 Level=1 Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/Templates/PNP.lib b/src/deviceModelLibrary/Templates/PNP.lib
index 23fe9d0f..7edda0ea 100644
--- a/src/deviceModelLibrary/Templates/PNP.lib
+++ b/src/deviceModelLibrary/Templates/PNP.lib
@@ -1 +1,4 @@
-.model Q2N2907A PNP( Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10 )
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/deviceModelLibrary/Transistor/BC547B.lib b/src/deviceModelLibrary/Transistor/BC547B.lib
new file mode 100644
index 00000000..723537a7
--- /dev/null
+++ b/src/deviceModelLibrary/Transistor/BC547B.lib
@@ -0,0 +1 @@
+.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14  NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56  RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8)
diff --git a/src/deviceModelLibrary/Transistor/BC547B.xml b/src/deviceModelLibrary/Transistor/BC547B.xml
new file mode 100644
index 00000000..da06e5c4
--- /dev/null
+++ b/src/deviceModelLibrary/Transistor/BC547B.xml
@@ -0,0 +1 @@
+<library><model_name>NPN</model_name><ref_model>BC547B</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Isc>0 </Isc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ise>14.34f </Ise><Br>6.092 </Br><Ikf>.2847 </Ikf><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Vjc>.75 </Vjc><Vje>.75 </Vje><Xtf>3 </Xtf><Itf>.6 </Itf><Is>14.34f </Is><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Transistor/NPN.lib b/src/deviceModelLibrary/Transistor/NPN.lib
index 382b5380..6509fe7a 100644
--- a/src/deviceModelLibrary/Transistor/NPN.lib
+++ b/src/deviceModelLibrary/Transistor/NPN.lib
@@ -1 +1,4 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/deviceModelLibrary/Transistor/NPN.xml b/src/deviceModelLibrary/Transistor/NPN.xml
index b2698bb1..ee2abcbc 100644
--- a/src/deviceModelLibrary/Transistor/NPN.xml
+++ b/src/deviceModelLibrary/Transistor/NPN.xml
@@ -1,33 +1 @@
-<library>
-<model_name>NPN</model_name>
-<ref_model>Q2N2222</ref_model>
-<param>
-<Is>14.34f </Is>
-<Xti>3 </Xti>
-<Eg>1.11 </Eg>
-<Vaf>74.03 </Vaf>
-<Bf>400 </Bf>
-<Ne>1.307 </Ne>
-<Ise>14.34f </Ise>
-<Ikf>.2847 </Ikf>
-<Xtb>1.5 </Xtb>
-<Br>6.092 </Br>
-<Nc>2 </Nc>
-<Isc>0 </Isc>
-<Ikr>0 </Ikr>
-<Rc>1 </Rc>
-<Cjc>7.306p </Cjc>
-<Mjc>.3416 </Mjc>
-<Vjc>.75 </Vjc>
-<Fc>.5 </Fc>
-<Cje>22.01p </Cje>
-<Mje>.377 </Mje>
-<Vje>.75 </Vje>
-<Tr>46.91n </Tr>
-<Tf>411.1p </Tf>
-<Itf>.6 </Itf>
-<Vtf>1.7 </Vtf>
-<Xtf>3 </Xtf>
-<Rb>10 </Rb>
-</param>
-</library>
+<library><model_name>NPN</model_name><ref_model>Q2N2222</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400</Bf><Fc>.5 </Fc><Ikf>.2847 </Ikf><Br>6.092 </Br><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Isc>0 </Isc><Ise>14.34f </Ise><Xtf>3 </Xtf><Vje>.75 </Vje><Is>14.34f </Is><Itf>.6 </Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Transistor/PNP.lib b/src/deviceModelLibrary/Transistor/PNP.lib
index 23fe9d0f..7edda0ea 100644
--- a/src/deviceModelLibrary/Transistor/PNP.lib
+++ b/src/deviceModelLibrary/Transistor/PNP.lib
@@ -1 +1,4 @@
-.model Q2N2907A PNP( Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10 )
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/deviceModelLibrary/User Libraries/userDiode.lib b/src/deviceModelLibrary/User Libraries/userDiode.lib
index 89b96f4a..ef18bb50 100644
--- a/src/deviceModelLibrary/User Libraries/userDiode.lib	
+++ b/src/deviceModelLibrary/User Libraries/userDiode.lib	
@@ -1 +1,20 @@
-.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
+.MODEL D1N750 D(
++  Vj=.75
++  Nbvl=14.976
++  Cjo=175p
++  Rs=.25
++  Isr=1.859n
++  Eg=1.11
++  M=.5516
++  Nbv=1.6989
++  N=1
++  Tbv1=-21.277u
++  Bv=8.1
++  Fc=.5
++  Ikf=0
++  Nr=2
++  Ibv=20.245m
++  Is=880.5E-18
++  Xti=3
++  Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 8973501d..6cb25e80 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -12,11 +12,10 @@
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
 #      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Tuesday 24 Feb 2015 
-#      REVISION: Wednesday 18 Dec 2019
+#       CREATED: Tuesday 24 February 2015 
+#      REVISION: Friday 14 February 2020
 # =========================================================================
 
-
 import pathmagic  # noqa
 from PyQt4 import QtGui, QtCore
 from configuration.Appconfig import Appconfig
@@ -32,11 +31,12 @@ import time
 from PyQt4.Qt import QSize
 import sys
 import os
+import shutil
 
 
 # Its our main window of application.
 class Application(QtGui.QMainWindow):
-    """This class initializes all objects used in this file(Application.py)."""
+    """This class initializes all objects used in this file."""
     global project_name
 
     def __init__(self, *args):
@@ -45,6 +45,9 @@ class Application(QtGui.QMainWindow):
         # Calling __init__ of super class
         QtGui.QMainWindow.__init__(self, *args)
 
+        #Flag for mode of operation. Default is set to offline mode.
+        self.online_flag = False
+                
         # Creating require Object
         self.obj_workspace = Workspace.Workspace()
         self.obj_Mainview = MainView()
@@ -62,57 +65,64 @@ class Application(QtGui.QMainWindow):
         self.setWindowTitle(self.obj_appconfig._APPLICATION)
         self.showMaximized()
         self.setWindowIcon(QtGui.QIcon('../../images/logo.png'))
-        # self.show()
+
         self.systemTrayIcon = QtGui.QSystemTrayIcon(self)
         self.systemTrayIcon.setIcon(QtGui.QIcon('../../images/logo.png'))
         self.systemTrayIcon.setVisible(True)
 
-    # This function initializes Tool Bars
     def initToolBar(self):
         """
-        In this function we are setting icons, short-cuts,and
-        defining functonality for:
-
-            - Top-tool-bar (New project, Open project, Close project,\
-                Help option )
-            - Left-tool-bar (Open Schematic, Convert KiCad to NgSpice,\
-                Simuation, Model Editor, Subcircuit, NGHDL, Modelica\
-                Converter, OM Optimisation )
+        This function initializes Tool Bars.
+        It setups the icons, short-cuts and defining functonality for:
+
+            - Top-tool-bar (New project, Open project, Close project, \
+                Mode switch, Help option)
+            - Left-tool-bar (Open Schematic, Convert KiCad to NgSpice, \
+                Simuation, Model Editor, Subcircuit, NGHDL, Modelica \
+                Converter, OM Optimisation)
         """
         # Top Tool bar
         self.newproj = QtGui.QAction(
             QtGui.QIcon('../../images/newProject.png'),
-            '<b>New Project</b>',
-            self)
+            '<b>New Project</b>', self
+        )
         self.newproj.setShortcut('Ctrl+N')
         self.newproj.triggered.connect(self.new_project)
-        # self.newproj.connect(self.newproj, QtCore.SIGNAL('triggered()'),
-        #                      self, QtCore.SLOT(self.new_project()))
 
         self.openproj = QtGui.QAction(
             QtGui.QIcon('../../images/openProject.png'),
-            '<b>Open Project</b>',
-            self)
+            '<b>Open Project</b>', self
+        )
         self.openproj.setShortcut('Ctrl+O')
         self.openproj.triggered.connect(self.open_project)
 
         self.closeproj = QtGui.QAction(
             QtGui.QIcon('../../images/closeProject.png'),
-            '<b>Close Project</b>',
-            self)
+            '<b>Close Project</b>', self
+        )
         self.closeproj.setShortcut('Ctrl+X')
         self.closeproj.triggered.connect(self.close_project)
 
+        self.switchmode = QtGui.QAction(
+            QtGui.QIcon('../../images/disable.png'),
+            '<b>Mode switching has been disabled. Relaunch ' +
+            'eSim to fix any config issues</b>', self
+        )
+        self.validate_mode()
+        self.switchmode.setShortcut('Ctrl+G')
+        self.switchmode.triggered.connect(self.change_mode)
+
         self.helpfile = QtGui.QAction(
-            QtGui.QIcon('../../images/helpProject.png'), '<b>Help</b>', self)
+            QtGui.QIcon('../../images/helpProject.png'), '<b>Help</b>', self
+        )
         self.helpfile.setShortcut('Ctrl+H')
         self.helpfile.triggered.connect(self.help_project)
 
         self.topToolbar = self.addToolBar('Top Tool Bar')
         self.topToolbar.addAction(self.newproj)
         self.topToolbar.addAction(self.openproj)
-
         self.topToolbar.addAction(self.closeproj)
+        self.topToolbar.addAction(self.switchmode)
         self.topToolbar.addAction(self.helpfile)
 
         # This part is setting fossee logo to the right
@@ -125,9 +135,8 @@ class Application(QtGui.QMainWindow):
         self.logo = QtGui.QLabel()
         self.logopic = QtGui.QPixmap(
             os.path.join(
-                os.path.abspath('../..'),
-                'images',
-                'fosseeLogo.png'))
+                os.path.abspath('../..'), 'images', 'fosseeLogo.png'
+            ))
         self.logopic = self.logopic.scaled(
             QSize(150, 150), QtCore.Qt.KeepAspectRatio)
         self.logo.setPixmap(self.logopic)
@@ -137,50 +146,48 @@ class Application(QtGui.QMainWindow):
         # Left Tool bar Action Widget
         self.kicad = QtGui.QAction(
             QtGui.QIcon('../../images/kicad.png'),
-            '<b>Open Schematic</b>',
-            self)
+            '<b>Open Schematic</b>', self
+        )
         self.kicad.triggered.connect(self.obj_kicad.openSchematic)
 
         self.conversion = QtGui.QAction(
             QtGui.QIcon('../../images/ki-ng.png'),
-            '<b>Convert Kicad to Ngspice</b>',
-            self)
+            '<b>Convert Kicad to Ngspice</b>', self
+        )
         self.conversion.triggered.connect(self.obj_kicad.openKicadToNgspice)
 
         self.ngspice = QtGui.QAction(
-            QtGui.QIcon('../../images/ngspice.png'),
-            '<b>Simulation</b>',
-            self)
+            QtGui.QIcon('../../images/ngspice.png'), '<b>Simulation</b>', self
+        )
         self.ngspice.triggered.connect(self.open_ngspice)
 
         self.model = QtGui.QAction(
             QtGui.QIcon('../../images/model.png'),
-            '<b>Model Editor</b>',
-            self)
+            '<b>Model Editor</b>', self
+        )
         self.model.triggered.connect(self.open_modelEditor)
 
         self.subcircuit = QtGui.QAction(
             QtGui.QIcon('../../images/subckt.png'),
-            '<b>Subcircuit</b>',
-            self)
+            '<b>Subcircuit</b>', self
+        )
         self.subcircuit.triggered.connect(self.open_subcircuit)
 
         self.nghdl = QtGui.QAction(
-            QtGui.QIcon('../../images/nghdl.png'),
-            '<b>Nghdl</b>',
-            self)
+            QtGui.QIcon('../../images/nghdl.png'), '<b>Nghdl</b>', self
+        )
         self.nghdl.triggered.connect(self.open_nghdl)
 
         self.omedit = QtGui.QAction(
             QtGui.QIcon('../../images/omedit.png'),
-            '<b>Modelica Converter</b>',
-            self)
+            '<b>Modelica Converter</b>', self
+        )
         self.omedit.triggered.connect(self.open_OMedit)
 
         self.omoptim = QtGui.QAction(
             QtGui.QIcon('../../images/omoptim.png'),
-            '<b>OM Optimisation</b>',
-            self)
+            '<b>OM Optimisation</b>', self
+        )
         self.omoptim.triggered.connect(self.open_OMoptim)
 
         # Adding Action Widget to tool bar
@@ -197,30 +204,30 @@ class Application(QtGui.QMainWindow):
         self.lefttoolbar.setOrientation(QtCore.Qt.Vertical)
         self.lefttoolbar.setIconSize(QSize(40, 40))
 
-    # This function closes the ongoing program(process).
     def closeEvent(self, event):
         '''
-        When exit button is pressed a Message box pops out with
+        This function closes the ongoing program (process).
+        When exit button is pressed a Message box pops out with \
         exit message and buttons 'Yes', 'No'.
 
             1. If 'Yes' is pressed:
-                - it checks that program(process) in procThread_list\
-                    (list made in Appconfig.py):
+                - check that program (process) in procThread_list \
+                  (a list made in Appconfig.py):
 
-                    - if available it terminates that program
-                    - if the program(process) is not available,\
-                        it checks for it
-                      in process_obj (list made in Appconfig.py) if found it
-                      closes the program.
+                    - if available it terminates that program.
+                    - if the program (process) is not available, \
+                      then check it in process_obj (a list made in \
+                      Appconfig.py) and if found, it closes the program.
 
             2. If 'No' is pressed:
                 - the program just continues as it was doing earlier.
         '''
-        exit_msg = "Are you sure you want to exit the program?" \
-            " All unsaved data will be lost."
+        exit_msg = "Are you sure you want to exit the program?"
+        exit_msg += " All unsaved data will be lost."
         reply = QtGui.QMessageBox.question(
             self, 'Message', exit_msg, QtGui.QMessageBox.Yes,
-            QtGui.QMessageBox.No)
+            QtGui.QMessageBox.No
+        )
 
         if reply == QtGui.QMessageBox.Yes:
             for proc in self.obj_appconfig.procThread_list:
@@ -236,8 +243,9 @@ class Application(QtGui.QMainWindow):
                         pass
             except BaseException:
                 pass
-            # Just checking if open project and New project window is open. If
-            # yes just close it when application is closed
+
+            # Check if "Open project" and "New project" window is open.
+            # If yes, just close it when application is closed.
             try:
                 self.project.close()
             except BaseException:
@@ -248,15 +256,48 @@ class Application(QtGui.QMainWindow):
         elif reply == QtGui.QMessageBox.No:
             event.ignore()
 
-    # This function closes the saved project.
+    def new_project(self):
+        """This function call New Project Info class."""
+        text, ok = QtGui.QInputDialog.getText(
+            self, 'New Project Info', 'Enter Project Name:'
+        )
+        if ok:
+            self.projname = (str(text))
+            self.project = NewProjectInfo()
+            directory, filelist = self.project.createProject(self.projname)
+            self.obj_Mainview.obj_projectExplorer.addTreeNode(
+                directory, filelist)
+        else:
+            print("No new project created")
+            self.obj_appconfig.print_info('No new project created')
+            try:
+                self.obj_appconfig.print_info(
+                    'Current project is : ' +
+                    self.obj_appconfig.current_project["ProjectName"]
+                )
+            except BaseException:
+                pass
+
+    def open_project(self):
+        """This project call Open Project Info class."""
+        print("Function : Open Project")
+        self.project = OpenProjectInfo()
+        try:
+            directory, filelist = self.project.body()
+            self.obj_Mainview.obj_projectExplorer.addTreeNode(
+                directory, filelist)
+        except BaseException:
+            pass
+
     def close_project(self):
         """
-        This function first checks whether project(file) is present in list.
+        This function closes the saved project.
+        It first checks whether project (file) is present in list.
 
             - If present:
                 - it first kills that process-id.
                 - closes that file.
-                - Shows message "Current project <path of file> is closed"
+                - Shows message "Current project <path_to_file> is closed"
 
             - If not present: pass
         """
@@ -274,60 +315,155 @@ class Application(QtGui.QMainWindow):
             self.obj_Mainview.obj_dockarea.closeDock()
             self.obj_appconfig.current_project['ProjectName'] = None
             self.systemTrayIcon.showMessage(
-                'Close',
-                'Current project ' +
-                os.path.basename(current_project) +
-                ' is Closed.')
-
-    # This function call New Project Info class.
-    def new_project(self):
-        text, ok = QtGui.QInputDialog.getText(
-            self, 'New Project Info', 'Enter Project Name:')
-        if ok:
-            self.projname = (str(text))
-            self.project = NewProjectInfo()
-            directory, filelist = self.project.createProject(self.projname)
+                'Close', 'Current project ' +
+                os.path.basename(current_project) + ' is Closed.'
+            )
 
-            self.obj_Mainview.obj_projectExplorer.addTreeNode(
-                directory, filelist)
+    def validate_mode(self):
+        """
+        This function is used for checking fp-lib-tables file.
+        If not than copy from supportFiles folder.
+        First it will check path for kicad folder is present or not. if present
+            1) it will check fp-lib-table file is present or not.
+                - If not present
+                    - Than copy form SourceFile folder
+            2) it will check for both file,
+               i.e online and offline file is present or not.
+                - If both are present
+                    -Than remove offline.
+            3) it will check wich file is present
+                - If fp-lib-table-offline is present
+                    - Than online mode will set and used
+                - If fp-lib-table-online is present
+                    - Than offline mode wiil set and used
+                - If both file are not present
+                    -Than copy fp-lib-table from source file
+        Otherwise the disable icon is set and feature is disabled.
+        """
 
+        if self.obj_appconfig.kicad_path is not None:
+            # -----------------------------------------------------
+            # fp-lib-table is not there than copy from supportFiles/
+            if not os.path.exists(
+                self.obj_appconfig.kicad_path + "/fp-lib-table"):
+                shutil.copy('../supportFiles/fp-lib-table' ,
+                    self.obj_appconfig.kicad_path + "/")
+            # -----------------------------------------------------
+            """checking online and offline both file's are avaliable.
+            if yes than remove offline file."""
+            if os.path.exists(self.obj_appconfig.kicad_path +
+                     "/fp-lib-table-offline") and os.path.exists(
+                self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-online"):
+                     os.remove(self.obj_appconfig.kicad_path +
+                        "/fp-lib-table-offline")
+            # -----------------------------------------------------
+            # This ladder is used for checking which file is present.
+            if os.path.exists(self.obj_appconfig.kicad_path +
+                     "/fp-lib-table-offline"):
+                self.switchmode = QtGui.QAction(
+                    QtGui.QIcon('../../images/online.png'),
+                    '<b>Go Offline</b>',self)
+                self.online_flag = True
+
+            elif os.path.exists(self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-online"):
+                self.switchmode = QtGui.QAction(
+                    QtGui.QIcon('../../images/offline.png'),
+                    '<b>Go Online</b>',self)
+                self.online_flag = False
+            else:
+                # if online and offline is not avaliable
+                shutil.copy('../supportFiles/fp-lib-table-online' ,
+                        self.obj_appconfig.kicad_path + "/")
+                if os.path.exists(self.obj_appconfig.kicad_path +
+                        "/fp-lib-table-online"):
+                    self.switchmode = QtGui.QAction(
+                        QtGui.QIcon('../../images/offline.png'),
+                        '<b>Go Online</b>',self)
+                    self.online_flag = False
+            #----------------------------------------------------
         else:
-            print("No new project created")
-            self.obj_appconfig.print_info('No new project created')
-            try:
-                self.obj_appconfig.print_info(
-                    'Current project is : ' +
-                    self.obj_appconfig.current_project["ProjectName"])
-            except BaseException:
-                pass
+            # if path is not found
+            self.switchmode = QtGui.QAction(QtGui.QIcon(
+                '../../images/disable.png'),
+                '<b>Mode switching has been disabled. Relaunch ' +
+                'eSim to fix any config issues</b>', self)
 
-    # This project call Open Project Info class
-    def open_project(self):
-        print("Function : Open Project")
-        self.project = OpenProjectInfo()
-
-        try:
-            directory, filelist = self.project.body()
-            self.obj_Mainview.obj_projectExplorer.addTreeNode(
-                directory, filelist)
-        except BaseException:
-            pass
+    def change_mode(self):
+        """
+        This function is used for changing mode of operation for KiCad. \
+        There are three modes of operation : 
+            - online 
+            - offline
+            - disable
+        
+        It will check whether kicad config path is present or not.
+            - If path is available and none of the KiCad tools \
+              (associated with eSim) are open, then depending on \
+              online_flag, it will swap appropriate fp-lib-table files.
+            - If any of the KiCad tools (associated with eSim) is open, \
+              then ask user to close all these tools.
+            - And if path is not found, then disable this feature.
+
+        @paramas
+
+        @return
+            None
+        """
+        if self.obj_appconfig.kicad_path is not None:
+            try:
+                if not self.obj_kicad.check_open_schematic():
+                    if self.online_flag:
+                        os.rename(
+                            self.obj_appconfig.kicad_path + "/fp-lib-table",
+                            self.obj_appconfig.kicad_path + "/fp-lib-table-online"
+                        )
+                        os.rename(
+                            self.obj_appconfig.kicad_path + "/fp-lib-table-offline",
+                            self.obj_appconfig.kicad_path + "/fp-lib-table"
+                        )
+                        self.switchmode.setIcon(QtGui.QIcon('../../images/offline.png'))
+                        self.switchmode.setText('<b>Go Online</b>')
+                        self.online_flag = False
+                    else:
+                        os.rename(
+                            self.obj_appconfig.kicad_path + "/fp-lib-table",
+                            self.obj_appconfig.kicad_path + "/fp-lib-table-offline")
+                        os.rename(
+                            self.obj_appconfig.kicad_path + "/fp-lib-table-online",
+                            self.obj_appconfig.kicad_path + "/fp-lib-table")
+                        self.switchmode.setIcon(QtGui.QIcon('../../images/online.png'))
+                        self.switchmode.setText('<b>Go Offline</b>')
+                        self.online_flag = True
+                else:
+                    self.msg = QtGui.QErrorMessage()
+                    self.msg.showMessage('Please save and close all the Kicad'
+                        'Windows first, and then change the online-offline mode')
+                    self.msg.setWindowTitle("Error Message")
+            except:
+                self.validate_mode()
+        else:
+            self.info_msg = QtGui.QMessageBox.critical(self,
+                            'Message',
+                            "Please make sure kicad_folder_file is " +
+                            "present in supportFiles folder.")
 
-    # This page opens usermanual in dockarea.
     def help_project(self):
         """
-        - It prints the message ""Function : Help""
-        - Uses print_info() method of class Appconfig
-          from Configuration/Appconfig.py file.
-        - Call method usermanual() from ./DockArea.py.
+        This function opens usermanual in dockarea.
+            - It prints the message ""Function : Help""
+            - Uses print_info() method of class Appconfig
+              from Configuration/Appconfig.py file.
+            - Call method usermanual() from ./DockArea.py.
         """
         print("Function : Help")
         self.obj_appconfig.print_info('Help is called')
         print("Current Project is : ", self.obj_appconfig.current_project)
         self.obj_Mainview.obj_dockarea.usermanual()
 
-    # This Function execute ngspice on current project.
     def open_ngspice(self):
+        """This Function execute ngspice on current project."""
         self.projDir = self.obj_appconfig.current_project["ProjectName"]
 
         if self.projDir is not None:
@@ -342,37 +478,39 @@ class Application(QtGui.QMainWindow):
                         break
                 except Exception:
                     pass
-                time.sleep(0.2)
+                time.sleep(0.5)
 
                 # Fail Safe ===>
                 count += 1
                 if count >= 100:
                     raise Exception(
-                        "ngspice taking too long, check netlist file")
+                        "Ngspice taking too long for simulation. "
+                        "Check netlist file to change simulation parameters."
+                    )
 
             # Calling Python Plotting
-
             try:
                 self.obj_Mainview.obj_dockarea.plottingEditor()
             except Exception as e:
                 self.msg = QtGui.QErrorMessage(None)
                 self.msg.showMessage(
                     'Error while opening python plotting Editor.'
-                    ' Please look at console for more details')
+                    ' Please look at console for more details.'
+                )
                 print("Exception Message:", str(e))
                 self.obj_appconfig.print_error('Exception Message : ' + str(e))
                 self.msg.setWindowTitle("Error Message")
-
         else:
             self.msg = QtGui.QErrorMessage()
             self.msg.showMessage(
                 'Please select the project first.'
-                ' You can either create new project or open existing project')
+                ' You can either create new project or open existing project'
+            )
             self.msg.setWindowTitle("Error Message")
 
-    # This function opens 'subcircuit' option in left-tool-bar.
     def open_subcircuit(self):
         """
+        This function opens 'subcircuit' option in left-tool-bar.
         When 'subcircuit' icon is clicked wich is present in
         left-tool-bar of main page:
 
@@ -384,36 +522,34 @@ class Application(QtGui.QMainWindow):
         self.obj_appconfig.print_info('Subcircuit editor is called')
         self.obj_Mainview.obj_dockarea.subcircuiteditor()
 
-    # This function calls NGHDl option in left-tool-bar.
     def open_nghdl(self):
         """
-        This function uses validateTool() method from
-        Validation.py:
+        This function calls NGHDL option in left-tool-bar.
+        It uses validateTool() method from Validation.py:
 
             - If 'nghdl' is present in executables list then
-              it adds passes command 'nghdl -e' to WorkerThread class of
+              it passes command 'nghdl -e' to WorkerThread class of
               Worker.py.
-            - If 'nghdl' not present then it shows error message.
+            - If 'nghdl' is not present, then it shows error message.
         """
-        print("Function : Nghdl")
-        self.obj_appconfig.print_info('Nghdl is called')
+        print("Function : NGHDL")
+        self.obj_appconfig.print_info('NGHDL is called')
 
         if self.obj_validation.validateTool('nghdl'):
             self.cmd = 'nghdl -e'
             self.obj_workThread = Worker.WorkerThread(self.cmd)
             self.obj_workThread.start()
-
         else:
             self.msg = QtGui.QErrorMessage(None)
-            self.msg.showMessage('Error while opening nghdl.\
-                Please make sure nghdl is installed')
-            self.obj_appconfig.print_error('Error while opening nghdl.\
-                Please make sure nghdl is installed')
-            self.msg.setWindowTitle('nghdl Error Message')
+            self.msg.showMessage('Error while opening NGHDL. ' +
+                'Please make sure it is installed')
+            self.obj_appconfig.print_error('Error while opening NGHDL. ' +
+                'Please make sure it is installed')
+            self.msg.setWindowTitle('NGHDL Error')
 
-    # This function opens model editor option in left-tool-bar.
     def open_modelEditor(self):
         """
+        This function opens model editor option in left-tool-bar.
         When model editor icon is clicked which is present in
         left-tool-bar of main page:
 
@@ -425,19 +561,22 @@ class Application(QtGui.QMainWindow):
         self.obj_appconfig.print_info('Model editor is called')
         self.obj_Mainview.obj_dockarea.modelEditor()
 
-    # This function call ngspice to OM edit converter
-    # and then launch OM edit.
     def open_OMedit(self):
-        self.obj_appconfig.print_info('OM edit is called')
+        """
+        This function calls ngspice to OMEdit converter and then launch OMEdit.
+        """
+        self.obj_appconfig.print_info('OMEdit is called')
         self.projDir = self.obj_appconfig.current_project["ProjectName"]
 
         if self.projDir is not None:
             if self.obj_validation.validateCirOut(self.projDir):
                 self.projName = os.path.basename(self.projDir)
                 self.ngspiceNetlist = os.path.join(
-                    self.projDir, self.projName + ".cir.out")
+                    self.projDir, self.projName + ".cir.out"
+                )
                 self.modelicaNetlist = os.path.join(
-                    self.projDir, self.projName + ".mo")
+                    self.projDir, self.projName + ".mo"
+                )
 
                 """
                 try:
@@ -487,31 +626,29 @@ class Application(QtGui.QMainWindow):
             else:
                 self.msg = QtGui.QErrorMessage()
                 self.msg.showMessage(
-                    'Current project does not contain any ngspice file.\
-                        Please create ngspice file with extension .cir.out')
+                    'Current project does not contain any Ngspice file. ' +
+                    'Please create Ngspice file with extension .cir.out'
+                )
                 self.msg.setWindowTitle("Missing Ngspice netlist")
         else:
             self.msg = QtGui.QErrorMessage()
             self.msg.showMessage(
-                'Please select the project first.\
-                    You can either create new project\
-                        or open existing project')
+                'Please select the project first. ' +
+                'You can either create a new project or open existing project'
+            )
             self.msg.setWindowTitle("Error Message")
 
-    # sdf
     def open_OMoptim(self):
         """
-        This function uses validateTool() method from
-        Validation.py:
+        This function uses validateTool() method from Validation.py:
 
             - If 'OMOptim' is present in executables list then
-              it adds passes command 'OMOptim' to WorkerThread class of
-              Worker.py.
-            - If 'OMOptim' not present then it shows error message with
+              it passes command 'OMOptim' to WorkerThread class of Worker.py
+            - If 'OMOptim' is not present, then it shows error message with
               link to download it on Linux and Windows.
         """
-        print("Function : OM Optim")
-        self.obj_appconfig.print_info('OM Optim is called')
+        print("Function : OMOptim")
+        self.obj_appconfig.print_info('OMOptim is called')
         # Check if OMOptim is installed
         if self.obj_validation.validateTool("OMOptim"):
             # Creating a command to run
@@ -531,7 +668,7 @@ class Application(QtGui.QMainWindow):
                 "To install it on Windows : Go to <a href="
                 "https://www.openmodelica.org/download/download-windows"
                 ">OpenModelica Windows</a> and install latest version.<br/>"
-                )
+            )
             self.msg.setTextFormat(QtCore.Qt.RichText)
             self.msg.setText(self.msgContent)
             self.msg.setWindowTitle("Error Message")
@@ -545,14 +682,11 @@ class MainView(QtGui.QWidget):
     This class defines whole view and style of main page:
 
         - Position of tool bars:
-
-         - Top tool bar.
-         - Left tool bar.
-
+            - Top tool bar.
+            - Left tool bar.
         - Project explorer Area.
         - Dock area.
         - Console area.
-
     """
 
     def __init__(self, *args):
@@ -606,7 +740,7 @@ class MainView(QtGui.QWidget):
         self.setLayout(self.mainLayout)
 
 
-# It is main function of the module.It starts the application
+# It is main function of the module and starts the application
 def main(args):
     """
     The splash screen opened at the starting of screen is performed
@@ -628,8 +762,6 @@ def main(args):
 
 
 # Call main function
-
-
 if __name__ == '__main__':
     # Create and display the splash screen
     main(sys.argv)
diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py
index db706fa7..9824a307 100644
--- a/src/frontEnd/DockArea.py
+++ b/src/frontEnd/DockArea.py
@@ -14,6 +14,7 @@ dockList = ['Welcome']
 count = 1
 dock = {}
 
+
 class DockArea(QtGui.QMainWindow):
     """
     This class contains function for designing UI of all the editors
@@ -22,8 +23,8 @@ class DockArea(QtGui.QMainWindow):
         - Test Editor.
         - Model Editor.
         - Python Plotting.
-        - NgSpice Editor.
-        - Kicad to NgSpice Editor.
+        - Ngspice Editor.
+        - Kicad to Ngspice Editor.
         - Subcircuit Editor.
         - Modelica editor.
     """
@@ -53,8 +54,9 @@ class DockArea(QtGui.QMainWindow):
         self.show()
 
     def createTestEditor(self):
-        """This function create widget for Library Editor."""
+        """This function create widget for Library Editor"""
         global count
+                
         self.testWidget = QtGui.QWidget()
         self.testArea = QtGui.QTextEdit()
         self.testLayout = QtGui.QVBoxLayout()
@@ -74,16 +76,18 @@ class DockArea(QtGui.QMainWindow):
 
         dock['Tips-' + str(count)].raise_()
 
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['Tips-' + str(count)])
+        temp = self.obj_appconfig.current_project['ProjectName']
+        if temp:
+            self.obj_appconfig.dock_dict[temp].append(
+                dock['Tips-' + str(count)]
+            )
         count = count + 1
 
     def plottingEditor(self):
-        """This function create widget for interactive PythonPlotting"""
+        """This function create widget for interactive PythonPlotting."""
         self.projDir = self.obj_appconfig.current_project["ProjectName"]
         self.projName = os.path.basename(self.projDir)
-        # self.project = os.path.join(self.projDir,self.projName)
+        # self.project = os.path.join(self.projDir, self.projName)
 
         global count
         self.plottingWidget = QtGui.QWidget()
@@ -104,13 +108,15 @@ class DockArea(QtGui.QMainWindow):
         dock['Plotting-' + str(count)].setFocus()
         dock['Plotting-' + str(count)].raise_()
 
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['Plotting-' + str(count)])
+        temp = self.obj_appconfig.current_project['ProjectName']
+        if temp:
+            self.obj_appconfig.dock_dict[temp].append(
+                dock['Plotting-' + str(count)]
+            )
         count = count + 1
 
     def ngspiceEditor(self, projDir):
-        """Sdf."""
+        """ This function creates widget for Ngspice window."""
         self.projDir = projDir
         self.projName = os.path.basename(self.projDir)
         self.ngspiceNetlist = os.path.join(
@@ -121,9 +127,8 @@ class DockArea(QtGui.QMainWindow):
 
         self.ngspiceLayout = QtGui.QVBoxLayout()
         self.ngspiceLayout.addWidget(
-            NgspiceWidget(
-                self.ngspiceNetlist,
-                self.projDir))
+            NgspiceWidget(self.ngspiceNetlist, self.projDir)
+        )
 
         # Adding to main Layout
         self.ngspiceWidget.setLayout(self.ngspiceLayout)
@@ -143,9 +148,12 @@ class DockArea(QtGui.QMainWindow):
         dock['NgSpice-' + str(count)].setVisible(True)
         dock['NgSpice-' + str(count)].setFocus()
         dock['NgSpice-' + str(count)].raise_()
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['NgSpice-' + str(count)])
+        
+        temp = self.obj_appconfig.current_project['ProjectName']
+        if temp:
+            self.obj_appconfig.dock_dict[temp].append(
+                dock['NgSpice-' + str(count)]
+            )
         count = count + 1
 
     def modelEditor(self):
@@ -178,15 +186,11 @@ class DockArea(QtGui.QMainWindow):
         dock['Model Editor-' + str(count)].setFocus()
         dock['Model Editor-' + str(count)].raise_()
 
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['Model Editor-' + str(count)])
         count = count + 1
 
     def kicadToNgspiceEditor(self, clarg1, clarg2=None):
         """
-        This function is creating Editor UI for-
-        Kicad to Ngspice conversion.
+        This function is creating Editor UI for Kicad to Ngspice conversion.
         """
         global count
         self.kicadToNgspiceWidget = QtGui.QWidget()
@@ -212,10 +216,13 @@ class DockArea(QtGui.QMainWindow):
         dock['kicadToNgspice-' + str(count)].setVisible(True)
         dock['kicadToNgspice-' + str(count)].setFocus()
         dock['kicadToNgspice-' + str(count)].raise_()
+        dock['kicadToNgspice-' + str(count)].activateWindow()
 
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['kicadToNgspice-' + str(count)])
+        temp = self.obj_appconfig.current_project['ProjectName']
+        if temp:
+            self.obj_appconfig.dock_dict[temp].append(
+                dock['kicadToNgspice-' + str(count)]
+            )
         count = count + 1
 
     def subcircuiteditor(self):
@@ -244,12 +251,10 @@ class DockArea(QtGui.QMainWindow):
         dock['Subcircuit-' + str(count)].setFocus()
         dock['Subcircuit-' + str(count)].raise_()
 
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['Subcircuit-' + str(count)])
         count = count + 1
 
     def usermanual(self):
+        """This function creates a widget for user manual."""
         global count
         self.usermanualWidget = QtGui.QWidget()
         self.usermanualLayout = QtGui.QVBoxLayout()
@@ -277,7 +282,7 @@ class DockArea(QtGui.QMainWindow):
         count = count + 1
 
     def modelicaEditor(self, projDir):
-        """Dfg."""
+        """This function sets up the UI for ngspice to modelica conversion."""
         global count
         self.modelicaWidget = QtGui.QWidget()
         self.modelicaLayout = QtGui.QVBoxLayout()
@@ -300,9 +305,11 @@ class DockArea(QtGui.QMainWindow):
         .QWidget { border-radius: 15px; border: 1px solid gray;\
             padding: 5px; width: 200px; height: 150px;  } \
         ")
-        # temp = self.obj_appconfig.current_project['ProjectName']
-        # self.obj_appconfig.dock_dict[temp].append(
-        #     dock['Modelica-' + str(count)])
+        temp = self.obj_appconfig.current_project['ProjectName']
+        if temp:
+            self.obj_appconfig.dock_dict[temp].append(
+                dock['Modelica-' + str(count)]
+            )
 
         count = count + 1
 
diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py
index 09e756af..1557d450 100644
--- a/src/frontEnd/ProjectExplorer.py
+++ b/src/frontEnd/ProjectExplorer.py
@@ -35,6 +35,8 @@ class ProjectExplorer(QtGui.QWidget):
 
         # CSS
         self.treewidget.setStyleSheet(" \
+            QTreeView { border-radius: 15px; border: 1px \
+            solid gray; padding: 5px; width: 200px; height: 150px;  }\
             QTreeView::branch:has-siblings:!adjoins-item { \
             border-image: url(../../images/vline.png) 0;} \
             QTreeView::branch:has-siblings:adjoins-item { \
@@ -61,7 +63,8 @@ class ProjectExplorer(QtGui.QWidget):
                 )
                 for files in children:
                     QtGui.QTreeWidgetItem(
-                        parentnode, [files, os.path.join(parents, files)])
+                        parentnode, [files, os.path.join(parents, files)]
+                    )
         self.window.addWidget(self.treewidget)
 
         self.treewidget.doubleClicked.connect(self.openProject)
@@ -74,7 +77,8 @@ class ProjectExplorer(QtGui.QWidget):
         os.path.join(parents)
         pathlist = parents.split(os.sep)
         parentnode = QtGui.QTreeWidgetItem(
-            self.treewidget, [pathlist[-1], parents])
+            self.treewidget, [pathlist[-1], parents]
+        )
         for files in children:
             QtGui.QTreeWidgetItem(
                 parentnode, [files, os.path.join(parents, files)]
@@ -90,7 +94,6 @@ class ProjectExplorer(QtGui.QWidget):
         ) = []
 
     def openMenu(self, position):
-
         indexes = self.treewidget.selectedIndexes()
         if len(indexes) > 0:
             level = 0
@@ -117,9 +120,8 @@ class ProjectExplorer(QtGui.QWidget):
         self.indexItem = self.treewidget.currentIndex()
         filename = str(self.indexItem.data())
         self.filePath = str(
-            self.indexItem.sibling(
-                self.indexItem.row(),
-                1).data())
+            self.indexItem.sibling(self.indexItem.row(), 1).data()
+        )
         self.obj_appconfig.print_info(
             'The current project is ' + self.filePath)
 
@@ -132,16 +134,15 @@ class ProjectExplorer(QtGui.QWidget):
         self.save = QtGui.QPushButton('Save and Exit')
         self.save.setDisabled(True)
         self.windowgrid = QtGui.QGridLayout()
-        # if (os.path.isfile(str(self.filePath))) == True:
+
         if (os.path.isfile(str(self.filePath))):
             self.fopen = open(str(self.filePath), 'r')
             lines = self.fopen.read()
             self.text.setText(lines)
 
             QtCore.QObject.connect(
-                self.text,
-                QtCore.SIGNAL("textChanged()"),
-                self.enable_save)
+                self.text, QtCore.SIGNAL("textChanged()"), self.enable_save
+            )
 
             vbox_main = QtGui.QVBoxLayout(self.textwindow)
             vbox_main.addWidget(self.text)
@@ -167,29 +168,30 @@ class ProjectExplorer(QtGui.QWidget):
                         self.obj_appconfig.current_project['ProjectName']]
                 ) = []
 
-    # This function is enabling save button option.
     def enable_save(self):
+        """This function enables save button option."""
         self.save.setEnabled(True)
 
-    # This function is saving data before it closes the given file.
     def save_data(self):
         """
-        This function first opens file in write-mode, when write
-        operation is performed it closes that file and then it closes window.
+        This function saves data before it closes the given file.
+        It first opens file in write-mode, write operation is performed, \
+        closes that file and then it closes window.
         """
         self.fopen = open(self.filePath, 'w')
         self.fopen.write(self.text.toPlainText())
         self.fopen.close()
         self.textwindow.close()
 
-    # This function removes the project in explorer area by right
-    # clicking on project and selecting remove option.
     def removeProject(self):
+        """
+        This function removes the project in explorer area by right \
+        clicking on project and selecting remove option.
+        """
         self.indexItem = self.treewidget.currentIndex()
         self.filePath = str(
-            self.indexItem.sibling(
-                self.indexItem.row(),
-                1).data())
+            self.indexItem.sibling(self.indexItem.row(), 1).data()
+        )
         self.int = self.indexItem.row()
         self.treewidget.takeTopLevelItem(self.int)
 
@@ -200,14 +202,15 @@ class ProjectExplorer(QtGui.QWidget):
         json.dump(self.obj_appconfig.project_explorer,
                   open(self.obj_appconfig.dictPath, 'w'))
 
-    # This function refresh the project in explorer area by right
-    # clicking on project and selecting refresh option.
     def refreshProject(self):
+        """
+        This function refresh the project in explorer area by right \
+        clicking on project and selecting refresh option.
+        """
         self.indexItem = self.treewidget.currentIndex()
         self.filePath = str(
-            self.indexItem.sibling(
-                self.indexItem.row(),
-                1).data())
+            self.indexItem.sibling(self.indexItem.row(), 1).data()
+        )
         filelistnew = os.listdir(os.path.join(self.filePath))
         parentnode = self.treewidget.currentItem()
         count = parentnode.childCount()
@@ -216,9 +219,8 @@ class ProjectExplorer(QtGui.QWidget):
                 items.removeChild(items.child(0))
         for files in filelistnew:
             QtGui.QTreeWidgetItem(
-                parentnode, [
-                    files, os.path.join(
-                        self.filePath, files)])
+                parentnode, [files, os.path.join(self.filePath, files)]
+            )
 
         self.obj_appconfig.project_explorer[self.filePath] = filelistnew
         json.dump(self.obj_appconfig.project_explorer,
@@ -226,23 +228,22 @@ class ProjectExplorer(QtGui.QWidget):
 
     def renameProject(self):
         """
-        This function renames the project present in project explorer area
-        it validates first:
+        This function renames the project present in project explorer area.
+        It validates first:
 
             - If project names is not empty.
             - Project name does not contain spaces between them.
             - Project name is different between what it was earlier.
             - Project name should not exist.
 
-        And after project name is changed it recreates
-        the project explorer tree.
+        After project name is changed, it recreates the project explorer tree.
         """
         self.indexItem = self.treewidget.currentIndex()
         self.baseFileName = str(self.indexItem.data())
         newBaseFileName, ok = QtGui.QInputDialog.getText(
-            self, 'Rename Project', 'Project Name:', QtGui.QLineEdit.Normal,
-            self.baseFileName
-            )
+            self, 'Rename Project', 'Project Name:',
+            QtGui.QLineEdit.Normal, self.baseFileName
+        )
         if ok and newBaseFileName:
             print(newBaseFileName)
             print("=================")
@@ -284,8 +285,8 @@ class ProjectExplorer(QtGui.QWidget):
                     # rename project folder
                     updatedProjectPath = newBaseFileName.join(
                         projectPath.rsplit(self.baseFileName, 1))
-                    print("Renaming " + projectPath + " to "
-                          + updatedProjectPath)
+                    print("Renaming " + projectPath + " to " +
+                          updatedProjectPath)
                     os.rename(projectPath, updatedProjectPath)
 
                     # rename files matching project name
@@ -297,8 +298,8 @@ class ProjectExplorer(QtGui.QWidget):
                                 self.baseFileName, newBaseFileName, 1)
                             newFilePath = os.path.join(
                                 updatedProjectPath, projectFile)
-                            print("Renaming " + oldFilePath + " to"
-                                  + newFilePath)
+                            print("Renaming " + oldFilePath + " to" +
+                                  newFilePath)
                             os.rename(oldFilePath, newFilePath)
                             updatedProjectFiles.append(projectFile)
 
@@ -323,10 +324,10 @@ class ProjectExplorer(QtGui.QWidget):
                     print("==========================")
                     msg = QtGui.QErrorMessage(self)
                     msg.showMessage(
-                        'The project "'
-                        + newBaseFileName
-                        + '" already exist.Please select the different name or'
-                        + ' delete existing project')
+                        'The project "' + newBaseFileName +
+                        '" already exist. Please select a different name or' +
+                        ' delete existing project'
+                    )
                     msg.setWindowTitle("Error Message")
 
                 elif reply == "CHECKNAME":
@@ -334,6 +335,7 @@ class ProjectExplorer(QtGui.QWidget):
                     print("===========================")
                     msg = QtGui.QErrorMessage(self)
                     msg.showMessage(
-                        'The project name should not'
-                        + 'contain space between them')
+                        'The project name should not ' +
+                        'contain space between them'
+                    )
                     msg.setWindowTitle("Error Message")
diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py
index 55a8c95e..29be09fc 100644
--- a/src/frontEnd/Workspace.py
+++ b/src/frontEnd/Workspace.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: Workspace.py
 #
 #         USAGE: ---
@@ -11,27 +10,26 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
 #       CREATED: Wednesday 05 February 2015
-#      REVISION:  ---
+#      REVISION: Friday 14 February 2020
 # =========================================================================
+
 from PyQt4 import QtCore, QtGui
 from configuration.Appconfig import Appconfig
 import time
 import os
 
 
-# This class creates Workspace GUI.
 class Workspace(QtGui.QWidget):
     """
     This class creates UI for WorkSpace selection window.
 
-        This window contains text area to select location of your choice
-        or browse location for workspace area.
-
-        By default workspace is set in ~/eSim-Workspace.
-
-         This workspace area contains all the projects made by user.
+        - This window contains text area to select location of your choice \
+          or browse location for workspace area.
+        - By default workspace is set in ~/eSim-Workspace.
+        - This workspace area contains all the projects made by user.
 
     """
 
@@ -43,7 +41,6 @@ class Workspace(QtGui.QWidget):
         self.initWorkspace()
 
     def initWorkspace(self):
-        # print "Calling workspace"
 
         self.mainwindow = QtGui.QVBoxLayout()
         self.split = QtGui.QSplitter()
diff --git a/src/frontEnd/pathmagic.py b/src/frontEnd/pathmagic.py
index 49c4932d..5f0d712c 100644
--- a/src/frontEnd/pathmagic.py
+++ b/src/frontEnd/pathmagic.py
@@ -1,5 +1,6 @@
 import os
 import sys
+
 # Setting PYTHONPATH
 cwd = os.getcwd()
 (setPath, fronEnd) = os.path.split(cwd)
diff --git a/src/kicadtoNgspice/Analysis.py b/src/kicadtoNgspice/Analysis.py
index b24f24c7..e5c05ebe 100644
--- a/src/kicadtoNgspice/Analysis.py
+++ b/src/kicadtoNgspice/Analysis.py
@@ -1,29 +1,27 @@
-
-from PyQt4 import QtGui
+from PyQt4 import QtGui, QtCore
 from . import TrackWidget
 import os
-# from xml.etree import ElementTree as ET
 import json
 
 
 class Analysis(QtGui.QWidget):
     """
     - This class create Analysis Tab in KicadtoNgspice Window. 4 sections -
-    - - Select Analysis Type
-    - - AC Analysis
-    - - DC Analysis
-    - - Transient Analysis
-    - Set various track widget options here, for tracking purposes across\
-    different functions and modules -
-    - - AC_entry_var
-    - - AC_Parameter
-    - - DC_entry_var
-    - - DC_Parameter
-    - - TRAN_entry_var
-    - - TRAN_Parameter
-    - - set_Checkbox
-    - - AC_type
-    - - op_check
+      - Select Analysis Type
+      - AC Analysis
+      - DC Analysis
+      - Transient Analysis
+    - Set various track widget options here, for tracking purposes across \
+      different functions and modules -
+      - AC_entry_var
+      - AC_Parameter
+      - DC_entry_var
+      - DC_Parameter
+      - TRAN_entry_var
+      - TRAN_Parameter
+      - set_Checkbox
+      - AC_type
+      - op_check
     """
 
     def __init__(self, clarg1):
@@ -42,19 +40,21 @@ class Analysis(QtGui.QWidget):
 
     def createAnalysisWidget(self):
         """
-        - Create the main anaylsis widget overwiew
-        - - Checkbox for analysis type
-        - - Place, `AC`, `DC` and `TRANSIENT` analysis tab
-        - - `self.acbox`, `self.dcbox`,`self.trbox`...
+        - Create the main anaylsis widget overwiew:
+          - Checkbox for analysis type
+          - Place, `AC`, `DC` and `TRANSIENT` analysis tab
+          - `self.acbox`, `self.dcbox`, `self.trbox`...
         - Check for `analysis` file, if any in projDir, extract data from it
         - Else set the default checkbox to `TRAN`
         - Accordingly set state for track widget options, as `TRAN`, `AC` ...
         """
         self.grid = QtGui.QGridLayout()
-        self.grid.addWidget(self.createCheckBox(), 0, 0)
-        self.grid.addWidget(self.createACgroup(), 1, 0)
-        self.grid.addWidget(self.createDCgroup(), 2, 0)
-        self.grid.addWidget(self.createTRANgroup(), 3, 0)
+        self.setLayout(self.grid)
+
+        self.grid.addWidget(self.createCheckBox(), 0, 0, QtCore.Qt.AlignTop)
+        self.grid.addWidget(self.createACgroup(), 1, 0, 5, 0)
+        self.grid.addWidget(self.createDCgroup(), 1, 0, 5, 0)
+        self.grid.addWidget(self.createTRANgroup(), 1, 0, 5, 0)
 
         try:
             kicadFile = self.clarg1
@@ -74,6 +74,10 @@ class Analysis(QtGui.QWidget):
                 self.acbox.setDisabled(False)
                 self.dcbox.setDisabled(True)
                 self.trbox.setDisabled(True)
+
+                self.acbox.setVisible(True)
+                self.dcbox.setVisible(False)
+                self.trbox.setVisible(False)
                 self.track_obj.set_CheckBox["ITEMS"] = "AC"
                 if contentlist[1] == 'lin':
                     self.Lin.setChecked(True)
@@ -90,6 +94,10 @@ class Analysis(QtGui.QWidget):
                 self.dcbox.setDisabled(False)
                 self.acbox.setDisabled(True)
                 self.trbox.setDisabled(True)
+
+                self.dcbox.setVisible(True)
+                self.acbox.setVisible(False)
+                self.trbox.setVisible(False)
                 self.track_obj.set_CheckBox["ITEMS"] = "DC"
 
             elif contentlist[0] == '.tran':
@@ -97,6 +105,10 @@ class Analysis(QtGui.QWidget):
                 self.trbox.setDisabled(False)
                 self.acbox.setDisabled(True)
                 self.dcbox.setDisabled(True)
+
+                self.trbox.setVisible(True)
+                self.dcbox.setVisible(False)
+                self.acbox.setVisible(False)
                 self.track_obj.set_CheckBox["ITEMS"] = "TRAN"
 
             elif contentlist[0] == '.op':
@@ -104,6 +116,10 @@ class Analysis(QtGui.QWidget):
                 self.dcbox.setDisabled(False)
                 self.acbox.setDisabled(True)
                 self.trbox.setDisabled(True)
+
+                self.dcbox.setVisible(True)
+                self.acbox.setVisible(False)
+                self.trbox.setVisible(False)
                 self.check.setChecked(True)
                 self.track_obj.set_CheckBox["ITEMS"] = "DC"
 
@@ -111,7 +127,6 @@ class Analysis(QtGui.QWidget):
             self.checkTRAN.setChecked(True)
             self.track_obj.set_CheckBox["ITEMS"] = "TRAN"
 
-        self.setLayout(self.grid)
         self.show()
 
     def createCheckBox(self):
@@ -151,25 +166,37 @@ class Analysis(QtGui.QWidget):
             self.acbox.setDisabled(False)
             self.dcbox.setDisabled(True)
             self.trbox.setDisabled(True)
+
+            self.acbox.setVisible(True)
+            self.dcbox.setVisible(False)
+            self.trbox.setVisible(False)
             self.track_obj.set_CheckBox["ITEMS"] = "AC"
 
         elif self.checkDC.isChecked():
             self.dcbox.setDisabled(False)
             self.acbox.setDisabled(True)
             self.trbox.setDisabled(True)
+
+            self.dcbox.setVisible(True)
+            self.acbox.setVisible(False)
+            self.trbox.setVisible(False)
             self.track_obj.set_CheckBox["ITEMS"] = "DC"
 
         elif self.checkTRAN.isChecked():
             self.trbox.setDisabled(False)
             self.acbox.setDisabled(True)
             self.dcbox.setDisabled(True)
+
+            self.trbox.setVisible(True)
+            self.acbox.setVisible(False)
+            self.dcbox.setVisible(False)
             self.track_obj.set_CheckBox["ITEMS"] = "TRAN"
 
     def createACgroup(self):
         """
         - Designing of AC group in analysis tab
         - 3 radio buttons - Lin | Dec | Oct
-        - 3 input boxes, with top 2 combos\
+        - 3 input boxes, with top 2 combos
         - If previous values exist then fill default values from
           previous value json file
         """
@@ -194,6 +221,7 @@ class Analysis(QtGui.QWidget):
         self.acbox = QtGui.QGroupBox()
         self.acbox.setTitle("AC Analysis")
         self.acbox.setDisabled(True)
+        self.acbox.setVisible(False)
         self.acgrid = QtGui.QGridLayout()
         self.radiobuttongroup = QtGui.QButtonGroup()
         self.Lin = QtGui.QRadioButton("Lin")
@@ -320,11 +348,10 @@ class Analysis(QtGui.QWidget):
 
     '''
     - Below 2 functions handle combo value event listeners for
-    - - start frequency for ac
-    - - stop frequency for ac
+        - start frequency for ac
+        - stop frequency for ac
     - And accordingly set the ac_parameters
     '''
-
     def start_combovalue(self, text):
         """
         - Handle start_fre_combo box event
@@ -343,7 +370,7 @@ class Analysis(QtGui.QWidget):
 
     def set_ac_type(self):
         """
-        - Set track object for AC, according to the type of radio box selected
+        Sets track object for AC, according to the type of radio box selected.
         """
         self.parameter_cnt = 0
 
@@ -353,17 +380,15 @@ class Analysis(QtGui.QWidget):
             self.track_obj.AC_type["ITEMS"] = "dec"
         elif self.Oct.isChecked():
             self.track_obj.AC_type["ITEMS"] = "oct"
-        else:
-            pass
 
     def createDCgroup(self):
         """
         - Create DC area under analysis tab
         - Source 1 and 2, each having 4 input boxes as follows
-        - - Source
-        - - Start
-        - - Increment
-        - - Stop
+            - Source
+            - Start
+            - Increment
+            - Stop
         - The last 3 have combo box pertaining to their unit as well
         - Also in the end a checkbox, for operating system point analysis
         """
@@ -388,6 +413,7 @@ class Analysis(QtGui.QWidget):
         self.dcbox = QtGui.QGroupBox()
         self.dcbox.setTitle("DC Analysis")
         self.dcbox.setDisabled(True)
+        self.dcbox.setVisible(False)
         self.dcgrid = QtGui.QGridLayout()
         self.dcbox.setLayout(self.dcgrid)
 
@@ -811,10 +837,10 @@ class Analysis(QtGui.QWidget):
                 print("Transient Analysis JSON Parse Error")
 
         return self.trbox
+    
     '''
     - Below 3 functions handle event for the combo box in transient group
     '''
-
     def start_combo_change(self, text):
         """Handle start combo box, ie. units, as second, ms"""
         self.tran_parameter[0] = str(text)
diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py
index 883ba534..99f8768a 100644
--- a/src/kicadtoNgspice/Convert.py
+++ b/src/kicadtoNgspice/Convert.py
@@ -1,5 +1,4 @@
 from PyQt4 import QtGui
-
 import os
 import shutil
 from . import TrackWidget
@@ -9,15 +8,15 @@ from xml.etree import ElementTree as ET
 class Convert:
     """
     - This class has all the necessary function required to convert \
-    kicad netlist to ngspice netlist.
+      kicad netlist to ngspice netlist.
     - Method List
-    - - addDeviceLibrary
-    - - addModelParameter
-    - - addSourceParameter
-    - - addSubcircuit
-    - - analysisInsertor
-    - - converttosciform
-    - - defaultvalue
+        - addDeviceLibrary
+        - addModelParameter
+        - addSourceParameter
+        - addSubcircuit
+        - analysisInsertor
+        - converttosciform
+        - defaultvalue
     """
 
     def __init__(self, sourcelisttrack, source_entry_var,
@@ -32,12 +31,12 @@ class Convert:
         """
         - This function extracts the source details to schematicInfo
         - keywords recognised and parsed -
-        - - sine
-        - - pulse
-        - - pwl
-        - - ac
-        - - dc
-        - - exp
+            - sine
+            - pulse
+            - pwl
+            - ac
+            - dc
+            - exp
         - Return updated schematic
         """
 
@@ -355,7 +354,7 @@ class Convert:
 
     def addModelParameter(self, schematicInfo):
         """
-        This function add the Ngspice Model details to schematicInfo
+        This function adds the Ngspice Model details to schematicInfo
         """
 
         # Create object of TrackWidget
@@ -446,8 +445,6 @@ class Convert:
                     # end = line[8]
                     addmodelLine = ".model " + line[3] + " " + line[2] + "("
                     for key, value in line[9].items():
-                        # print "Tags: ",key
-                        # print "Value: ",value
                         # Checking for default value and accordingly assign
                         # param and default.
                         if ':' in key:
@@ -457,7 +454,7 @@ class Convert:
                         else:
                             param = key
                             default = 0
-                        # Cheking if value is iterable.its for vector
+                        # Checking if value is iterable.its for vector
                         if (
                             not isinstance(value, str) and
                             hasattr(value, '__iter__')
@@ -516,17 +513,16 @@ class Convert:
         includeLine = []  # All .include line list
 
         if not deviceLibList:
-            print("No Library Added in the schematic")
-            pass
+            print("No library added in the schematic")
         else:
             for eachline in schematicInfo:
                 words = eachline.split()
                 if words[0] in deviceLibList:
-                    print("Found Library line")
+                    # print("Found Library line")
                     index = schematicInfo.index(eachline)
                     completeLibPath = deviceLibList[words[0]]
                     (libpath, libname) = os.path.split(completeLibPath)
-                    print("Library Path :", libpath)
+                    # print("Library Path :", libpath)
                     # Copying library from devicemodelLibrary to Project Path
                     # Special case for MOSFET
                     if eachline[0] == 'm':
@@ -562,9 +558,6 @@ class Convert:
                         dst = projpath
                         shutil.copy2(src, dst)
 
-                else:
-                    pass
-
             # Adding device line to schematicInfo
             for index, value in deviceLine.items():
                 # Update the device line
@@ -582,7 +575,6 @@ class Convert:
         """
         This function add the subcircuit to schematicInfo
         """
-
         (projpath, filename) = os.path.split(kicadFile)
 
         subList = self.obj_track.subcircuitTrack
@@ -600,7 +592,6 @@ class Convert:
             raise Exception('All subcircuit directories need to be specified.')
         elif not subList:
             print("No Subcircuit Added in the schematic")
-            pass
         else:
             for eachline in schematicInfo:
                 words = eachline.split()
@@ -624,8 +615,6 @@ class Convert:
                         if os.path.isfile(os.path.join(src, files)):
                             if files != "analysis":
                                 shutil.copy2(os.path.join(src, files), dst)
-                else:
-                    pass
 
             # Adding subcircuit line to schematicInfo
             for index, value in subLine.items():
@@ -649,6 +638,5 @@ class Convert:
         for child in libtree.iter():
             if child.tag == 'ref_model':
                 retVal = child.text
-            else:
-                pass
+                
         return retVal
diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py
index 7f63a43b..41faa6f0 100644
--- a/src/kicadtoNgspice/DeviceModel.py
+++ b/src/kicadtoNgspice/DeviceModel.py
@@ -1,6 +1,5 @@
 from PyQt4 import QtGui
 import os
-# from xml.etree import ElementTree as ET
 import json
 from . import TrackWidget
 
@@ -12,13 +11,13 @@ class DeviceModel(QtGui.QWidget):
       transistor and jfet.
     - Same function as the subCircuit file, except for
       this takes different parameters in the if block
-    - - q   TRANSISTOR
-    - - d   DIODE
-    - - j   JFET
-    - - m   MOSFET
+        - q   TRANSISTOR
+        - d   DIODE
+        - j   JFET
+        - m   MOSFET
     - Other 2 functions same as the ones in subCircuit
-    - - trackLibrary
-    - - trackLibraryWithoutButton
+        - trackLibrary
+        - trackLibraryWithoutButton
     """
 
     def __init__(self, schematicInfo, clarg1):
@@ -62,14 +61,14 @@ class DeviceModel(QtGui.QWidget):
         # Set Layout
         self.grid = QtGui.QGridLayout()
         self.setLayout(self.grid)
-        print("Reading Device model details from Schematic")
+        # print("Reading Device model details from Schematic")
 
         for eachline in schematicInfo:
             print("=========================================")
             print(eachline)
             words = eachline.split()
             if eachline[0] == 'q':
-                print("Device Model Transistor: ", words[0])
+                # print("Device Model Transistor: ", words[0])
                 self.devicemodel_dict_beg[words[0]] = self.count
                 transbox = QtGui.QGroupBox()
                 transgrid = QtGui.QGridLayout()
@@ -85,8 +84,6 @@ class DeviceModel(QtGui.QWidget):
                 try:
                     for key in json_data["deviceModel"]:
                         if key == words[0]:
-                            # print "DEVICE MODEL MATCHING---",child.tag[0],\
-                            # child.tag[1],eachline[0],eachline[1]
                             try:
                                 if os.path.exists(
                                         json_data["deviceModel"][key][0]):
@@ -128,7 +125,7 @@ class DeviceModel(QtGui.QWidget):
 
                 self.grid.addWidget(transbox)
 
-                # Adding Device Details
+                # Adding Device Details #
 
                 # Increment row and widget count
                 self.row = self.row + 1
@@ -136,7 +133,7 @@ class DeviceModel(QtGui.QWidget):
                 self.count = self.count + 1
 
             elif eachline[0] == 'd':
-                print("Device Model Diode:", words[0])
+                # print("Device Model Diode:", words[0])
                 self.devicemodel_dict_beg[words[0]] = self.count
                 diodebox = QtGui.QGroupBox()
                 diodegrid = QtGui.QGridLayout()
@@ -151,8 +148,6 @@ class DeviceModel(QtGui.QWidget):
                 try:
                     for key in json_data["deviceModel"]:
                         if key == words[0]:
-                            # print "DEVICE MODEL MATCHING---",child.tag[0],\
-                            # child.tag[1],eachline[0],eachline[1]
                             try:
                                 if os.path.exists(
                                         json_data["deviceModel"][key][0]):
@@ -193,7 +188,7 @@ class DeviceModel(QtGui.QWidget):
 
                 self.grid.addWidget(diodebox)
 
-                # Adding Device Details
+                # Adding Device Details #
 
                 # Increment row and widget count
                 self.row = self.row + 1
@@ -201,7 +196,7 @@ class DeviceModel(QtGui.QWidget):
                 self.count = self.count + 1
 
             elif eachline[0] == 'j':
-                print("Device Model JFET:", words[0])
+                # print("Device Model JFET:", words[0])
                 self.devicemodel_dict_beg[words[0]] = self.count
                 jfetbox = QtGui.QGroupBox()
                 jfetgrid = QtGui.QGridLayout()
@@ -216,8 +211,6 @@ class DeviceModel(QtGui.QWidget):
                 try:
                     for key in json_data["deviceModel"]:
                         if key == words[0]:
-                            # print "DEVICE MODEL MATCHING---",child.tag[0],\
-                            # child.tag[1],eachline[0],eachline[1]
                             try:
                                 if os.path.exists(
                                         json_data["deviceModel"][key][0]):
@@ -258,7 +251,8 @@ class DeviceModel(QtGui.QWidget):
 
                 self.grid.addWidget(jfetbox)
 
-                # Adding Device Details
+                # Adding Device Details #
+
                 # Increment row and widget count
                 self.row = self.row + 1
                 self.devicemodel_dict_end[words[0]] = self.count
@@ -329,8 +323,6 @@ class DeviceModel(QtGui.QWidget):
                 try:
                     for key in json_data["deviceModel"]:
                         if key == words[0]:
-                            # print "DEVICE MODEL MATCHING---",child.tag[0],\
-                            # child.tag[1],eachline[0],eachline[1]
                             while i <= end:
                                 self.entry_var[i].setText(
                                     json_data["deviceModel"][key][i - beg])
@@ -367,7 +359,6 @@ class DeviceModel(QtGui.QWidget):
         """
         print("Calling Track Device Model Library funtion")
         sending_btn = self.sender()
-        # print "Object Called is ",sending_btn.objectName()
         self.widgetObjCount = int(sending_btn.objectName())
 
         self.libfile = str(
@@ -376,14 +367,12 @@ class DeviceModel(QtGui.QWidget):
                 "Open Library Directory",
                 "../deviceModelLibrary",
                 "*.lib"))
-        # print "Selected Library File :",self.libfile
 
         # Setting Library to Text Edit Line
         self.entry_var[self.widgetObjCount].setText(self.libfile)
         self.deviceName = self.deviceDetail[self.widgetObjCount]
 
         # Storing to track it during conversion
-
         if self.deviceName[0] == 'm':
             width = str(self.entry_var[self.widgetObjCount + 1].text())
             length = str(self.entry_var[self.widgetObjCount + 2].text())
@@ -406,19 +395,16 @@ class DeviceModel(QtGui.QWidget):
         This function is use to keep track of all Device Model widget
         """
         print("Calling Track Library function Without Button")
-        # print "Object Called is ",sending_btn.objectName()
         self.widgetObjCount = iter_value
         print("self.widgetObjCount-----", self.widgetObjCount)
         self.libfile = path_value
         print("PATH VALUE", path_value)
-        # print "Selected Library File :",self.libfile
 
         # Setting Library to Text Edit Line
         self.entry_var[self.widgetObjCount].setText(self.libfile)
         self.deviceName = self.deviceDetail[self.widgetObjCount]
 
         # Storing to track it during conversion
-
         if self.deviceName[0] == 'm':
             width = str(self.entry_var[self.widgetObjCount + 1].text())
             length = str(self.entry_var[self.widgetObjCount + 2].text())
diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index ef9201cb..ab2e55e8 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: kicadtoNgspice.py
 #
 #         USAGE: ---
@@ -11,10 +10,12 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
 #       CREATED: Wednesday 04 March 2015
-#      REVISION:  ---
+#      REVISION: Friday 14 February 2020
 # =========================================================================
+
 import sys
 import os
 from PyQt4 import QtGui
@@ -28,8 +29,6 @@ from . import Convert
 from . import TrackWidget
 import json
 
-# from xml.etree import ElementTree as ET
-
 
 class MainWindow(QtGui.QWidget):
     """
@@ -37,7 +36,7 @@ class MainWindow(QtGui.QWidget):
     - And Call Convert function if convert button is pressed.
     - The convert function takes all the value entered by user and create
       a final netlist "*.cir.out".
-    - This final netlist is compatible with NgSpice.
+    - This final netlist is compatible with Ngspice.
     - clarg1 is the path to the .cir file
     - clarg2 is either None or "sub" depending on the analysis type
     """
@@ -54,10 +53,10 @@ class MainWindow(QtGui.QWidget):
         self.clarg2 = clarg2
 
         # Create object of track widget
-        # Track the dynamically created widget of KicadtoNgSpice Window
+        # Track the dynamically created widget of KicadtoNgspice Window
         self.obj_track = TrackWidget.TrackWidget()
 
-        # Clear Dictionary/List item of sub circuit and ngspice model
+        # Clear Dictionary/List item of sub circuit and Ngspice model
         # Dictionary
         self.obj_track.subcircuitList.clear()
         self.obj_track.subcircuitTrack.clear()
@@ -70,22 +69,21 @@ class MainWindow(QtGui.QWidget):
 
         # Read the netlist, ie the .cir file
         kicadNetlist = obj_proc.readNetlist(self.kicadFile)
-        print("=============================================================")
-        print("Given Kicad Schematic Netlist Info :", kicadNetlist)
+        # print("=============================================================")
+        # print("Given Kicad Schematic Netlist Info :", kicadNetlist)
 
         # Construct parameter information
         param = obj_proc.readParamInfo(kicadNetlist)
 
         # Replace parameter with values
         netlist, infoline = obj_proc.preprocessNetlist(kicadNetlist, param)
-        print("=============================================================")
-        print("Schematic Info after processing Kicad Netlist: ", netlist)
-        # print "INFOLINE",infoline
+        # print("=============================================================")
+        # print("Schematic Info after processing Kicad Netlist: ", netlist)
 
         # Separate option and schematic information
         optionInfo, schematicInfo = obj_proc.separateNetlistInfo(netlist)
-        print("=============================================================")
-        print("OPTIONINFO in the Netlist", optionInfo)
+        # print("=============================================================")
+        # print("OPTIONINFO in the Netlist", optionInfo)
 
         # List for storing source and its value
         global sourcelist, sourcelisttrack
@@ -111,8 +109,8 @@ class MainWindow(QtGui.QWidget):
         ) = obj_proc.convertICintoBasicBlocks(
             schematicInfo, outputOption, modelList, plotText
         )
-        print("=======================================")
-        print("Model available in the Schematic :", modelList)
+        # print("=======================================")
+        # print("Model available in the Schematic :", modelList)
 
         """
         - Checking if any unknown model is used in schematic which is not
@@ -141,13 +139,13 @@ class MainWindow(QtGui.QWidget):
 
     def createMainWindow(self):
         """
-        - This function create main window of Kicad to Ngspice converter
+        - This function create main window of KiCad to Ngspice converter
         - Two components
-        - - createcreateConvertWidget
-        - - Convert button => callConvert
+            - createcreateConvertWidget
+            - Convert button => callConvert
         """
-        self.vbox = QtGui.QVBoxLayout(self)
-        self.hbox = QtGui.QHBoxLayout(self)
+        self.vbox = QtGui.QVBoxLayout()
+        self.hbox = QtGui.QHBoxLayout()
         self.hbox.addStretch(1)
         self.convertbtn = QtGui.QPushButton("Convert")
         self.convertbtn.clicked.connect(self.callConvert)
@@ -162,23 +160,23 @@ class MainWindow(QtGui.QWidget):
     def createcreateConvertWidget(self):
         """
         - Contains the tabs for various convertor elements
-        - - Analysis            => obj_analysis
+            - Analysis            => obj_analysis
             => Analysis.Analysis(`path_to_projFile`)
 
-        - - Source Details      => obj_source
+            - Source Details      => obj_source
             => Source.Source(`sourcelist`,`sourcelisttrack`,`path_to_projFile`)
 
-        - - NgSpice Model       => obj_model
+            - NgSpice Model       => obj_model
             => Model.Model(`schematicInfo`,`modelList`,`path_to_projFile`)
 
-        - - Device Modelling    => obj_devicemodel
+            - Device Modelling    => obj_devicemodel
             => DeviceModel.DeviceModel(`schematicInfo`,`path_to_projFile`)
 
-        - - Subcircuits         => obj_subcircuitTab
+            - Subcircuits         => obj_subcircuitTab
             => SubcircuitTab.SubcircuitTab(`schematicInfo`,`path_to_projFile`)
 
         - Finally pass each of these objects, to widgets
-        - convertWindow > mainLayout > tabWidgets > AnalysisTab, SourceTab ....
+        - convertWindow > mainLayout > tabWidgets > AnalysisTab, SourceTab ...
         """
         global obj_analysis
         self.convertWindow = QtGui.QWidget()
@@ -268,8 +266,6 @@ class MainWindow(QtGui.QWidget):
             json_data["analysis"]["ac"]["Lin"] = "false"
             json_data["analysis"]["ac"]["Dec"] = "false"
             json_data["analysis"]["ac"]["Oct"] = "true"
-        else:
-            pass
 
         json_data["analysis"]["ac"]["Start Frequency"] = str(
             obj_analysis.ac_entry_var[0].text())
@@ -594,11 +590,11 @@ class MainWindow(QtGui.QWidget):
             print("=========================================================")
             self.createNetlistFile(store_schematicInfo, plotText)
 
-            self.msg = "The Kicad to Ngspice Conversion completed\
-            successfully!"
+            self.msg = "The Kicad to Ngspice Conversion completed "
+            self.msg += "successfully!"
             QtGui.QMessageBox.information(
-                self, "Information", self.msg, QtGui.QMessageBox.Ok)
-
+                self, "Information", self.msg, QtGui.QMessageBox.Ok
+            )
         except Exception as e:
             print("Exception Message: ", e)
             print("There was error while converting kicad to ngspice")
@@ -615,31 +611,26 @@ class MainWindow(QtGui.QWidget):
         """
         - Creating .cir.out file
         - If analysis file present uses that and extract
-        - - Simulator
-        - - Initial
-        - - Analysis
+            - Simulator
+            - Initial
+            - Analysis
         - Finally add the following components to .cir.out file
-        - - SimulatorOption
-        - - InitialCondOption
-        - - Store_SchematicInfo
-        - - AnalysisOption
+            - SimulatorOption
+            - InitialCondOption
+            - Store_SchematicInfo
+            - AnalysisOption
         - In the end add control statements and allv, alli, end statements
         """
         print("=============================================================")
         print("Creating Final netlist")
-        # print "INFOLINE",infoline
-        # print "OPTIONINFO",optionInfo
-        # print "Device MODEL LIST ",devicemodelList
-        # print "SUBCKT ",subcktList
-        # print "OUTPUTOPTION",outputOption
-        # print "KicadfIle",kicadFile
+
         # To avoid writing optionInfo twice in final netlist
         store_optionInfo = list(optionInfo)
 
         # checking if analysis files is present
         (projpath, filename) = os.path.split(self.kicadFile)
         analysisFileLoc = os.path.join(projpath, "analysis")
-        # print "Analysis File Location",analysisFileLoc
+
         if os.path.exists(analysisFileLoc):
             try:
                 f = open(analysisFileLoc)
@@ -653,7 +644,7 @@ class MainWindow(QtGui.QWidget):
                  Please check it")
                 sys.exit()
         else:
-            print("========================================================")
+            # print("========================================================")
             print(analysisFileLoc + " does not exist")
             sys.exit()
 
@@ -664,10 +655,7 @@ class MainWindow(QtGui.QWidget):
             if len(eachline) > 1:
                 if eachline[0] == '.':
                     store_optionInfo.append(eachline)
-                else:
-                    pass
 
-        # print "Option Info",optionInfo
         analysisOption = []
         initialCondOption = []
         simulatorOption = []
@@ -743,7 +731,7 @@ class MainWindow(QtGui.QWidget):
             except BaseException:
                 print("Error in opening .cir.out file.")
         else:
-            print("=========================================================")
+            # print("=========================================================")
             print(
                 self.projName +
                 ".cir.out does not exist. Please create a spice netlist.")
@@ -751,8 +739,8 @@ class MainWindow(QtGui.QWidget):
         # Read the data from file
         data = f.read()
         # Close the file
-
         f.close()
+
         newNetlist = []
         netlist = iter(data.splitlines())
         for eachline in netlist:
@@ -803,5 +791,5 @@ class MainWindow(QtGui.QWidget):
         out.writelines('\n')
 
         out.writelines('.ends ' + self.projName)
-        print("=============================================================")
+        # print("=============================================================")
         print("The subcircuit has been written in " + self.projName + ".sub")
diff --git a/src/kicadtoNgspice/Model.py b/src/kicadtoNgspice/Model.py
index a182dd4e..3cc3a0cb 100644
--- a/src/kicadtoNgspice/Model.py
+++ b/src/kicadtoNgspice/Model.py
@@ -1,7 +1,6 @@
 from PyQt4 import QtGui
 import json
 from . import TrackWidget
-# from xml.etree import ElementTree as ET
 import os
 
 
@@ -59,8 +58,6 @@ class Model(QtGui.QWidget):
             # line[7] is parameter dictionary holding parameter tags.
             i = 0
             for key, value in line[7].items():
-                # print "Key : ",key
-                # print "Value : ",value
                 # Check if value is iterable
                 if not isinstance(value, str) and hasattr(value, '__iter__'):
                     # For tag having vector value
@@ -127,7 +124,6 @@ class Model(QtGui.QWidget):
                     self.nextrow = self.nextrow + 1
 
             self.end = self.nextcount - 1
-            # print "End",self.end
             modelbox.setLayout(modelgrid)
 
             # CSS
@@ -173,6 +169,4 @@ class Model(QtGui.QWidget):
             if check == 0:
                 self.obj_trac.modelTrack.append(lst)
 
-            # print "The tag dictionary : ",tag_dict
-
         self.show()
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index a0f2c79f..1e58daac 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -13,30 +13,28 @@ class PrcocessNetlist:
     def __init__(self):
         pass
 
-    """
-    - Read the circuit file and return splitted lines
-    """
-
     def readNetlist(self, filename):
+        """
+        - Read the circuit file and return splitted lines
+        """
         f = open(filename)
         data = f.read()
         f.close()
-        print("=============================================================")
-        print("readNetList called, from Processing")
-        print("=============================================================")
-        print("NETLIST", data.splitlines())
-        print("=============================================================")
+        # print("=============================================================")
+        # print("readNetList called, from Processing")
+        # print("=============================================================")
+        # print("NETLIST", data.splitlines())
+        # print("=============================================================")
         return data.splitlines()
 
-    """
-    - Read Parameter information and store it into dictionary
-    - kicadNetlis is the .cir file content
-    """
-
-    def readParamInfo(self, kicadNetlis):
+    def readParamInfo(self, kicadNetlist):
+        """
+        - Read Parameter information and store it into dictionary
+        - kicadNetlist is the .cir file content
+        """
         param = {}
-        print("=========================KICADNETLIST========================")
-        for eachline in kicadNetlis:
+        # print("=========================KICADNETLIST========================")
+        for eachline in kicadNetlist:
             print(eachline)
             eachline = eachline.strip()
             if len(eachline) > 1:
@@ -46,21 +44,20 @@ class PrcocessNetlist:
                     for i in range(1, len(words), 1):
                         paramList = words[i].split('=')
                         param[paramList[0]] = paramList[1]
-        print("=============================================================")
-        print("readParamInfo called, from Processing")
-        print("=============================================================")
-        print("PARAM", param)
-        print("=============================================================")
+        # print("=============================================================")
+        # print("readParamInfo called, from Processing")
+        # print("=============================================================")
+        # print("PARAM", param)
+        # print("=============================================================")
         return param
 
-    """
-    - Preprocess netlist (replace parameters)
-    - Separate infoline (first line) from the rest of netlist
-    """
-
-    def preprocessNetlist(self, kicadNetlis, param):
+    def preprocessNetlist(self, kicadNetlist, param):
+        """
+        - Preprocess netlist (replace parameters)
+        - Separate infoline (first line) from the rest of netlist
+        """
         netlist = []
-        for eachline in kicadNetlis:
+        for eachline in kicadNetlist:
             # Remove leading and trailing blanks spaces from line
             eachline = eachline.strip()
             # Remove special character $
@@ -89,12 +86,12 @@ class PrcocessNetlist:
         # Copy information line
         infoline = netlist[0]
         netlist.remove(netlist[0])
-        print("=============================================================")
+        """print("=============================================================")
         print("preprocessNetList called, from Processing")
         print("=============================================================")
         print("NETLIST", netlist)
         print("INFOLINE", infoline)
-        print("=============================================================")
+        print("=============================================================")"""
         return netlist, infoline
 
     def separateNetlistInfo(self, netlist):
@@ -114,26 +111,25 @@ class PrcocessNetlist:
                 optionInfo.append(eachline)
             else:
                 schematicInfo.append(eachline)
-        print("=============================================================")
+        """print("=============================================================")
         print("separateNetlistInfo called, from Processing")
         print("=============================================================")
         print("OPTIONINFO", optionInfo)
         print("SCHEMATICINFO", schematicInfo)
-        print("=============================================================")
+        print("=============================================================")"""
         return optionInfo, schematicInfo
 
-    """
-    - Insert Special source parameter
-    - As per the parameters passed create source list, start with v or i
-    - Then check for type whether ac, dc, sine, etc...
-    - Handle starting with h and f as well
-    """
-
     def insertSpecialSourceParam(self, schematicInfo, sourcelist):
+        """
+        - Insert Special source parameter
+        - As per the parameters passed create source list, start with v or i
+        - Then check for type whether ac, dc, sine, etc...
+        - Handle starting with h and f as well
+        """
         schematicInfo1 = []
-        print("=============================================================")
-        print("Reading schematic info for source details")
-        print("=============================================================")
+        # print("=============================================================")
+        # print("Reading schematic info for source details")
+        # print("=============================================================")
         for compline in schematicInfo:
             words = compline.split()
             compName = words[0]
@@ -217,14 +213,14 @@ class PrcocessNetlist:
                     words[5])
 
         schematicInfo = schematicInfo + schematicInfo1
-        print("Source List : ", sourcelist)
-        # print schematicInfo
-        print("=============================================================")
+        # print("Source List : ", sourcelist)
+
+        """print("=============================================================")
         print("insertSpecialSourceParam called, from Processing")
         print("=============================================================")
         print("SCHEMATICINFO", schematicInfo)
         print("SOURCELIST", sourcelist)
-        print("=============================================================")
+        print("=============================================================")"""
         return schematicInfo, sourcelist
 
     def convertICintoBasicBlocks(
@@ -239,8 +235,8 @@ class PrcocessNetlist:
         - - Plot text
         - Parsing info is provided below
         """
-        print("=============================================================")
-        print("Reading Schematic info for Model")
+        # print("=============================================================")
+        # print("Reading Schematic info for Model")
         # Insert details of Ngspice model
         unknownModelList = []
         multipleModelList = []
@@ -293,8 +289,8 @@ class PrcocessNetlist:
                         unknownModelList.append(compType)
                     elif count == 1:
                         try:
-                            print("==========================================\
-                                ===========================")
+                            # print("==========================================\
+                            #     ===========================")
                             print(
                                 "Start Parsing Previous Values XML\
                                  for ngspice model :", modelPath)
@@ -355,9 +351,9 @@ class PrcocessNetlist:
                                 modelLine += compName
 
                             else:
-                                print("=====================================\
-                                    ================================")
-                                print("Split Details :", splitDetail)
+                                # print("=====================================\
+                                #     ================================")
+                                # print("Split Details :", splitDetail)
                                 modelLine = "a" + str(k) + " "
                                 vectorDetail = splitDetail.split(':')
                                 # print "Vector Details",vectorDetail
@@ -507,7 +503,7 @@ class PrcocessNetlist:
 
                 else:
                     schematicInfo.insert(index, "* " + compline)
-                print("=====================================================")
+                # print("=====================================================")
                 print(
                     "UnknownModelList Used in the Schematic",
                     unknownModelList)
@@ -516,7 +512,7 @@ class PrcocessNetlist:
                     "Multiple Model XML file with same name ",
                     multipleModelList)
                 print("=====================================================")
-                print("Model List Details : ", modelList)
+                # print("Model List Details : ", modelList)
         print("=============================================================")
         print("convertICIntoBasicBlocks called, from Processing")
         print("=============================================================")
diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py
index 26555197..6c5ae637 100644
--- a/src/kicadtoNgspice/Source.py
+++ b/src/kicadtoNgspice/Source.py
@@ -1,7 +1,6 @@
 import os
 from PyQt4 import QtGui
 from . import TrackWidget
-# from xml.etree import ElementTree as ET
 import json
 
 
@@ -13,7 +12,7 @@ class Source(QtGui.QWidget):
     def __init__(self, sourcelist, sourcelisttrack, clarg1):
         QtGui.QWidget.__init__(self)
         self.obj_track = TrackWidget.TrackWidget()
-        # Variable
+        # Variables
         self.count = 1
         self.clarg1 = clarg1
         self.start = 0
@@ -45,10 +44,10 @@ class Source(QtGui.QWidget):
         - Each line in sourcelist corresponds to a source
         - According to the source type modify the source and add it to the tab
         """
-        print("============================================================")
+        """print("============================================================")
         print("SOURCE LIST TRACK", sourcelisttrack)
         print("SOURCE LIST", sourcelist)
-        print("============================================================")
+        print("============================================================")"""
         kicadFile = self.clarg1
         (projpath, filename) = os.path.split(kicadFile)
         project_name = os.path.basename(projpath)
@@ -71,10 +70,8 @@ class Source(QtGui.QWidget):
 
         if sourcelist:
             for line in sourcelist:
-                # print "Voltage source line index: ",line[0]
                 print("SourceList line: ", line)
                 track_id = line[0]
-                # print "track_id is ",track_id
                 if line[2] == 'ac':
                     acbox = QtGui.QGroupBox()
                     acbox.setTitle(line[3])
@@ -372,7 +369,7 @@ class Source(QtGui.QWidget):
         else:
             print("No source is present in your circuit")
 
-        print("============================================================")
+        # print("============================================================")
         # This is used to keep the track of dynamically created widget
         self.obj_track.sourcelisttrack["ITEMS"] = sourcelisttrack
         self.obj_track.source_entry_var["ITEMS"] = self.entry_var
diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py
index d15407f7..116b70b1 100644
--- a/src/kicadtoNgspice/SubcircuitTab.py
+++ b/src/kicadtoNgspice/SubcircuitTab.py
@@ -3,7 +3,6 @@ import json
 from . import TrackWidget
 from projManagement import Validation
 import os
-# from xml.etree import ElementTree as ET
 
 
 class SubcircuitTab(QtGui.QWidget):
@@ -61,7 +60,7 @@ class SubcircuitTab(QtGui.QWidget):
         for eachline in schematicInfo:
             words = eachline.split()
             if eachline[0] == 'x':
-                print("Subcircuit : Words", words[0])
+                # print("Subcircuit : Words", words[0])
                 self.obj_trac.subcircuitList[project_name + words[0]] = words
                 self.subcircuit_dict_beg[words[0]] = self.count
                 subbox = QtGui.QGroupBox()
@@ -74,8 +73,6 @@ class SubcircuitTab(QtGui.QWidget):
                 try:
                     for key in json_data["subcircuit"]:
                         if key == words[0]:
-                            # print "Subcircuit MATCHING---",child.tag[0], \
-                            # child.tag[1], eachline[0], eachline[1]
                             try:
                                 if os.path.exists(
                                         json_data["subcircuit"][key][0]):
@@ -97,7 +94,7 @@ class SubcircuitTab(QtGui.QWidget):
                 # eg. If the line is 'x1 4 0 3 ua741', there are 3 ports(4, 0
                 # and 3).
                 self.numPorts.append(len(words) - 2)
-                print("Number of ports of sub circuit : ", self.numPorts)
+                # print("Number of ports of sub circuit : ", self.numPorts)
                 self.addbtn.clicked.connect(self.trackSubcircuit)
                 subgrid.addWidget(self.addbtn, self.row, 2)
                 subbox.setLayout(subgrid)
@@ -166,8 +163,8 @@ class SubcircuitTab(QtGui.QWidget):
         elif self.reply == "DIREC":
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                "Please select a valid Subcircuit directory \
-                (Containing '.sub' file).")
+                "Please select a valid Subcircuit directory "
+                "(Containing '.sub' file).")
             self.msg.setWindowTitle("Error Message")
             self.msg.show()
 
@@ -189,7 +186,6 @@ class SubcircuitTab(QtGui.QWidget):
             self.subName = self.subDetail[self.widgetObjCount]
 
             # Storing to track it during conversion
-
             self.obj_trac.subcircuitTrack[self.subName] = self.subfile
         elif self.reply == "PORT":
             self.msg = QtGui.QErrorMessage(self)
@@ -200,7 +196,7 @@ class SubcircuitTab(QtGui.QWidget):
         elif self.reply == "DIREC":
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                "Please select a valid Subcircuit directory \
-                (Containing '.sub' file).")
+                "Please select a valid Subcircuit directory "
+                "(Containing '.sub' file).")
             self.msg.setWindowTitle("Error Message")
             self.msg.show()
diff --git a/src/kicadtoNgspice/TrackWidget.py b/src/kicadtoNgspice/TrackWidget.py
index ec5c2c81..3a8b0dac 100644
--- a/src/kicadtoNgspice/TrackWidget.py
+++ b/src/kicadtoNgspice/TrackWidget.py
@@ -2,11 +2,11 @@ class TrackWidget:
     """
     - This Class track the dynamically created widget of KicadtoNgSpice Window.
     - Tracks using dictionary and lists ==>
-    - - Sources
-    - - Parameters
-    - - References
-    - - Model Details
-    - - ... etc
+        - Sources
+        - Parameters
+        - References
+        - Model Details
+        - ... etc
     """
     # Track widget list for Source details
     sourcelisttrack = {"ITEMS": "None"}
diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py
index 634c1fe3..3f616808 100644
--- a/src/modelEditor/ModelEditor.py
+++ b/src/modelEditor/ModelEditor.py
@@ -12,20 +12,20 @@ class ModelEditorclass(QtGui.QWidget):
     - Initalise directory to save new models,
       savepathtest = '../deviceModelLibrary'
     - Initialise buttons and options ====>
-    - - Name            Function Called
+        - Name            Function Called
     ========================================
-    - - New             opennew
-    - - Edit            openedit
-    - - Save            savemodelfile
-    - - Upload          converttoxml
-    - - Add             addparameters
-    - - Remove          removeparameter
-    - - Diode           diode_click
-    - - BJT             bjt_click
-    - - MOS             mos_click
-    - - JFET            jfet_click
-    - - IGBT            igbt_click
-    - - Magnetic Core   magnetic_click
+        - New             opennew
+        - Edit            openedit
+        - Save            savemodelfile
+        - Upload          converttoxml
+        - Add             addparameters
+        - Remove          removeparameter
+        - Diode           diode_click
+        - BJT             bjt_click
+        - MOS             mos_click
+        - JFET            jfet_click
+        - IGBT            igbt_click
+        - Magnetic Core   magnetic_click
     '''
 
     def __init__(self):
@@ -301,8 +301,6 @@ class ModelEditorclass(QtGui.QWidget):
             if filetype == 'Magnetic Core':
                 path = os.path.join(self.path, 'CORE.xml')
                 self.createtable(path)
-        else:
-            pass
 
     def openedit(self):
         '''
diff --git a/src/modelParamXML/Analog/gain.xml b/src/modelParamXML/Analog/gain.xml
index ff71d46a..a8656072 100644
--- a/src/modelParamXML/Analog/gain.xml
+++ b/src/modelParamXML/Analog/gain.xml
@@ -6,7 +6,7 @@
 <split>None</split>
 <param>
 	<in_offset default="0.0">Enter offset for input (default=0.0)</in_offset>
-	<gain vector="2" default="1.0">Enter gain (default=1.0)</gain>
+	<gain vector="1" default="1.0">Enter gain (default=1.0)</gain>
 	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
 </param>
 </model>
\ No newline at end of file
diff --git a/src/modelParamXML/Nghdl/.gitignore b/src/modelParamXML/Nghdl/.gitignore
new file mode 100644
index 00000000..86d0cb27
--- /dev/null
+++ b/src/modelParamXML/Nghdl/.gitignore
@@ -0,0 +1,4 @@
+# Ignore everything in this directory
+*
+# Except this file
+!.gitignore
\ No newline at end of file
diff --git a/src/modelParamXML/Nghdl/inverter.xml b/src/modelParamXML/Nghdl/inverter.xml
deleted file mode 100644
index 894389e0..00000000
--- a/src/modelParamXML/Nghdl/inverter.xml
+++ /dev/null
@@ -1 +0,0 @@
-<model><name>inverter</name><type>Nghdl</type><node_number>2</node_number><title>Add parameters for inverter</title><split>2-V:2-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id></param></model>
\ No newline at end of file
diff --git a/src/modelParamXML/Nghdl/myxor.xml b/src/modelParamXML/Nghdl/myxor.xml
deleted file mode 100644
index c245879e..00000000
--- a/src/modelParamXML/Nghdl/myxor.xml
+++ /dev/null
@@ -1 +0,0 @@
-<model><name>myxor</name><type>Nghdl</type><node_number>3</node_number><title>Add parameters for myxor</title><split>1-V:1-V:1-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id></param></model>
\ No newline at end of file
diff --git a/src/ngspiceSimulation/pythonPlotting.py b/src/ngspiceSimulation/pythonPlotting.py
index bbcc981f..e19b49de 100644
--- a/src/ngspiceSimulation/pythonPlotting.py
+++ b/src/ngspiceSimulation/pythonPlotting.py
@@ -1,5 +1,5 @@
-from __future__ import division  # Used for decimal division eg
-# 2/3=0.66 and not '0' 6/2=3.0 and 6//2=3
+from __future__ import division  # Used for decimal division
+# eg: 2/3=0.66 and not '0' 6/2=3.0 and 6//2=3
 import os
 from PyQt4 import QtGui, QtCore
 from decimal import Decimal, getcontext
@@ -264,20 +264,17 @@ class plotWindow(QtGui.QMainWindow):
         # p = 0
 
         for i in range(len(self.parts)):
-            # print "I",i
             if i % 2 == 0:
-                # print "I'm in:"
                 for j in range(len(self.obj_dataext.NBList)):
                     if self.parts[i] == self.obj_dataext.NBList[j]:
-                        # print "I got you:",self.parts[i]
                         a.append(j)
 
         if len(a) != len(self.parts) // 2 + 1:
             QtGui.QMessageBox.about(
                 self,
                 "Warning!!",
-                "One of the operands doesn't belong to\
-                    the above list of Nodes!!")
+                "One of the operands doesn't belong to "
+                "the above list of Nodes!!")
 
         for i in a:
             self.comboAll.append(self.obj_dataext.y[i])
@@ -286,11 +283,11 @@ class plotWindow(QtGui.QMainWindow):
 
             if a[i] == len(self.obj_dataext.NBList):
                 QtGui.QMessageBox.about(
-                    self, "Warning!!", "One of the operands doesn't belong\
-                        to the above list!!")
+                    self, "Warning!!", "One of the operands doesn't belong "
+                        "to the above list!!")
                 self.warnning.setText(
-                    "<font color='red'>To Err Is Human!<br>One of the operands\
-                        doesn't belong to the above list!!</font>")
+                    "<font color='red'>To Err Is Human!<br>One of the " +
+                    "operands doesn't belong to the above list!!</font>")
 
         if self.parts[1] == 'vs':
             if len(self.parts) > 3:
@@ -391,7 +388,6 @@ class plotWindow(QtGui.QMainWindow):
     # definition of functions onPush_decade, onPush_ac, onPush_trans,\
     # onPush_dc, color and multimeter and getRMSValue.
     def onPush_decade(self):
-        # print "Calling on push Decade"
         boxCheck = 0
         self.axes.cla()
 
@@ -591,7 +587,6 @@ class DataExtraction:
         # 'inumber' gives total number of current
 
         p = npv = vnumber = inumber = 0
-        # print "VoltsData : ",self.voltData
 
         # Finding totla number of voltage node
         for i in self.voltData[3:]:
@@ -599,22 +594,16 @@ class DataExtraction:
             if "Index" in i:  # "V(" in i or "x1" in i or "u3" in i:
                 vnumber += 1
 
-        # print "Voltage Number :",vnumber
-
         # Reading Current Source Data
         with open(os.path.join(fpath, "plot_data_i.txt")) as f1:
             self.currentData = f1.read()
         self.currentData = self.currentData.split("\n")
 
-        # print "CurrentData : ",self.currentData
-
         # Finding Number of Branch
         for i in self.currentData[3:]:
             if "#branch" in i:
                 inumber += 1
 
-        # print "Current Number :",inumber
-
         self.dec = 0
 
         # For AC
@@ -655,14 +644,9 @@ class DataExtraction:
                 if "DC" in i:  # DC for dc files and AC for ac ones
                     break
 
-        # print "VoltNumber",vnumber
-        # print "CurrentNumber",inumber
         vnumber = vnumber // npv  # vnumber gives the no of voltage nodes
         inumber = inumber // npv  # inumber gives the no of branches
 
-        # print "VoltNumber",vnumber
-        # print "CurrentNumber",inumber
-
         p = [p, vnumber, self.analysisType, self.dec, inumber]
 
         return p
@@ -691,7 +675,6 @@ class DataExtraction:
                     self.NBIList.append(l)
             self.NBIList = self.NBIList[2:]
             len_NBIList = len(self.NBIList)
-            # print "NBILIST : ",self.NBIList
         except Exception as e:
             print("Exception Message : ", str(e))
             self.obj_appconfig.print_error('Exception Message :' + str(e))
@@ -706,7 +689,6 @@ class DataExtraction:
         d4 = d[4]
 
         dec = [d3, d[3]]
-        # print "No. of Nodes:", d2
         self.NBList = []
         allv = allv.split("\n")
         for l in allv[3].split(" "):
@@ -747,13 +729,11 @@ class DataExtraction:
             for i in alli[5:d1 - 1]:
                 if len(i.split("\t")) == inum_i:
                     j2 = i.split("\t")
-                    # print j2
                     j2.pop(0)
                     j2.pop(0)
                     j2.pop()
                     if d3 == 0:  # not in trans
                         j2.pop()
-                    # print j2
 
                     for l in range(1, d4):
                         j3 = alli[5 + l * d1 + k].split("\t")
@@ -763,14 +743,11 @@ class DataExtraction:
                             j3.pop()  # not required for dc
                         j3.pop()
                         j2 = j2 + j3
-                        # print j2
 
                     full_data.append(j2)
 
                 k += 1
 
-            # print "FULL DATA :",full_data
-
             for i in allv[5:d1 - 1]:
                 if len(i.split("\t")) == inum:
                     j = i.split("\t")
@@ -790,9 +767,8 @@ class DataExtraction:
                         j1.pop()
                         j = j + j1
                     j = j + full_data[m]
-                    # print j
                     m += 1
-                    # print j[:20]
+
                     j = "\t".join(j[1:])
                     j = j.replace(",", "")
                     ivals.append(j)
@@ -801,7 +777,6 @@ class DataExtraction:
 
             self.data = ivals
 
-        # print "volts:",self.butnames
         self.volts_length = len(self.NBList)
         self.NBList = self.NBList + self.NBIList
 
@@ -811,12 +786,10 @@ class DataExtraction:
     def numVals(self):
         a = self.volts_length        # No of voltage nodes
         b = len(self.data[0].split("\t"))
-        # print "numvals:",b
         return [b, a]
 
     def computeAxes(self):
         nums = len(self.data[0].split("\t"))
-        # print "i'm nums:",nums
         self.y = []
         var = self.data[0].split("\t")
         for i in range(1, nums):
diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py
index eca03534..d5daf9ad 100644
--- a/src/ngspicetoModelica/ModelicaUI.py
+++ b/src/ngspicetoModelica/ModelicaUI.py
@@ -44,13 +44,11 @@ class OpenModelicaEditor(QtGui.QWidget):
         self.show()
 
     def browseFile(self):
-
         self.ngspiceNetlist = QtGui.QFileDialog.getOpenFileName(
             self, 'Open Ngspice file', BROWSE_LOCATION)
         self.FileEdit.setText(self.ngspiceNetlist)
 
     def callConverter(self):
-
         try:
             self.cmd1 = (
                 "python3 ../ngspicetoModelica/NgspicetoModelica.py " +
@@ -67,17 +65,18 @@ class OpenModelicaEditor(QtGui.QWidget):
                 stderr=STDOUT,
                 close_fds=True)
             error_code = convert_process.stdout.read()
+
             if not error_code:
                 self.msg = QtGui.QMessageBox()
                 self.msg.setText(
                     "Ngspice netlist successfully converted to OpenModelica" +
-                    "netlist")
+                    "netlist"
+                )
                 self.obj_appconfig.print_info(
                     "Ngspice netlist successfully converted to OpenModelica" +
                     "netlist"
                 )
                 self.msg.exec_()
-
             else:
                 self.err_msg = QtGui.QErrorMessage()
                 self.err_msg.showMessage(
diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py
index 0b34015f..02695ef4 100644
--- a/src/projManagement/Kicad.py
+++ b/src/projManagement/Kicad.py
@@ -1,19 +1,19 @@
 # =========================================================================
-#
-#          FILE: openKicad.py
+#          FILE: Kicad.py
 #
 #         USAGE: ---
 #
-#   DESCRIPTION: It call kicad schematic
+#   DESCRIPTION: It calls kicad schematic
 #
 #       OPTIONS: ---
 #  REQUIREMENTS: ---
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Tuesday 17 Feb 2015
-#      REVISION:  ---
+#       CREATED: Tuesday 17 February 2015
+#      REVISION: Friday 14 February 2020
 # =========================================================================
 
 import os
@@ -24,7 +24,6 @@ from PyQt4 import QtGui
 
 
 class Kicad:
-
     """
     This class called the Kicad Schematic,KicadtoNgspice Converter,Layout
     editor and Footprint Editor
@@ -41,6 +40,28 @@ class Kicad:
         self.obj_validation = Validation.Validation()
         self.obj_appconfig = Appconfig()
         self.obj_dockarea = dockarea
+        self.obj_workThread = Worker.WorkerThread(None)
+
+    def check_open_schematic(self):
+        """
+        This function checks if any of the project's schematic is open or not
+
+        @params
+
+        @return
+            True        => If the project's schematic is not open
+            False       => If the project's schematic is open        
+        """
+        if self.obj_workThread:
+            procList = self.obj_workThread.get_proc_threads()[:]
+            if procList:
+                for proc in procList:
+                    if proc.poll() is None:
+                        return True
+                    else:
+                        self.obj_workThread.get_proc_threads().remove(proc)
+
+        return False
 
     def openSchematic(self):
         """
@@ -61,27 +82,26 @@ class Kicad:
         # Validating if current project is available or not
 
         if self.obj_validation.validateKicad(self.projDir):
-            # print "calling Kicad schematic ",self.projDir
             self.projName = os.path.basename(self.projDir)
             self.project = os.path.join(self.projDir, self.projName)
 
             # Creating a command to run
             self.cmd = "eeschema " + self.project + ".sch "
-            self.obj_workThread = Worker.WorkerThread(self.cmd)
+            self.obj_workThread.args = self.cmd
             self.obj_workThread.start()
 
         else:
             self.msg = QtGui.QErrorMessage(None)
             self.msg.showMessage(
-                'Please select the project first. You can either create'
-                + 'new project or open existing project')
+                'Please select the project first. You can either ' +
+                'create new project or open existing project')
             self.obj_appconfig.print_warning(
-                'Please select the project first. You can either create'
-                + 'new project or open existing project')
+                'Please select the project first. You can either ' +
+                'create new project or open existing project')
             self.msg.setWindowTitle("Error Message")
 
     '''
-    # Commenting as it is no longer needed as PBC and Layout will open from
+    # Commenting as it is no longer needed as PCB and Layout will open from
     # eeschema
     def openFootprint(self):
         """
@@ -168,7 +188,7 @@ class Kicad:
             pass
         # Validating if current project is available or not
         if self.obj_validation.validateKicad(self.projDir):
-            # Cheking if project has .cir file or not
+            # Checking if project has .cir file or not
             if self.obj_validation.validateCir(self.projDir):
                 self.projName = os.path.basename(self.projDir)
                 self.project = os.path.join(self.projDir, self.projName)
@@ -186,19 +206,19 @@ class Kicad:
             else:
                 self.msg = QtGui.QErrorMessage(None)
                 self.msg.showMessage(
-                    'The project does not contain any Kicad netlist file for'
-                    + 'conversion.')
+                    'The project does not contain any Kicad netlist file ' +
+                    'for conversion.')
                 self.obj_appconfig.print_error(
-                    'The project does not contain any Kicad netlist file for'
-                    + 'conversion.')
+                    'The project does not contain any Kicad netlist file ' +
+                    'for conversion.')
                 self.msg.setWindowTitle("Error Message")
 
         else:
             self.msg = QtGui.QErrorMessage(None)
             self.msg.showMessage(
-                'Please select the project first. You can either create'
-                + 'new project or open existing project')
+                'Please select the project first. You can either ' +
+                'create new project or open existing project')
             self.obj_appconfig.print_warning(
-                'Please select the project first. You can either create'
-                + 'new project or open existing project')
+                'Please select the project first. You can either ' +
+                'create new project or open existing project')
             self.msg.setWindowTitle("Error Message")
diff --git a/src/projManagement/Validation.py b/src/projManagement/Validation.py
index 451fe831..b2d568e4 100644
--- a/src/projManagement/Validation.py
+++ b/src/projManagement/Validation.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: Validation.py
 #
 #         USAGE: ---
@@ -12,33 +11,22 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
 #       CREATED: Wednesday 12 February 2015
-#      REVISION:  ---
+#      REVISION: Friday 14 February 2020
 # =========================================================================
+
 import os
 import re
 import distutils.spawn
 
-"""
-This is Validation class use for validating Project.
-e.g if .proj is present in project directory
-or if new project name is already exist in workspace etc
-"""
-
 
 class Validation:
     """
-    Takes as input the path of the project and checks if
-    projName.proj file exists
-    projName is same as the folder selected
-
-    @params
-        :projDir    => contains the path of the project folder selected to open
-
-    @return
-        True        => If the folder contains the projName.proj file
-        False       => If the folder doesn't contain projName.proj file
+    This is Validation class use for validating Project.
+    e.g if .proj is present in project directory
+    or if new project name is already exist in workspace etc
     """
 
     def __init__(self):
@@ -46,7 +34,15 @@ class Validation:
 
     def validateOpenproj(self, projDir):
         """
-        This function validate Open Project Information.
+        Takes as input the path of the project and checks if
+        projName.proj file exists or not
+
+        @params
+            :projDir    => contains the path of the project folder selected to open
+
+        @return
+            True        => If the folder contains the projName.proj file
+            False       => If the folder doesn't contain projName.proj file
         """
         print("Function: Validating Open Project Information")
         projName = os.path.basename(str(projDir))
@@ -57,21 +53,17 @@ class Validation:
         else:
             return False
 
-    """
-    Validate new project created
-
-    @params
-        :projDir        => Contains path of the new projDir created
-
-    @return
-        :"CHECKEXIST"   => If smae project name folder exists
-        :"CHECKNAME"    => If space is there in name
-        :"VALID"        => If valid project name given
-    """
-
     def validateNewproj(self, projDir):
         """
-        This Project Validate New Project Information
+        Validate new project created
+
+        @params
+            :projDir        => Contains path of the new projDir created
+
+        @return
+            :"CHECKEXIST"   => If smae project name folder exists
+            :"CHECKNAME"    => If space is there in name
+            :"VALID"        => If valid project name given
         """
         print("Function: Validating New Project Information")
 
@@ -85,44 +77,36 @@ class Validation:
             else:
                 return "VALID"
 
-    """
-    Validate if projDir is set appropriately in the function calling file
-    and if Kicad components are present
-
-    @params
-        :projDir    => the path of the project directory, passed from
-                       the calling function
-
-    @return
-        True
-        False
-    """
-
     def validateKicad(self, projDir):
         """
-        This function validate if Kicad components are present
+        Validate if projDir is set appropriately in the function calling file
+        and if Kicad components are present
+
+        @params
+            :projDir    => the path of the project directory, passed from
+                           the calling function
+
+        @return
+            True
+            False
         """
-        print("FUnction : Validating for Kicad components")
+        print("Function : Validating for Kicad components")
         if projDir is None:
             return False
         else:
             return True
 
-    """
-    Validate if cir file present in the directory with the appropriate .cir
-    file name, same as the project directory base
-
-    @params
-        :projDir    => the path to the project diretory
-
-    @return
-        True
-        False
-    """
-
     def validateCir(self, projDir):
         """
-        This function checks if ".cir" file is present.
+        Validate if cir file present in the directory with the appropriate .cir
+        file name, same as the project directory base
+
+        @params
+            :projDir    => the path to the project diretory
+
+        @return
+            True
+            False
         """
         projName = os.path.basename(str(projDir))
         lookCir = os.path.join(str(projDir), projName + ".cir")
diff --git a/src/projManagement/Worker.py b/src/projManagement/Worker.py
index 9b9f57e4..e523b533 100644
--- a/src/projManagement/Worker.py
+++ b/src/projManagement/Worker.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: WorkerThread.py
 #
 #         USAGE: ---
@@ -11,10 +10,12 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Tuesday 24 Feb 2015
-#      REVISION:  ---
+#       CREATED: Tuesday 24 February 2015
+#      REVISION: Friday 14 February 2020
 # =========================================================================
+
 from PyQt4 import QtCore
 import subprocess
 from configuration.Appconfig import Appconfig
@@ -27,7 +28,6 @@ class WorkerThread(QtCore.QThread):
     other PyQT windows
     This is a helper functions, used to create threads for various commands
 
-
     @params
         :args   => takes a space separated string of comamnds to be execute
                    in different child processes (see subproces.Popen())
@@ -39,6 +39,7 @@ class WorkerThread(QtCore.QThread):
     def __init__(self, args):
         QtCore.QThread.__init__(self)
         self.args = args
+        self.my_workers = []
 
     def __del__(self):
         """
@@ -53,6 +54,18 @@ class WorkerThread(QtCore.QThread):
         """
         self.wait()
 
+    def get_proc_threads(self):
+        """
+        This function is a getter for the list of project's workers,
+        and is called to check if project's schematic is open or not.
+
+        @params
+        
+        @return
+            :self.my_workers
+        """        
+        return self.my_workers
+
     def run(self):
         """
         run is the function that is called, when we start the thread as
@@ -82,6 +95,7 @@ class WorkerThread(QtCore.QThread):
 
         procThread = Appconfig()
         proc = subprocess.Popen(command.split())
+        self.my_workers.append(proc)
         procThread.procThread_list.append(proc)
         procThread.proc_dict[procThread.current_project['ProjectName']].append(
             proc.pid)
diff --git a/src/projManagement/newProject.py b/src/projManagement/newProject.py
index 6f8de2b9..b7cce397 100644
--- a/src/projManagement/newProject.py
+++ b/src/projManagement/newProject.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: newProject.py
 #
 #         USAGE: ---
@@ -11,10 +10,12 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
 #       CREATED: Wednesday 12 February 2015
-#      REVISION:  ---
+#      REVISION: Friday 14 February 2020
 # =========================================================================
+
 from PyQt4 import QtGui
 from .Validation import Validation
 from configuration.Appconfig import Appconfig
@@ -59,7 +60,6 @@ class NewProjectInfo(QtGui.QWidget):
             :filelist    => The files inside the project folder
 
         """
-        # print "Create Project Called"
         self.projName = projName
         self.workspace = self.obj_appconfig.default_workspace['workspace']
         # self.projName = self.projEdit.text()
@@ -84,12 +84,11 @@ class NewProjectInfo(QtGui.QWidget):
                     self.projDir, self.projName + ".proj")
                 f = open(self.projFile, "w")
             except BaseException:
-                # print "Some Thing Went Wrong"
                 self.msg = QtGui.QErrorMessage(self)
                 self.msg.showMessage(
-                    'Unable to create project. Please make sure you have'
-                    + ' write permission on '
-                    + self.workspace)
+                    'Unable to create project. Please make sure you have ' +
+                    'write permission on ' + self.workspace
+                )
                 self.msg.setWindowTitle("Error Message")
             f.write("schematicFile " + self.projName + ".sch\n")
             f.close()
@@ -112,24 +111,21 @@ class NewProjectInfo(QtGui.QWidget):
             return self.projDir, newprojlist
 
         elif self.reply == "CHECKEXIST":
-            # print "Project already exist"
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                'The project "'
-                + self.projName
-                + '" already exist.Please select the different name or delete'
-                + ' existing project')
+                'The project "' + self.projName +
+                '" already exist.Please select the different name or delete' +
+                ' existing project'
+            )
             self.msg.setWindowTitle("Error Message")
 
         elif self.reply == "CHECKNAME":
-            # print "Name is not proper"
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
                 'The project name should not contain space between them')
             self.msg.setWindowTitle("Error Message")
 
         elif self.reply == "NONE":
-            # print "Empty Project Name"
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage('The project name cannot be empty')
             self.msg.setWindowTitle("Error Message")
diff --git a/src/projManagement/openProject.py b/src/projManagement/openProject.py
index 23e2c361..504bb473 100644
--- a/src/projManagement/openProject.py
+++ b/src/projManagement/openProject.py
@@ -1,5 +1,4 @@
 # =========================================================================
-#
 #          FILE: openProject.py
 #
 #         USAGE: ---
@@ -11,9 +10,10 @@
 #          BUGS: ---
 #         NOTES: ---
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
+#      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
 #       CREATED: Wednesday 12 February 2015
-#      REVISION:  ---
+#      REVISION: Friday 14 February 2020
 # =========================================================================
 
 from PyQt4 import QtGui
@@ -52,7 +52,7 @@ class OpenProjectInfo(QtGui.QWidget):
             self.obj_Appconfig.current_project['ProjectName'] = str(
                 self.projDir)
             if os.path.isdir(self.projDir):
-                print("true")
+                print("True")
 
             for dirs, subdirs, filelist in os.walk(
                     self.obj_Appconfig.current_project["ProjectName"]):
@@ -70,15 +70,17 @@ class OpenProjectInfo(QtGui.QWidget):
 
         else:
             self.obj_Appconfig.print_error(
-                "The project doesn't contain .proj file. Please select the"
-                + "proper directory else you won't be able to perform any"
-                + "operation")
+                "The project doesn't contain .proj file. Please select the " +
+                "proper directory else you won't be able to perform any " +
+                "operation"
+            )
             reply = QtGui.QMessageBox.critical(
                 None, "Error Message",
                 "<b>Error: The project doesn't contain .proj file.</b><br/>"
                 "<b>Please select the proper project directory else you won't"
                 " be able to perform any operation</b>",
-                QtGui.QMessageBox.Ok | QtGui.QMessageBox.Cancel)
+                QtGui.QMessageBox.Ok | QtGui.QMessageBox.Cancel
+            )
 
             if reply == QtGui.QMessageBox.Ok:
                 self.body()
@@ -87,5 +89,3 @@ class OpenProjectInfo(QtGui.QWidget):
                     'Current Project is ' + self.projDir)
             elif reply == QtGui.QMessageBox.Cancel:
                 self.obj_Appconfig.print_info('No Project opened')
-            else:
-                pass
diff --git a/src/subcircuit/convertSub.py b/src/subcircuit/convertSub.py
index 7bdccfb2..1439f140 100644
--- a/src/subcircuit/convertSub.py
+++ b/src/subcircuit/convertSub.py
@@ -4,8 +4,7 @@ from configuration.Appconfig import Appconfig
 import os
 
 
-# This class is called when User create new Project and contains \
-# functions to convert kicad to Ngspice.
+# This class is called when user creates new Project
 class convertSub(QtGui.QWidget):
     """
     Contains functions that checks project present for conversion and
@@ -34,7 +33,6 @@ class convertSub(QtGui.QWidget):
         if self.obj_validation.validateKicad(self.projDir):
             # Checking if project has .cir file or not
             if self.obj_validation.validateCir(self.projDir):
-                # print "CIR file present"
                 self.projName = os.path.basename(self.projDir)
                 self.project = os.path.join(self.projDir, self.projName)
 
@@ -44,12 +42,14 @@ class convertSub(QtGui.QWidget):
             else:
                 self.msg = QtGui.QErrorMessage(None)
                 self.msg.showMessage(
-                    'The subcircuit does not contain any Kicad netlist file'
-                    + ' for conversion.')
+                    'The subcircuit does not contain any Kicad netlist file' +
+                    ' for conversion.'
+                )
                 self.msg.setWindowTitle("Error Message")
         else:
             self.msg = QtGui.QErrorMessage(None)
             self.msg.showMessage(
-                'Please select the subcircuit first. You can either create'
-                + ' new subcircuit or open existing subcircuit')
+                'Please select the subcircuit first. You can either create ' +
+                'new subcircuit or open existing subcircuit'
+            )
             self.msg.setWindowTitle("Error Message")
diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py
index bd88064a..90f60319 100644
--- a/src/subcircuit/newSub.py
+++ b/src/subcircuit/newSub.py
@@ -5,7 +5,7 @@ from projManagement import Worker
 import os
 
 
-# This class is called when User create new Project.
+# This class is called when User creates new Project.
 class NewSub(QtGui.QWidget):
     """
     Contains functions to check :
@@ -54,32 +54,30 @@ class NewSub(QtGui.QWidget):
                 self.obj_workThread.start()
                 self.close()
             except BaseException:
-                # print "Some Thing Went Wrong"
                 self.msg = QtGui.QErrorMessage(self)
                 self.msg.showMessage(
-                    'Unable to create subcircuit. Please make sure\
-                     you have write permission on ' +
-                    self.schematic_path)
+                    'Unable to create subcircuit. Please make sure ' +
+                    'you have write permission on ' + self.schematic_path
+                )
                 self.msg.setWindowTitle("Error Message")
 
             self.obj_appconfig.current_subcircuit['SubcircuitName'] \
                 = self.schematic_path
 
         elif self.reply == "CHECKEXIST":
-            # print "Project already exist"
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                'The subcircuit "' +
-                self.create_schematic +
-                '" already exist.Please select the different name or delete'
-                + 'existing subcircuit')
+                'The subcircuit "' + self.create_schematic +
+                '" already exist.Please select the different name or delete' +
+                'existing subcircuit'
+            )
             self.msg.setWindowTitle("Error Message")
 
         elif self.reply == "CHECKNAME":
-            # print "Name is not proper"
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                'The subcircuit name should not contain space between them')
+                'The subcircuit name should not contain space between them'
+            )
             self.msg.setWindowTitle("Error Message")
 
         elif self.reply == "NONE":
diff --git a/src/subcircuit/uploadSub.py b/src/subcircuit/uploadSub.py
index 00cc9df0..34ec8c33 100644
--- a/src/subcircuit/uploadSub.py
+++ b/src/subcircuit/uploadSub.py
@@ -50,10 +50,11 @@ class UploadSub(QtGui.QWidget):
         if not valid:
             self.msg = QtGui.QErrorMessage(self)
             self.msg.showMessage(
-                "Content of file does not meet the required format.\
-                 Please ensure that file starts with **.subckt \
-                 " + create_subcircuit + "** and ends with **.ends \
-                 " + create_subcircuit + "**")
+                "Content of file does not meet the required format. " +
+                "Please ensure that file starts with **.subckt " +
+                create_subcircuit + " ** and ends with **.ends " +
+                create_subcircuit + " **"
+            )
             self.msg.setWindowTitle("Error Message")
             print("Invalid file format")
             return
@@ -80,8 +81,8 @@ class UploadSub(QtGui.QWidget):
             print("==========================")
             msg = QtGui.QErrorMessage(self)
             msg.showMessage(
-                "The project already exist. Please select  \
-                the different name or delete existing project")
+                "The project already exist. Please select "
+                "a different name or delete existing project")
             msg.setWindowTitle("Error Message")
 
         elif reply == "CHECKNAME":
diff --git a/src/supportFiles/fp-lib-table b/src/supportFiles/fp-lib-table
new file mode 100644
index 00000000..ff605eaf
--- /dev/null
+++ b/src/supportFiles/fp-lib-table
@@ -0,0 +1,92 @@
+(fp_lib_table
+  (lib (name Battery_Holders)(type KiCad)(uri ${KISYSMOD}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders"))
+  (lib (name Buttons_Switches_SMD)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount"))
+  (lib (name Buttons_Switches_THT)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole"))
+  (lib (name Buzzers_Beepers)(type KiCad)(uri ${KISYSMOD}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices"))
+  (lib (name Capacitors_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount"))
+  (lib (name Capacitors_Tantalum_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount"))
+  (lib (name Capacitors_THT)(type KiCad)(uri ${KISYSMOD}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole"))
+  (lib (name Connectors_Card)(type KiCad)(uri ${KISYSMOD}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders"))
+  (lib (name Connectors_Harwin)(type KiCad)(uri ${KISYSMOD}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com"))
+  (lib (name Connectors_HDMI)(type KiCad)(uri ${KISYSMOD}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints"))
+  (lib (name Connectors_Hirose)(type KiCad)(uri ${KISYSMOD}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com"))
+  (lib (name Connectors_IEC_DIN)(type KiCad)(uri ${KISYSMOD}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints"))
+  (lib (name Connectors_JAE)(type KiCad)(uri ${KISYSMOD}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors"))
+  (lib (name Connectors_JST)(type KiCad)(uri ${KISYSMOD}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com"))
+  (lib (name Connectors_Mini-Universal)(type KiCad)(uri ${KISYSMOD}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok))
+  (lib (name Connectors_Molex)(type KiCad)(uri ${KISYSMOD}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com"))
+  (lib (name Connectors_Multicomp)(type KiCad)(uri ${KISYSMOD}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints"))
+  (lib (name Connectors_Phoenix)(type KiCad)(uri ${KISYSMOD}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints"))
+  (lib (name Connectors_Samtec)(type KiCad)(uri ${KISYSMOD}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints"))
+  (lib (name Connectors_TE-Connectivity)(type KiCad)(uri ${KISYSMOD}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com"))
+  (lib (name Connectors_Terminal_Blocks)(type KiCad)(uri ${KISYSMOD}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors"))
+  (lib (name Connectors_WAGO)(type KiCad)(uri ${KISYSMOD}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com"))
+  (lib (name Connectors_USB)(type KiCad)(uri ${KISYSMOD}/Connectors_USB.pretty)(options "")(descr "USB connector footprints"))
+  (lib (name Connectors)(type KiCad)(uri ${KISYSMOD}/Connectors.pretty)(options "")(descr "Assorted connector footprints"))
+  (lib (name Converters_DCDC_ACDC)(type KiCad)(uri ${KISYSMOD}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules"))
+  (lib (name Crystals)(type KiCad)(uri ${KISYSMOD}/Crystals.pretty)(options "")(descr "Crystals and oscillators"))
+  (lib (name Diodes_SMD)(type KiCad)(uri ${KISYSMOD}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount"))
+  (lib (name Diodes_THT)(type KiCad)(uri ${KISYSMOD}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole"))
+  (lib (name Displays_7-Segment)(type KiCad)(uri ${KISYSMOD}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays"))
+  (lib (name Displays)(type KiCad)(uri ${KISYSMOD}/Displays.pretty)(options "")(descr "Display modules"))
+  (lib (name Enclosures)(type KiCad)(uri ${KISYSMOD}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings"))
+  (lib (name EuroBoard_Outline)(type KiCad)(uri ${KISYSMOD}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed"))
+  (lib (name Fiducials)(type KiCad)(uri ${KISYSMOD}/Fiducials.pretty)(options "")(descr "Fiducial markings"))
+  (lib (name Fuse_Holders_and_Fuses)(type KiCad)(uri ${KISYSMOD}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders"))
+  (lib (name Hall-Effect_Transducers_LEM)(type KiCad)(uri ${KISYSMOD}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers"))
+  (lib (name Heatsinks)(type KiCad)(uri ${KISYSMOD}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products"))
+  (lib (name Housings_BGA)(type KiCad)(uri ${KISYSMOD}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)"))
+  (lib (name Housings_CSP)(type KiCad)(uri ${KISYSMOD}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)"))
+  (lib (name Housings_DFN_QFN)(type KiCad)(uri ${KISYSMOD}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN"))
+  (lib (name Housings_DIP)(type KiCad)(uri ${KISYSMOD}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP"))
+  (lib (name Housings_LCC)(type KiCad)(uri ${KISYSMOD}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)"))
+  (lib (name Housings_LGA)(type KiCad)(uri ${KISYSMOD}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)"))
+  (lib (name Housings_PGA)(type KiCad)(uri ${KISYSMOD}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)"))
+  (lib (name Housings_QFP)(type KiCad)(uri ${KISYSMOD}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)"))
+  (lib (name Housings_SIP)(type KiCad)(uri ${KISYSMOD}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)"))
+  (lib (name Housings_SOIC)(type KiCad)(uri ${KISYSMOD}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)"))
+  (lib (name Housings_SON)(type KiCad)(uri ${KISYSMOD}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)"))
+  (lib (name Housings_SSOP)(type KiCad)(uri ${KISYSMOD}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages"))
+  (lib (name Inductors_SMD)(type KiCad)(uri ${KISYSMOD}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount"))
+  (lib (name Inductors_THT)(type KiCad)(uri ${KISYSMOD}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole"))
+  (lib (name IR-DirectFETs)(type KiCad)(uri ${KISYSMOD}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier"))
+  (lib (name LEDs)(type KiCad)(uri ${KISYSMOD}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)"))
+  (lib (name Measurement_Points)(type KiCad)(uri ${KISYSMOD}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment"))
+  (lib (name Measurement_Scales)(type KiCad)(uri ${KISYSMOD}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges"))
+  (lib (name Microwave)(type KiCad)(uri ${KISYSMOD}/Microwave.pretty)(options "")(descr Microwave))
+  (lib (name Modules)(type KiCad)(uri ${KISYSMOD}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module"))
+  (lib (name Mounting_Holes)(type KiCad)(uri ${KISYSMOD}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners"))
+  (lib (name Opto-Devices)(type KiCad)(uri ${KISYSMOD}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices"))
+  (lib (name Oscillators)(type KiCad)(uri ${KISYSMOD}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules"))
+  (lib (name PFF_PSF_PSS_Leadforms)(type KiCad)(uri ${KISYSMOD}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages"))
+  (lib (name Pin_Headers)(type KiCad)(uri ${KISYSMOD}/Pin_Headers.pretty)(options "")(descr "Male pin headers"))
+  (lib (name Potentiometers)(type KiCad)(uri ${KISYSMOD}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors"))
+  (lib (name Power_Integrations)(type KiCad)(uri ${KISYSMOD}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints"))
+  (lib (name Relays_SMD)(type KiCad)(uri ${KISYSMOD}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages"))
+  (lib (name Relays_THT)(type KiCad)(uri ${KISYSMOD}/Relays_THT.pretty)(options "")(descr "Through hole relay packages"))
+  (lib (name Resistors_SMD)(type KiCad)(uri ${KISYSMOD}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount"))
+  (lib (name Resistors_THT)(type KiCad)(uri ${KISYSMOD}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole"))
+  (lib (name Resistors_Universal)(type KiCad)(uri ${KISYSMOD}/Resistors_Universal.pretty)(options "")(descr Experimental))
+  (lib (name RF_Antennas)(type KiCad)(uri ${KISYSMOD}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints"))
+  (lib (name RF_Modules)(type KiCad)(uri ${KISYSMOD}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules"))
+  (lib (name Shielding_Cabinets)(type KiCad)(uri ${KISYSMOD}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields"))
+  (lib (name SMD_Packages)(type KiCad)(uri ${KISYSMOD}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries"))
+  (lib (name Socket_Strips)(type KiCad)(uri ${KISYSMOD}/Socket_Strips.pretty)(options "")(descr "Female socket strips"))
+  (lib (name Sockets)(type KiCad)(uri ${KISYSMOD}/Sockets.pretty)(options "")(descr "IC sockets"))
+  (lib (name Symbols)(type KiCad)(uri ${KISYSMOD}/Symbols.pretty)(options "")(descr "PCB symbols"))
+  (lib (name TerminalBlocks_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks"))
+  (lib (name TerminalBlocks_WAGO)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks"))
+  (lib (name TO_SOT_Packages_SMD)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages"))
+  (lib (name TO_SOT_Packages_THT)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages"))
+  (lib (name Transformers_SMD)(type KiCad)(uri ${KISYSMOD}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers"))
+  (lib (name Transformers_THT)(type KiCad)(uri ${KISYSMOD}/Transformers_THT.pretty)(options "")(descr "Through hole transformers"))
+  (lib (name Transistors_OldSowjetAera)(type KiCad)(uri ${KISYSMOD}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors"))
+  (lib (name Valves)(type KiCad)(uri ${KISYSMOD}/Valves.pretty)(options "")(descr Valves))
+  (lib (name Varistors)(type KiCad)(uri ${KISYSMOD}/Varistors.pretty)(options "")(descr Varistors))
+  (lib (name Wire_Connections_Bridges)(type KiCad)(uri ${KISYSMOD}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points"))
+  (lib (name Wire_Pads)(type KiCad)(uri ${KISYSMOD}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points"))
+  (lib (name Choke_Common-Mode_Wurth)(type KiCad)(uri "$(KISYSMOD)Choke_Common-Mode_Wurth.pretty")(options "")(descr ""))
+  (lib (name Choke_Radial_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Radial_ThroughHole.pretty")(options "")(descr ""))
+  (lib (name Choke_SMD)(type KiCad)(uri "$(KISYSMOD)Choke_SMD.pretty")(options "")(descr ""))
+  (lib (name Choke_Toroid_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Toroid_ThroughHole.pretty")(options "")(descr ""))
+)
diff --git a/src/supportFiles/fp-lib-table-online b/src/supportFiles/fp-lib-table-online
new file mode 100644
index 00000000..5b4081ff
--- /dev/null
+++ b/src/supportFiles/fp-lib-table-online
@@ -0,0 +1,88 @@
+(fp_lib_table
+  (lib (name Battery_Holders)(type Github)(uri ${KIGITHUB}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders"))
+  (lib (name Buttons_Switches_SMD)(type Github)(uri ${KIGITHUB}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount"))
+  (lib (name Buttons_Switches_THT)(type Github)(uri ${KIGITHUB}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole"))
+  (lib (name Buzzers_Beepers)(type Github)(uri ${KIGITHUB}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices"))
+  (lib (name Capacitors_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount"))
+  (lib (name Capacitors_Tantalum_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount"))
+  (lib (name Capacitors_THT)(type Github)(uri ${KIGITHUB}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole"))
+  (lib (name Connectors_Card)(type Github)(uri ${KIGITHUB}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders"))
+  (lib (name Connectors_Harwin)(type Github)(uri ${KIGITHUB}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com"))
+  (lib (name Connectors_HDMI)(type Github)(uri ${KIGITHUB}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints"))
+  (lib (name Connectors_Hirose)(type Github)(uri ${KIGITHUB}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com"))
+  (lib (name Connectors_IEC_DIN)(type Github)(uri ${KIGITHUB}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints"))
+  (lib (name Connectors_JAE)(type Github)(uri ${KIGITHUB}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors"))
+  (lib (name Connectors_JST)(type Github)(uri ${KIGITHUB}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com"))
+  (lib (name Connectors_Mini-Universal)(type Github)(uri ${KIGITHUB}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok))
+  (lib (name Connectors_Molex)(type Github)(uri ${KIGITHUB}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com"))
+  (lib (name Connectors_Multicomp)(type Github)(uri ${KIGITHUB}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints"))
+  (lib (name Connectors_Phoenix)(type Github)(uri ${KIGITHUB}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints"))
+  (lib (name Connectors_Samtec)(type Github)(uri ${KIGITHUB}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints"))
+  (lib (name Connectors_TE-Connectivity)(type Github)(uri ${KIGITHUB}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com"))
+  (lib (name Connectors_Terminal_Blocks)(type Github)(uri ${KIGITHUB}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors"))
+  (lib (name Connectors_WAGO)(type Github)(uri ${KIGITHUB}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com"))
+  (lib (name Connectors_USB)(type Github)(uri ${KIGITHUB}/Connectors_USB.pretty)(options "")(descr "USB connector footprints"))
+  (lib (name Connectors)(type Github)(uri ${KIGITHUB}/Connectors.pretty)(options "")(descr "Assorted connector footprints"))
+  (lib (name Converters_DCDC_ACDC)(type Github)(uri ${KIGITHUB}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules"))
+  (lib (name Crystals)(type Github)(uri ${KIGITHUB}/Crystals.pretty)(options "")(descr "Crystals and oscillators"))
+  (lib (name Diodes_SMD)(type Github)(uri ${KIGITHUB}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount"))
+  (lib (name Diodes_THT)(type Github)(uri ${KIGITHUB}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole"))
+  (lib (name Displays_7-Segment)(type Github)(uri ${KIGITHUB}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays"))
+  (lib (name Displays)(type Github)(uri ${KIGITHUB}/Displays.pretty)(options "")(descr "Display modules"))
+  (lib (name Enclosures)(type Github)(uri ${KIGITHUB}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings"))
+  (lib (name EuroBoard_Outline)(type Github)(uri ${KIGITHUB}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed"))
+  (lib (name Fiducials)(type Github)(uri ${KIGITHUB}/Fiducials.pretty)(options "")(descr "Fiducial markings"))
+  (lib (name Fuse_Holders_and_Fuses)(type Github)(uri ${KIGITHUB}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders"))
+  (lib (name Hall-Effect_Transducers_LEM)(type Github)(uri ${KIGITHUB}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers"))
+  (lib (name Heatsinks)(type Github)(uri ${KIGITHUB}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products"))
+  (lib (name Housings_BGA)(type Github)(uri ${KIGITHUB}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)"))
+  (lib (name Housings_CSP)(type Github)(uri ${KIGITHUB}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)"))
+  (lib (name Housings_DFN_QFN)(type Github)(uri ${KIGITHUB}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN"))
+  (lib (name Housings_DIP)(type Github)(uri ${KIGITHUB}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP"))
+  (lib (name Housings_LCC)(type Github)(uri ${KIGITHUB}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)"))
+  (lib (name Housings_LGA)(type Github)(uri ${KIGITHUB}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)"))
+  (lib (name Housings_PGA)(type Github)(uri ${KIGITHUB}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)"))
+  (lib (name Housings_QFP)(type Github)(uri ${KIGITHUB}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)"))
+  (lib (name Housings_SIP)(type Github)(uri ${KIGITHUB}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)"))
+  (lib (name Housings_SOIC)(type Github)(uri ${KIGITHUB}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)"))
+  (lib (name Housings_SON)(type Github)(uri ${KIGITHUB}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)"))
+  (lib (name Housings_SSOP)(type Github)(uri ${KIGITHUB}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages"))
+  (lib (name Inductors_SMD)(type Github)(uri ${KIGITHUB}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount"))
+  (lib (name Inductors_THT)(type Github)(uri ${KIGITHUB}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole"))
+  (lib (name IR-DirectFETs)(type Github)(uri ${KIGITHUB}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier"))
+  (lib (name LEDs)(type Github)(uri ${KIGITHUB}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)"))
+  (lib (name Measurement_Points)(type Github)(uri ${KIGITHUB}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment"))
+  (lib (name Measurement_Scales)(type Github)(uri ${KIGITHUB}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges"))
+  (lib (name Microwave)(type Github)(uri ${KIGITHUB}/Microwave.pretty)(options "")(descr "Microwave"))
+  (lib (name Modules)(type Github)(uri ${KIGITHUB}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module"))
+  (lib (name Mounting_Holes)(type Github)(uri ${KIGITHUB}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners"))
+  (lib (name Opto-Devices)(type Github)(uri ${KIGITHUB}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices"))
+  (lib (name Oscillators)(type Github)(uri ${KIGITHUB}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules"))
+  (lib (name PFF_PSF_PSS_Leadforms)(type Github)(uri ${KIGITHUB}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages"))
+  (lib (name Pin_Headers)(type Github)(uri ${KIGITHUB}/Pin_Headers.pretty)(options "")(descr "Male pin headers"))
+  (lib (name Potentiometers)(type Github)(uri ${KIGITHUB}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors"))
+  (lib (name Power_Integrations)(type Github)(uri ${KIGITHUB}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints"))
+  (lib (name Relays_SMD)(type Github)(uri ${KIGITHUB}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages"))
+  (lib (name Relays_THT)(type Github)(uri ${KIGITHUB}/Relays_THT.pretty)(options "")(descr "Through hole relay packages"))
+  (lib (name Resistors_SMD)(type Github)(uri ${KIGITHUB}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount"))
+  (lib (name Resistors_THT)(type Github)(uri ${KIGITHUB}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole"))
+  (lib (name Resistors_Universal)(type Github)(uri ${KIGITHUB}/Resistors_Universal.pretty)(options "")(descr Experimental))
+  (lib (name RF_Antennas)(type Github)(uri ${KIGITHUB}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints"))
+  (lib (name RF_Modules)(type Github)(uri ${KIGITHUB}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules"))
+  (lib (name Shielding_Cabinets)(type Github)(uri ${KIGITHUB}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields"))
+  (lib (name SMD_Packages)(type Github)(uri ${KIGITHUB}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries"))
+  (lib (name Socket_Strips)(type Github)(uri ${KIGITHUB}/Socket_Strips.pretty)(options "")(descr "Female socket strips"))
+  (lib (name Sockets)(type Github)(uri ${KIGITHUB}/Sockets.pretty)(options "")(descr "IC sockets"))
+  (lib (name Symbols)(type Github)(uri ${KIGITHUB}/Symbols.pretty)(options "")(descr "PCB symbols"))
+  (lib (name TerminalBlocks_Phoenix)(type Github)(uri ${KIGITHUB}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks"))
+  (lib (name TerminalBlocks_WAGO)(type Github)(uri ${KIGITHUB}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks"))
+  (lib (name TO_SOT_Packages_SMD)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages"))
+  (lib (name TO_SOT_Packages_THT)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages"))
+  (lib (name Transformers_SMD)(type Github)(uri ${KIGITHUB}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers"))
+  (lib (name Transformers_THT)(type Github)(uri ${KIGITHUB}/Transformers_THT.pretty)(options "")(descr "Through hole transformers"))
+  (lib (name Transistors_OldSowjetAera)(type Github)(uri ${KIGITHUB}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors"))
+  (lib (name Valves)(type Github)(uri ${KIGITHUB}/Valves.pretty)(options "")(descr "Valves"))
+  (lib (name Varistors)(type Github)(uri ${KIGITHUB}/Varistors.pretty)(options "")(descr "Varistors"))
+  (lib (name Wire_Connections_Bridges)(type Github)(uri ${KIGITHUB}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points"))
+  (lib (name Wire_Pads)(type Github)(uri ${KIGITHUB}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points"))
+)
-- 
cgit 


From b173d88ac0059b67e60a042293b1e486c9620d8a Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 17:21:28 +0530
Subject: pep8 compliant

---
 src/frontEnd/Application.py             | 92 +++++++++++++++++++--------------
 src/frontEnd/DockArea.py                |  4 +-
 src/kicadtoNgspice/Analysis.py          |  2 +-
 src/kicadtoNgspice/Convert.py           |  2 +-
 src/kicadtoNgspice/Processing.py        |  6 +--
 src/kicadtoNgspice/Source.py            |  2 +-
 src/ngspiceSimulation/pythonPlotting.py |  8 +--
 src/projManagement/Kicad.py             |  2 +-
 src/projManagement/Validation.py        |  2 +-
 src/projManagement/Worker.py            |  4 +-
 10 files changed, 69 insertions(+), 55 deletions(-)

(limited to 'src')

diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 6cb25e80..1ea43224 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -12,7 +12,7 @@
 #        AUTHOR: Fahim Khan, fahim.elex@gmail.com
 #      MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in
 #  ORGANIZATION: eSim team at FOSSEE, IIT Bombay.
-#       CREATED: Tuesday 24 February 2015 
+#       CREATED: Tuesday 24 February 2015
 #      REVISION: Friday 14 February 2020
 # =========================================================================
 
@@ -45,9 +45,9 @@ class Application(QtGui.QMainWindow):
         # Calling __init__ of super class
         QtGui.QMainWindow.__init__(self, *args)
 
-        #Flag for mode of operation. Default is set to offline mode.
+        # Flag for mode of operation. Default is set to offline mode.
         self.online_flag = False
-                
+
         # Creating require Object
         self.obj_workspace = Workspace.Workspace()
         self.obj_Mainview = MainView()
@@ -345,44 +345,45 @@ class Application(QtGui.QMainWindow):
             # -----------------------------------------------------
             # fp-lib-table is not there than copy from supportFiles/
             if not os.path.exists(
-                self.obj_appconfig.kicad_path + "/fp-lib-table"):
-                shutil.copy('../supportFiles/fp-lib-table' ,
-                    self.obj_appconfig.kicad_path + "/")
+                self.obj_appconfig.kicad_path +
+                "/fp-lib-table"
+            ):
+                shutil.copy('../supportFiles/fp-lib-table',
+                            self.obj_appconfig.kicad_path + "/")
             # -----------------------------------------------------
             """checking online and offline both file's are avaliable.
             if yes than remove offline file."""
             if os.path.exists(self.obj_appconfig.kicad_path +
-                     "/fp-lib-table-offline") and os.path.exists(
-                self.obj_appconfig.kicad_path +
-                    "/fp-lib-table-online"):
-                     os.remove(self.obj_appconfig.kicad_path +
-                        "/fp-lib-table-offline")
+                              "/fp-lib-table-offline") and os.path.exists(
+                    self.obj_appconfig.kicad_path + "/fp-lib-table-online"):
+                os.remove(self.obj_appconfig.kicad_path +
+                          "/fp-lib-table-offline")
             # -----------------------------------------------------
             # This ladder is used for checking which file is present.
             if os.path.exists(self.obj_appconfig.kicad_path +
-                     "/fp-lib-table-offline"):
+                              "/fp-lib-table-offline"):
                 self.switchmode = QtGui.QAction(
                     QtGui.QIcon('../../images/online.png'),
-                    '<b>Go Offline</b>',self)
+                    '<b>Go Offline</b>', self)
                 self.online_flag = True
 
             elif os.path.exists(self.obj_appconfig.kicad_path +
-                    "/fp-lib-table-online"):
+                                "/fp-lib-table-online"):
                 self.switchmode = QtGui.QAction(
                     QtGui.QIcon('../../images/offline.png'),
-                    '<b>Go Online</b>',self)
+                    '<b>Go Online</b>', self)
                 self.online_flag = False
             else:
                 # if online and offline is not avaliable
-                shutil.copy('../supportFiles/fp-lib-table-online' ,
-                        self.obj_appconfig.kicad_path + "/")
+                shutil.copy('../supportFiles/fp-lib-table-online',
+                            self.obj_appconfig.kicad_path + "/")
                 if os.path.exists(self.obj_appconfig.kicad_path +
-                        "/fp-lib-table-online"):
+                                  "/fp-lib-table-online"):
                     self.switchmode = QtGui.QAction(
                         QtGui.QIcon('../../images/offline.png'),
-                        '<b>Go Online</b>',self)
+                        '<b>Go Online</b>', self)
                     self.online_flag = False
-            #----------------------------------------------------
+            # ----------------------------------------------------
         else:
             # if path is not found
             self.switchmode = QtGui.QAction(QtGui.QIcon(
@@ -393,11 +394,11 @@ class Application(QtGui.QMainWindow):
     def change_mode(self):
         """
         This function is used for changing mode of operation for KiCad. \
-        There are three modes of operation : 
-            - online 
+        There are three modes of operation :
+            - online
             - offline
             - disable
-        
+
         It will check whether kicad config path is present or not.
             - If path is available and none of the KiCad tools \
               (associated with eSim) are open, then depending on \
@@ -417,37 +418,48 @@ class Application(QtGui.QMainWindow):
                     if self.online_flag:
                         os.rename(
                             self.obj_appconfig.kicad_path + "/fp-lib-table",
-                            self.obj_appconfig.kicad_path + "/fp-lib-table-online"
+                            self.obj_appconfig.kicad_path +
+                            "/fp-lib-table-online"
                         )
                         os.rename(
-                            self.obj_appconfig.kicad_path + "/fp-lib-table-offline",
+                            self.obj_appconfig.kicad_path +
+                            "/fp-lib-table-offline",
                             self.obj_appconfig.kicad_path + "/fp-lib-table"
                         )
-                        self.switchmode.setIcon(QtGui.QIcon('../../images/offline.png'))
+                        self.switchmode.setIcon(
+                            QtGui.QIcon('../../images/offline.png')
+                        )
                         self.switchmode.setText('<b>Go Online</b>')
                         self.online_flag = False
                     else:
                         os.rename(
                             self.obj_appconfig.kicad_path + "/fp-lib-table",
-                            self.obj_appconfig.kicad_path + "/fp-lib-table-offline")
+                            self.obj_appconfig.kicad_path +
+                            "/fp-lib-table-offline"
+                        )
                         os.rename(
-                            self.obj_appconfig.kicad_path + "/fp-lib-table-online",
-                            self.obj_appconfig.kicad_path + "/fp-lib-table")
-                        self.switchmode.setIcon(QtGui.QIcon('../../images/online.png'))
+                            self.obj_appconfig.kicad_path +
+                            "/fp-lib-table-online",
+                            self.obj_appconfig.kicad_path + "/fp-lib-table"
+                        )
+                        self.switchmode.setIcon(
+                            QtGui.QIcon('../../images/online.png')
+                        )
                         self.switchmode.setText('<b>Go Offline</b>')
                         self.online_flag = True
                 else:
                     self.msg = QtGui.QErrorMessage()
-                    self.msg.showMessage('Please save and close all the Kicad'
-                        'Windows first, and then change the online-offline mode')
+                    self.msg.showMessage(
+                        'Please save and close all the Kicad ' +
+                        'windows first, then change the online-offline mode')
                     self.msg.setWindowTitle("Error Message")
-            except:
+            except BaseException:
                 self.validate_mode()
         else:
-            self.info_msg = QtGui.QMessageBox.critical(self,
-                            'Message',
-                            "Please make sure kicad_folder_file is " +
-                            "present in supportFiles folder.")
+            self.info_msg = QtGui.QMessageBox.critical(
+                self, 'Message', "Please make sure kicad_folder_file is " +
+                "present in supportFiles folder."
+            )
 
     def help_project(self):
         """
@@ -542,9 +554,9 @@ class Application(QtGui.QMainWindow):
         else:
             self.msg = QtGui.QErrorMessage(None)
             self.msg.showMessage('Error while opening NGHDL. ' +
-                'Please make sure it is installed')
+                                 'Please make sure it is installed')
             self.obj_appconfig.print_error('Error while opening NGHDL. ' +
-                'Please make sure it is installed')
+                                           'Please make sure it is installed')
             self.msg.setWindowTitle('NGHDL Error')
 
     def open_modelEditor(self):
@@ -610,7 +622,7 @@ class Application(QtGui.QMainWindow):
                         self.msg.setWindowTitle("Missing OpenModelica")
                         self.obj_appconfig.print_info(self.msgContent)
                         self.msg.exec_()
-                
+
                 except Exception as e:
                     self.msg = QtGui.QErrorMessage()
                     self.msg.showMessage(
diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py
index 9824a307..b8ebfac4 100644
--- a/src/frontEnd/DockArea.py
+++ b/src/frontEnd/DockArea.py
@@ -56,7 +56,7 @@ class DockArea(QtGui.QMainWindow):
     def createTestEditor(self):
         """This function create widget for Library Editor"""
         global count
-                
+
         self.testWidget = QtGui.QWidget()
         self.testArea = QtGui.QTextEdit()
         self.testLayout = QtGui.QVBoxLayout()
@@ -148,7 +148,7 @@ class DockArea(QtGui.QMainWindow):
         dock['NgSpice-' + str(count)].setVisible(True)
         dock['NgSpice-' + str(count)].setFocus()
         dock['NgSpice-' + str(count)].raise_()
-        
+
         temp = self.obj_appconfig.current_project['ProjectName']
         if temp:
             self.obj_appconfig.dock_dict[temp].append(
diff --git a/src/kicadtoNgspice/Analysis.py b/src/kicadtoNgspice/Analysis.py
index e5c05ebe..9e91cca9 100644
--- a/src/kicadtoNgspice/Analysis.py
+++ b/src/kicadtoNgspice/Analysis.py
@@ -837,7 +837,7 @@ class Analysis(QtGui.QWidget):
                 print("Transient Analysis JSON Parse Error")
 
         return self.trbox
-    
+
     '''
     - Below 3 functions handle event for the combo box in transient group
     '''
diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py
index 99f8768a..ae26f3b8 100644
--- a/src/kicadtoNgspice/Convert.py
+++ b/src/kicadtoNgspice/Convert.py
@@ -638,5 +638,5 @@ class Convert:
         for child in libtree.iter():
             if child.tag == 'ref_model':
                 retVal = child.text
-                
+
         return retVal
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index 1e58daac..427f0823 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -91,7 +91,7 @@ class PrcocessNetlist:
         print("=============================================================")
         print("NETLIST", netlist)
         print("INFOLINE", infoline)
-        print("=============================================================")"""
+        print("===========================================================")"""
         return netlist, infoline
 
     def separateNetlistInfo(self, netlist):
@@ -116,7 +116,7 @@ class PrcocessNetlist:
         print("=============================================================")
         print("OPTIONINFO", optionInfo)
         print("SCHEMATICINFO", schematicInfo)
-        print("=============================================================")"""
+        print("===========================================================")"""
         return optionInfo, schematicInfo
 
     def insertSpecialSourceParam(self, schematicInfo, sourcelist):
@@ -220,7 +220,7 @@ class PrcocessNetlist:
         print("=============================================================")
         print("SCHEMATICINFO", schematicInfo)
         print("SOURCELIST", sourcelist)
-        print("=============================================================")"""
+        print("===========================================================")"""
         return schematicInfo, sourcelist
 
     def convertICintoBasicBlocks(
diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py
index 6c5ae637..e76118d4 100644
--- a/src/kicadtoNgspice/Source.py
+++ b/src/kicadtoNgspice/Source.py
@@ -47,7 +47,7 @@ class Source(QtGui.QWidget):
         """print("============================================================")
         print("SOURCE LIST TRACK", sourcelisttrack)
         print("SOURCE LIST", sourcelist)
-        print("============================================================")"""
+        print("===========================================================")"""
         kicadFile = self.clarg1
         (projpath, filename) = os.path.split(kicadFile)
         project_name = os.path.basename(projpath)
diff --git a/src/ngspiceSimulation/pythonPlotting.py b/src/ngspiceSimulation/pythonPlotting.py
index e19b49de..4a32f658 100644
--- a/src/ngspiceSimulation/pythonPlotting.py
+++ b/src/ngspiceSimulation/pythonPlotting.py
@@ -283,11 +283,13 @@ class plotWindow(QtGui.QMainWindow):
 
             if a[i] == len(self.obj_dataext.NBList):
                 QtGui.QMessageBox.about(
-                    self, "Warning!!", "One of the operands doesn't belong "
-                        "to the above list!!")
+                    self, "Warning!!", "One of the operands doesn't belong " +
+                    "to the above list!!"
+                )
                 self.warnning.setText(
                     "<font color='red'>To Err Is Human!<br>One of the " +
-                    "operands doesn't belong to the above list!!</font>")
+                    "operands doesn't belong to the above list!!</font>"
+                )
 
         if self.parts[1] == 'vs':
             if len(self.parts) > 3:
diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py
index 02695ef4..c522af56 100644
--- a/src/projManagement/Kicad.py
+++ b/src/projManagement/Kicad.py
@@ -50,7 +50,7 @@ class Kicad:
 
         @return
             True        => If the project's schematic is not open
-            False       => If the project's schematic is open        
+            False       => If the project's schematic is open
         """
         if self.obj_workThread:
             procList = self.obj_workThread.get_proc_threads()[:]
diff --git a/src/projManagement/Validation.py b/src/projManagement/Validation.py
index b2d568e4..23a66416 100644
--- a/src/projManagement/Validation.py
+++ b/src/projManagement/Validation.py
@@ -38,7 +38,7 @@ class Validation:
         projName.proj file exists or not
 
         @params
-            :projDir    => contains the path of the project folder selected to open
+            :projDir    => contains the path of the project selected to open
 
         @return
             True        => If the folder contains the projName.proj file
diff --git a/src/projManagement/Worker.py b/src/projManagement/Worker.py
index e523b533..8ced35a7 100644
--- a/src/projManagement/Worker.py
+++ b/src/projManagement/Worker.py
@@ -60,10 +60,10 @@ class WorkerThread(QtCore.QThread):
         and is called to check if project's schematic is open or not.
 
         @params
-        
+
         @return
             :self.my_workers
-        """        
+        """
         return self.my_workers
 
     def run(self):
-- 
cgit 


From 94326c365e361137412272a46caafe7f97620196 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Sat, 15 Feb 2020 14:41:09 +0530
Subject: set modality to QErrorMessage

---
 src/frontEnd/Application.py             | 36 ++++++++++++++++++++++++---------
 src/frontEnd/ProjectExplorer.py         | 22 +++++++++++++-------
 src/kicadtoNgspice/Convert.py           |  5 +++--
 src/kicadtoNgspice/KicadtoNgspice.py    |  8 ++++++--
 src/kicadtoNgspice/SubcircuitTab.py     | 20 ++++++++++--------
 src/modelEditor/ModelEditor.py          |  8 ++++++--
 src/ngspiceSimulation/pythonPlotting.py | 14 ++++++++-----
 src/ngspicetoModelica/ModelicaUI.py     |  8 ++++++--
 src/projManagement/Kicad.py             | 31 ++++++++++++++++++----------
 src/projManagement/newProject.py        | 18 +++++++++++++----
 src/subcircuit/convertSub.py            | 12 +++++++----
 src/subcircuit/newSub.py                | 16 +++++++++++----
 src/subcircuit/uploadSub.py             | 16 +++++++++++----
 13 files changed, 149 insertions(+), 65 deletions(-)

(limited to 'src')

diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 1ea43224..6e46925b 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -449,10 +449,13 @@ class Application(QtGui.QMainWindow):
                         self.online_flag = True
                 else:
                     self.msg = QtGui.QErrorMessage()
+                    self.msg.setModal(True)
+                    self.msg.setWindowTitle("Error Message")
                     self.msg.showMessage(
                         'Please save and close all the Kicad ' +
                         'windows first, then change the online-offline mode')
-                    self.msg.setWindowTitle("Error Message")
+                    self.msg.exec_()
+
             except BaseException:
                 self.validate_mode()
         else:
@@ -504,21 +507,26 @@ class Application(QtGui.QMainWindow):
             try:
                 self.obj_Mainview.obj_dockarea.plottingEditor()
             except Exception as e:
-                self.msg = QtGui.QErrorMessage(None)
+                self.msg = QtGui.QErrorMessage()
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'Error while opening python plotting Editor.'
                     ' Please look at console for more details.'
                 )
+                self.msg.exec_()
                 print("Exception Message:", str(e))
                 self.obj_appconfig.print_error('Exception Message : ' + str(e))
-                self.msg.setWindowTitle("Error Message")
+
         else:
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'Please select the project first.'
                 ' You can either create new project or open existing project'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
 
     def open_subcircuit(self):
         """
@@ -552,12 +560,14 @@ class Application(QtGui.QMainWindow):
             self.obj_workThread = Worker.WorkerThread(self.cmd)
             self.obj_workThread.start()
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle('NGHDL Error')
             self.msg.showMessage('Error while opening NGHDL. ' +
                                  'Please make sure it is installed')
             self.obj_appconfig.print_error('Error while opening NGHDL. ' +
                                            'Please make sure it is installed')
-            self.msg.setWindowTitle('NGHDL Error')
+            self.msg.exec_()
 
     def open_modelEditor(self):
         """
@@ -625,11 +635,13 @@ class Application(QtGui.QMainWindow):
 
                 except Exception as e:
                     self.msg = QtGui.QErrorMessage()
+                    self.msg.setModal(True)
+                    self.msg.setWindowTitle(
+                        "Ngspice to Modelica conversion error")
                     self.msg.showMessage(
                         'Unable to convert NgSpice netlist to\
                             Modelica netlist :'+str(e))
-                    self.msg.setWindowTitle(
-                        "Ngspice to Modelica conversion error")
+                    self.msg.exec_()
                     self.obj_appconfig.print_error(str(e))
                 """
 
@@ -637,18 +649,22 @@ class Application(QtGui.QMainWindow):
 
             else:
                 self.msg = QtGui.QErrorMessage()
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Missing Ngspice netlist")
                 self.msg.showMessage(
                     'Current project does not contain any Ngspice file. ' +
                     'Please create Ngspice file with extension .cir.out'
                 )
-                self.msg.setWindowTitle("Missing Ngspice netlist")
+                self.msg.exec_()
         else:
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'Please select the project first. ' +
                 'You can either create a new project or open existing project'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.exec_()
 
     def open_OMoptim(self):
         """
diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py
index 1557d450..54f0148f 100644
--- a/src/frontEnd/ProjectExplorer.py
+++ b/src/frontEnd/ProjectExplorer.py
@@ -246,7 +246,7 @@ class ProjectExplorer(QtGui.QWidget):
         )
         if ok and newBaseFileName:
             print(newBaseFileName)
-            print("=================")
+            print("==================")
             newBaseFileName = str(newBaseFileName)
 
             i = -1
@@ -264,19 +264,23 @@ class ProjectExplorer(QtGui.QWidget):
             newBaseFileName = str(newBaseFileName).rstrip().lstrip()
             projDir = os.path.join(self.workspace, str(newBaseFileName))
 
-            if newBaseFileName == "":
-                print("Project name can not be empty")
+            if not newBaseFileName.strip():
+                print("Project name cannot be empty")
                 print("==================")
                 msg = QtGui.QErrorMessage(self)
-                msg.showMessage('The project name cannot be empty')
+                msg.setModal(True)
                 msg.setWindowTitle("Error Message")
+                msg.showMessage('The project name cannot be empty')
+                msg.exec_()
 
             elif self.baseFileName == newBaseFileName:
                 print("Project name has to be different")
                 print("==================")
                 msg = QtGui.QErrorMessage(self)
-                msg.showMessage('The project name has to be different')
+                msg.setModal(True)
                 msg.setWindowTitle("Error Message")
+                msg.showMessage('The project name has to be different')
+                msg.exec_()
 
             else:
                 reply = self.obj_validation.validateNewproj(str(projDir))
@@ -323,19 +327,23 @@ class ProjectExplorer(QtGui.QWidget):
                     print("Project name already exists.")
                     print("==========================")
                     msg = QtGui.QErrorMessage(self)
+                    msg.setModal(True)
+                    msg.setWindowTitle("Error Message")
                     msg.showMessage(
                         'The project "' + newBaseFileName +
                         '" already exist. Please select a different name or' +
                         ' delete existing project'
                     )
-                    msg.setWindowTitle("Error Message")
+                    msg.exec_()
 
                 elif reply == "CHECKNAME":
                     print("Name can not contain space between them")
                     print("===========================")
                     msg = QtGui.QErrorMessage(self)
+                    msg.setModal(True)
+                    msg.setWindowTitle("Error Message")
                     msg.showMessage(
                         'The project name should not ' +
                         'contain space between them'
                     )
-                    msg.setWindowTitle("Error Message")
+                    msg.exec_()
diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py
index ae26f3b8..7ab57427 100644
--- a/src/kicadtoNgspice/Convert.py
+++ b/src/kicadtoNgspice/Convert.py
@@ -585,10 +585,11 @@ class Convert:
         if len(self.obj_track.subcircuitList) != len(
                 self.obj_track.subcircuitTrack):
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Conversion failed. Please add all Subcircuits.")
-            self.msg.setWindowTitle("Error Message")
-            self.msg.show()
+            self.msg.exec_()
             raise Exception('All subcircuit directories need to be specified.')
         elif not subList:
             print("No Subcircuit Added in the schematic")
diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index ab2e55e8..cfc4f671 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -121,18 +121,22 @@ class MainWindow(QtGui.QWidget):
         if unknownModelList:
             print("Unknown Model List is : ", unknownModelList)
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Unknown Models")
             self.content = "Your schematic contain unknown model " + \
                 ', '.join(unknownModelList)
             self.msg.showMessage(self.content)
-            self.msg.setWindowTitle("Unknown Models")
+            self.msg.exec_()
 
         elif multipleModelList:
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Multiple Models")
             self.mcontent = "Look like you have duplicate model in \
             modelParamXML directory " + \
                 ', '.join(multipleModelList[0])
             self.msg.showMessage(self.mcontent)
-            self.msg.setWindowTitle("Multiple Models")
+            self.msg.exec_()
 
         else:
             self.createMainWindow()
diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py
index 116b70b1..08ad7332 100644
--- a/src/kicadtoNgspice/SubcircuitTab.py
+++ b/src/kicadtoNgspice/SubcircuitTab.py
@@ -156,17 +156,19 @@ class SubcircuitTab(QtGui.QWidget):
             self.obj_trac.subcircuitTrack[self.subName] = self.subfile
         elif self.reply == "PORT":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Please select a Subcircuit with correct number of ports.")
-            self.msg.setWindowTitle("Error Message")
-            self.msg.show()
+            self.msg.exec_()
         elif self.reply == "DIREC":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Please select a valid Subcircuit directory "
                 "(Containing '.sub' file).")
-            self.msg.setWindowTitle("Error Message")
-            self.msg.show()
+            self.msg.exec_()
 
     def trackSubcircuitWithoutButton(self, iter_value, path_value):
         """
@@ -189,14 +191,16 @@ class SubcircuitTab(QtGui.QWidget):
             self.obj_trac.subcircuitTrack[self.subName] = self.subfile
         elif self.reply == "PORT":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Please select a Subcircuit with correct number of ports.")
-            self.msg.setWindowTitle("Error Message")
-            self.msg.show()
+            self.msg.exec_()
         elif self.reply == "DIREC":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Please select a valid Subcircuit directory "
                 "(Containing '.sub' file).")
-            self.msg.setWindowTitle("Error Message")
-            self.msg.show()
+            self.msg.exec_()
diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py
index 3f616808..7db35251 100644
--- a/src/modelEditor/ModelEditor.py
+++ b/src/modelEditor/ModelEditor.py
@@ -424,9 +424,11 @@ class ModelEditorclass(QtGui.QWidget):
         if ok:
             if text1 in list(self.modeldict.keys()):
                 self.msg = QtGui.QErrorMessage(self)
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     "The paramaeter " + text1 + " is already in the list")
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
                 return
             text2, ok = QtGui.QInputDialog.getText(
                 self, 'Value', 'Enter Value')
@@ -614,9 +616,11 @@ class ModelEditorclass(QtGui.QWidget):
             all_files = os.listdir(each_dir)
             if newfilename in all_files:
                 self.msg = QtGui.QErrorMessage(self)
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'The file with name ' + text + ' already exists.')
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
 
     def savethefile(self, editfile):
         '''
diff --git a/src/ngspiceSimulation/pythonPlotting.py b/src/ngspiceSimulation/pythonPlotting.py
index 4a32f658..032b1eeb 100644
--- a/src/ngspiceSimulation/pythonPlotting.py
+++ b/src/ngspiceSimulation/pythonPlotting.py
@@ -667,9 +667,11 @@ class DataExtraction:
         except Exception as e:
             print("Exception Message : ", str(e))
             self.obj_appconfig.print_error('Exception Message :' + str(e))
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage('Unable to open plot data files.')
-            self.msg.setWindowTitle("Error Message:openFile")
+            self.msg.exec_()
 
         try:
             for l in alli[3].split(" "):
@@ -680,9 +682,11 @@ class DataExtraction:
         except Exception as e:
             print("Exception Message : ", str(e))
             self.obj_appconfig.print_error('Exception Message :' + str(e))
-            self.msg = QtGui.QErrorMessage(None)
-            self.msg.showMessage('Error in Analysis File.')
-            self.msg.setWindowTitle("Error Message:openFile")
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
+            self.msg.showMessage('Unable to read Analysis File.')
+            self.msg.exec_()
 
         d = self.numberFinder(fpath)
         d1 = int(d[0] + 1)
diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py
index d5daf9ad..168b5c14 100644
--- a/src/ngspicetoModelica/ModelicaUI.py
+++ b/src/ngspicetoModelica/ModelicaUI.py
@@ -79,16 +79,20 @@ class OpenModelicaEditor(QtGui.QWidget):
                 self.msg.exec_()
             else:
                 self.err_msg = QtGui.QErrorMessage()
+                self.msg.setModal(True)
+                self.msg.setWindowTitle(
+                    "Ngspice to Modelica conversion error")
                 self.err_msg.showMessage(
                     'Unable to convert NgSpice netlist to Modelica netlist.' +
                     'Check the netlist :' +
                     error_code)
-                self.err_msg.setWindowTitle(
-                    "Ngspice to Modelica conversion error")
+                self.err_msg.exec_()
                 self.obj_appconfig.print_error(error_code)
 
         except Exception as e:
             self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Ngspice to Modelica conversion error")
             self.msg.showMessage(
                 'Unable to convert NgSpice netlist to Modelica netlist.' +
                 'Check the netlist :' +
diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py
index c522af56..b2fcb87a 100644
--- a/src/projManagement/Kicad.py
+++ b/src/projManagement/Kicad.py
@@ -91,14 +91,16 @@ class Kicad:
             self.obj_workThread.start()
 
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'Please select the project first. You can either ' +
                 'create new project or open existing project')
+            self.msg.exec_()
             self.obj_appconfig.print_warning(
                 'Please select the project first. You can either ' +
                 'create new project or open existing project')
-            self.msg.setWindowTitle("Error Message")
 
     '''
     # Commenting as it is no longer needed as PCB and Layout will open from
@@ -127,13 +129,15 @@ class Kicad:
             self.obj_workThread.start()
 
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage('Please select the project first. You can'
             + 'either create new project or open existing project')
+            self.msg.exec_()
             self.obj_appconfig.print_warning('Please select the project'
             + 'first. You can either create new project or open existing'
             + 'project')
-            self.msg.setWindowTitle("Error Message")
 
     def openLayout(self):
         """
@@ -158,14 +162,15 @@ class Kicad:
             self.obj_workThread.start()
 
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage('Please select the project first. You can'
             + 'either create new project or open existing project')
+            self.msg.exec_()
             self.obj_appconfig.print_warning('Please select the project'
             + 'first. You can either create new project or open existing'
             + 'project')
-            self.msg.setWindowTitle("Error Message")
-
     '''
 
     def openKicadToNgspice(self):
@@ -204,21 +209,25 @@ class Kicad:
                 self.obj_dockarea.kicadToNgspiceEditor(var)
 
             else:
-                self.msg = QtGui.QErrorMessage(None)
+                self.msg = QtGui.QErrorMessage()
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'The project does not contain any Kicad netlist file ' +
                     'for conversion.')
                 self.obj_appconfig.print_error(
                     'The project does not contain any Kicad netlist file ' +
                     'for conversion.')
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
 
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'Please select the project first. You can either ' +
                 'create new project or open existing project')
+            self.msg.exec_()
             self.obj_appconfig.print_warning(
                 'Please select the project first. You can either ' +
                 'create new project or open existing project')
-            self.msg.setWindowTitle("Error Message")
diff --git a/src/projManagement/newProject.py b/src/projManagement/newProject.py
index b7cce397..b04dbd10 100644
--- a/src/projManagement/newProject.py
+++ b/src/projManagement/newProject.py
@@ -83,13 +83,17 @@ class NewProjectInfo(QtGui.QWidget):
                 self.projFile = os.path.join(
                     self.projDir, self.projName + ".proj")
                 f = open(self.projFile, "w")
+
             except BaseException:
                 self.msg = QtGui.QErrorMessage(self)
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'Unable to create project. Please make sure you have ' +
                     'write permission on ' + self.workspace
                 )
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
+
             f.write("schematicFile " + self.projName + ".sch\n")
             f.close()
 
@@ -112,23 +116,29 @@ class NewProjectInfo(QtGui.QWidget):
 
         elif self.reply == "CHECKEXIST":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'The project "' + self.projName +
                 '" already exist.Please select the different name or delete' +
                 ' existing project'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
 
         elif self.reply == "CHECKNAME":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'The project name should not contain space between them')
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
 
         elif self.reply == "NONE":
             self.msg = QtGui.QErrorMessage(self)
-            self.msg.showMessage('The project name cannot be empty')
+            self.msg.setModal(True)
             self.msg.setWindowTitle("Error Message")
+            self.msg.showMessage('The project name cannot be empty')
+            self.msg.exec_()
 
     def cancelProject(self):
         self.close()
diff --git a/src/subcircuit/convertSub.py b/src/subcircuit/convertSub.py
index 1439f140..efad8603 100644
--- a/src/subcircuit/convertSub.py
+++ b/src/subcircuit/convertSub.py
@@ -40,16 +40,20 @@ class convertSub(QtGui.QWidget):
                 var2 = "sub"
                 self.obj_dockarea.kicadToNgspiceEditor(var1, var2)
             else:
-                self.msg = QtGui.QErrorMessage(None)
+                self.msg = QtGui.QErrorMessage()
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'The subcircuit does not contain any Kicad netlist file' +
                     ' for conversion.'
                 )
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
         else:
-            self.msg = QtGui.QErrorMessage(None)
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'Please select the subcircuit first. You can either create ' +
                 'new subcircuit or open existing subcircuit'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py
index 90f60319..f4b3100c 100644
--- a/src/subcircuit/newSub.py
+++ b/src/subcircuit/newSub.py
@@ -55,32 +55,40 @@ class NewSub(QtGui.QWidget):
                 self.close()
             except BaseException:
                 self.msg = QtGui.QErrorMessage(self)
+                self.msg.setModal(True)
+                self.msg.setWindowTitle("Error Message")
                 self.msg.showMessage(
                     'Unable to create subcircuit. Please make sure ' +
                     'you have write permission on ' + self.schematic_path
                 )
-                self.msg.setWindowTitle("Error Message")
+                self.msg.exec_()
 
             self.obj_appconfig.current_subcircuit['SubcircuitName'] \
                 = self.schematic_path
 
         elif self.reply == "CHECKEXIST":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'The subcircuit "' + self.create_schematic +
                 '" already exist.Please select the different name or delete' +
                 'existing subcircuit'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
 
         elif self.reply == "CHECKNAME":
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 'The subcircuit name should not contain space between them'
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
 
         elif self.reply == "NONE":
             self.msg = QtGui.QErrorMessage(self)
-            self.msg.showMessage('The subcircuit name cannot be empty')
+            self.msg.setModal(True)
             self.msg.setWindowTitle("Error Message")
+            self.msg.showMessage('The subcircuit name cannot be empty')
+            self.msg.exec_()
diff --git a/src/subcircuit/uploadSub.py b/src/subcircuit/uploadSub.py
index 34ec8c33..4bb8df34 100644
--- a/src/subcircuit/uploadSub.py
+++ b/src/subcircuit/uploadSub.py
@@ -41,21 +41,25 @@ class UploadSub(QtGui.QWidget):
 
         if ext != '.sub':
             self.msg = QtGui.QErrorMessage(self)
-            self.msg.showMessage("Please ensure that filename ends with .sub")
+            self.msg.setModal(True)
             self.msg.setWindowTitle("Error Message")
+            self.msg.showMessage("Please ensure that filename ends with .sub")
+            self.msg.exec_()
             print("Invalid filename")
             return
 
         valid = self.obj_validation.validateSubcir(editfile, create_subcircuit)
         if not valid:
             self.msg = QtGui.QErrorMessage(self)
+            self.msg.setModal(True)
+            self.msg.setWindowTitle("Error Message")
             self.msg.showMessage(
                 "Content of file does not meet the required format. " +
                 "Please ensure that file starts with **.subckt " +
                 create_subcircuit + " ** and ends with **.ends " +
                 create_subcircuit + " **"
             )
-            self.msg.setWindowTitle("Error Message")
+            self.msg.exec_()
             print("Invalid file format")
             return
 
@@ -80,15 +84,19 @@ class UploadSub(QtGui.QWidget):
             print("Project name already exists.")
             print("==========================")
             msg = QtGui.QErrorMessage(self)
+            msg.setModal(True)
+            msg.setWindowTitle("Error Message")
             msg.showMessage(
                 "The project already exist. Please select "
                 "a different name or delete existing project")
-            msg.setWindowTitle("Error Message")
+            msg.exec_()
 
         elif reply == "CHECKNAME":
             print("Name can not contain space between them")
             print("===========================")
             msg = QtGui.QErrorMessage(self)
+            msg.setModal(True)
+            msg.setWindowTitle("Error Message")
             msg.showMessage(
                 'The project name should not contain space between them')
-            msg.setWindowTitle("Error Message")
+            msg.exec_()
-- 
cgit 


From 3e27f0dcb8555e1708497b48ad251e93fed93b6e Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Sun, 16 Feb 2020 11:55:10 +0530
Subject: mode feature

---
 src/configuration/Appconfig.py |   5 -
 src/frontEnd/Application.py    | 249 +++++++++++++++++++++--------------------
 2 files changed, 127 insertions(+), 127 deletions(-)

(limited to 'src')

diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py
index 8a29ad72..9958f819 100644
--- a/src/configuration/Appconfig.py
+++ b/src/configuration/Appconfig.py
@@ -63,10 +63,8 @@ class Appconfig(QtGui.QWidget):
     try:
         modelica_map_json = parser_esim.get('eSim', 'MODELICA_MAP_JSON')
     except BaseException as e:
-        print("===============================================")
         print("Cannot access Modelica map file --- .esim folder")
         print(str(e))
-        print("===============================================")
 
     # Open file and read KiCad config path
     try:
@@ -75,10 +73,7 @@ class Appconfig(QtGui.QWidget):
         file.close()
     except BaseException as e:
         kicad_path = None
-        print("===============================================")
-        print("Cannot access kicad path file --- supportFiles")
         print(str(e))
-        print("===============================================")
 
     try:
         project_explorer = json.load(open(dictPath))
diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 6e46925b..cd40214b 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -103,12 +103,25 @@ class Application(QtGui.QMainWindow):
         self.closeproj.setShortcut('Ctrl+X')
         self.closeproj.triggered.connect(self.close_project)
 
-        self.switchmode = QtGui.QAction(
-            QtGui.QIcon('../../images/disable.png'),
-            '<b>Mode switching has been disabled. Relaunch ' +
-            'eSim to fix any config issues</b>', self
-        )
+        self.switchmode = None
         self.validate_mode()
+        if self.online_flag == True:
+            self.switchmode = QtGui.QAction(QtGui.QIcon(
+                '../../images/online.png'),
+                '<b>Go Offline</b>', self
+            )
+        elif self.online_flag == False:
+            self.switchmode = QtGui.QAction(QtGui.QIcon(
+                '../../images/offline.png'),
+                '<b>Go Online</b>', self
+            )
+        elif self.online_flag is None:
+            self.switchmode = QtGui.QAction(QtGui.QIcon(
+                '../../images/disable.png'),
+                '<b>Mode switching has been disabled. ' +
+                'Default mode set to offline</b>', self
+            )
+            self.switchmode.setEnabled(False)
         self.switchmode.setShortcut('Ctrl+G')
         self.switchmode.triggered.connect(self.change_mode)
 
@@ -321,148 +334,140 @@ class Application(QtGui.QMainWindow):
 
     def validate_mode(self):
         """
-        This function is used for checking fp-lib-tables file.
-        If not than copy from supportFiles folder.
-        First it will check path for kicad folder is present or not. if present
-            1) it will check fp-lib-table file is present or not.
-                - If not present
-                    - Than copy form SourceFile folder
-            2) it will check for both file,
-               i.e online and offline file is present or not.
-                - If both are present
-                    -Than remove offline.
-            3) it will check wich file is present
-                - If fp-lib-table-offline is present
-                    - Than online mode will set and used
-                - If fp-lib-table-online is present
-                    - Than offline mode wiil set and used
-                - If both file are not present
-                    -Than copy fp-lib-table from source file
-        Otherwise the disable icon is set and feature is disabled.
+        This functions checks whether proper fp-lib-table* files are \
+        available or not. If not, then move appropriate files from \
+        supportFiles folder and set `self.online_flag` accordingly.
+
+        @params
+
+        @return
+            None
         """
+        remove = False
 
         if self.obj_appconfig.kicad_path is not None:
-            # -----------------------------------------------------
-            # fp-lib-table is not there than copy from supportFiles/
+
             if not os.path.exists(
-                self.obj_appconfig.kicad_path +
-                "/fp-lib-table"
+                self.obj_appconfig.kicad_path + "/fp-lib-table"
             ):
-                shutil.copy('../supportFiles/fp-lib-table',
-                            self.obj_appconfig.kicad_path + "/")
-            # -----------------------------------------------------
-            """checking online and offline both file's are avaliable.
-            if yes than remove offline file."""
-            if os.path.exists(self.obj_appconfig.kicad_path +
-                              "/fp-lib-table-offline") and os.path.exists(
-                    self.obj_appconfig.kicad_path + "/fp-lib-table-online"):
-                os.remove(self.obj_appconfig.kicad_path +
-                          "/fp-lib-table-offline")
-            # -----------------------------------------------------
-            # This ladder is used for checking which file is present.
-            if os.path.exists(self.obj_appconfig.kicad_path +
-                              "/fp-lib-table-offline"):
-                self.switchmode = QtGui.QAction(
-                    QtGui.QIcon('../../images/online.png'),
-                    '<b>Go Offline</b>', self)
-                self.online_flag = True
-
+                remove = True
             elif os.path.exists(self.obj_appconfig.kicad_path +
-                                "/fp-lib-table-online"):
-                self.switchmode = QtGui.QAction(
-                    QtGui.QIcon('../../images/offline.png'),
-                    '<b>Go Online</b>', self)
-                self.online_flag = False
-            else:
-                # if online and offline is not avaliable
-                shutil.copy('../supportFiles/fp-lib-table-online',
-                            self.obj_appconfig.kicad_path + "/")
+                                "/fp-lib-table-offline"):
                 if os.path.exists(self.obj_appconfig.kicad_path +
                                   "/fp-lib-table-online"):
-                    self.switchmode = QtGui.QAction(
-                        QtGui.QIcon('../../images/offline.png'),
-                        '<b>Go Online</b>', self)
+                    remove = True
+                    os.remove(self.obj_appconfig.kicad_path +
+                              "/fp-lib-table")
+                else:
+                    self.online_flag = True
+            else:
+                if not os.path.exists(self.obj_appconfig.kicad_path +
+                                      "/fp-lib-table-online"):
+                    remove = True
+                    os.remove(self.obj_appconfig.kicad_path +
+                              "/fp-lib-table")
+                else:
                     self.online_flag = False
-            # ----------------------------------------------------
+                        
+            if remove:
+                # Remove invalid files
+                if os.path.exists(
+                    self.obj_appconfig.kicad_path + "/fp-lib-table-offline"
+                ):
+                    os.remove(self.obj_appconfig.kicad_path +
+                              "/fp-lib-table-offline")
+
+                if os.path.exists(
+                    self.obj_appconfig.kicad_path + "/fp-lib-table-online"
+                ):
+                    os.remove(self.obj_appconfig.kicad_path +
+                              "/fp-lib-table-online")
+
+                # Restore original files
+                shutil.copy('../supportFiles/fp-lib-table-online',
+                            self.obj_appconfig.kicad_path + "/")
+                shutil.copy('../supportFiles/fp-lib-table',
+                            self.obj_appconfig.kicad_path + "/")
+
+                self.online_flag = False
         else:
-            # if path is not found
-            self.switchmode = QtGui.QAction(QtGui.QIcon(
-                '../../images/disable.png'),
-                '<b>Mode switching has been disabled. Relaunch ' +
-                'eSim to fix any config issues</b>', self)
+            self.online_flag = None
 
     def change_mode(self):
         """
-        This function is used for changing mode of operation for KiCad. \
-        There are three modes of operation :
+        - This function is used for changing mode of operation for KiCad. \
+        - There are three modes of operation :
             - online
             - offline
             - disable
 
-        It will check whether kicad config path is present or not.
-            - If path is available and none of the KiCad tools \
-              (associated with eSim) are open, then depending on \
-              online_flag, it will swap appropriate fp-lib-table files.
-            - If any of the KiCad tools (associated with eSim) is open, \
-              then ask user to close all these tools.
-            - And if path is not found, then disable this feature.
+        - If none of the KiCad tools (associated with eSim) are \
+          open, then validate this mode by calling the function \
+          `validate_mode` and depending on online_flag, swap \
+          appropriate fp-lib-table files.
+        - If any of the KiCad tools (associated with eSim) is open, \
+          then ask user to close all these tools.
+        - If `online_flag` is `None`, then disable this feature.
 
-        @paramas
+        @params
 
         @return
             None
         """
-        if self.obj_appconfig.kicad_path is not None:
-            try:
-                if not self.obj_kicad.check_open_schematic():
-                    if self.online_flag:
-                        os.rename(
-                            self.obj_appconfig.kicad_path + "/fp-lib-table",
-                            self.obj_appconfig.kicad_path +
-                            "/fp-lib-table-online"
-                        )
-                        os.rename(
-                            self.obj_appconfig.kicad_path +
-                            "/fp-lib-table-offline",
-                            self.obj_appconfig.kicad_path + "/fp-lib-table"
-                        )
-                        self.switchmode.setIcon(
-                            QtGui.QIcon('../../images/offline.png')
-                        )
-                        self.switchmode.setText('<b>Go Online</b>')
-                        self.online_flag = False
-                    else:
-                        os.rename(
-                            self.obj_appconfig.kicad_path + "/fp-lib-table",
-                            self.obj_appconfig.kicad_path +
-                            "/fp-lib-table-offline"
-                        )
-                        os.rename(
-                            self.obj_appconfig.kicad_path +
-                            "/fp-lib-table-online",
-                            self.obj_appconfig.kicad_path + "/fp-lib-table"
-                        )
-                        self.switchmode.setIcon(
-                            QtGui.QIcon('../../images/online.png')
-                        )
-                        self.switchmode.setText('<b>Go Offline</b>')
-                        self.online_flag = True
-                else:
-                    self.msg = QtGui.QErrorMessage()
-                    self.msg.setModal(True)
-                    self.msg.setWindowTitle("Error Message")
-                    self.msg.showMessage(
-                        'Please save and close all the Kicad ' +
-                        'windows first, then change the online-offline mode')
-                    self.msg.exec_()
+        if not self.obj_kicad.check_open_schematic():
+            self.validate_mode()
+            if self.online_flag is True:
+                os.rename(
+                    self.obj_appconfig.kicad_path + "/fp-lib-table",
+                    self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-online"
+                )
+                os.rename(
+                    self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-offline",
+                    self.obj_appconfig.kicad_path + "/fp-lib-table"
+                )
+                self.switchmode.setIcon(
+                    QtGui.QIcon('../../images/offline.png')
+                )
+                self.switchmode.setText('<b>Go Online</b>')
+                self.switchmode.setEnabled(True)
+                self.online_flag = False
 
-            except BaseException:
-                self.validate_mode()
+            elif self.online_flag is False:
+                os.rename(
+                    self.obj_appconfig.kicad_path + "/fp-lib-table",
+                    self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-offline"
+                )
+                os.rename(
+                    self.obj_appconfig.kicad_path +
+                    "/fp-lib-table-online",
+                    self.obj_appconfig.kicad_path + "/fp-lib-table"
+                )
+                self.switchmode.setIcon(
+                    QtGui.QIcon('../../images/online.png')
+                )
+                self.switchmode.setText('<b>Go Offline</b>')
+                self.switchmode.setEnabled(True)
+                self.online_flag = True
+
+            elif self.online_flag is None:
+                self.switchmode.setIcon(
+                    QtGui.QIcon('../../images/disable.png')
+                )
+                self.switchmode.setText('<b>Mode switching has been ' +
+                    'disabled. Default mode set to offline</b>.')
+                self.switchmode.setEnabled(False)
         else:
-            self.info_msg = QtGui.QMessageBox.critical(
-                self, 'Message', "Please make sure kicad_folder_file is " +
-                "present in supportFiles folder."
+            self.msg = QtGui.QErrorMessage()
+            self.msg.setWindowTitle("Error Message")
+            self.msg.setModal(True)
+            self.msg.showMessage(
+                'Please save and close all the Kicad ' +
+                'windows first, then change the mode'
             )
+            self.msg.exec_()
 
     def help_project(self):
         """
-- 
cgit 


From 453c2dab78f81046fcbd42034a86c4e759a0ff68 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Sun, 16 Feb 2020 22:56:59 +0530
Subject: workspace functionality

---
 src/configuration/Appconfig.py    | 24 ++++++++++++-----
 src/frontEnd/Application.py       | 34 ++++++++++++++++++++++--
 src/frontEnd/ProjectExplorer.py   |  8 +++---
 src/frontEnd/Workspace.py         | 54 ++++++++++++++++++++++++++++++++++++---
 src/projManagement/newProject.py  |  2 +-
 src/projManagement/openProject.py |  2 +-
 6 files changed, 106 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py
index 9958f819..dfe4363f 100644
--- a/src/configuration/Appconfig.py
+++ b/src/configuration/Appconfig.py
@@ -34,7 +34,16 @@ class Appconfig(QtGui.QWidget):
     """
 
     # Home directory
-    home = os.path.join(os.path.expanduser("~"), "eSim-Workspace")
+    try:
+        file = open(os.path.join(
+        	os.path.expanduser("~"), ".esim/workspace.txt"), 'r'
+        )
+        workspace_check, home = file.readline().split(' ', 1)
+        file.close()
+    except IOError:
+        home = os.path.join(os.path.expanduser("~"), "eSim-Workspace")
+        workspace_check = 0
+
     default_workspace = {"workspace": home}
     # Current Project detail
     current_project = {"ProjectName": None}
@@ -44,12 +53,15 @@ class Appconfig(QtGui.QWidget):
     workspace_text = "eSim stores your project in a folder called "
     workspace_text += "eSim-Workspace. You can choose a different "
     workspace_text += "workspace folder to use for this session."
+    
     procThread_list = []
-    proc_dict = {}
-    # holds the pids of all external windows corresponds to the current project
+    proc_dict = {}  # hold pids of all external windows of the current project
     dock_dict = {}  # holds all dockwidgets
-    dictPath = os.path.join(os.path.expanduser("~"), ".projectExplorer.txt")
-    noteArea = {}
+    dictPath = {"path": os.path.join(
+        default_workspace["workspace"], ".projectExplorer.txt")
+    }
+
+    noteArea = {"Note" : []}
 
     parser_esim = SafeConfigParser()
     parser_esim.read(
@@ -76,7 +88,7 @@ class Appconfig(QtGui.QWidget):
         print(str(e))
 
     try:
-        project_explorer = json.load(open(dictPath))
+        project_explorer = json.load(open(dictPath["path"]))
     except BaseException:
         project_explorer = {}
     process_obj = []
diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index cd40214b..1b8a18c5 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -103,6 +103,13 @@ class Application(QtGui.QMainWindow):
         self.closeproj.setShortcut('Ctrl+X')
         self.closeproj.triggered.connect(self.close_project)
 
+        self.wrkspce = QtGui.QAction(
+            QtGui.QIcon('../../images/workspace.ico'),
+            '<b>Change Workspace</b>', self
+        )
+        self.wrkspce.setShortcut('Ctrl+W')
+        self.wrkspce.triggered.connect(self.change_workspace)
+
         self.switchmode = None
         self.validate_mode()
         if self.online_flag == True:
@@ -135,6 +142,7 @@ class Application(QtGui.QMainWindow):
         self.topToolbar.addAction(self.newproj)
         self.topToolbar.addAction(self.openproj)
         self.topToolbar.addAction(self.closeproj)
+        self.topToolbar.addAction(self.wrkspce)
         self.topToolbar.addAction(self.switchmode)
         self.topToolbar.addAction(self.helpfile)
 
@@ -332,6 +340,15 @@ class Application(QtGui.QMainWindow):
                 os.path.basename(current_project) + ' is Closed.'
             )
 
+    def change_workspace(self):
+        """
+        This function call changes Workspace
+        """
+        print("Function : Change Workspace")
+        self.obj_workspace.returnWhetherClickedOrNot(self)
+        self.hide()
+        self.obj_workspace.show()
+
     def validate_mode(self):
         """
         This functions checks whether proper fp-lib-table* files are \
@@ -789,8 +806,21 @@ def main(args):
     appView = Application()
     appView.splash = splash
     appView.obj_workspace.returnWhetherClickedOrNot(appView)
-    appView.hide()
-    appView.obj_workspace.show()
+
+    try:
+        file = open(os.path.join(
+            os.path.expanduser("~"),".esim/workspace.txt"), 'r'
+        )
+        work = int(file.read(1))
+        file.close()
+    except IOError:
+        work = 0
+    if work is not 0:
+        appView.obj_workspace.defaultWorkspace()
+    else:
+        appView.hide()
+        appView.obj_workspace.show()
+
     sys.exit(app.exec_())
 
 
diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py
index 54f0148f..4462c584 100644
--- a/src/frontEnd/ProjectExplorer.py
+++ b/src/frontEnd/ProjectExplorer.py
@@ -200,7 +200,7 @@ class ProjectExplorer(QtGui.QWidget):
 
         del self.obj_appconfig.project_explorer[str(self.filePath)]
         json.dump(self.obj_appconfig.project_explorer,
-                  open(self.obj_appconfig.dictPath, 'w'))
+                  open(self.obj_appconfig.dictPath["path"], 'w'))
 
     def refreshProject(self):
         """
@@ -224,7 +224,7 @@ class ProjectExplorer(QtGui.QWidget):
 
         self.obj_appconfig.project_explorer[self.filePath] = filelistnew
         json.dump(self.obj_appconfig.project_explorer,
-                  open(self.obj_appconfig.dictPath, 'w'))
+                  open(self.obj_appconfig.dictPath["path"], 'w'))
 
     def renameProject(self):
         """
@@ -246,7 +246,7 @@ class ProjectExplorer(QtGui.QWidget):
         )
         if ok and newBaseFileName:
             print(newBaseFileName)
-            print("==================")
+            print("=================")
             newBaseFileName = str(newBaseFileName)
 
             i = -1
@@ -314,7 +314,7 @@ class ProjectExplorer(QtGui.QWidget):
 
                     # save project_explorer dictionary on disk
                     json.dump(self.obj_appconfig.project_explorer, open(
-                        self.obj_appconfig.dictPath, 'w'))
+                        self.obj_appconfig.dictPath["path"], 'w'))
 
                     # recreate project explorer tree
                     self.treewidget.clear()
diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py
index 29be09fc..09092a69 100644
--- a/src/frontEnd/Workspace.py
+++ b/src/frontEnd/Workspace.py
@@ -20,6 +20,7 @@ from PyQt4 import QtCore, QtGui
 from configuration.Appconfig import Appconfig
 import time
 import os
+import json
 
 
 class Workspace(QtGui.QWidget):
@@ -62,13 +63,19 @@ class Workspace(QtGui.QWidget):
         self.okbtn.clicked.connect(self.createWorkspace)
         self.cancelbtn = QtGui.QPushButton('Cancel')
         self.cancelbtn.clicked.connect(self.defaultWorkspace)
+
+        #Checkbox
+        self.chkbox = QtGui.QCheckBox('Set Default', self)
+        self.chkbox.setCheckState(int(self.obj_appconfig.workspace_check))
+
         # Layout
         self.grid.addWidget(self.note, 0, 0, 1, 15)
         self.grid.addWidget(self.workspace_label, 2, 1)
         self.grid.addWidget(self.workspace_loc, 2, 2, 2, 12)
         self.grid.addWidget(self.browsebtn, 2, 14)
-        self.grid.addWidget(self.okbtn, 4, 13)
-        self.grid.addWidget(self.cancelbtn, 4, 14)
+        self.grid.addWidget(self.chkbox, 4, 2)
+        self.grid.addWidget(self.okbtn, 5, 13)
+        self.grid.addWidget(self.cancelbtn, 5, 14)
 
         self.setGeometry(QtCore.QRect(500, 250, 400, 400))
         self.setMaximumSize(4000, 200)
@@ -77,7 +84,6 @@ class Workspace(QtGui.QWidget):
         self.note.setReadOnly(True)
         self.setWindowIcon(QtGui.QIcon('../../images/logo.png'))
         self.setLayout(self.grid)
-        self.show()
 
     def defaultWorkspace(self):
         print("Default workspace selected : " +
@@ -87,6 +93,13 @@ class Workspace(QtGui.QWidget):
             'Default workspace selected : ' +
             self.obj_appconfig.default_workspace["workspace"])
         self.close()
+
+        var_appView.obj_Mainview.obj_projectExplorer.treewidget.clear()
+        for parent, children in self.obj_appconfig.project_explorer.items():
+            var_appView.obj_Mainview.obj_projectExplorer.addTreeNode(
+                parent, children
+            )
+
         var_appView.show()
         time.sleep(1)
         var_appView.splash.close()
@@ -102,6 +115,17 @@ class Workspace(QtGui.QWidget):
 
     def createWorkspace(self):
         print("Function : Create workspace")
+
+        self.obj_appconfig.workspace_check = self.chkbox.checkState()
+        print(self.workspace_loc.text())
+        file = open(os.path.join(
+            os.path.expanduser("~"), ".esim/workspace.txt"), 'w'
+        )
+        file.writelines(str(self.obj_appconfig.workspace_check) +
+            " " + self.workspace_loc.text()
+        )
+        file.close()
+
         self.create_workspace = str(self.workspace_loc.text())
         self.obj_appconfig.print_info('Workspace : ' + self.create_workspace)
         # Checking if Workspace already exist or not
@@ -114,6 +138,27 @@ class Workspace(QtGui.QWidget):
                 = self.create_workspace
         self.imp_var = 1
         self.close()
+
+        self.obj_appconfig.dictPath["path"] = os.path.join(
+            self.obj_appconfig.default_workspace["workspace"],
+            ".projectExplorer.txt"
+        )
+
+        try:
+            self.obj_appconfig.project_explorer = json.load(
+                open(self.obj_appconfig.dictPath["path"])
+            )
+        except:
+            self.obj_appconfig.project_explorer = {}
+
+        Appconfig.project_explorer = self.obj_appconfig.project_explorer        
+
+        var_appView.obj_Mainview.obj_projectExplorer.treewidget.clear()
+        for parent, children in self.obj_appconfig.project_explorer.items():
+            var_appView.obj_Mainview.obj_projectExplorer.addTreeNode(
+                parent, children
+            )
+
         var_appView.show()
         time.sleep(1)
         var_appView.splash.close()
@@ -121,5 +166,6 @@ class Workspace(QtGui.QWidget):
     def browseLocation(self):
         print("Function : Browse Location")
         self.workspace_directory = QtGui.QFileDialog.getExistingDirectory(
-            self, "Browse Location", os.path.expanduser("~"))
+            self, "Browse Location", os.path.expanduser("~")
+        )
         self.workspace_loc.setText(self.workspace_directory)
diff --git a/src/projManagement/newProject.py b/src/projManagement/newProject.py
index b04dbd10..8382883d 100644
--- a/src/projManagement/newProject.py
+++ b/src/projManagement/newProject.py
@@ -111,7 +111,7 @@ class NewProjectInfo(QtGui.QWidget):
 
             json.dump(
                 self.obj_appconfig.project_explorer, open(
-                    self.obj_appconfig.dictPath, 'w'))
+                    self.obj_appconfig.dictPath["path"], 'w'))
             return self.projDir, newprojlist
 
         elif self.reply == "CHECKEXIST":
diff --git a/src/projManagement/openProject.py b/src/projManagement/openProject.py
index 504bb473..507105ab 100644
--- a/src/projManagement/openProject.py
+++ b/src/projManagement/openProject.py
@@ -63,7 +63,7 @@ class OpenProjectInfo(QtGui.QWidget):
             self.obj_Appconfig.project_explorer[dirs] = filelist
             json.dump(
                 self.obj_Appconfig.project_explorer, open(
-                    self.obj_Appconfig.dictPath, 'w'))
+                    self.obj_Appconfig.dictPath["path"], 'w'))
             self.obj_Appconfig.print_info('Open Project called')
             self.obj_Appconfig.print_info('Current Project is ' + self.projDir)
             return dirs, filelist
-- 
cgit 


From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 .../2bit_upcounter/2bit_upcounter-cache.lib        |   62 -
 .../2bit_upcounter/2bit_upcounter.cir              |   13 -
 .../2bit_upcounter/2bit_upcounter.cir.out          |   20 -
 .../2bit_upcounter/2bit_upcounter.pro              |   45 -
 .../2bit_upcounter/2bit_upcounter.sch              |  151 -
 .../2bit_upcounter/2bit_upcounter.sub              |   14 -
 .../2bit_upcounter_Previous_Values.xml             |    1 -
 src/SubcircuitLibrary/2bit_upcounter/analysis      |    1 -
 src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib    |   77 -
 src/SubcircuitLibrary/2bitmul/2bitmul.cir          |   17 -
 src/SubcircuitLibrary/2bitmul/2bitmul.cir.out      |   31 -
 src/SubcircuitLibrary/2bitmul/2bitmul.pro          |   74 -
 src/SubcircuitLibrary/2bitmul/2bitmul.sch          |  284 --
 src/SubcircuitLibrary/2bitmul/2bitmul.sub          |   25 -
 .../2bitmul/2bitmul_Previous_Values.xml            |    1 -
 src/SubcircuitLibrary/2bitmul/analysis             |    1 -
 src/SubcircuitLibrary/2bitmul/half_adder-cache.lib |   63 -
 src/SubcircuitLibrary/2bitmul/half_adder.cir       |   11 -
 src/SubcircuitLibrary/2bitmul/half_adder.cir.out   |   20 -
 src/SubcircuitLibrary/2bitmul/half_adder.pro       |   69 -
 src/SubcircuitLibrary/2bitmul/half_adder.sch       |  152 -
 src/SubcircuitLibrary/2bitmul/half_adder.sub       |   14 -
 .../2bitmul/half_adder_Previous_Values.xml         |    1 -
 src/SubcircuitLibrary/3_and/3_and-cache.lib        |   61 -
 src/SubcircuitLibrary/3_and/3_and.cir              |   13 -
 src/SubcircuitLibrary/3_and/3_and.cir.out          |   20 -
 src/SubcircuitLibrary/3_and/3_and.pro              |   44 -
 src/SubcircuitLibrary/3_and/3_and.sch              |  130 -
 src/SubcircuitLibrary/3_and/3_and.sub              |   14 -
 .../3_and/3_and_Previous_Values.xml                |    1 -
 src/SubcircuitLibrary/3_and/analysis               |    1 -
 src/SubcircuitLibrary/4002/4002-cache.lib          |   82 -
 src/SubcircuitLibrary/4002/4002.cir                |   17 -
 src/SubcircuitLibrary/4002/4002.cir.out            |   36 -
 src/SubcircuitLibrary/4002/4002.pro                |   44 -
 src/SubcircuitLibrary/4002/4002.sch                |  315 --
 src/SubcircuitLibrary/4002/4002.sub                |   30 -
 .../4002/4002_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4002/analysis                |    1 -
 src/SubcircuitLibrary/4012/4012-cache.lib          |   75 -
 src/SubcircuitLibrary/4012/4012.cir                |   19 -
 src/SubcircuitLibrary/4012/4012.cir.out            |   44 -
 src/SubcircuitLibrary/4012/4012.pro                |   44 -
 src/SubcircuitLibrary/4012/4012.sch                |  342 --
 src/SubcircuitLibrary/4012/4012.sub                |   38 -
 .../4012/4012_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4012/analysis                |    1 -
 src/SubcircuitLibrary/4017/4017-cache.lib          |   79 -
 src/SubcircuitLibrary/4017/4017.cir                |   26 -
 src/SubcircuitLibrary/4017/4017.cir.out            |   72 -
 src/SubcircuitLibrary/4017/4017.pro                |   72 -
 src/SubcircuitLibrary/4017/4017.sch                |  580 ----
 src/SubcircuitLibrary/4017/4017.sub                |   66 -
 .../4017/4017_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4017/D.lib                   |   11 -
 src/SubcircuitLibrary/4017/analysis                |    1 -
 src/SubcircuitLibrary/4023/3_and-cache.lib         |   61 -
 src/SubcircuitLibrary/4023/3_and.cir               |   13 -
 src/SubcircuitLibrary/4023/3_and.cir.out           |   20 -
 src/SubcircuitLibrary/4023/3_and.pro               |   44 -
 src/SubcircuitLibrary/4023/3_and.sch               |  130 -
 src/SubcircuitLibrary/4023/3_and.sub               |   14 -
 .../4023/3_and_Previous_Values.xml                 |    1 -
 src/SubcircuitLibrary/4023/4023-cache.lib          |   76 -
 src/SubcircuitLibrary/4023/4023.cir                |   17 -
 src/SubcircuitLibrary/4023/4023.cir.out            |   28 -
 src/SubcircuitLibrary/4023/4023.pro                |   44 -
 src/SubcircuitLibrary/4023/4023.sch                |  309 --
 src/SubcircuitLibrary/4023/4023.sub                |   22 -
 .../4023/4023_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4023/analysis                |    1 -
 src/SubcircuitLibrary/4025/4025-cache.lib          |   82 -
 src/SubcircuitLibrary/4025/4025.cir                |   17 -
 src/SubcircuitLibrary/4025/4025.cir.out            |   36 -
 src/SubcircuitLibrary/4025/4025.pro                |   45 -
 src/SubcircuitLibrary/4025/4025.sch                |  302 --
 src/SubcircuitLibrary/4025/4025.sub                |   30 -
 .../4025/4025_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4025/analysis                |    1 -
 src/SubcircuitLibrary/4028/4028-cache.lib          |   94 -
 src/SubcircuitLibrary/4028/4028.cir                |   32 -
 src/SubcircuitLibrary/4028/4028.cir.out            |   96 -
 src/SubcircuitLibrary/4028/4028.pro                |   43 -
 src/SubcircuitLibrary/4028/4028.sch                |  628 ----
 src/SubcircuitLibrary/4028/4028.sub                |   90 -
 .../4028/4028_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4028/analysis                |    1 -
 src/SubcircuitLibrary/4072/4072-cache.lib          |   63 -
 src/SubcircuitLibrary/4072/4072.cir                |   17 -
 src/SubcircuitLibrary/4072/4072.cir.out            |   36 -
 src/SubcircuitLibrary/4072/4072.pro                |   45 -
 src/SubcircuitLibrary/4072/4072.sch                |  334 --
 src/SubcircuitLibrary/4072/4072.sub                |   30 -
 .../4072/4072_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4072/analysis                |    1 -
 src/SubcircuitLibrary/4073/3_and-cache.lib         |   61 -
 src/SubcircuitLibrary/4073/3_and.cir               |   13 -
 src/SubcircuitLibrary/4073/3_and.cir.out           |   20 -
 src/SubcircuitLibrary/4073/3_and.pro               |   44 -
 src/SubcircuitLibrary/4073/3_and.sch               |  130 -
 src/SubcircuitLibrary/4073/3_and.sub               |   14 -
 .../4073/3_and_Previous_Values.xml                 |    1 -
 src/SubcircuitLibrary/4073/4073-cache.lib          |   62 -
 src/SubcircuitLibrary/4073/4073.cir                |   14 -
 src/SubcircuitLibrary/4073/4073.cir.out            |   16 -
 src/SubcircuitLibrary/4073/4073.pro                |   43 -
 src/SubcircuitLibrary/4073/4073.sch                |  263 --
 src/SubcircuitLibrary/4073/4073.sub                |   10 -
 .../4073/4073_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4073/analysis                |    1 -
 src/SubcircuitLibrary/4_OR/4_OR-cache.lib          |   63 -
 src/SubcircuitLibrary/4_OR/4_OR.cir                |   14 -
 src/SubcircuitLibrary/4_OR/4_OR.cir.out            |   24 -
 src/SubcircuitLibrary/4_OR/4_OR.pro                |   45 -
 src/SubcircuitLibrary/4_OR/4_OR.sch                |  150 -
 src/SubcircuitLibrary/4_OR/4_OR.sub                |   18 -
 .../4_OR/4_OR_Previous_Values.xml                  |    1 -
 src/SubcircuitLibrary/4_OR/analysis                |    1 -
 src/SubcircuitLibrary/4_and/3_and-cache.lib        |   61 -
 src/SubcircuitLibrary/4_and/3_and.cir              |   13 -
 src/SubcircuitLibrary/4_and/3_and.cir.out          |   20 -
 src/SubcircuitLibrary/4_and/3_and.pro              |   44 -
 src/SubcircuitLibrary/4_and/3_and.sch              |  130 -
 src/SubcircuitLibrary/4_and/3_and.sub              |   14 -
 .../4_and/3_and_Previous_Values.xml                |    1 -
 src/SubcircuitLibrary/4_and/4_and-cache.lib        |   79 -
 src/SubcircuitLibrary/4_and/4_and-rescue.lib       |   22 -
 src/SubcircuitLibrary/4_and/4_and.cir              |   13 -
 src/SubcircuitLibrary/4_and/4_and.cir.out          |   18 -
 src/SubcircuitLibrary/4_and/4_and.pro              |   58 -
 src/SubcircuitLibrary/4_and/4_and.sch              |  151 -
 src/SubcircuitLibrary/4_and/4_and.sub              |   12 -
 .../4_and/4_and_Previous_Values.xml                |    1 -
 src/SubcircuitLibrary/4_and/analysis               |    1 -
 src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib     |   61 -
 src/SubcircuitLibrary/4_bit_FA/3_and.cir           |   13 -
 src/SubcircuitLibrary/4_bit_FA/3_and.cir.out       |   20 -
 src/SubcircuitLibrary/4_bit_FA/3_and.pro           |   58 -
 src/SubcircuitLibrary/4_bit_FA/3_and.sch           |  121 -
 src/SubcircuitLibrary/4_bit_FA/3_and.sub           |   14 -
 .../4_bit_FA/3_and_Previous_Values.xml             |    1 -
 src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib      |   63 -
 src/SubcircuitLibrary/4_bit_FA/4_OR.cir            |   14 -
 src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out        |   24 -
 src/SubcircuitLibrary/4_bit_FA/4_OR.pro            |   45 -
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diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib
deleted file mode 100644
index b3857f54..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib
+++ /dev/null
@@ -1,62 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_dff
-#
-DEF d_dff U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_dff" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 350 450 -350 -400 0 1 0 N
-X Din 1 -550 350 200 R 50 50 1 1 I
-X Clk 2 -550 -300 200 R 50 50 1 1 I C
-X Set 3 0 650 200 D 50 50 1 1 I
-X Reset 4 0 -600 200 U 50 50 1 1 I
-X Dout 5 550 350 200 L 50 50 1 1 O
-X Ndout 6 550 -300 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir
deleted file mode 100644
index d5d8760a..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:44:38 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U2-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ d_dff		
-U3  Net-_U3-Pad1_ Net-_U2-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U3-Pad1_ d_dff		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out
deleted file mode 100644
index 4232f26a..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir
-
-* u2  net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff
-* u3  net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2
-a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro
deleted file mode 100644
index 7fc2f37d..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=Sat Jun 22 11:40:56 2019
-version=1
-last_client=eeschema
-[general]
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-[pcbnew]
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-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch
deleted file mode 100644
index 45c6e1de..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch
+++ /dev/null
@@ -1,151 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:2bit-Up_counter-cache
-EELAYER 25 0
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-F 2 "" H 2350 3700 60  0000 C CNN
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-L PORT U1
-U 2 1 5D0DC6F4
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-$Comp
-L PORT U1
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-	3    7050 2600
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5D0DC6F6
-P 7300 3050
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub
deleted file mode 100644
index f888aa71..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 2bit_upcounter
-.subckt 2bit_upcounter net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir
-* u2  net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff
-* u3  net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff
-a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2
-a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 2bit_upcounter
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml
deleted file mode 100644
index 2daa4f78..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bit_upcounter/analysis b/src/SubcircuitLibrary/2bit_upcounter/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/2bit_upcounter/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
deleted file mode 100644
index e16831e4..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
+++ /dev/null
@@ -1,77 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
deleted file mode 100644
index 0f4deb6c..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
-U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
-U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
-X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
-X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
deleted file mode 100644
index 71766bd8..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
+++ /dev/null
@@ -1,31 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
deleted file mode 100644
index eafbfb80..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=03/07/19 09:55:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
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-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
-[eeschema/libraries]
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-LibName2=memory
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-LibName4=microcontrollers
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-LibName13=digital-audio
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-LibName16=cypress
-LibName17=siliconi
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-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
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-LibName34=eSim_Power
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-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
deleted file mode 100644
index 0ba61912..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch
+++ /dev/null
@@ -1,284 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
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-LIBS:digital-audio
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-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:2bitmul-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
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-	6450 3400 6450 3650
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-$EndComp
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-	2    7900 850 
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-$EndComp
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diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
deleted file mode 100644
index e77495a6..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub
+++ /dev/null
@@ -1,25 +0,0 @@
-* Subcircuit 2bitmul
-.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 2bitmul
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml
deleted file mode 100644
index 8a55af97..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/analysis b/src/SubcircuitLibrary/2bitmul/analysis
deleted file mode 100644
index 660a46cc..00000000
--- a/src/SubcircuitLibrary/2bitmul/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.cir
+++ /dev/null
@@ -1,11 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2  1 4 3 d_xor		
-U3  1 4 2 d_and		
-U1  1 4 3 2 PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.pro b/src/SubcircuitLibrary/2bitmul/half_adder.pro
deleted file mode 100644
index 695ae0f6..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 11:27:22 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sch b/src/SubcircuitLibrary/2bitmul/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.sch
+++ /dev/null
@@ -1,152 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
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-	1    5650 3050
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-$EndComp
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-U 1 1 558A94D5
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-F 3 "" H 5700 3800 60  0000 C CNN
-	1    5700 3800
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-U 1 1 558A94F6
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-F 1 "PORT" H 4150 3000 30  0000 C CNN
-F 2 "" H 4150 3000 60  0000 C CNN
-F 3 "" H 4150 3000 60  0000 C CNN
-	1    4150 3000
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-$EndComp
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-L PORT U1
-U 2 1 558A9543
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-F 3 "" H 4150 3450 60  0000 C CNN
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-U 3 1 558A9573
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-F 1 "PORT" H 6650 3000 30  0000 C CNN
-F 2 "" H 6650 3000 60  0000 C CNN
-F 3 "" H 6650 3000 60  0000 C CNN
-	3    6650 3000
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-U 4 1 558A9606
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-F 2 "" H 6700 3750 60  0000 C CNN
-F 3 "" H 6700 3750 60  0000 C CNN
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-Wire Wire Line
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-Text Notes 4550 2950 0    60   ~ 0
-IN1\n\n
-Text Notes 4600 3150 0    60   ~ 0
-IN2
-Text Notes 6200 2950 0    60   ~ 0
-SUM\n
-Text Notes 6200 3650 0    60   ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml
deleted file mode 100644
index b915f0da..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/3_and/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/3_and/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/3_and/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/3_and/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/3_and/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/3_and/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/3_and/analysis b/src/SubcircuitLibrary/3_and/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/3_and/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib
deleted file mode 100644
index 677411a9..00000000
--- a/src/SubcircuitLibrary/4002/4002-cache.lib
+++ /dev/null
@@ -1,82 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir
deleted file mode 100644
index 5d5c1ed7..00000000
--- a/src/SubcircuitLibrary/4002/4002.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or		
-U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or		
-U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor		
-
-.end
diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out
deleted file mode 100644
index e9cc6862..00000000
--- a/src/SubcircuitLibrary/4002/4002.cir.out
+++ /dev/null
@@ -1,36 +0,0 @@
-* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
-
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro
deleted file mode 100644
index 225ef82a..00000000
--- a/src/SubcircuitLibrary/4002/4002.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 09:35:41
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
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-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
-LibName11=power
diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch
deleted file mode 100644
index 545f46fe..00000000
--- a/src/SubcircuitLibrary/4002/4002.sch
+++ /dev/null
@@ -1,315 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-$Comp
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-	5550 4600 5550 4300
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-	5550 4300 5700 4300
-$Comp
-L PORT U1
-U 9 1 5CEE4EEF
-P 4000 4000
-F 0 "U1" H 4050 4100 30  0000 C CNN
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-F 2 "" H 4000 4000 60  0000 C CNN
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-	9    4000 4000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CEE4EF5
-P 4050 4250
-F 0 "U1" H 4100 4350 30  0000 C CNN
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-	11   4050 4450
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-$EndComp
-$Comp
-L PORT U1
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-	12   4050 4750
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-$EndComp
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-	6    6300 5350
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-$EndComp
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-	8    6300 5800
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-	14   6300 6000
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diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub
deleted file mode 100644
index b9726625..00000000
--- a/src/SubcircuitLibrary/4002/4002.sub
+++ /dev/null
@@ -1,30 +0,0 @@
-* Subcircuit 4002
-.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4002
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
deleted file mode 100644
index 75360e5e..00000000
--- a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4002/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/4012-cache.lib b/src/SubcircuitLibrary/4012/4012-cache.lib
deleted file mode 100644
index ea0d2d70..00000000
--- a/src/SubcircuitLibrary/4012/4012-cache.lib
+++ /dev/null
@@ -1,75 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
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-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
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-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4012/4012.cir b/src/SubcircuitLibrary/4012/4012.cir
deleted file mode 100644
index a88a9da4..00000000
--- a/src/SubcircuitLibrary/4012/4012.cir
+++ /dev/null
@@ -1,19 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U8  Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter		
-U9  Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and		
-U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and		
-U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and		
-U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and		
-U3  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and		
-U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and		
-
-.end
diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out
deleted file mode 100644
index c43dda8c..00000000
--- a/src/SubcircuitLibrary/4012/4012.cir.out
+++ /dev/null
@@ -1,44 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
-
-* u8  net-_u6-pad3_ net-_u1-pad1_ d_inverter
-* u9  net-_u7-pad3_ net-_u1-pad13_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
-* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
-a1 net-_u6-pad3_ net-_u1-pad1_ u8
-a2 net-_u7-pad3_ net-_u1-pad13_ u9
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
-a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
-a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
-a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4012/4012.pro b/src/SubcircuitLibrary/4012/4012.pro
deleted file mode 100644
index 0f76f4bb..00000000
--- a/src/SubcircuitLibrary/4012/4012.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=06/01/19 13:10:32
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_User
-LibName11=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4012/4012.sch b/src/SubcircuitLibrary/4012/4012.sch
deleted file mode 100644
index b3320871..00000000
--- a/src/SubcircuitLibrary/4012/4012.sch
+++ /dev/null
@@ -1,342 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:4012-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
-	3350 2600 2550 2600
-Wire Wire Line
-	3350 2700 3150 2700
-Wire Wire Line
-	3150 2700 3150 2850
-Wire Wire Line
-	3150 2850 2550 2850
-Wire Wire Line
-	3350 3200 3150 3200
-Wire Wire Line
-	3150 3200 3150 3100
-Wire Wire Line
-	3150 3100 2550 3100
-Wire Wire Line
-	3350 3300 2550 3300
-Wire Wire Line
-	5200 2950 5500 2950
-$Comp
-L d_inverter U8
-U 1 1 5CEE55AB
-P 5800 2950
-F 0 "U8" H 5800 2850 60  0000 C CNN
-F 1 "d_inverter" H 5800 3100 60  0000 C CNN
-F 2 "" H 5850 2900 60  0000 C CNN
-F 3 "" H 5850 2900 60  0000 C CNN
-	1    5800 2950
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6100 2950 6500 2950
-Wire Wire Line
-	3400 3950 2600 3950
-Wire Wire Line
-	3400 4050 3200 4050
-Wire Wire Line
-	3200 4050 3200 4200
-Wire Wire Line
-	3200 4200 2600 4200
-Wire Wire Line
-	3400 4550 3200 4550
-Wire Wire Line
-	3200 4550 3200 4450
-Wire Wire Line
-	3200 4450 2600 4450
-Wire Wire Line
-	3400 4650 2600 4650
-Wire Wire Line
-	5250 4300 5550 4300
-$Comp
-L d_inverter U9
-U 1 1 5CEE5715
-P 5850 4300
-F 0 "U9" H 5850 4200 60  0000 C CNN
-F 1 "d_inverter" H 5850 4450 60  0000 C CNN
-F 2 "" H 5900 4250 60  0000 C CNN
-F 3 "" H 5900 4250 60  0000 C CNN
-	1    5850 4300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6150 4300 6550 4300
-$Comp
-L PORT U1
-U 2 1 5CEE57D6
-P 2300 2600
-F 0 "U1" H 2350 2700 30  0000 C CNN
-F 1 "PORT" H 2300 2600 30  0000 C CNN
-F 2 "" H 2300 2600 60  0000 C CNN
-F 3 "" H 2300 2600 60  0000 C CNN
-	2    2300 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CEE587B
-P 2300 2850
-F 0 "U1" H 2350 2950 30  0000 C CNN
-F 1 "PORT" H 2300 2850 30  0000 C CNN
-F 2 "" H 2300 2850 60  0000 C CNN
-F 3 "" H 2300 2850 60  0000 C CNN
-	3    2300 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CEE58AF
-P 2300 3100
-F 0 "U1" H 2350 3200 30  0000 C CNN
-F 1 "PORT" H 2300 3100 30  0000 C CNN
-F 2 "" H 2300 3100 60  0000 C CNN
-F 3 "" H 2300 3100 60  0000 C CNN
-	4    2300 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CEE58E6
-P 6800 4300
-F 0 "U1" H 6850 4400 30  0000 C CNN
-F 1 "PORT" H 6800 4300 30  0000 C CNN
-F 2 "" H 6800 4300 60  0000 C CNN
-F 3 "" H 6800 4300 60  0000 C CNN
-	13   6800 4300
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CEE5922
-P 2300 3300
-AR Path="/5CEE58E6" Ref="U1"  Part="1" 
-AR Path="/5CEE5922" Ref="U1"  Part="5" 
-F 0 "U1" H 2350 3400 30  0000 C CNN
-F 1 "PORT" H 2300 3300 30  0000 C CNN
-F 2 "" H 2300 3300 60  0000 C CNN
-F 3 "" H 2300 3300 60  0000 C CNN
-	5    2300 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CEE596F
-P 2350 3950
-AR Path="/5CEE5922" Ref="U1"  Part="5" 
-AR Path="/5CEE596F" Ref="U1"  Part="9" 
-F 0 "U1" H 2400 4050 30  0000 C CNN
-F 1 "PORT" H 2350 3950 30  0000 C CNN
-F 2 "" H 2350 3950 60  0000 C CNN
-F 3 "" H 2350 3950 60  0000 C CNN
-	9    2350 3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CEE59AF
-P 2350 4200
-AR Path="/5CEE596F" Ref="U1"  Part="6" 
-AR Path="/5CEE59AF" Ref="U1"  Part="10" 
-F 0 "U1" H 2400 4300 30  0000 C CNN
-F 1 "PORT" H 2350 4200 30  0000 C CNN
-F 2 "" H 2350 4200 60  0000 C CNN
-F 3 "" H 2350 4200 60  0000 C CNN
-	10   2350 4200
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CEE59F6
-P 2350 4450
-AR Path="/5CEE59AF" Ref="U1"  Part="7" 
-AR Path="/5CEE59F6" Ref="U1"  Part="11" 
-F 0 "U1" H 2400 4550 30  0000 C CNN
-F 1 "PORT" H 2350 4450 30  0000 C CNN
-F 2 "" H 2350 4450 60  0000 C CNN
-F 3 "" H 2350 4450 60  0000 C CNN
-	11   2350 4450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CEE5A6A
-P 2350 4650
-AR Path="/5CEE59F6" Ref="U1"  Part="8" 
-AR Path="/5CEE5A6A" Ref="U1"  Part="12" 
-F 0 "U1" H 2400 4750 30  0000 C CNN
-F 1 "PORT" H 2350 4650 30  0000 C CNN
-F 2 "" H 2350 4650 60  0000 C CNN
-F 3 "" H 2350 4650 60  0000 C CNN
-	12   2350 4650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CEE5BF8
-P 6750 2950
-AR Path="/5CEE5A6A" Ref="U1"  Part="9" 
-AR Path="/5CEE5BF8" Ref="U1"  Part="1" 
-F 0 "U1" H 6800 3050 30  0000 C CNN
-F 1 "PORT" H 6750 2950 30  0000 C CNN
-F 2 "" H 6750 2950 60  0000 C CNN
-F 3 "" H 6750 2950 60  0000 C CNN
-	1    6750 2950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CEE5C72
-P 7850 1450
-F 0 "U1" H 7900 1550 30  0000 C CNN
-F 1 "PORT" H 7850 1450 30  0000 C CNN
-F 2 "" H 7850 1450 60  0000 C CNN
-F 3 "" H 7850 1450 60  0000 C CNN
-	6    7850 1450
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CEE5D23
-P 7850 1700
-F 0 "U1" H 7900 1800 30  0000 C CNN
-F 1 "PORT" H 7850 1700 30  0000 C CNN
-F 2 "" H 7850 1700 60  0000 C CNN
-F 3 "" H 7850 1700 60  0000 C CNN
-	7    7850 1700
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CEE5D75
-P 7850 1950
-F 0 "U1" H 7900 2050 30  0000 C CNN
-F 1 "PORT" H 7850 1950 30  0000 C CNN
-F 2 "" H 7850 1950 60  0000 C CNN
-F 3 "" H 7850 1950 60  0000 C CNN
-	14   7850 1950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CEE5DCA
-P 7850 2250
-F 0 "U1" H 7900 2350 30  0000 C CNN
-F 1 "PORT" H 7850 2250 30  0000 C CNN
-F 2 "" H 7850 2250 60  0000 C CNN
-F 3 "" H 7850 2250 60  0000 C CNN
-	8    7850 2250
-	-1   0    0    1   
-$EndComp
-NoConn ~ 7600 1450
-NoConn ~ 7600 1700
-NoConn ~ 7600 1950
-NoConn ~ 7600 2250
-$Comp
-L d_and U4
-U 1 1 5CEE56F6
-P 3850 4050
-F 0 "U4" H 3850 4050 60  0000 C CNN
-F 1 "d_and" H 3900 4150 60  0000 C CNN
-F 2 "" H 3850 4050 60  0000 C CNN
-F 3 "" H 3850 4050 60  0000 C CNN
-	1    3850 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U5
-U 1 1 5CEE56FC
-P 3850 4650
-F 0 "U5" H 3850 4650 60  0000 C CNN
-F 1 "d_and" H 3900 4750 60  0000 C CNN
-F 2 "" H 3850 4650 60  0000 C CNN
-F 3 "" H 3850 4650 60  0000 C CNN
-	1    3850 4650
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4350 4600 4300 4600
-Wire Wire Line
-	4350 4350 4350 4600
-Wire Wire Line
-	4350 4000 4350 4250
-Wire Wire Line
-	4300 4000 4350 4000
-$Comp
-L d_and U7
-U 1 1 5CEE5702
-P 4800 4350
-F 0 "U7" H 4800 4350 60  0000 C CNN
-F 1 "d_and" H 4850 4450 60  0000 C CNN
-F 2 "" H 4800 4350 60  0000 C CNN
-F 3 "" H 4800 4350 60  0000 C CNN
-	1    4800 4350
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4250 2650 4300 2650
-Wire Wire Line
-	4300 3250 4250 3250
-Wire Wire Line
-	4300 2650 4300 2900
-Wire Wire Line
-	4300 3000 4300 3250
-$Comp
-L d_and U6
-U 1 1 5CEE5432
-P 4750 3000
-F 0 "U6" H 4750 3000 60  0000 C CNN
-F 1 "d_and" H 4800 3100 60  0000 C CNN
-F 2 "" H 4750 3000 60  0000 C CNN
-F 3 "" H 4750 3000 60  0000 C CNN
-	1    4750 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5CEE540C
-P 3800 3300
-F 0 "U3" H 3800 3300 60  0000 C CNN
-F 1 "d_and" H 3850 3400 60  0000 C CNN
-F 2 "" H 3800 3300 60  0000 C CNN
-F 3 "" H 3800 3300 60  0000 C CNN
-	1    3800 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5CEE53DC
-P 3800 2700
-F 0 "U2" H 3800 2700 60  0000 C CNN
-F 1 "d_and" H 3850 2800 60  0000 C CNN
-F 2 "" H 3800 2700 60  0000 C CNN
-F 3 "" H 3800 2700 60  0000 C CNN
-	1    3800 2700
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4012/4012.sub b/src/SubcircuitLibrary/4012/4012.sub
deleted file mode 100644
index 65263f03..00000000
--- a/src/SubcircuitLibrary/4012/4012.sub
+++ /dev/null
@@ -1,38 +0,0 @@
-* Subcircuit 4012
-.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
-* u8  net-_u6-pad3_ net-_u1-pad1_ d_inverter
-* u9  net-_u7-pad3_ net-_u1-pad13_ d_inverter
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
-* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
-a1 net-_u6-pad3_ net-_u1-pad1_ u8
-a2 net-_u7-pad3_ net-_u1-pad13_ u9
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
-a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
-a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
-a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4012
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml
deleted file mode 100644
index 4e7e73b2..00000000
--- a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4012/analysis b/src/SubcircuitLibrary/4012/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4012/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib
deleted file mode 100644
index efa6746f..00000000
--- a/src/SubcircuitLibrary/4017/4017-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_dff
-#
-DEF d_dff U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_dff" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 350 450 -350 -400 0 1 0 N
-X Din 1 -550 350 200 R 50 50 1 1 I
-X Clk 2 -550 -300 200 R 50 50 1 1 I C
-X Set 3 0 650 200 D 50 50 1 1 I
-X Reset 4 0 -600 200 U 50 50 1 1 I
-X Dout 5 550 350 200 L 50 50 1 1 O
-X Ndout 6 550 -300 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir
deleted file mode 100644
index 67ac9971..00000000
--- a/src/SubcircuitLibrary/4017/4017.cir
+++ /dev/null
@@ -1,26 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U7  Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff		
-U11  Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff		
-U15  Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff		
-U19  Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff		
-U22  Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT		
-U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and		
-U3  Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and		
-U4  Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and		
-U5  Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and		
-U6  Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and		
-U8  Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and		
-U9  Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and		
-U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and		
-U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and		
-U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and		
-
-.end
diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out
deleted file mode 100644
index e3a384c5..00000000
--- a/src/SubcircuitLibrary/4017/4017.cir.out
+++ /dev/null
@@ -1,72 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
-
-* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
-* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
-* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
-* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
-* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
-* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
-* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
-* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
-* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
-* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
-* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
-* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
-* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
-* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
-a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
-a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
-a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
-a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
-a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
-a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
-a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
-a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
-a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
-a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
-a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
-a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
-a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
-a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
-a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 5e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro
deleted file mode 100644
index 8cdecd6c..00000000
--- a/src/SubcircuitLibrary/4017/4017.pro
+++ /dev/null
@@ -1,72 +0,0 @@
-update=Fri Jun 14 10:14:54 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-
diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch
deleted file mode 100644
index 05549a32..00000000
--- a/src/SubcircuitLibrary/4017/4017.sch
+++ /dev/null
@@ -1,580 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:4017-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_dff U7
-U 1 1 5C7B9B95
-P 2300 4100
-F 0 "U7" H 2300 4100 60  0000 C CNN
-F 1 "d_dff" H 2300 4250 60  0000 C CNN
-F 2 "" H 2300 4100 60  0000 C CNN
-F 3 "" H 2300 4100 60  0000 C CNN
-	1    2300 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_dff U11
-U 1 1 5C7B9CEE
-P 3700 4100
-F 0 "U11" H 3700 4100 60  0000 C CNN
-F 1 "d_dff" H 3700 4250 60  0000 C CNN
-F 2 "" H 3700 4100 60  0000 C CNN
-F 3 "" H 3700 4100 60  0000 C CNN
-	1    3700 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_dff U15
-U 1 1 5C7B9D3E
-P 5150 4100
-F 0 "U15" H 5150 4100 60  0000 C CNN
-F 1 "d_dff" H 5150 4250 60  0000 C CNN
-F 2 "" H 5150 4100 60  0000 C CNN
-F 3 "" H 5150 4100 60  0000 C CNN
-	1    5150 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_dff U19
-U 1 1 5C7B9D85
-P 6550 4100
-F 0 "U19" H 6550 4100 60  0000 C CNN
-F 1 "d_dff" H 6550 4250 60  0000 C CNN
-F 2 "" H 6550 4100 60  0000 C CNN
-F 3 "" H 6550 4100 60  0000 C CNN
-	1    6550 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_dff U22
-U 1 1 5C7B9DD9
-P 8050 4100
-F 0 "U22" H 8050 4100 60  0000 C CNN
-F 1 "d_dff" H 8050 4250 60  0000 C CNN
-F 2 "" H 8050 4100 60  0000 C CNN
-F 3 "" H 8050 4100 60  0000 C CNN
-	1    8050 4100
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1750 4400 1500 4400
-Wire Wire Line
-	1500 4400 1500 5350
-Wire Wire Line
-	1500 5350 7500 5350
-Wire Wire Line
-	7500 5350 7500 4400
-Wire Wire Line
-	2300 4700 2300 6700
-Wire Wire Line
-	2300 4900 8050 4900
-Wire Wire Line
-	8050 4900 8050 4700
-Wire Wire Line
-	3700 4700 3700 4900
-Connection ~ 3700 4900
-Wire Wire Line
-	5150 4700 5150 4900
-Connection ~ 5150 4900
-Wire Wire Line
-	6550 4700 6550 4900
-Connection ~ 6550 4900
-Wire Wire Line
-	6000 4400 6000 5350
-Connection ~ 6000 5350
-Wire Wire Line
-	4600 4400 4600 5350
-Connection ~ 4600 5350
-Wire Wire Line
-	3150 4400 3150 5350
-Connection ~ 3150 5350
-Wire Wire Line
-	2300 3450 2300 3350
-Wire Wire Line
-	1550 3350 8050 3350
-Wire Wire Line
-	8050 3350 8050 3450
-Wire Wire Line
-	6550 3450 6550 3350
-Connection ~ 6550 3350
-Wire Wire Line
-	5150 3450 5150 3350
-Connection ~ 5150 3350
-Wire Wire Line
-	3700 3350 3700 3450
-Connection ~ 3700 3350
-Wire Wire Line
-	7100 3750 7500 3750
-Wire Wire Line
-	5700 3750 6000 3750
-Wire Wire Line
-	2850 3750 3150 3750
-Wire Wire Line
-	4250 3750 4600 3750
-Wire Wire Line
-	4250 4400 4400 4400
-Wire Wire Line
-	5700 4400 5850 4400
-Wire Wire Line
-	2850 4400 3000 4400
-Wire Wire Line
-	2100 2300 2100 3300
-Wire Wire Line
-	2100 2500 5800 2500
-Wire Wire Line
-	5800 2500 5800 2300
-Wire Wire Line
-	2750 2300 2750 3200
-Wire Wire Line
-	2750 2550 6350 2550
-Wire Wire Line
-	6350 2550 6350 2300
-Wire Wire Line
-	3450 2300 3450 3150
-Wire Wire Line
-	3450 2600 7000 2600
-Wire Wire Line
-	7000 2600 7000 2300
-Wire Wire Line
-	4000 2300 4000 3050
-Wire Wire Line
-	4000 2650 7700 2650
-Wire Wire Line
-	7700 2650 7700 2300
-Wire Wire Line
-	2650 2300 2650 3250
-Wire Wire Line
-	2650 2700 5350 2700
-Wire Wire Line
-	5350 2700 5350 2300
-Wire Wire Line
-	3350 2300 3350 3250
-Wire Wire Line
-	3350 2750 5900 2750
-Wire Wire Line
-	5900 2750 5900 2300
-Wire Wire Line
-	3900 2300 3900 3100
-Wire Wire Line
-	3900 2800 6450 2800
-Wire Wire Line
-	6450 2800 6450 2300
-Wire Wire Line
-	4550 2300 4550 3000
-Wire Wire Line
-	4550 2850 7100 2850
-Wire Wire Line
-	7100 2850 7100 2300
-Wire Wire Line
-	5250 2300 5250 2950
-Wire Wire Line
-	5250 2900 7800 2900
-Wire Wire Line
-	7800 2900 7800 2300
-Wire Wire Line
-	2000 2300 2000 2450
-Wire Wire Line
-	1750 2450 4650 2450
-Wire Wire Line
-	4650 2450 4650 2300
-Wire Wire Line
-	1750 2450 1750 3750
-Connection ~ 2000 2450
-Wire Wire Line
-	8600 4400 8800 4400
-Wire Wire Line
-	8800 4400 8800 6350
-Wire Wire Line
-	8800 6350 1350 6350
-Wire Wire Line
-	1350 6350 1350 3600
-Wire Wire Line
-	1350 3600 1750 3600
-Connection ~ 1750 3600
-Wire Wire Line
-	2100 3300 3000 3300
-Wire Wire Line
-	3000 3300 3000 4400
-Connection ~ 2900 4400
-Connection ~ 2100 2500
-Connection ~ 2650 2700
-Wire Wire Line
-	2650 3250 2950 3250
-Wire Wire Line
-	2950 3250 2950 3750
-Connection ~ 2950 3750
-Wire Wire Line
-	4400 4400 4400 3200
-Wire Wire Line
-	4400 3200 2750 3200
-Connection ~ 2750 2550
-Wire Wire Line
-	3350 3250 4250 3250
-Wire Wire Line
-	4250 3250 4250 3750
-Connection ~ 3350 2750
-Wire Wire Line
-	3450 3150 5850 3150
-Wire Wire Line
-	5850 3150 5850 4400
-Connection ~ 5750 4400
-Connection ~ 3450 2600
-Wire Wire Line
-	3900 3100 5750 3100
-Wire Wire Line
-	5750 3100 5750 3750
-Connection ~ 5750 3750
-Connection ~ 3900 2800
-Wire Wire Line
-	4000 3050 7350 3050
-Wire Wire Line
-	7350 3050 7350 4400
-Wire Wire Line
-	7350 4400 7100 4400
-Connection ~ 4000 2650
-Wire Wire Line
-	4550 3000 7200 3000
-Wire Wire Line
-	7200 3000 7200 3750
-Connection ~ 7200 3750
-Connection ~ 4550 2850
-Wire Wire Line
-	5250 2950 8700 2950
-Wire Wire Line
-	8700 2950 8700 3750
-Wire Wire Line
-	8700 3750 8600 3750
-Connection ~ 5250 2900
-Wire Wire Line
-	2300 6700 1100 6700
-Connection ~ 2300 4900
-Wire Wire Line
-	1550 3350 1550 5150
-Wire Wire Line
-	1550 5150 2300 5150
-Connection ~ 2300 5150
-Connection ~ 2300 3350
-Wire Wire Line
-	2550 5350 2550 6650
-Wire Wire Line
-	2550 6650 2950 6650
-Wire Wire Line
-	2950 6650 2950 7200
-Wire Wire Line
-	2950 7200 2700 7200
-Connection ~ 2550 5350
-$Comp
-L PORT U1
-U 6 1 5C7C1634
-P 5300 1000
-F 0 "U1" H 5350 1100 30  0000 C CNN
-F 1 "PORT" H 5300 1000 30  0000 C CNN
-F 2 "" H 5300 1000 60  0000 C CNN
-F 3 "" H 5300 1000 60  0000 C CNN
-	6    5300 1000
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	5300 1250 5300 1400
-$Comp
-L PORT U1
-U 2 1 5C7BC7B8
-P 2700 1000
-F 0 "U1" H 2750 1100 30  0000 C CNN
-F 1 "PORT" H 2700 1000 30  0000 C CNN
-F 2 "" H 2700 1000 60  0000 C CNN
-F 3 "" H 2700 1000 60  0000 C CNN
-	2    2700 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C7BC953
-P 2050 950
-F 0 "U1" H 2100 1050 30  0000 C CNN
-F 1 "PORT" H 2050 950 30  0000 C CNN
-F 2 "" H 2050 950 60  0000 C CNN
-F 3 "" H 2050 950 60  0000 C CNN
-	1    2050 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C7BC9D8
-P 3400 950
-F 0 "U1" H 3450 1050 30  0000 C CNN
-F 1 "PORT" H 3400 950 30  0000 C CNN
-F 2 "" H 3400 950 60  0000 C CNN
-F 3 "" H 3400 950 60  0000 C CNN
-	3    3400 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C7BCAA7
-P 5850 950
-F 0 "U1" H 5900 1050 30  0000 C CNN
-F 1 "PORT" H 5850 950 30  0000 C CNN
-F 2 "" H 5850 950 60  0000 C CNN
-F 3 "" H 5850 950 60  0000 C CNN
-	7    5850 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C7BCB20
-P 6400 1000
-F 0 "U1" H 6450 1100 30  0000 C CNN
-F 1 "PORT" H 6400 1000 30  0000 C CNN
-F 2 "" H 6400 1000 60  0000 C CNN
-F 3 "" H 6400 1000 60  0000 C CNN
-	8    6400 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C7BCBB1
-P 3950 950
-F 0 "U1" H 4000 1050 30  0000 C CNN
-F 1 "PORT" H 3950 950 30  0000 C CNN
-F 2 "" H 3950 950 60  0000 C CNN
-F 3 "" H 3950 950 60  0000 C CNN
-	4    3950 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C7BCF23
-P 7050 1000
-F 0 "U1" H 7100 1100 30  0000 C CNN
-F 1 "PORT" H 7050 1000 30  0000 C CNN
-F 2 "" H 7050 1000 60  0000 C CNN
-F 3 "" H 7050 1000 60  0000 C CNN
-	9    7050 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C7BCFC0
-P 4600 950
-F 0 "U1" H 4650 1050 30  0000 C CNN
-F 1 "PORT" H 4600 950 30  0000 C CNN
-F 2 "" H 4600 950 60  0000 C CNN
-F 3 "" H 4600 950 60  0000 C CNN
-	5    4600 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C7BD0A5
-P 7750 1000
-F 0 "U1" H 7800 1100 30  0000 C CNN
-F 1 "PORT" H 7750 1000 30  0000 C CNN
-F 2 "" H 7750 1000 60  0000 C CNN
-F 3 "" H 7750 1000 60  0000 C CNN
-	10   7750 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C7BD5BB
-P 850 6700
-F 0 "U1" H 900 6800 30  0000 C CNN
-F 1 "PORT" H 850 6700 30  0000 C CNN
-F 2 "" H 850 6700 60  0000 C CNN
-F 3 "" H 850 6700 60  0000 C CNN
-	11   850  6700
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2050 1200 2050 1400
-Wire Wire Line
-	2700 1250 2700 1400
-Wire Wire Line
-	3400 1200 3400 1400
-Wire Wire Line
-	3950 1200 3950 1400
-Wire Wire Line
-	4600 1200 4600 1400
-Wire Wire Line
-	5850 1200 5850 1400
-Wire Wire Line
-	6400 1250 6400 1400
-Wire Wire Line
-	7050 1250 7050 1400
-Wire Wire Line
-	7750 1250 7750 1400
-$Comp
-L PORT U1
-U 12 1 5C8A0119
-P 2450 7200
-F 0 "U1" H 2500 7300 30  0000 C CNN
-F 1 "PORT" H 2450 7200 30  0000 C CNN
-F 2 "" H 2450 7200 60  0000 C CNN
-F 3 "" H 2450 7200 60  0000 C CNN
-	12   2450 7200
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C89F7BC
-P 2100 1850
-F 0 "U2" H 2100 1850 60  0000 C CNN
-F 1 "d_and" H 2150 1950 60  0000 C CNN
-F 2 "" H 2100 1850 60  0000 C CNN
-F 3 "" H 2100 1850 60  0000 C CNN
-	1    2100 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C89FA46
-P 2750 1850
-F 0 "U3" H 2750 1850 60  0000 C CNN
-F 1 "d_and" H 2800 1950 60  0000 C CNN
-F 2 "" H 2750 1850 60  0000 C CNN
-F 3 "" H 2750 1850 60  0000 C CNN
-	1    2750 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C89FAD5
-P 3450 1850
-F 0 "U4" H 3450 1850 60  0000 C CNN
-F 1 "d_and" H 3500 1950 60  0000 C CNN
-F 2 "" H 3450 1850 60  0000 C CNN
-F 3 "" H 3450 1850 60  0000 C CNN
-	1    3450 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U5
-U 1 1 5C89FB62
-P 4000 1850
-F 0 "U5" H 4000 1850 60  0000 C CNN
-F 1 "d_and" H 4050 1950 60  0000 C CNN
-F 2 "" H 4000 1850 60  0000 C CNN
-F 3 "" H 4000 1850 60  0000 C CNN
-	1    4000 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U6
-U 1 1 5C89FEBF
-P 4650 1850
-F 0 "U6" H 4650 1850 60  0000 C CNN
-F 1 "d_and" H 4700 1950 60  0000 C CNN
-F 2 "" H 4650 1850 60  0000 C CNN
-F 3 "" H 4650 1850 60  0000 C CNN
-	1    4650 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U8
-U 1 1 5C89FF2C
-P 5350 1850
-F 0 "U8" H 5350 1850 60  0000 C CNN
-F 1 "d_and" H 5400 1950 60  0000 C CNN
-F 2 "" H 5350 1850 60  0000 C CNN
-F 3 "" H 5350 1850 60  0000 C CNN
-	1    5350 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U9
-U 1 1 5C89FF96
-P 5900 1850
-F 0 "U9" H 5900 1850 60  0000 C CNN
-F 1 "d_and" H 5950 1950 60  0000 C CNN
-F 2 "" H 5900 1850 60  0000 C CNN
-F 3 "" H 5900 1850 60  0000 C CNN
-	1    5900 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U10
-U 1 1 5C8A066D
-P 6450 1850
-F 0 "U10" H 6450 1850 60  0000 C CNN
-F 1 "d_and" H 6500 1950 60  0000 C CNN
-F 2 "" H 6450 1850 60  0000 C CNN
-F 3 "" H 6450 1850 60  0000 C CNN
-	1    6450 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U12
-U 1 1 5C8A06D8
-P 7100 1850
-F 0 "U12" H 7100 1850 60  0000 C CNN
-F 1 "d_and" H 7150 1950 60  0000 C CNN
-F 2 "" H 7100 1850 60  0000 C CNN
-F 3 "" H 7100 1850 60  0000 C CNN
-	1    7100 1850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U13
-U 1 1 5C8A12F5
-P 7800 1850
-F 0 "U13" H 7800 1850 60  0000 C CNN
-F 1 "d_and" H 7850 1950 60  0000 C CNN
-F 2 "" H 7800 1850 60  0000 C CNN
-F 3 "" H 7800 1850 60  0000 C CNN
-	1    7800 1850
-	0    -1   -1   0   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub
deleted file mode 100644
index 2e27ab61..00000000
--- a/src/SubcircuitLibrary/4017/4017.sub
+++ /dev/null
@@ -1,66 +0,0 @@
-* Subcircuit 4017
-.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ 
-* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
-* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
-* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
-* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
-* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
-* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
-* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
-* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
-* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
-* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
-* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
-* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
-* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
-* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
-* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
-a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
-a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
-a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
-a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
-a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
-a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
-a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
-a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
-a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
-a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
-a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
-a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
-a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
-a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
-a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4017
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
deleted file mode 100644
index 9dfd97a3..00000000
--- a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib
deleted file mode 100644
index adbdfb35..00000000
--- a/src/SubcircuitLibrary/4017/D.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.MODEL 1N4148 D(
-+  Vj=1
-+  Cjo=1.700E-12
-+  Rs=4.755E-01
-+  Is=2.495E-09
-+  M=1.959E-01
-+  N=1.679E+00
-+  Bv=1.000E+02
-+  tt=3.030E-09
-+  Ibv=1.000E-04
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis
deleted file mode 100644
index 40bd9d97..00000000
--- a/src/SubcircuitLibrary/4017/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 5e-03 100e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/4023/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/4023/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/4023/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/4023/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/4023/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/4023/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib
deleted file mode 100644
index c989d8c7..00000000
--- a/src/SubcircuitLibrary/4023/4023-cache.lib
+++ /dev/null
@@ -1,76 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0  -150 200  200 200 N
-P 3 0 1 0  -150 200  -150 -100  200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir
deleted file mode 100644
index 6aad9b84..00000000
--- a/src/SubcircuitLibrary/4023/4023.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X3  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and		
-U4  Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-X2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U3  Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter		
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter		
-
-.end
diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out
deleted file mode 100644
index 7f48d16f..00000000
--- a/src/SubcircuitLibrary/4023/4023.cir.out
+++ /dev/null
@@ -1,28 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
-
-.include 3_and.sub
-x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
-* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
-a1 net-_u4-pad1_ net-_u1-pad10_ u4
-a2 net-_u3-pad1_ net-_u1-pad6_ u3
-a3 net-_u2-pad1_ net-_u1-pad9_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro
deleted file mode 100644
index 5a5ce355..00000000
--- a/src/SubcircuitLibrary/4023/4023.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:32:35
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch
deleted file mode 100644
index 57dd7868..00000000
--- a/src/SubcircuitLibrary/4023/4023.sch
+++ /dev/null
@@ -1,309 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X3
-U 1 1 5CF0FA82
-P 4800 2500
-F 0 "X3" H 4900 2450 60  0000 C CNN
-F 1 "3_and" H 4950 2650 60  0000 C CNN
-F 2 "" H 4800 2500 60  0000 C CNN
-F 3 "" H 4800 2500 60  0000 C CNN
-	1    4800 2500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U4
-U 1 1 5CF0FB13
-P 6150 2450
-F 0 "U4" H 6150 2350 60  0000 C CNN
-F 1 "d_inverter" H 6150 2600 60  0000 C CNN
-F 2 "" H 6200 2400 60  0000 C CNN
-F 3 "" H 6200 2400 60  0000 C CNN
-	1    6150 2450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF0FB34
-P 3100 1950
-F 0 "U1" H 3150 2050 30  0000 C CNN
-F 1 "PORT" H 3100 1950 30  0000 C CNN
-F 2 "" H 3100 1950 60  0000 C CNN
-F 3 "" H 3100 1950 60  0000 C CNN
-	11   3100 1950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF0FB90
-P 3100 2350
-F 0 "U1" H 3150 2450 30  0000 C CNN
-F 1 "PORT" H 3100 2350 30  0000 C CNN
-F 2 "" H 3100 2350 60  0000 C CNN
-F 3 "" H 3100 2350 60  0000 C CNN
-	12   3100 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF0FBB8
-P 3100 2750
-F 0 "U1" H 3150 2850 30  0000 C CNN
-F 1 "PORT" H 3100 2750 30  0000 C CNN
-F 2 "" H 3100 2750 60  0000 C CNN
-F 3 "" H 3100 2750 60  0000 C CNN
-	13   3100 2750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF0FBED
-P 7800 2450
-F 0 "U1" H 7850 2550 30  0000 C CNN
-F 1 "PORT" H 7800 2450 30  0000 C CNN
-F 2 "" H 7800 2450 60  0000 C CNN
-F 3 "" H 7800 2450 60  0000 C CNN
-	10   7800 2450
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7550 2450 6450 2450
-Wire Wire Line
-	5850 2450 5300 2450
-Wire Wire Line
-	4450 2350 4450 1950
-Wire Wire Line
-	4450 1950 3350 1950
-Wire Wire Line
-	4450 2450 4100 2450
-Wire Wire Line
-	4100 2450 4100 2350
-Wire Wire Line
-	4100 2350 3350 2350
-Wire Wire Line
-	3350 2750 3950 2750
-Wire Wire Line
-	3950 2750 3950 2550
-Wire Wire Line
-	3950 2550 4450 2550
-$Comp
-L 3_and X2
-U 1 1 5CF0FF35
-P 4700 3800
-F 0 "X2" H 4800 3750 60  0000 C CNN
-F 1 "3_and" H 4850 3950 60  0000 C CNN
-F 2 "" H 4700 3800 60  0000 C CNN
-F 3 "" H 4700 3800 60  0000 C CNN
-	1    4700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U3
-U 1 1 5CF0FF3B
-P 6050 3750
-F 0 "U3" H 6050 3650 60  0000 C CNN
-F 1 "d_inverter" H 6050 3900 60  0000 C CNN
-F 2 "" H 6100 3700 60  0000 C CNN
-F 3 "" H 6100 3700 60  0000 C CNN
-	1    6050 3750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF0FF41
-P 3000 3250
-F 0 "U1" H 3050 3350 30  0000 C CNN
-F 1 "PORT" H 3000 3250 30  0000 C CNN
-F 2 "" H 3000 3250 60  0000 C CNN
-F 3 "" H 3000 3250 60  0000 C CNN
-	4    3000 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CF0FF47
-P 3000 3650
-F 0 "U1" H 3050 3750 30  0000 C CNN
-F 1 "PORT" H 3000 3650 30  0000 C CNN
-F 2 "" H 3000 3650 60  0000 C CNN
-F 3 "" H 3000 3650 60  0000 C CNN
-	5    3000 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF0FF4D
-P 3000 4050
-F 0 "U1" H 3050 4150 30  0000 C CNN
-F 1 "PORT" H 3000 4050 30  0000 C CNN
-F 2 "" H 3000 4050 60  0000 C CNN
-F 3 "" H 3000 4050 60  0000 C CNN
-	3    3000 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF0FF53
-P 7700 3750
-F 0 "U1" H 7750 3850 30  0000 C CNN
-F 1 "PORT" H 7700 3750 30  0000 C CNN
-F 2 "" H 7700 3750 60  0000 C CNN
-F 3 "" H 7700 3750 60  0000 C CNN
-	6    7700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7450 3750 6350 3750
-Wire Wire Line
-	5750 3750 5200 3750
-Wire Wire Line
-	4350 3650 4350 3250
-Wire Wire Line
-	4350 3250 3250 3250
-Wire Wire Line
-	4350 3750 4000 3750
-Wire Wire Line
-	4000 3750 4000 3650
-Wire Wire Line
-	4000 3650 3250 3650
-Wire Wire Line
-	3250 4050 3850 4050
-Wire Wire Line
-	3850 4050 3850 3850
-Wire Wire Line
-	3850 3850 4350 3850
-$Comp
-L 3_and X1
-U 1 1 5CF100B9
-P 4650 5100
-F 0 "X1" H 4750 5050 60  0000 C CNN
-F 1 "3_and" H 4800 5250 60  0000 C CNN
-F 2 "" H 4650 5100 60  0000 C CNN
-F 3 "" H 4650 5100 60  0000 C CNN
-	1    4650 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U2
-U 1 1 5CF100BF
-P 6000 5050
-F 0 "U2" H 6000 4950 60  0000 C CNN
-F 1 "d_inverter" H 6000 5200 60  0000 C CNN
-F 2 "" H 6050 5000 60  0000 C CNN
-F 3 "" H 6050 5000 60  0000 C CNN
-	1    6000 5050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF100C5
-P 2950 4550
-F 0 "U1" H 3000 4650 30  0000 C CNN
-F 1 "PORT" H 2950 4550 30  0000 C CNN
-F 2 "" H 2950 4550 60  0000 C CNN
-F 3 "" H 2950 4550 60  0000 C CNN
-	1    2950 4550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF100CB
-P 2950 4950
-F 0 "U1" H 3000 5050 30  0000 C CNN
-F 1 "PORT" H 2950 4950 30  0000 C CNN
-F 2 "" H 2950 4950 60  0000 C CNN
-F 3 "" H 2950 4950 60  0000 C CNN
-	2    2950 4950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF100D1
-P 2950 5350
-F 0 "U1" H 3000 5450 30  0000 C CNN
-F 1 "PORT" H 2950 5350 30  0000 C CNN
-F 2 "" H 2950 5350 60  0000 C CNN
-F 3 "" H 2950 5350 60  0000 C CNN
-	8    2950 5350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF100D7
-P 7650 5050
-F 0 "U1" H 7700 5150 30  0000 C CNN
-F 1 "PORT" H 7650 5050 30  0000 C CNN
-F 2 "" H 7650 5050 60  0000 C CNN
-F 3 "" H 7650 5050 60  0000 C CNN
-	9    7650 5050
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7400 5050 6300 5050
-Wire Wire Line
-	5700 5050 5150 5050
-Wire Wire Line
-	4300 4950 4300 4550
-Wire Wire Line
-	4300 4550 3200 4550
-Wire Wire Line
-	4300 5050 3950 5050
-Wire Wire Line
-	3950 5050 3950 4950
-Wire Wire Line
-	3950 4950 3200 4950
-Wire Wire Line
-	3200 5350 3800 5350
-Wire Wire Line
-	3800 5350 3800 5150
-Wire Wire Line
-	3800 5150 4300 5150
-$Comp
-L PORT U1
-U 7 1 5CF101BF
-P 9950 3350
-F 0 "U1" H 10000 3450 30  0000 C CNN
-F 1 "PORT" H 9950 3350 30  0000 C CNN
-F 2 "" H 9950 3350 60  0000 C CNN
-F 3 "" H 9950 3350 60  0000 C CNN
-	7    9950 3350
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF1025C
-P 9950 3900
-F 0 "U1" H 10000 4000 30  0000 C CNN
-F 1 "PORT" H 9950 3900 30  0000 C CNN
-F 2 "" H 9950 3900 60  0000 C CNN
-F 3 "" H 9950 3900 60  0000 C CNN
-	14   9950 3900
-	-1   0    0    1   
-$EndComp
-NoConn ~ 9700 3350
-NoConn ~ 9700 3900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub
deleted file mode 100644
index b953da2e..00000000
--- a/src/SubcircuitLibrary/4023/4023.sub
+++ /dev/null
@@ -1,22 +0,0 @@
-* Subcircuit 4023
-.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
-.include 3_and.sub
-x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
-* u4  net-_u4-pad1_ net-_u1-pad10_ d_inverter
-x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u3  net-_u3-pad1_ net-_u1-pad6_ d_inverter
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad9_ d_inverter
-a1 net-_u4-pad1_ net-_u1-pad10_ u4
-a2 net-_u3-pad1_ net-_u1-pad6_ u3
-a3 net-_u2-pad1_ net-_u1-pad9_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4023
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
deleted file mode 100644
index ad900de2..00000000
--- a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4023/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4025/4025-cache.lib b/src/SubcircuitLibrary/4025/4025-cache.lib
deleted file mode 100644
index dd565db9..00000000
--- a/src/SubcircuitLibrary/4025/4025-cache.lib
+++ /dev/null
@@ -1,82 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4025/4025.cir b/src/SubcircuitLibrary/4025/4025.cir
deleted file mode 100644
index a2431c71..00000000
--- a/src/SubcircuitLibrary/4025/4025.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4025\4025.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:34:19
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U6  Net-_U3-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_nor		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-U4  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U4-Pad3_ d_or		
-U7  Net-_U4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad10_ d_nor		
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U5  Net-_U2-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_nor		
-
-.end
diff --git a/src/SubcircuitLibrary/4025/4025.cir.out b/src/SubcircuitLibrary/4025/4025.cir.out
deleted file mode 100644
index b22d91a3..00000000
--- a/src/SubcircuitLibrary/4025/4025.cir.out
+++ /dev/null
@@ -1,36 +0,0 @@
-* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
-
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6  net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4  net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
-* u7  net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u5  net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
-a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
-a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
-a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
-a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4025/4025.pro b/src/SubcircuitLibrary/4025/4025.pro
deleted file mode 100644
index 3c05588e..00000000
--- a/src/SubcircuitLibrary/4025/4025.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=05/31/19 09:27:16
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/4025/4025.sch b/src/SubcircuitLibrary/4025/4025.sch
deleted file mode 100644
index 2a0cb4bc..00000000
--- a/src/SubcircuitLibrary/4025/4025.sch
+++ /dev/null
@@ -1,302 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4025-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U3
-U 1 1 5CEE0A15
-P 4850 3000
-F 0 "U3" H 4850 3000 60  0000 C CNN
-F 1 "d_or" H 4850 3100 60  0000 C CNN
-F 2 "" H 4850 3000 60  0000 C CNN
-F 3 "" H 4850 3000 60  0000 C CNN
-	1    4850 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U6
-U 1 1 5CEE0AE8
-P 6100 3050
-F 0 "U6" H 6100 3050 60  0000 C CNN
-F 1 "d_nor" H 6150 3150 60  0000 C CNN
-F 2 "" H 6100 3050 60  0000 C CNN
-F 3 "" H 6100 3050 60  0000 C CNN
-	1    6100 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CEE0B21
-P 3900 2900
-F 0 "U1" H 3950 3000 30  0000 C CNN
-F 1 "PORT" H 3900 2900 30  0000 C CNN
-F 2 "" H 3900 2900 60  0000 C CNN
-F 3 "" H 3900 2900 60  0000 C CNN
-	3    3900 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CEE0B4F
-P 3900 3150
-F 0 "U1" H 3950 3250 30  0000 C CNN
-F 1 "PORT" H 3900 3150 30  0000 C CNN
-F 2 "" H 3900 3150 60  0000 C CNN
-F 3 "" H 3900 3150 60  0000 C CNN
-	4    3900 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CEE0B87
-P 5200 4450
-F 0 "U1" H 5250 4550 30  0000 C CNN
-F 1 "PORT" H 5200 4450 30  0000 C CNN
-F 2 "" H 5200 4450 60  0000 C CNN
-F 3 "" H 5200 4450 60  0000 C CNN
-	8    5200 4450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CEE0BBA
-P 3900 3500
-F 0 "U1" H 3950 3600 30  0000 C CNN
-F 1 "PORT" H 3900 3500 30  0000 C CNN
-F 2 "" H 3900 3500 60  0000 C CNN
-F 3 "" H 3900 3500 60  0000 C CNN
-	11   3900 3500
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4150 2900 4400 2900
-Wire Wire Line
-	4150 3150 4300 3150
-Wire Wire Line
-	4300 3150 4300 3000
-Wire Wire Line
-	4300 3000 4400 3000
-Wire Wire Line
-	5300 2950 5650 2950
-Wire Wire Line
-	5500 3150 5650 3150
-Wire Wire Line
-	5650 3150 5650 3050
-Wire Wire Line
-	6550 3000 6750 3000
-$Comp
-L d_or U4
-U 1 1 5CEE1CD2
-P 4850 3600
-F 0 "U4" H 4850 3600 60  0000 C CNN
-F 1 "d_or" H 4850 3700 60  0000 C CNN
-F 2 "" H 4850 3600 60  0000 C CNN
-F 3 "" H 4850 3600 60  0000 C CNN
-	1    4850 3600
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U7
-U 1 1 5CEE1CD8
-P 6100 3650
-F 0 "U7" H 6100 3650 60  0000 C CNN
-F 1 "d_nor" H 6150 3750 60  0000 C CNN
-F 2 "" H 6100 3650 60  0000 C CNN
-F 3 "" H 6100 3650 60  0000 C CNN
-	1    6100 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CEE1CDE
-P 5250 3150
-F 0 "U1" H 5300 3250 30  0000 C CNN
-F 1 "PORT" H 5250 3150 30  0000 C CNN
-F 2 "" H 5250 3150 60  0000 C CNN
-F 3 "" H 5250 3150 60  0000 C CNN
-	5    5250 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CEE1CE4
-P 7000 3000
-F 0 "U1" H 7050 3100 30  0000 C CNN
-F 1 "PORT" H 7000 3000 30  0000 C CNN
-F 2 "" H 7000 3000 60  0000 C CNN
-F 3 "" H 7000 3000 60  0000 C CNN
-	6    7000 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CEE1CEA
-P 6950 4300
-F 0 "U1" H 7000 4400 30  0000 C CNN
-F 1 "PORT" H 6950 4300 30  0000 C CNN
-F 2 "" H 6950 4300 60  0000 C CNN
-F 3 "" H 6950 4300 60  0000 C CNN
-	9    6950 4300
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CEE1CF0
-P 3900 3750
-F 0 "U1" H 3950 3850 30  0000 C CNN
-F 1 "PORT" H 3900 3750 30  0000 C CNN
-F 2 "" H 3900 3750 60  0000 C CNN
-F 3 "" H 3900 3750 60  0000 C CNN
-	12   3900 3750
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4150 3500 4400 3500
-Wire Wire Line
-	4150 3750 4300 3750
-Wire Wire Line
-	4300 3750 4300 3600
-Wire Wire Line
-	4300 3600 4400 3600
-Wire Wire Line
-	5300 3550 5650 3550
-Wire Wire Line
-	5500 3750 5650 3750
-Wire Wire Line
-	5650 3750 5650 3650
-Wire Wire Line
-	6550 3600 6750 3600
-$Comp
-L d_or U2
-U 1 1 5CEE1F80
-P 4800 4300
-F 0 "U2" H 4800 4300 60  0000 C CNN
-F 1 "d_or" H 4800 4400 60  0000 C CNN
-F 2 "" H 4800 4300 60  0000 C CNN
-F 3 "" H 4800 4300 60  0000 C CNN
-	1    4800 4300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U5
-U 1 1 5CEE1F86
-P 6050 4350
-F 0 "U5" H 6050 4350 60  0000 C CNN
-F 1 "d_nor" H 6100 4450 60  0000 C CNN
-F 2 "" H 6050 4350 60  0000 C CNN
-F 3 "" H 6050 4350 60  0000 C CNN
-	1    6050 4350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CEE1F8C
-P 3850 4200
-F 0 "U1" H 3900 4300 30  0000 C CNN
-F 1 "PORT" H 3850 4200 30  0000 C CNN
-F 2 "" H 3850 4200 60  0000 C CNN
-F 3 "" H 3850 4200 60  0000 C CNN
-	1    3850 4200
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CEE1F92
-P 3850 4450
-F 0 "U1" H 3900 4550 30  0000 C CNN
-F 1 "PORT" H 3850 4450 30  0000 C CNN
-F 2 "" H 3850 4450 60  0000 C CNN
-F 3 "" H 3850 4450 60  0000 C CNN
-	2    3850 4450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CEE1F98
-P 8450 3500
-F 0 "U1" H 8500 3600 30  0000 C CNN
-F 1 "PORT" H 8450 3500 30  0000 C CNN
-F 2 "" H 8450 3500 60  0000 C CNN
-F 3 "" H 8450 3500 60  0000 C CNN
-	7    8450 3500
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CEE1F9E
-P 7000 3600
-F 0 "U1" H 7050 3700 30  0000 C CNN
-F 1 "PORT" H 7000 3600 30  0000 C CNN
-F 2 "" H 7000 3600 60  0000 C CNN
-F 3 "" H 7000 3600 60  0000 C CNN
-	10   7000 3600
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4100 4200 4350 4200
-Wire Wire Line
-	4100 4450 4250 4450
-Wire Wire Line
-	4250 4450 4250 4300
-Wire Wire Line
-	4250 4300 4350 4300
-Wire Wire Line
-	5250 4250 5600 4250
-Wire Wire Line
-	5450 4450 5600 4450
-Wire Wire Line
-	5600 4450 5600 4350
-Wire Wire Line
-	6500 4300 6700 4300
-Wire Wire Line
-	7800 3500 8200 3500
-NoConn ~ 7800 3500
-$Comp
-L PORT U1
-U 13 1 5CEE2827
-P 5250 3750
-F 0 "U1" H 5300 3850 30  0000 C CNN
-F 1 "PORT" H 5250 3750 30  0000 C CNN
-F 2 "" H 5250 3750 60  0000 C CNN
-F 3 "" H 5250 3750 60  0000 C CNN
-	13   5250 3750
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7800 3850 8200 3850
-NoConn ~ 7800 3850
-$Comp
-L PORT U1
-U 14 1 5CEE289D
-P 8450 3850
-F 0 "U1" H 8500 3950 30  0000 C CNN
-F 1 "PORT" H 8450 3850 30  0000 C CNN
-F 2 "" H 8450 3850 60  0000 C CNN
-F 3 "" H 8450 3850 60  0000 C CNN
-	14   8450 3850
-	-1   0    0    1   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4025/4025.sub b/src/SubcircuitLibrary/4025/4025.sub
deleted file mode 100644
index 867617fd..00000000
--- a/src/SubcircuitLibrary/4025/4025.sub
+++ /dev/null
@@ -1,30 +0,0 @@
-* Subcircuit 4025
-.subckt 4025 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6  net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
-* u4  net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
-* u7  net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u5  net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
-a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
-a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
-a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
-a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4025
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml
deleted file mode 100644
index 228a19a0..00000000
--- a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u7 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u7><u2 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4025/analysis b/src/SubcircuitLibrary/4025/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4025/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/4028-cache.lib b/src/SubcircuitLibrary/4028/4028-cache.lib
deleted file mode 100644
index 5b7e8ebd..00000000
--- a/src/SubcircuitLibrary/4028/4028-cache.lib
+++ /dev/null
@@ -1,94 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4028/4028.cir b/src/SubcircuitLibrary/4028/4028.cir
deleted file mode 100644
index ff25eb55..00000000
--- a/src/SubcircuitLibrary/4028/4028.cir
+++ /dev/null
@@ -1,32 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U9  Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor		
-U10  Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor		
-U11  Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor		
-U12  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor		
-U6  Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor		
-U7  Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor		
-U8  Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor		
-U2  Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter		
-U3  Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter		
-U4  Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter		
-U15  Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and		
-U16  Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and		
-U17  Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and		
-U18  Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and		
-U19  Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and		
-U20  Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and		
-U21  Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and		
-U13  Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and		
-U14  Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT		
-U22  Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and		
-
-.end
diff --git a/src/SubcircuitLibrary/4028/4028.cir.out b/src/SubcircuitLibrary/4028/4028.cir.out
deleted file mode 100644
index 882115b7..00000000
--- a/src/SubcircuitLibrary/4028/4028.cir.out
+++ /dev/null
@@ -1,96 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
-
-* u9  net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
-* u10  net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
-* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
-* u12  net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
-* u6  net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
-* u7  net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
-* u8  net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
-* u2  net-_u1-pad10_ net-_u11-pad1_ d_inverter
-* u3  net-_u1-pad13_ net-_u10-pad2_ d_inverter
-* u4  net-_u1-pad12_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad11_ net-_u5-pad2_ d_inverter
-* u15  net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
-* u16  net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
-* u17  net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
-* u18  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
-* u19  net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
-* u20  net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
-* u21  net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
-* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
-* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-* u22  net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
-a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
-a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
-a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
-a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
-a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
-a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
-a8 net-_u1-pad10_ net-_u11-pad1_ u2
-a9 net-_u1-pad13_ net-_u10-pad2_ u3
-a10 net-_u1-pad12_ net-_u4-pad2_ u4
-a11 net-_u1-pad11_ net-_u5-pad2_ u5
-a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
-a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
-a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
-a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
-a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
-a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
-a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
-a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
-a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
-a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4028/4028.pro b/src/SubcircuitLibrary/4028/4028.pro
deleted file mode 100644
index a63207b3..00000000
--- a/src/SubcircuitLibrary/4028/4028.pro
+++ /dev/null
@@ -1,43 +0,0 @@
-update=05/31/19 15:43:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
diff --git a/src/SubcircuitLibrary/4028/4028.sch b/src/SubcircuitLibrary/4028/4028.sch
deleted file mode 100644
index 373a95e6..00000000
--- a/src/SubcircuitLibrary/4028/4028.sch
+++ /dev/null
@@ -1,628 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_nor U9
-U 1 1 5CF0FE64
-P 3750 2500
-F 0 "U9" H 3750 2500 60  0000 C CNN
-F 1 "d_nor" H 3800 2600 60  0000 C CNN
-F 2 "" H 3750 2500 60  0000 C CNN
-F 3 "" H 3750 2500 60  0000 C CNN
-	1    3750 2500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U10
-U 1 1 5CF0FEA4
-P 3750 3050
-F 0 "U10" H 3750 3050 60  0000 C CNN
-F 1 "d_nor" H 3800 3150 60  0000 C CNN
-F 2 "" H 3750 3050 60  0000 C CNN
-F 3 "" H 3750 3050 60  0000 C CNN
-	1    3750 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U11
-U 1 1 5CF0FECC
-P 3750 3550
-F 0 "U11" H 3750 3550 60  0000 C CNN
-F 1 "d_nor" H 3800 3650 60  0000 C CNN
-F 2 "" H 3750 3550 60  0000 C CNN
-F 3 "" H 3750 3550 60  0000 C CNN
-	1    3750 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U12
-U 1 1 5CF0FEF5
-P 3750 4150
-F 0 "U12" H 3750 4150 60  0000 C CNN
-F 1 "d_nor" H 3800 4250 60  0000 C CNN
-F 2 "" H 3750 4150 60  0000 C CNN
-F 3 "" H 3750 4150 60  0000 C CNN
-	1    3750 4150
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U6
-U 1 1 5CF0FF23
-P 3700 4750
-F 0 "U6" H 3700 4750 60  0000 C CNN
-F 1 "d_nor" H 3750 4850 60  0000 C CNN
-F 2 "" H 3700 4750 60  0000 C CNN
-F 3 "" H 3700 4750 60  0000 C CNN
-	1    3700 4750
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U7
-U 1 1 5CF0FF59
-P 3700 5250
-F 0 "U7" H 3700 5250 60  0000 C CNN
-F 1 "d_nor" H 3750 5350 60  0000 C CNN
-F 2 "" H 3700 5250 60  0000 C CNN
-F 3 "" H 3700 5250 60  0000 C CNN
-	1    3700 5250
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_nor U8
-U 1 1 5CF0FFA9
-P 3750 2000
-F 0 "U8" H 3750 2000 60  0000 C CNN
-F 1 "d_nor" H 3800 2100 60  0000 C CNN
-F 2 "" H 3750 2000 60  0000 C CNN
-F 3 "" H 3750 2000 60  0000 C CNN
-	1    3750 2000
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U2
-U 1 1 5CF1003A
-P 2150 2400
-F 0 "U2" H 2150 2300 60  0000 C CNN
-F 1 "d_inverter" H 2150 2550 60  0000 C CNN
-F 2 "" H 2200 2350 60  0000 C CNN
-F 3 "" H 2200 2350 60  0000 C CNN
-	1    2150 2400
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U3
-U 1 1 5CF1007F
-P 2150 3300
-F 0 "U3" H 2150 3200 60  0000 C CNN
-F 1 "d_inverter" H 2150 3450 60  0000 C CNN
-F 2 "" H 2200 3250 60  0000 C CNN
-F 3 "" H 2200 3250 60  0000 C CNN
-	1    2150 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U4
-U 1 1 5CF100CC
-P 2150 4150
-F 0 "U4" H 2150 4050 60  0000 C CNN
-F 1 "d_inverter" H 2150 4300 60  0000 C CNN
-F 2 "" H 2200 4100 60  0000 C CNN
-F 3 "" H 2200 4100 60  0000 C CNN
-	1    2150 4150
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U5
-U 1 1 5CF10114
-P 2150 4900
-F 0 "U5" H 2150 4800 60  0000 C CNN
-F 1 "d_inverter" H 2150 5050 60  0000 C CNN
-F 2 "" H 2200 4850 60  0000 C CNN
-F 3 "" H 2200 4850 60  0000 C CNN
-	1    2150 4900
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1400 2400 1850 2400
-Wire Wire Line
-	1400 3300 1850 3300
-Wire Wire Line
-	1450 4150 1850 4150
-Wire Wire Line
-	1450 4900 1850 4900
-Wire Wire Line
-	2450 4900 2500 4900
-Wire Wire Line
-	2500 4900 2500 5250
-Wire Wire Line
-	2500 5250 3250 5250
-Wire Wire Line
-	2450 4150 2550 4150
-Wire Wire Line
-	2550 4150 2550 4650
-Wire Wire Line
-	2550 4650 3250 4650
-Wire Wire Line
-	2450 3300 2550 3300
-Wire Wire Line
-	2550 3300 2550 3550
-Wire Wire Line
-	2550 3550 3300 3550
-Wire Wire Line
-	2450 2400 2450 2500
-Wire Wire Line
-	2450 2500 3300 2500
-Wire Wire Line
-	2800 2500 2800 3450
-Wire Wire Line
-	2800 3450 3300 3450
-Connection ~ 2800 2500
-Wire Wire Line
-	1650 2400 1650 1900
-Wire Wire Line
-	1650 1900 3300 1900
-Connection ~ 1650 2400
-Wire Wire Line
-	3300 2000 2850 2000
-Wire Wire Line
-	2850 2000 2850 3000
-Wire Wire Line
-	2850 3000 1650 3000
-Wire Wire Line
-	1650 3000 1650 3300
-Connection ~ 1650 3300
-Wire Wire Line
-	2850 2400 3300 2400
-Connection ~ 2850 2400
-Wire Wire Line
-	2950 1900 2950 2950
-Wire Wire Line
-	2950 2950 3300 2950
-Connection ~ 2950 1900
-Wire Wire Line
-	3100 3550 3100 3050
-Wire Wire Line
-	3100 3050 3300 3050
-Connection ~ 3100 3550
-Wire Wire Line
-	1650 3900 1650 4150
-Wire Wire Line
-	1650 3900 3050 3900
-Wire Wire Line
-	3050 3900 3050 5150
-Wire Wire Line
-	3050 4050 3300 4050
-Connection ~ 1650 4150
-Wire Wire Line
-	1750 4900 1750 5150
-Wire Wire Line
-	1750 5150 2750 5150
-Connection ~ 1750 4900
-Wire Wire Line
-	2750 5150 2750 4150
-Wire Wire Line
-	2750 4150 3300 4150
-Wire Wire Line
-	2750 4750 3250 4750
-Connection ~ 2750 4750
-Wire Wire Line
-	3050 5150 3250 5150
-Connection ~ 3050 4050
-$Comp
-L d_and U15
-U 1 1 5CF106B1
-P 6600 1850
-F 0 "U15" H 6600 1850 60  0000 C CNN
-F 1 "d_and" H 6650 1950 60  0000 C CNN
-F 2 "" H 6600 1850 60  0000 C CNN
-F 3 "" H 6600 1850 60  0000 C CNN
-	1    6600 1850
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U16
-U 1 1 5CF10756
-P 6600 2350
-F 0 "U16" H 6600 2350 60  0000 C CNN
-F 1 "d_and" H 6650 2450 60  0000 C CNN
-F 2 "" H 6600 2350 60  0000 C CNN
-F 3 "" H 6600 2350 60  0000 C CNN
-	1    6600 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U17
-U 1 1 5CF107A1
-P 6600 2800
-F 0 "U17" H 6600 2800 60  0000 C CNN
-F 1 "d_and" H 6650 2900 60  0000 C CNN
-F 2 "" H 6600 2800 60  0000 C CNN
-F 3 "" H 6600 2800 60  0000 C CNN
-	1    6600 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U18
-U 1 1 5CF107E9
-P 6600 3200
-F 0 "U18" H 6600 3200 60  0000 C CNN
-F 1 "d_and" H 6650 3300 60  0000 C CNN
-F 2 "" H 6600 3200 60  0000 C CNN
-F 3 "" H 6600 3200 60  0000 C CNN
-	1    6600 3200
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U19
-U 1 1 5CF10834
-P 6600 3650
-F 0 "U19" H 6600 3650 60  0000 C CNN
-F 1 "d_and" H 6650 3750 60  0000 C CNN
-F 2 "" H 6600 3650 60  0000 C CNN
-F 3 "" H 6600 3650 60  0000 C CNN
-	1    6600 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U20
-U 1 1 5CF1087E
-P 6600 4050
-F 0 "U20" H 6600 4050 60  0000 C CNN
-F 1 "d_and" H 6650 4150 60  0000 C CNN
-F 2 "" H 6600 4050 60  0000 C CNN
-F 3 "" H 6600 4050 60  0000 C CNN
-	1    6600 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U21
-U 1 1 5CF108F9
-P 6600 4450
-F 0 "U21" H 6600 4450 60  0000 C CNN
-F 1 "d_and" H 6650 4550 60  0000 C CNN
-F 2 "" H 6600 4450 60  0000 C CNN
-F 3 "" H 6600 4450 60  0000 C CNN
-	1    6600 4450
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U13
-U 1 1 5CF1094D
-P 6550 4900
-F 0 "U13" H 6550 4900 60  0000 C CNN
-F 1 "d_and" H 6600 5000 60  0000 C CNN
-F 2 "" H 6550 4900 60  0000 C CNN
-F 3 "" H 6550 4900 60  0000 C CNN
-	1    6550 4900
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U14
-U 1 1 5CF109A6
-P 6550 5350
-F 0 "U14" H 6550 5350 60  0000 C CNN
-F 1 "d_and" H 6600 5450 60  0000 C CNN
-F 2 "" H 6550 5350 60  0000 C CNN
-F 3 "" H 6550 5350 60  0000 C CNN
-	1    6550 5350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF11966
-P 1150 2400
-F 0 "U1" H 1200 2500 30  0000 C CNN
-F 1 "PORT" H 1150 2400 30  0000 C CNN
-F 2 "" H 1150 2400 60  0000 C CNN
-F 3 "" H 1150 2400 60  0000 C CNN
-	10   1150 2400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF119D4
-P 1150 3300
-F 0 "U1" H 1200 3400 30  0000 C CNN
-F 1 "PORT" H 1150 3300 30  0000 C CNN
-F 2 "" H 1150 3300 60  0000 C CNN
-F 3 "" H 1150 3300 60  0000 C CNN
-	13   1150 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF11AFC
-P 1200 4150
-F 0 "U1" H 1250 4250 30  0000 C CNN
-F 1 "PORT" H 1200 4150 30  0000 C CNN
-F 2 "" H 1200 4150 60  0000 C CNN
-F 3 "" H 1200 4150 60  0000 C CNN
-	12   1200 4150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF11B6B
-P 1200 4900
-F 0 "U1" H 1250 5000 30  0000 C CNN
-F 1 "PORT" H 1200 4900 30  0000 C CNN
-F 2 "" H 1200 4900 60  0000 C CNN
-F 3 "" H 1200 4900 60  0000 C CNN
-	11   1200 4900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF11BDB
-P 8000 1800
-F 0 "U1" H 8050 1900 30  0000 C CNN
-F 1 "PORT" H 8000 1800 30  0000 C CNN
-F 2 "" H 8000 1800 60  0000 C CNN
-F 3 "" H 8000 1800 60  0000 C CNN
-	3    8000 1800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF11F59
-P 8000 2300
-F 0 "U1" H 8050 2400 30  0000 C CNN
-F 1 "PORT" H 8000 2300 30  0000 C CNN
-F 2 "" H 8000 2300 60  0000 C CNN
-F 3 "" H 8000 2300 60  0000 C CNN
-	14   8000 2300
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF11FC5
-P 8000 2750
-F 0 "U1" H 8050 2850 30  0000 C CNN
-F 1 "PORT" H 8000 2750 30  0000 C CNN
-F 2 "" H 8000 2750 60  0000 C CNN
-F 3 "" H 8000 2750 60  0000 C CNN
-	2    8000 2750
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 15 1 5CF1204F
-P 8000 3150
-F 0 "U1" H 8050 3250 30  0000 C CNN
-F 1 "PORT" H 8000 3150 30  0000 C CNN
-F 2 "" H 8000 3150 60  0000 C CNN
-F 3 "" H 8000 3150 60  0000 C CNN
-	15   8000 3150
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF120C5
-P 7950 3600
-F 0 "U1" H 8000 3700 30  0000 C CNN
-F 1 "PORT" H 7950 3600 30  0000 C CNN
-F 2 "" H 7950 3600 60  0000 C CNN
-F 3 "" H 7950 3600 60  0000 C CNN
-	1    7950 3600
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF1213C
-P 7950 4000
-F 0 "U1" H 8000 4100 30  0000 C CNN
-F 1 "PORT" H 7950 4000 30  0000 C CNN
-F 2 "" H 7950 4000 60  0000 C CNN
-F 3 "" H 7950 4000 60  0000 C CNN
-	6    7950 4000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CF121B2
-P 7900 4400
-F 0 "U1" H 7950 4500 30  0000 C CNN
-F 1 "PORT" H 7900 4400 30  0000 C CNN
-F 2 "" H 7900 4400 60  0000 C CNN
-F 3 "" H 7900 4400 60  0000 C CNN
-	7    7900 4400
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF1223D
-P 7900 4850
-F 0 "U1" H 7950 4950 30  0000 C CNN
-F 1 "PORT" H 7900 4850 30  0000 C CNN
-F 2 "" H 7900 4850 60  0000 C CNN
-F 3 "" H 7900 4850 60  0000 C CNN
-	4    7900 4850
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF1237B
-P 7900 5300
-F 0 "U1" H 7950 5400 30  0000 C CNN
-F 1 "PORT" H 7900 5300 30  0000 C CNN
-F 2 "" H 7900 5300 60  0000 C CNN
-F 3 "" H 7900 5300 60  0000 C CNN
-	9    7900 5300
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7750 1800 7050 1800
-Wire Wire Line
-	7050 2300 7750 2300
-Wire Wire Line
-	7750 2750 7050 2750
-Wire Wire Line
-	7050 3150 7750 3150
-Wire Wire Line
-	7700 3600 7050 3600
-Wire Wire Line
-	7050 4000 7700 4000
-Wire Wire Line
-	7650 4400 7050 4400
-Wire Wire Line
-	7000 4850 7650 4850
-Wire Wire Line
-	7650 5300 7000 5300
-$Comp
-L d_and U22
-U 1 1 5CF14904
-P 6550 5800
-F 0 "U22" H 6550 5800 60  0000 C CNN
-F 1 "d_and" H 6600 5900 60  0000 C CNN
-F 2 "" H 6550 5800 60  0000 C CNN
-F 3 "" H 6550 5800 60  0000 C CNN
-	1    6550 5800
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4200 1950 4600 1950
-Wire Wire Line
-	4600 1750 4600 5250
-Wire Wire Line
-	4600 1750 6150 1750
-Wire Wire Line
-	4600 5250 6100 5250
-Connection ~ 4600 1950
-Wire Wire Line
-	6100 5800 5900 5800
-Wire Wire Line
-	5900 5800 5900 5350
-Wire Wire Line
-	5900 5350 6100 5350
-Wire Wire Line
-	5850 4900 6100 4900
-Wire Wire Line
-	5850 3650 5850 4900
-Wire Wire Line
-	5850 4450 6150 4450
-Wire Wire Line
-	5850 4050 6150 4050
-Connection ~ 5850 4450
-Wire Wire Line
-	5850 3650 6150 3650
-Connection ~ 5850 4050
-Wire Wire Line
-	5050 3200 6150 3200
-Wire Wire Line
-	5850 1850 5850 3200
-Wire Wire Line
-	5850 2800 6150 2800
-Wire Wire Line
-	5850 2350 6150 2350
-Connection ~ 5850 2800
-Wire Wire Line
-	5850 1850 6150 1850
-Connection ~ 5850 2350
-Wire Wire Line
-	4200 2450 4700 2450
-Wire Wire Line
-	4700 2250 4700 5700
-Wire Wire Line
-	4700 2250 6150 2250
-Wire Wire Line
-	4200 3000 4800 3000
-Wire Wire Line
-	4800 2700 4800 4350
-Wire Wire Line
-	4800 2700 6150 2700
-Wire Wire Line
-	4700 5700 6100 5700
-Connection ~ 4700 2450
-Wire Wire Line
-	6150 3550 4600 3550
-Connection ~ 4600 3550
-Wire Wire Line
-	6150 3950 4700 3950
-Connection ~ 4700 3950
-Wire Wire Line
-	4800 4350 6150 4350
-Connection ~ 4800 3000
-Wire Wire Line
-	4200 3500 4900 3500
-Wire Wire Line
-	4900 3100 4900 4800
-Wire Wire Line
-	4900 3100 6150 3100
-Wire Wire Line
-	4900 4800 6100 4800
-Connection ~ 4900 3500
-Wire Wire Line
-	4200 4100 5050 4100
-Wire Wire Line
-	5050 4100 5050 3200
-Connection ~ 5850 3200
-Wire Wire Line
-	4150 4700 5850 4700
-Connection ~ 5850 4700
-Wire Wire Line
-	4150 5200 4500 5200
-Wire Wire Line
-	4500 5200 4500 5550
-Wire Wire Line
-	4500 5550 5900 5550
-Connection ~ 5900 5550
-$Comp
-L PORT U1
-U 5 1 5CF1563E
-P 7950 5750
-F 0 "U1" H 8000 5850 30  0000 C CNN
-F 1 "PORT" H 7950 5750 30  0000 C CNN
-F 2 "" H 7950 5750 60  0000 C CNN
-F 3 "" H 7950 5750 60  0000 C CNN
-	5    7950 5750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	7700 5750 7000 5750
-$Comp
-L PORT U1
-U 8 1 5CF15953
-P 9550 4800
-F 0 "U1" H 9600 4900 30  0000 C CNN
-F 1 "PORT" H 9550 4800 30  0000 C CNN
-F 2 "" H 9550 4800 60  0000 C CNN
-F 3 "" H 9550 4800 60  0000 C CNN
-	8    9550 4800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 16 1 5CF15A07
-P 9550 5250
-F 0 "U1" H 9600 5350 30  0000 C CNN
-F 1 "PORT" H 9550 5250 30  0000 C CNN
-F 2 "" H 9550 5250 60  0000 C CNN
-F 3 "" H 9550 5250 60  0000 C CNN
-	16   9550 5250
-	-1   0    0    1   
-$EndComp
-NoConn ~ 9300 4800
-NoConn ~ 9300 5250
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4028/4028.sub b/src/SubcircuitLibrary/4028/4028.sub
deleted file mode 100644
index 828e0b67..00000000
--- a/src/SubcircuitLibrary/4028/4028.sub
+++ /dev/null
@@ -1,90 +0,0 @@
-* Subcircuit 4028
-.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
-* u9  net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
-* u10  net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
-* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
-* u12  net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
-* u6  net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
-* u7  net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
-* u8  net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
-* u2  net-_u1-pad10_ net-_u11-pad1_ d_inverter
-* u3  net-_u1-pad13_ net-_u10-pad2_ d_inverter
-* u4  net-_u1-pad12_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad11_ net-_u5-pad2_ d_inverter
-* u15  net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
-* u16  net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
-* u17  net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
-* u18  net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
-* u19  net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
-* u20  net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
-* u21  net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
-* u13  net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
-* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
-* u22  net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
-a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
-a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
-a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
-a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
-a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
-a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
-a8 net-_u1-pad10_ net-_u11-pad1_ u2
-a9 net-_u1-pad13_ net-_u10-pad2_ u3
-a10 net-_u1-pad12_ net-_u4-pad2_ u4
-a11 net-_u1-pad11_ net-_u5-pad2_ u5
-a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
-a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
-a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
-a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
-a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
-a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
-a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
-a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
-a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
-a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4028
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml
deleted file mode 100644
index 189fb200..00000000
--- a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4028/analysis b/src/SubcircuitLibrary/4028/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4028/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4072/4072-cache.lib b/src/SubcircuitLibrary/4072/4072-cache.lib
deleted file mode 100644
index a3c1c972..00000000
--- a/src/SubcircuitLibrary/4072/4072-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4072/4072.cir b/src/SubcircuitLibrary/4072/4072.cir
deleted file mode 100644
index 0f2e56f0..00000000
--- a/src/SubcircuitLibrary/4072/4072.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4072\4072.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 10:17:30
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or		
-U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or		
-U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_or		
-U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_or		
-
-.end
diff --git a/src/SubcircuitLibrary/4072/4072.cir.out b/src/SubcircuitLibrary/4072/4072.cir.out
deleted file mode 100644
index 61e8e949..00000000
--- a/src/SubcircuitLibrary/4072/4072.cir.out
+++ /dev/null
@@ -1,36 +0,0 @@
-* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
-
-* u2  net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
-a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4072/4072.pro b/src/SubcircuitLibrary/4072/4072.pro
deleted file mode 100644
index 64662931..00000000
--- a/src/SubcircuitLibrary/4072/4072.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=05/31/19 10:11:54
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/4072/4072.sch b/src/SubcircuitLibrary/4072/4072.sch
deleted file mode 100644
index 782d3e69..00000000
--- a/src/SubcircuitLibrary/4072/4072.sch
+++ /dev/null
@@ -1,334 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:4002-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5CF0AF1E
-P 4750 2900
-F 0 "U2" H 4750 2900 60  0000 C CNN
-F 1 "d_or" H 4750 3000 60  0000 C CNN
-F 2 "" H 4750 2900 60  0000 C CNN
-F 3 "" H 4750 2900 60  0000 C CNN
-	1    4750 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5CF0AF1F
-P 4750 3450
-F 0 "U3" H 4750 3450 60  0000 C CNN
-F 1 "d_or" H 4750 3550 60  0000 C CNN
-F 2 "" H 4750 3450 60  0000 C CNN
-F 3 "" H 4750 3450 60  0000 C CNN
-	1    4750 3450
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5200 2850 5400 2850
-Wire Wire Line
-	5400 2850 5400 3000
-Wire Wire Line
-	5400 3000 5550 3000
-Wire Wire Line
-	5200 3400 5400 3400
-Wire Wire Line
-	5400 3400 5400 3100
-Wire Wire Line
-	5400 3100 5550 3100
-Wire Wire Line
-	5650 5350 6050 5350
-Wire Wire Line
-	5650 5550 6050 5550
-Wire Wire Line
-	5650 5800 6050 5800
-Wire Wire Line
-	5650 6000 6050 6000
-NoConn ~ 5650 5350
-NoConn ~ 5650 5550
-NoConn ~ 5650 5800
-NoConn ~ 5650 6000
-$Comp
-L PORT U1
-U 5 1 5CF0AF21
-P 3850 2800
-F 0 "U1" H 3900 2900 30  0000 C CNN
-F 1 "PORT" H 3850 2800 30  0000 C CNN
-F 2 "" H 3850 2800 60  0000 C CNN
-F 3 "" H 3850 2800 60  0000 C CNN
-	5    3850 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF0AF22
-P 3900 3050
-F 0 "U1" H 3950 3150 30  0000 C CNN
-F 1 "PORT" H 3900 3050 30  0000 C CNN
-F 2 "" H 3900 3050 60  0000 C CNN
-F 3 "" H 3900 3050 60  0000 C CNN
-	2    3900 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF0AF23
-P 3900 3250
-F 0 "U1" H 3950 3350 30  0000 C CNN
-F 1 "PORT" H 3900 3250 30  0000 C CNN
-F 2 "" H 3900 3250 60  0000 C CNN
-F 3 "" H 3900 3250 60  0000 C CNN
-	3    3900 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF0AF24
-P 3900 3550
-F 0 "U1" H 3950 3650 30  0000 C CNN
-F 1 "PORT" H 3900 3550 30  0000 C CNN
-F 2 "" H 3900 3550 60  0000 C CNN
-F 3 "" H 3900 3550 60  0000 C CNN
-	4    3900 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF0AF25
-P 6950 3050
-F 0 "U1" H 7000 3150 30  0000 C CNN
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-	8    6300 5800
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diff --git a/src/SubcircuitLibrary/4072/4072.sub b/src/SubcircuitLibrary/4072/4072.sub
deleted file mode 100644
index 174ea00d..00000000
--- a/src/SubcircuitLibrary/4072/4072.sub
+++ /dev/null
@@ -1,30 +0,0 @@
-* Subcircuit 4072
-.subckt 4072 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
-* u2  net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
-* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
-a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4072
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4072/4072_Previous_Values.xml b/src/SubcircuitLibrary/4072/4072_Previous_Values.xml
deleted file mode 100644
index 0ccd120c..00000000
--- a/src/SubcircuitLibrary/4072/4072_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_or<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4072/analysis b/src/SubcircuitLibrary/4072/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4072/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/4073/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/4073/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/4073/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/4073/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/4073/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
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-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/4073/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib
deleted file mode 100644
index 4ee605a2..00000000
--- a/src/SubcircuitLibrary/4073/4073-cache.lib
+++ /dev/null
@@ -1,62 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0  -150 200  200 200 N
-P 3 0 1 0  -150 200  -150 -100  200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir
deleted file mode 100644
index e159f055..00000000
--- a/src/SubcircuitLibrary/4073/4073.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
-X3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and		
-X2  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and		
-
-.end
diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out
deleted file mode 100644
index b25337cd..00000000
--- a/src/SubcircuitLibrary/4073/4073.cir.out
+++ /dev/null
@@ -1,16 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro
deleted file mode 100644
index 94cd9bd4..00000000
--- a/src/SubcircuitLibrary/4073/4073.pro
+++ /dev/null
@@ -1,43 +0,0 @@
-update=05/31/19 16:37:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch
deleted file mode 100644
index 045208e6..00000000
--- a/src/SubcircuitLibrary/4073/4073.sch
+++ /dev/null
@@ -1,263 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5CF10AEA
-P 4550 2650
-F 0 "X1" H 4650 2600 60  0000 C CNN
-F 1 "3_and" H 4700 2800 60  0000 C CNN
-F 2 "" H 4550 2650 60  0000 C CNN
-F 3 "" H 4550 2650 60  0000 C CNN
-	1    4550 2650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF10B72
-P 3100 2200
-F 0 "U1" H 3150 2300 30  0000 C CNN
-F 1 "PORT" H 3100 2200 30  0000 C CNN
-F 2 "" H 3100 2200 60  0000 C CNN
-F 3 "" H 3100 2200 60  0000 C CNN
-	1    3100 2200
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF10BC9
-P 3100 2500
-F 0 "U1" H 3150 2600 30  0000 C CNN
-F 1 "PORT" H 3100 2500 30  0000 C CNN
-F 2 "" H 3100 2500 60  0000 C CNN
-F 3 "" H 3100 2500 60  0000 C CNN
-	2    3100 2500
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF10BEA
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
-F 1 "PORT" H 3100 2850 30  0000 C CNN
-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	8    3100 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF10C10
-P 6200 2600
-F 0 "U1" H 6250 2700 30  0000 C CNN
-F 1 "PORT" H 6200 2600 30  0000 C CNN
-F 2 "" H 6200 2600 60  0000 C CNN
-F 3 "" H 6200 2600 60  0000 C CNN
-	9    6200 2600
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5950 2600 5050 2600
-Wire Wire Line
-	4200 2500 4200 2200
-Wire Wire Line
-	4200 2200 3350 2200
-Wire Wire Line
-	3350 2500 3850 2500
-Wire Wire Line
-	3850 2500 3850 2600
-Wire Wire Line
-	3850 2600 4200 2600
-Wire Wire Line
-	4200 2700 4200 2850
-Wire Wire Line
-	4200 2850 3350 2850
-$Comp
-L 3_and X3
-U 1 1 5CF10DE5
-P 4600 4100
-F 0 "X3" H 4700 4050 60  0000 C CNN
-F 1 "3_and" H 4750 4250 60  0000 C CNN
-F 2 "" H 4600 4100 60  0000 C CNN
-F 3 "" H 4600 4100 60  0000 C CNN
-	1    4600 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF10DEB
-P 3150 3650
-F 0 "U1" H 3200 3750 30  0000 C CNN
-F 1 "PORT" H 3150 3650 30  0000 C CNN
-F 2 "" H 3150 3650 60  0000 C CNN
-F 3 "" H 3150 3650 60  0000 C CNN
-	3    3150 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF10DF1
-P 3150 3950
-F 0 "U1" H 3200 4050 30  0000 C CNN
-F 1 "PORT" H 3150 3950 30  0000 C CNN
-F 2 "" H 3150 3950 60  0000 C CNN
-F 3 "" H 3150 3950 60  0000 C CNN
-	4    3150 3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CF10DF7
-P 3150 4300
-F 0 "U1" H 3200 4400 30  0000 C CNN
-F 1 "PORT" H 3150 4300 30  0000 C CNN
-F 2 "" H 3150 4300 60  0000 C CNN
-F 3 "" H 3150 4300 60  0000 C CNN
-	5    3150 4300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF10DFD
-P 6250 4050
-F 0 "U1" H 6300 4150 30  0000 C CNN
-F 1 "PORT" H 6250 4050 30  0000 C CNN
-F 2 "" H 6250 4050 60  0000 C CNN
-F 3 "" H 6250 4050 60  0000 C CNN
-	6    6250 4050
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	6000 4050 5100 4050
-Wire Wire Line
-	4250 3950 4250 3650
-Wire Wire Line
-	4250 3650 3400 3650
-Wire Wire Line
-	3400 3950 3900 3950
-Wire Wire Line
-	3900 3950 3900 4050
-Wire Wire Line
-	3900 4050 4250 4050
-Wire Wire Line
-	4250 4150 4250 4300
-Wire Wire Line
-	4250 4300 3400 4300
-$Comp
-L 3_and X2
-U 1 1 5CF10E9C
-P 4550 5450
-F 0 "X2" H 4650 5400 60  0000 C CNN
-F 1 "3_and" H 4700 5600 60  0000 C CNN
-F 2 "" H 4550 5450 60  0000 C CNN
-F 3 "" H 4550 5450 60  0000 C CNN
-	1    4550 5450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF10EA2
-P 3100 5000
-F 0 "U1" H 3150 5100 30  0000 C CNN
-F 1 "PORT" H 3100 5000 30  0000 C CNN
-F 2 "" H 3100 5000 60  0000 C CNN
-F 3 "" H 3100 5000 60  0000 C CNN
-	11   3100 5000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF10EA8
-P 3100 5300
-F 0 "U1" H 3150 5400 30  0000 C CNN
-F 1 "PORT" H 3100 5300 30  0000 C CNN
-F 2 "" H 3100 5300 60  0000 C CNN
-F 3 "" H 3100 5300 60  0000 C CNN
-	12   3100 5300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF10EAE
-P 3100 5650
-F 0 "U1" H 3150 5750 30  0000 C CNN
-F 1 "PORT" H 3100 5650 30  0000 C CNN
-F 2 "" H 3100 5650 60  0000 C CNN
-F 3 "" H 3100 5650 60  0000 C CNN
-	13   3100 5650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF10EB4
-P 6200 5400
-F 0 "U1" H 6250 5500 30  0000 C CNN
-F 1 "PORT" H 6200 5400 30  0000 C CNN
-F 2 "" H 6200 5400 60  0000 C CNN
-F 3 "" H 6200 5400 60  0000 C CNN
-	10   6200 5400
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5950 5400 5050 5400
-Wire Wire Line
-	4200 5300 4200 5000
-Wire Wire Line
-	4200 5000 3350 5000
-Wire Wire Line
-	3350 5300 3850 5300
-Wire Wire Line
-	3850 5300 3850 5400
-Wire Wire Line
-	3850 5400 4200 5400
-Wire Wire Line
-	4200 5500 4200 5650
-Wire Wire Line
-	4200 5650 3350 5650
-$Comp
-L PORT U1
-U 7 1 5CF11A2A
-P 7500 4100
-F 0 "U1" H 7550 4200 30  0000 C CNN
-F 1 "PORT" H 7500 4100 30  0000 C CNN
-F 2 "" H 7500 4100 60  0000 C CNN
-F 3 "" H 7500 4100 60  0000 C CNN
-	7    7500 4100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF11A8A
-P 7550 4600
-F 0 "U1" H 7600 4700 30  0000 C CNN
-F 1 "PORT" H 7550 4600 30  0000 C CNN
-F 2 "" H 7550 4600 60  0000 C CNN
-F 3 "" H 7550 4600 60  0000 C CNN
-	14   7550 4600
-	-1   0    0    1   
-$EndComp
-NoConn ~ 7250 4100
-NoConn ~ 7300 4600
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub
deleted file mode 100644
index 15208169..00000000
--- a/src/SubcircuitLibrary/4073/4073.sub
+++ /dev/null
@@ -1,10 +0,0 @@
-* Subcircuit 4073
-.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-* Control Statements
-
-.ends 4073
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml
deleted file mode 100644
index 5acac768..00000000
--- a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4073/analysis b/src/SubcircuitLibrary/4073/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4073/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
deleted file mode 100644
index 155f5e60..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir
deleted file mode 100644
index b338b7b5..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
deleted file mode 100644
index adb6b01b..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro
deleted file mode 100644
index 9daf26bc..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch
deleted file mode 100644
index 11896865..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60  0000 C CNN
-F 1 "d_or" H 4300 3050 60  0000 C CNN
-F 2 "" H 4300 2950 60  0000 C CNN
-F 3 "" H 4300 2950 60  0000 C CNN
-	1    4300 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60  0000 C CNN
-F 1 "d_or" H 4300 3450 60  0000 C CNN
-F 2 "" H 4300 3350 60  0000 C CNN
-F 3 "" H 4300 3350 60  0000 C CNN
-	1    4300 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60  0000 C CNN
-F 1 "d_or" H 5250 3250 60  0000 C CNN
-F 2 "" H 5250 3150 60  0000 C CNN
-F 3 "" H 5250 3150 60  0000 C CNN
-	1    5250 3150
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-$EndComp
-Wire Wire Line
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-	3600 2950 3600 3000
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-Wire Wire Line
-	5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
-F 1 "PORT" H 3100 2850 30  0000 C CNN
-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	1    3100 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
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-F 0 "U1" H 3150 3100 30  0000 C CNN
-F 1 "PORT" H 3100 3000 30  0000 C CNN
-F 2 "" H 3100 3000 60  0000 C CNN
-F 3 "" H 3100 3000 60  0000 C CNN
-	2    3100 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30  0000 C CNN
-F 1 "PORT" H 3100 3250 30  0000 C CNN
-F 2 "" H 3100 3250 60  0000 C CNN
-F 3 "" H 3100 3250 60  0000 C CNN
-	3    3100 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30  0000 C CNN
-F 1 "PORT" H 3100 3400 30  0000 C CNN
-F 2 "" H 3100 3400 60  0000 C CNN
-F 3 "" H 3100 3400 60  0000 C CNN
-	4    3100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30  0000 C CNN
-F 1 "PORT" H 6450 3100 30  0000 C CNN
-F 2 "" H 6450 3100 60  0000 C CNN
-F 3 "" H 6450 3100 60  0000 C CNN
-	5    6450 3100
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2850 0    60   ~ 12
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-Text Notes 3450 3250 0    60   ~ 12
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-Text Notes 3450 3400 0    60   ~ 12
-in4
-Text Notes 5800 3100 0    60   ~ 12
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub
deleted file mode 100644
index d1fd3a24..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml
deleted file mode 100644
index 0683d9eb..00000000
--- a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_OR/analysis b/src/SubcircuitLibrary/4_OR/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4_OR/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/4_and/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/4_and/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/4_and/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/4_and/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/4_and/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
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-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
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-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
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-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
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-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
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-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/4_and/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib
deleted file mode 100644
index 60f1a83d..00000000
--- a/src/SubcircuitLibrary/4_and/4_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib
deleted file mode 100644
index e3833051..00000000
--- a/src/SubcircuitLibrary/4_and/4_and-rescue.lib
+++ /dev/null
@@ -1,22 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir
deleted file mode 100644
index fdf2e107..00000000
--- a/src/SubcircuitLibrary/4_and/4_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out
deleted file mode 100644
index f40e5bc6..00000000
--- a/src/SubcircuitLibrary/4_and/4_and.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro
deleted file mode 100644
index 9c0be79e..00000000
--- a/src/SubcircuitLibrary/4_and/4_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch
deleted file mode 100644
index f5e8febd..00000000
--- a/src/SubcircuitLibrary/4_and/4_and.sch
+++ /dev/null
@@ -1,151 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60  0000 C CNN
-F 1 "3_and" H 4650 4000 60  0000 C CNN
-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60  0000 C CNN
-F 1 "d_and" H 5500 3500 60  0000 C CNN
-F 2 "" H 5450 3400 60  0000 C CNN
-F 3 "" H 5450 3400 60  0000 C CNN
-	1    5450 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5000 3100 5000 3300
-Wire Wire Line
-	4150 3000 4150 2700
-Wire Wire Line
-	4150 2700 3200 2700
-Wire Wire Line
-	4150 3100 4000 3100
-Wire Wire Line
-	4000 3100 4000 3000
-Wire Wire Line
-	4000 3000 3200 3000
-Wire Wire Line
-	4150 3200 4150 3300
-Wire Wire Line
-	4150 3300 3250 3300
-Wire Wire Line
-	5000 3400 5000 3550
-Wire Wire Line
-	5000 3550 3250 3550
-Wire Wire Line
-	5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30  0000 C CNN
-F 1 "PORT" H 2950 2700 30  0000 C CNN
-F 2 "" H 2950 2700 60  0000 C CNN
-F 3 "" H 2950 2700 60  0000 C CNN
-	1    2950 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30  0000 C CNN
-F 1 "PORT" H 2950 3000 30  0000 C CNN
-F 2 "" H 2950 3000 60  0000 C CNN
-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30  0000 C CNN
-F 1 "PORT" H 3000 3300 30  0000 C CNN
-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30  0000 C CNN
-F 1 "PORT" H 3000 3550 30  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	4    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30  0000 C CNN
-F 1 "PORT" H 6750 3350 30  0000 C CNN
-F 2 "" H 6750 3350 60  0000 C CNN
-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2650 0    60   ~ 12
-in1
-Text Notes 3450 2950 0    60   ~ 12
-in2
-Text Notes 3500 3300 0    60   ~ 12
-in3
-Text Notes 3500 3550 0    60   ~ 12
-in4
-Text Notes 6150 3350 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub
deleted file mode 100644
index 8663f37e..00000000
--- a/src/SubcircuitLibrary/4_and/4_and.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml
deleted file mode 100644
index f2ba0130..00000000
--- a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_and/analysis b/src/SubcircuitLibrary/4_and/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4_and/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib
deleted file mode 100644
index 0a3ccf7f..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir b/src/SubcircuitLibrary/4_bit_FA/3_and.cir
deleted file mode 100644
index 15f8954d..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out
deleted file mode 100644
index e3c96645..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.pro b/src/SubcircuitLibrary/4_bit_FA/3_and.pro
deleted file mode 100644
index 1b535492..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sch b/src/SubcircuitLibrary/4_bit_FA/3_and.sch
deleted file mode 100644
index 6c8d3d4a..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and.sch
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
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-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sub b/src/SubcircuitLibrary/4_bit_FA/3_and.sub
deleted file mode 100644
index b949ae4f..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib
deleted file mode 100644
index a3c1c972..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir
deleted file mode 100644
index 7adbf177..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out
deleted file mode 100644
index 4388b975..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro
deleted file mode 100644
index 8bd4bbf5..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=03/28/19 22:43:48
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch
deleted file mode 100644
index 2f28896c..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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-Comment4 ""
-$EndDescr
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-F 3 "" H 4300 2950 60  0000 C CNN
-	1    4300 2950
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-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60  0000 C CNN
-F 1 "d_or" H 4300 3450 60  0000 C CNN
-F 2 "" H 4300 3350 60  0000 C CNN
-F 3 "" H 4300 3350 60  0000 C CNN
-	1    4300 3350
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-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60  0000 C CNN
-F 1 "d_or" H 5250 3250 60  0000 C CNN
-F 2 "" H 5250 3150 60  0000 C CNN
-F 3 "" H 5250 3150 60  0000 C CNN
-	1    5250 3150
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-$EndComp
-Wire Wire Line
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-	3350 2850 3850 2850
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-	5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
-F 1 "PORT" H 3100 2850 30  0000 C CNN
-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	1    3100 2850
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-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
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-F 1 "PORT" H 3100 3000 30  0000 C CNN
-F 2 "" H 3100 3000 60  0000 C CNN
-F 3 "" H 3100 3000 60  0000 C CNN
-	2    3100 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
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-F 0 "U1" H 3150 3350 30  0000 C CNN
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-F 2 "" H 3100 3250 60  0000 C CNN
-F 3 "" H 3100 3250 60  0000 C CNN
-	3    3100 3250
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
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-F 2 "" H 3100 3400 60  0000 C CNN
-F 3 "" H 3100 3400 60  0000 C CNN
-	4    3100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30  0000 C CNN
-F 1 "PORT" H 6450 3100 30  0000 C CNN
-F 2 "" H 6450 3100 60  0000 C CNN
-F 3 "" H 6450 3100 60  0000 C CNN
-	5    6450 3100
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2850 0    60   ~ 12
-in1
-Text Notes 3450 3000 0    60   ~ 12
-in2
-Text Notes 3450 3250 0    60   ~ 12
-in3
-Text Notes 3450 3400 0    60   ~ 12
-in4
-Text Notes 5800 3100 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
deleted file mode 100644
index 53fc8b33..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml
deleted file mode 100644
index 23698d37..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib
deleted file mode 100644
index 4cf915be..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir b/src/SubcircuitLibrary/4_bit_FA/4_and.cir
deleted file mode 100644
index 25e839cd..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out
deleted file mode 100644
index 6e35b18a..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.pro b/src/SubcircuitLibrary/4_bit_FA/4_and.pro
deleted file mode 100644
index cc0f1b93..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/26/19 18:58:33
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sch b/src/SubcircuitLibrary/4_bit_FA/4_and.sch
deleted file mode 100644
index bcc3cecf..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and.sch
+++ /dev/null
@@ -1,139 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60  0000 C CNN
-F 1 "3_and" H 4650 4000 60  0000 C CNN
-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60  0000 C CNN
-F 1 "d_and" H 5500 3500 60  0000 C CNN
-F 2 "" H 5450 3400 60  0000 C CNN
-F 3 "" H 5450 3400 60  0000 C CNN
-	1    5450 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5000 3100 5000 3300
-Wire Wire Line
-	4150 3000 4150 2700
-Wire Wire Line
-	4150 2700 3200 2700
-Wire Wire Line
-	4150 3100 4000 3100
-Wire Wire Line
-	4000 3100 4000 3000
-Wire Wire Line
-	4000 3000 3200 3000
-Wire Wire Line
-	4150 3200 4150 3300
-Wire Wire Line
-	4150 3300 3250 3300
-Wire Wire Line
-	5000 3400 5000 3550
-Wire Wire Line
-	5000 3550 3250 3550
-Wire Wire Line
-	5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30  0000 C CNN
-F 1 "PORT" H 2950 2700 30  0000 C CNN
-F 2 "" H 2950 2700 60  0000 C CNN
-F 3 "" H 2950 2700 60  0000 C CNN
-	1    2950 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30  0000 C CNN
-F 1 "PORT" H 2950 3000 30  0000 C CNN
-F 2 "" H 2950 3000 60  0000 C CNN
-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30  0000 C CNN
-F 1 "PORT" H 3000 3300 30  0000 C CNN
-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30  0000 C CNN
-F 1 "PORT" H 3000 3550 30  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	4    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30  0000 C CNN
-F 1 "PORT" H 6750 3350 30  0000 C CNN
-F 2 "" H 6750 3350 60  0000 C CNN
-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
-	-1   0    0    1   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sub b/src/SubcircuitLibrary/4_bit_FA/4_and.sub
deleted file mode 100644
index bf20b628..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml
deleted file mode 100644
index f2ba0130..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib
deleted file mode 100644
index f787854a..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib
+++ /dev/null
@@ -1,172 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_OR
-#
-DEF 4_OR X 0 40 Y Y 1 F N
-F0 "X" 3900 3050 60 H V C CNN
-F1 "4_OR" 3900 3250 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900
-A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150
-A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150
-P 2 0 1 0  3550 2900  3900 2900 N
-P 2 0 1 0  3550 3400  3900 3400 N
-X in1 1 3400 3300 200 R 50 50 1 1 I
-X in2 2 3400 3200 200 R 50 50 1 1 I
-X in3 3 3400 3100 200 R 50 50 1 1 I
-X in4 4 3400 3000 200 R 50 50 1 1 I
-X out 5 4300 3150 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0  1250 1300  1600 1300 N
-P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir
deleted file mode 100644
index 8fe97f7e..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir
+++ /dev/null
@@ -1,48 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_bit_FA\4_bit_FA.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:04:20
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U16-Pad2_ d_or		
-U3  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U24-Pad2_ d_and		
-U4  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U17-Pad2_ d_or		
-U5  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U26-Pad2_ d_and		
-U6  Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U18-Pad2_ d_or		
-U7  Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad2_ d_and		
-U8  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or		
-U9  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U31-Pad2_ d_and		
-U16  Net-_U1-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and		
-U24  Net-_U16-Pad3_ Net-_U24-Pad2_ Net-_U17-Pad1_ d_or		
-U33  Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U33-Pad3_ d_or		
-U23  Net-_U16-Pad2_ Net-_U23-Pad2_ d_inverter		
-U38  Net-_U1-Pad1_ Net-_U33-Pad3_ Net-_U38-Pad3_ d_xor		
-U42  Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter		
-U17  Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and		
-U26  Net-_U17-Pad3_ Net-_U26-Pad2_ Net-_U18-Pad1_ d_or		
-U34  Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U34-Pad3_ d_or		
-U25  Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter		
-U39  Net-_U17-Pad1_ Net-_U34-Pad3_ Net-_U39-Pad3_ d_xor		
-U44  Net-_U39-Pad3_ Net-_U1-Pad10_ d_inverter		
-U18  Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and		
-U28  Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_or		
-U35  Net-_U27-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad3_ d_or		
-U27  Net-_U18-Pad2_ Net-_U27-Pad2_ d_inverter		
-U40  Net-_U18-Pad1_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_xor		
-U45  Net-_U40-Pad3_ Net-_U1-Pad11_ d_inverter		
-U31  Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or		
-U21  Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter		
-U37  Net-_U28-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_xor		
-U43  Net-_U37-Pad3_ Net-_U1-Pad12_ d_inverter		
-U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
-U32  Net-_U1-Pad1_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and		
-U41  Net-_U32-Pad3_ Net-_U41-Pad2_ Net-_U1-Pad14_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-X1  Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U32-Pad2_ 4_and		
-X4  Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_X3-Pad3_ 3_and		
-X2  Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U24-Pad2_ Net-_X2-Pad5_ 4_and		
-X3  Net-_U31-Pad2_ Net-_U10-Pad3_ Net-_X3-Pad3_ Net-_X2-Pad5_ Net-_U41-Pad2_ 4_OR		
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out
deleted file mode 100644
index 4d05d64a..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out
+++ /dev/null
@@ -1,151 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
-
-.include 4_and.sub
-.include 3_and.sub
-.include 4_OR.sub
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
-* u3  net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
-* u4  net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
-* u5  net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
-* u6  net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
-* u7  net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
-* u8  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
-* u9  net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
-* u16  net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
-* u24  net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
-* u33  net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
-* u23  net-_u16-pad2_ net-_u23-pad2_ d_inverter
-* u38  net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
-* u42  net-_u38-pad3_ net-_u1-pad13_ d_inverter
-* u17  net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
-* u26  net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
-* u34  net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
-* u25  net-_u17-pad2_ net-_u25-pad2_ d_inverter
-* u39  net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
-* u44  net-_u39-pad3_ net-_u1-pad10_ d_inverter
-* u18  net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u28  net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
-* u35  net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
-* u27  net-_u18-pad2_ net-_u27-pad2_ d_inverter
-* u40  net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
-* u45  net-_u40-pad3_ net-_u1-pad11_ d_inverter
-* u31  net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
-* u21  net-_u10-pad1_ net-_u21-pad2_ d_inverter
-* u37  net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
-* u43  net-_u37-pad3_ net-_u1-pad12_ d_inverter
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u32  net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u41  net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
-x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
-x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
-x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
-a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
-a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
-a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
-a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
-a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
-a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
-a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
-a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
-a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
-a12 net-_u16-pad2_ net-_u23-pad2_ u23
-a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
-a14 net-_u38-pad3_ net-_u1-pad13_ u42
-a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
-a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
-a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
-a18 net-_u17-pad2_ net-_u25-pad2_ u25
-a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
-a20 net-_u39-pad3_ net-_u1-pad10_ u44
-a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
-a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
-a24 net-_u18-pad2_ net-_u27-pad2_ u27
-a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
-a26 net-_u40-pad3_ net-_u1-pad11_ u45
-a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
-a28 net-_u10-pad1_ net-_u21-pad2_ u21
-a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
-a30 net-_u37-pad3_ net-_u1-pad12_ u43
-a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro
deleted file mode 100644
index 2d0c38b5..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/28/19 23:02:17
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_User
-LibName25=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch
deleted file mode 100644
index d3507ac7..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch
+++ /dev/null
@@ -1,945 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:4_bit_FA-cache
-EELAYER 25 0
-EELAYER END
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diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub
deleted file mode 100644
index 2f2bc4ef..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub
+++ /dev/null
@@ -1,145 +0,0 @@
-* Subcircuit 4_bit_FA
-.subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
-.include 4_and.sub
-.include 3_and.sub
-.include 4_OR.sub
-* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
-* u3  net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
-* u4  net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
-* u5  net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
-* u6  net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
-* u7  net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
-* u8  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
-* u9  net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
-* u16  net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
-* u24  net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
-* u33  net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
-* u23  net-_u16-pad2_ net-_u23-pad2_ d_inverter
-* u38  net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
-* u42  net-_u38-pad3_ net-_u1-pad13_ d_inverter
-* u17  net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
-* u26  net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
-* u34  net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
-* u25  net-_u17-pad2_ net-_u25-pad2_ d_inverter
-* u39  net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
-* u44  net-_u39-pad3_ net-_u1-pad10_ d_inverter
-* u18  net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u28  net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
-* u35  net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
-* u27  net-_u18-pad2_ net-_u27-pad2_ d_inverter
-* u40  net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
-* u45  net-_u40-pad3_ net-_u1-pad11_ d_inverter
-* u31  net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
-* u21  net-_u10-pad1_ net-_u21-pad2_ d_inverter
-* u37  net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
-* u43  net-_u37-pad3_ net-_u1-pad12_ d_inverter
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u32  net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u41  net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
-x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
-x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
-x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
-x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
-a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
-a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
-a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
-a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
-a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
-a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
-a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
-a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
-a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
-a12 net-_u16-pad2_ net-_u23-pad2_ u23
-a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
-a14 net-_u38-pad3_ net-_u1-pad13_ u42
-a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
-a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
-a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
-a18 net-_u17-pad2_ net-_u25-pad2_ u25
-a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
-a20 net-_u39-pad3_ net-_u1-pad10_ u44
-a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
-a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
-a24 net-_u18-pad2_ net-_u27-pad2_ u27
-a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
-a26 net-_u40-pad3_ net-_u1-pad11_ u45
-a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
-a28 net-_u10-pad1_ net-_u21-pad2_ u21
-a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
-a30 net-_u37-pad3_ net-_u1-pad12_ u43
-a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_bit_FA
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml
deleted file mode 100644
index 49a53e5c..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u9><u16 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u24 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u24><u33 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u33><u23 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u23><u38 name="type">d_xor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_inverter<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u42><u17 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u26 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u26><u34 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u34><u25 name="type">d_inverter<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u25><u39 name="type">d_xor<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u39><u44 name="type">d_inverter<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u44><u18 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u18><u28 name="type">d_or<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u28><u35 name="type">d_or<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u35><u27 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u27><u40 name="type">d_xor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u40><u45 name="type">d_inverter<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u45><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u21 name="type">d_inverter<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u21><u37 name="type">d_xor<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u37><u43 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u43><u14 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_and<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u13><u20 name="type">d_and<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u20><u29 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u29><u36 name="type">d_or<field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /><field123 name="Enter Rise Delay (default=1.0e-9)" /></u36><u30 name="type">d_or<field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /><field126 name="Enter Rise Delay (default=1.0e-9)" /></u30><u32 name="type">d_and<field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /></u32><u41 name="type">d_or<field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /><field132 name="Enter Rise Delay (default=1.0e-9)" /></u41></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x1><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4_bit_FA/analysis b/src/SubcircuitLibrary/4_bit_FA/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib
deleted file mode 100644
index 898ea926..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib
+++ /dev/null
@@ -1,97 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_nand
-#
-DEF 5_nand X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_nand" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir
deleted file mode 100644
index c97c2f8b..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir
+++ /dev/null
@@ -1,32 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter		
-U4  Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter		
-U6  Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter		
-U2  Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT		
-X1  Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand		
-X2  Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand		
-X3  Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand		
-X4  Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand		
-X5  Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand		
-X6  Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand		
-X7  Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand		
-X8  Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand		
-X9  Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand		
-X10  Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand		
-X11  Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand		
-X12  Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand		
-X13  Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand		
-X14  Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand		
-X15  Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand		
-X16  Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand		
-
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out
deleted file mode 100644
index eecdfb06..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out
+++ /dev/null
@@ -1,49 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir
-
-.include 5_nand.sub
-* u3  net-_u1-pad23_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad22_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad21_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad20_ net-_u6-pad2_ d_inverter
-* u2  net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port
-x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand
-x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand
-x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand
-x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand
-x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand
-x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand
-x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand
-x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand
-x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand
-x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand
-x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand
-x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand
-x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand
-x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand
-x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand
-x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand
-a1 net-_u1-pad23_ net-_u3-pad2_ u3
-a2 net-_u1-pad22_ net-_u4-pad2_ u4
-a3 net-_u1-pad21_ net-_u5-pad2_ u5
-a4 net-_u1-pad20_ net-_u6-pad2_ u6
-a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro
deleted file mode 100644
index 5a167cd9..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro
+++ /dev/null
@@ -1,43 +0,0 @@
-update=Fri Jun 21 16:58:10 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_User
-LibName10=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch
deleted file mode 100644
index c9142e27..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch
+++ /dev/null
@@ -1,889 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:4to16_demux-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_inverter U3
-U 1 1 5CF2315F
-P 4700 1900
-F 0 "U3" H 4700 1800 60  0000 C CNN
-F 1 "d_inverter" H 4700 2050 60  0000 C CNN
-F 2 "" H 4750 1850 60  0000 C CNN
-F 3 "" H 4750 1850 60  0000 C CNN
-	1    4700 1900
-	0    1    1    0   
-$EndComp
-$Comp
-L d_inverter U4
-U 1 1 5CF231D7
-P 5600 1850
-F 0 "U4" H 5600 1750 60  0000 C CNN
-F 1 "d_inverter" H 5600 2000 60  0000 C CNN
-F 2 "" H 5650 1800 60  0000 C CNN
-F 3 "" H 5650 1800 60  0000 C CNN
-	1    5600 1850
-	0    1    1    0   
-$EndComp
-$Comp
-L d_inverter U5
-U 1 1 5CF23245
-P 6550 1850
-F 0 "U5" H 6550 1750 60  0000 C CNN
-F 1 "d_inverter" H 6550 2000 60  0000 C CNN
-F 2 "" H 6600 1800 60  0000 C CNN
-F 3 "" H 6600 1800 60  0000 C CNN
-	1    6550 1850
-	0    1    1    0   
-$EndComp
-$Comp
-L d_inverter U6
-U 1 1 5CF232B2
-P 7500 1800
-F 0 "U6" H 7500 1700 60  0000 C CNN
-F 1 "d_inverter" H 7500 1950 60  0000 C CNN
-F 2 "" H 7550 1750 60  0000 C CNN
-F 3 "" H 7550 1750 60  0000 C CNN
-	1    7500 1800
-	0    1    1    0   
-$EndComp
-Text Notes 1300 5450 0    60   ~ 0
-~Y0
-Text Notes 1950 5450 0    60   ~ 0
-~Y1\n
-Text Notes 2500 5450 0    60   ~ 0
-~Y2\n
-Text Notes 3050 5450 0    60   ~ 0
-~Y3\n
-Text Notes 3600 5450 0    60   ~ 0
-~Y4\n
-Text Notes 4150 5500 0    60   ~ 0
-~Y5\n
-Text Notes 4700 5500 0    60   ~ 0
-~Y6\n
-Text Notes 5250 5500 0    60   ~ 0
-~Y7\n
-Text Notes 5800 5500 0    60   ~ 0
-~Y8\n
-Text Notes 6400 5500 0    60   ~ 0
-~Y9\n
-Text Notes 6950 5500 0    60   ~ 0
-~Y10\n
-Text Notes 7500 5500 0    60   ~ 0
-~Y11\n
-Text Notes 8050 5500 0    60   ~ 0
-~Y12\n
-Text Notes 8600 5500 0    60   ~ 0
-~Y13\n
-Text Notes 9150 5500 0    60   ~ 0
-~Y14\n
-Text Notes 9700 5500 0    60   ~ 0
-~Y15\n
-Wire Wire Line
-	4700 1250 4700 1600
-Wire Wire Line
-	5600 1150 5600 1550
-Wire Wire Line
-	6550 1100 6550 1550
-Wire Wire Line
-	7500 1050 7500 1500
-Wire Wire Line
-	1400 4400 1400 2950
-Wire Wire Line
-	1400 2950 9700 2950
-Wire Wire Line
-	1950 2950 1950 4400
-Wire Wire Line
-	2500 2950 2500 4400
-Connection ~ 1950 2950
-Wire Wire Line
-	3050 2950 3050 4400
-Connection ~ 2500 2950
-Wire Wire Line
-	3600 2950 3600 4400
-Connection ~ 3050 2950
-Wire Wire Line
-	4150 2950 4150 4400
-Connection ~ 3600 2950
-Wire Wire Line
-	4700 2950 4700 4400
-Connection ~ 4150 2950
-Wire Wire Line
-	5250 2950 5250 4400
-Connection ~ 4700 2950
-Wire Wire Line
-	5800 2950 5800 4400
-Connection ~ 5250 2950
-Wire Wire Line
-	6400 2950 6400 4400
-Connection ~ 5800 2950
-Wire Wire Line
-	6950 2950 6950 4400
-Connection ~ 6400 2950
-Wire Wire Line
-	7500 2950 7500 4400
-Connection ~ 6950 2950
-Wire Wire Line
-	8050 2950 8050 4400
-Connection ~ 7500 2950
-Wire Wire Line
-	8600 2950 8600 4400
-Connection ~ 8050 2950
-Wire Wire Line
-	9150 2950 9150 4400
-Connection ~ 8600 2950
-Wire Wire Line
-	9700 2950 9700 4400
-Connection ~ 9150 2950
-Wire Wire Line
-	7500 2100 7500 2800
-Wire Wire Line
-	7500 2800 7400 2800
-Wire Wire Line
-	7400 2800 7400 3050
-Wire Wire Line
-	7400 3050 1500 3050
-Wire Wire Line
-	1500 3050 1500 4400
-Wire Wire Line
-	2050 4400 2050 3050
-Connection ~ 2050 3050
-Wire Wire Line
-	2600 4400 2600 3050
-Connection ~ 2600 3050
-Wire Wire Line
-	3150 4400 3150 3050
-Connection ~ 3150 3050
-Wire Wire Line
-	3700 4400 3700 3050
-Connection ~ 3700 3050
-Wire Wire Line
-	4250 4400 4250 3050
-Connection ~ 4250 3050
-Wire Wire Line
-	4800 4400 4800 3050
-Connection ~ 4800 3050
-Wire Wire Line
-	5350 4400 5350 3050
-Connection ~ 5350 3050
-Wire Wire Line
-	6550 3150 6550 2150
-Wire Wire Line
-	1600 3150 7700 3150
-Wire Wire Line
-	1600 3150 1600 4400
-Wire Wire Line
-	2150 4400 2150 3150
-Connection ~ 2150 3150
-Wire Wire Line
-	2700 4400 2700 3150
-Connection ~ 2700 3150
-Wire Wire Line
-	3250 4400 3250 3150
-Connection ~ 3250 3150
-Wire Wire Line
-	5600 3250 5600 2150
-Wire Wire Line
-	1700 3250 8900 3250
-Wire Wire Line
-	1700 3250 1700 4400
-Wire Wire Line
-	2250 4400 2250 3250
-Connection ~ 2250 3250
-Wire Wire Line
-	3900 4400 3900 3250
-Connection ~ 3900 3250
-Wire Wire Line
-	4450 4400 4450 3250
-Connection ~ 4450 3250
-Wire Wire Line
-	6100 3250 6100 4400
-Connection ~ 5600 3250
-Wire Wire Line
-	6700 3250 6700 4400
-Connection ~ 6100 3250
-Wire Wire Line
-	8350 3250 8350 4400
-Connection ~ 6700 3250
-Wire Wire Line
-	8900 3250 8900 4400
-Connection ~ 8350 3250
-Wire Wire Line
-	4700 2200 4700 2850
-Wire Wire Line
-	4700 2850 4600 2850
-Wire Wire Line
-	4600 2850 4600 3350
-Wire Wire Line
-	1800 3350 1800 4400
-Wire Wire Line
-	2900 4400 2900 3350
-Connection ~ 2900 3350
-Connection ~ 4600 3350
-Wire Wire Line
-	2350 2650 2350 4400
-Wire Wire Line
-	4000 3350 4000 4400
-Connection ~ 4000 3350
-Wire Wire Line
-	5100 3350 5100 4400
-Connection ~ 5100 3350
-Wire Wire Line
-	6200 3350 6200 4400
-Connection ~ 6200 3350
-Wire Wire Line
-	7350 3350 7350 4400
-Connection ~ 7350 3350
-Wire Wire Line
-	8450 3350 8450 4400
-Connection ~ 8450 3350
-Wire Wire Line
-	1800 3350 9550 3350
-Wire Wire Line
-	9550 3350 9550 4400
-Wire Wire Line
-	2350 3450 10100 3450
-Wire Wire Line
-	3450 3450 3450 4400
-Wire Wire Line
-	4550 3450 4550 4400
-Connection ~ 3450 3450
-Wire Wire Line
-	5650 3450 5650 4400
-Connection ~ 4550 3450
-Wire Wire Line
-	6800 3450 6800 4400
-Connection ~ 5650 3450
-Wire Wire Line
-	7900 3450 7900 4400
-Connection ~ 6800 3450
-Wire Wire Line
-	9000 3450 9000 4400
-Connection ~ 7900 3450
-Wire Wire Line
-	10100 3450 10100 4400
-Connection ~ 9000 3450
-Wire Wire Line
-	10000 3550 10000 4400
-Wire Wire Line
-	2800 3550 10000 3550
-Wire Wire Line
-	9450 3550 9450 4400
-Wire Wire Line
-	7800 3550 7800 4400
-Connection ~ 9450 3550
-Wire Wire Line
-	7250 3550 7250 4400
-Connection ~ 7800 3550
-Wire Wire Line
-	5550 3550 5550 4400
-Connection ~ 7250 3550
-Wire Wire Line
-	5000 1400 5000 4400
-Connection ~ 5550 3550
-Wire Wire Line
-	3350 3550 3350 4400
-Connection ~ 5000 3550
-Wire Wire Line
-	2800 3550 2800 4400
-Connection ~ 3350 3550
-Wire Wire Line
-	5000 1400 5600 1400
-Connection ~ 5600 1400
-Wire Wire Line
-	9900 3700 9900 4400
-Wire Wire Line
-	3800 3700 9900 3700
-Wire Wire Line
-	9350 3700 9350 4400
-Wire Wire Line
-	8800 3700 8800 4400
-Connection ~ 9350 3700
-Wire Wire Line
-	8250 3700 8250 4400
-Connection ~ 8800 3700
-Wire Wire Line
-	5450 3700 5450 4400
-Connection ~ 8250 3700
-Wire Wire Line
-	4900 3700 4900 4400
-Connection ~ 5450 3700
-Wire Wire Line
-	4350 3700 4350 4400
-Connection ~ 4900 3700
-Wire Wire Line
-	3800 3700 3800 4400
-Connection ~ 4350 3700
-Wire Wire Line
-	5950 3700 5950 1350
-Wire Wire Line
-	5950 1350 6550 1350
-Connection ~ 6550 1350
-Connection ~ 5950 3700
-Wire Wire Line
-	9800 3850 9800 4400
-Wire Wire Line
-	5900 3850 9800 3850
-Wire Wire Line
-	9250 3850 9250 4400
-Wire Wire Line
-	8700 3850 8700 4400
-Connection ~ 9250 3850
-Wire Wire Line
-	8150 3850 8150 4400
-Connection ~ 8700 3850
-Wire Wire Line
-	7600 3850 7600 4400
-Connection ~ 8150 3850
-Wire Wire Line
-	7050 1350 7050 4400
-Connection ~ 7600 3850
-Wire Wire Line
-	6500 3850 6500 4400
-Connection ~ 7050 3850
-Wire Wire Line
-	5900 3850 5900 4400
-Connection ~ 6500 3850
-Wire Wire Line
-	7050 1350 7500 1350
-Connection ~ 7500 1350
-Wire Wire Line
-	7700 3150 7700 4400
-Connection ~ 6550 3150
-Wire Wire Line
-	7150 4400 7150 3150
-Connection ~ 7150 3150
-Wire Wire Line
-	6600 3150 6600 4400
-Connection ~ 6600 3150
-Wire Wire Line
-	6000 4400 6000 3150
-Connection ~ 6000 3150
-Connection ~ 2350 3450
-Connection ~ 4700 1450
-Wire Wire Line
-	4000 1450 4700 1450
-Wire Wire Line
-	2350 2650 4000 2650
-Wire Wire Line
-	4000 2650 4000 1450
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-U 1 1 5CF2CBDC
-P 1600 2050
-F 0 "U2" H 1600 2050 60  0000 C CNN
-F 1 "d_nor" H 1650 2150 60  0000 C CNN
-F 2 "" H 1600 2050 60  0000 C CNN
-F 3 "" H 1600 2050 60  0000 C CNN
-	1    1600 2050
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	1650 2500 1650 2950
-Connection ~ 1650 2950
-Wire Wire Line
-	1700 1600 1700 1200
-Wire Wire Line
-	1600 1600 1600 1200
-$Comp
-L PORT U1
-U 18 1 5CF2D1A2
-P 1600 950
-F 0 "U1" H 1650 1050 30  0000 C CNN
-F 1 "PORT" H 1600 950 30  0000 C CNN
-F 2 "" H 1600 950 60  0000 C CNN
-F 3 "" H 1600 950 60  0000 C CNN
-	18   1600 950 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 19 1 5CF2D207
-P 1900 900
-F 0 "U1" H 1950 1000 30  0000 C CNN
-F 1 "PORT" H 1900 900 30  0000 C CNN
-F 2 "" H 1900 900 60  0000 C CNN
-F 3 "" H 1900 900 60  0000 C CNN
-	19   1900 900 
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	1900 1150 1900 1200
-Wire Wire Line
-	1900 1200 1700 1200
-$Comp
-L PORT U1
-U 23 1 5CF2D33A
-P 4700 1000
-F 0 "U1" H 4750 1100 30  0000 C CNN
-F 1 "PORT" H 4700 1000 30  0000 C CNN
-F 2 "" H 4700 1000 60  0000 C CNN
-F 3 "" H 4700 1000 60  0000 C CNN
-	23   4700 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 22 1 5CF2D510
-P 5600 900
-F 0 "U1" H 5650 1000 30  0000 C CNN
-F 1 "PORT" H 5600 900 30  0000 C CNN
-F 2 "" H 5600 900 60  0000 C CNN
-F 3 "" H 5600 900 60  0000 C CNN
-	22   5600 900 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 21 1 5CF2D57F
-P 6550 850
-F 0 "U1" H 6600 950 30  0000 C CNN
-F 1 "PORT" H 6550 850 30  0000 C CNN
-F 2 "" H 6550 850 60  0000 C CNN
-F 3 "" H 6550 850 60  0000 C CNN
-	21   6550 850 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 20 1 5CF2D6A5
-P 7500 800
-F 0 "U1" H 7550 900 30  0000 C CNN
-F 1 "PORT" H 7500 800 30  0000 C CNN
-F 2 "" H 7500 800 60  0000 C CNN
-F 3 "" H 7500 800 60  0000 C CNN
-	20   7500 800 
-	0    1    1    0   
-$EndComp
-Text Notes 7700 950  0    60   ~ 0
-A3\n
-$Comp
-L PORT U1
-U 1 1 5CF2DE5C
-P 1600 6200
-F 0 "U1" H 1650 6300 30  0000 C CNN
-F 1 "PORT" H 1600 6200 30  0000 C CNN
-F 2 "" H 1600 6200 60  0000 C CNN
-F 3 "" H 1600 6200 60  0000 C CNN
-	1    1600 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF2E1AE
-P 2150 6200
-F 0 "U1" H 2200 6300 30  0000 C CNN
-F 1 "PORT" H 2150 6200 30  0000 C CNN
-F 2 "" H 2150 6200 60  0000 C CNN
-F 3 "" H 2150 6200 60  0000 C CNN
-	2    2150 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF2E23B
-P 2700 6200
-F 0 "U1" H 2750 6300 30  0000 C CNN
-F 1 "PORT" H 2700 6200 30  0000 C CNN
-F 2 "" H 2700 6200 60  0000 C CNN
-F 3 "" H 2700 6200 60  0000 C CNN
-	3    2700 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF2E2B3
-P 3250 6200
-F 0 "U1" H 3300 6300 30  0000 C CNN
-F 1 "PORT" H 3250 6200 30  0000 C CNN
-F 2 "" H 3250 6200 60  0000 C CNN
-F 3 "" H 3250 6200 60  0000 C CNN
-	4    3250 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CF2E32C
-P 3800 6200
-F 0 "U1" H 3850 6300 30  0000 C CNN
-F 1 "PORT" H 3800 6200 30  0000 C CNN
-F 2 "" H 3800 6200 60  0000 C CNN
-F 3 "" H 3800 6200 60  0000 C CNN
-	5    3800 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF2E3CE
-P 4350 6200
-F 0 "U1" H 4400 6300 30  0000 C CNN
-F 1 "PORT" H 4350 6200 30  0000 C CNN
-F 2 "" H 4350 6200 60  0000 C CNN
-F 3 "" H 4350 6200 60  0000 C CNN
-	6    4350 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CF2E4B6
-P 4900 6200
-F 0 "U1" H 4950 6300 30  0000 C CNN
-F 1 "PORT" H 4900 6200 30  0000 C CNN
-F 2 "" H 4900 6200 60  0000 C CNN
-F 3 "" H 4900 6200 60  0000 C CNN
-	7    4900 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF2E5CA
-P 5450 6200
-F 0 "U1" H 5500 6300 30  0000 C CNN
-F 1 "PORT" H 5450 6200 30  0000 C CNN
-F 2 "" H 5450 6200 60  0000 C CNN
-F 3 "" H 5450 6200 60  0000 C CNN
-	8    5450 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF2E651
-P 6000 6200
-F 0 "U1" H 6050 6300 30  0000 C CNN
-F 1 "PORT" H 6000 6200 30  0000 C CNN
-F 2 "" H 6000 6200 60  0000 C CNN
-F 3 "" H 6000 6200 60  0000 C CNN
-	9    6000 6200
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF2E6E3
-P 6600 6150
-F 0 "U1" H 6650 6250 30  0000 C CNN
-F 1 "PORT" H 6600 6150 30  0000 C CNN
-F 2 "" H 6600 6150 60  0000 C CNN
-F 3 "" H 6600 6150 60  0000 C CNN
-	10   6600 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF2E770
-P 7150 6150
-F 0 "U1" H 7200 6250 30  0000 C CNN
-F 1 "PORT" H 7150 6150 30  0000 C CNN
-F 2 "" H 7150 6150 60  0000 C CNN
-F 3 "" H 7150 6150 60  0000 C CNN
-	11   7150 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF2E7F8
-P 7700 6150
-F 0 "U1" H 7750 6250 30  0000 C CNN
-F 1 "PORT" H 7700 6150 30  0000 C CNN
-F 2 "" H 7700 6150 60  0000 C CNN
-F 3 "" H 7700 6150 60  0000 C CNN
-	13   7700 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF2E989
-P 8250 6150
-F 0 "U1" H 8300 6250 30  0000 C CNN
-F 1 "PORT" H 8250 6150 30  0000 C CNN
-F 2 "" H 8250 6150 60  0000 C CNN
-F 3 "" H 8250 6150 60  0000 C CNN
-	14   8250 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 15 1 5CF2EA23
-P 8800 6150
-F 0 "U1" H 8850 6250 30  0000 C CNN
-F 1 "PORT" H 8800 6150 30  0000 C CNN
-F 2 "" H 8800 6150 60  0000 C CNN
-F 3 "" H 8800 6150 60  0000 C CNN
-	15   8800 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 16 1 5CF2EABA
-P 9350 6150
-F 0 "U1" H 9400 6250 30  0000 C CNN
-F 1 "PORT" H 9350 6150 30  0000 C CNN
-F 2 "" H 9350 6150 60  0000 C CNN
-F 3 "" H 9350 6150 60  0000 C CNN
-	16   9350 6150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 17 1 5CF2EB7A
-P 9900 6100
-F 0 "U1" H 9950 6200 30  0000 C CNN
-F 1 "PORT" H 9900 6100 30  0000 C CNN
-F 2 "" H 9900 6100 60  0000 C CNN
-F 3 "" H 9900 6100 60  0000 C CNN
-	17   9900 6100
-	0    -1   -1   0   
-$EndComp
-Wire Wire Line
-	9900 5850 9900 5400
-Wire Wire Line
-	9350 5400 9350 5900
-Wire Wire Line
-	8800 5400 8800 5900
-Wire Wire Line
-	8250 5400 8250 5900
-Wire Wire Line
-	7700 5400 7700 5900
-Wire Wire Line
-	7150 5400 7150 5900
-Wire Wire Line
-	6600 5400 6600 5900
-Wire Wire Line
-	6000 5400 6000 5950
-Wire Wire Line
-	5450 5400 5450 5950
-Wire Wire Line
-	4900 5400 4900 5950
-Wire Wire Line
-	4350 5400 4350 5950
-Wire Wire Line
-	3800 5400 3800 5950
-Wire Wire Line
-	3250 5400 3250 5950
-Wire Wire Line
-	2700 5400 2700 5950
-Wire Wire Line
-	2150 5400 2150 5950
-Wire Wire Line
-	1600 5400 1600 5950
-$Comp
-L PORT U1
-U 24 1 5CF327C1
-P 6500 6950
-F 0 "U1" H 6550 7050 30  0000 C CNN
-F 1 "PORT" H 6500 6950 30  0000 C CNN
-F 2 "" H 6500 6950 60  0000 C CNN
-F 3 "" H 6500 6950 60  0000 C CNN
-	24   6500 6950
-	0    -1   -1   0   
-$EndComp
-NoConn ~ 6500 6700
-$Comp
-L PORT U1
-U 12 1 5CF33A86
-P 3400 900
-F 0 "U1" H 3450 1000 30  0000 C CNN
-F 1 "PORT" H 3400 900 30  0000 C CNN
-F 2 "" H 3400 900 60  0000 C CNN
-F 3 "" H 3400 900 60  0000 C CNN
-	12   3400 900 
-	0    1    1    0   
-$EndComp
-NoConn ~ 3400 1150
-$Comp
-L 5_nand X1
-U 1 1 5D0CC4BF
-P 1600 4850
-F 0 "X1" H 1650 4750 60  0000 C CNN
-F 1 "5_nand" H 1700 5000 60  0000 C CNN
-F 2 "" H 1600 4850 60  0000 C CNN
-F 3 "" H 1600 4850 60  0000 C CNN
-	1    1600 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X2
-U 1 1 5D0CC967
-P 2150 4850
-F 0 "X2" H 2200 4750 60  0000 C CNN
-F 1 "5_nand" H 2250 5000 60  0000 C CNN
-F 2 "" H 2150 4850 60  0000 C CNN
-F 3 "" H 2150 4850 60  0000 C CNN
-	1    2150 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X3
-U 1 1 5D0CC9F8
-P 2700 4850
-F 0 "X3" H 2750 4750 60  0000 C CNN
-F 1 "5_nand" H 2800 5000 60  0000 C CNN
-F 2 "" H 2700 4850 60  0000 C CNN
-F 3 "" H 2700 4850 60  0000 C CNN
-	1    2700 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X4
-U 1 1 5D0CCA7E
-P 3250 4850
-F 0 "X4" H 3300 4750 60  0000 C CNN
-F 1 "5_nand" H 3350 5000 60  0000 C CNN
-F 2 "" H 3250 4850 60  0000 C CNN
-F 3 "" H 3250 4850 60  0000 C CNN
-	1    3250 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X5
-U 1 1 5D0CCB6A
-P 3800 4850
-F 0 "X5" H 3850 4750 60  0000 C CNN
-F 1 "5_nand" H 3900 5000 60  0000 C CNN
-F 2 "" H 3800 4850 60  0000 C CNN
-F 3 "" H 3800 4850 60  0000 C CNN
-	1    3800 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X6
-U 1 1 5D0CCBF6
-P 4350 4850
-F 0 "X6" H 4400 4750 60  0000 C CNN
-F 1 "5_nand" H 4450 5000 60  0000 C CNN
-F 2 "" H 4350 4850 60  0000 C CNN
-F 3 "" H 4350 4850 60  0000 C CNN
-	1    4350 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X7
-U 1 1 5D0CCC81
-P 4900 4850
-F 0 "X7" H 4950 4750 60  0000 C CNN
-F 1 "5_nand" H 5000 5000 60  0000 C CNN
-F 2 "" H 4900 4850 60  0000 C CNN
-F 3 "" H 4900 4850 60  0000 C CNN
-	1    4900 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X8
-U 1 1 5D0CCD0B
-P 5450 4850
-F 0 "X8" H 5500 4750 60  0000 C CNN
-F 1 "5_nand" H 5550 5000 60  0000 C CNN
-F 2 "" H 5450 4850 60  0000 C CNN
-F 3 "" H 5450 4850 60  0000 C CNN
-	1    5450 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X9
-U 1 1 5D0CCE34
-P 6000 4850
-F 0 "X9" H 6050 4750 60  0000 C CNN
-F 1 "5_nand" H 6100 5000 60  0000 C CNN
-F 2 "" H 6000 4850 60  0000 C CNN
-F 3 "" H 6000 4850 60  0000 C CNN
-	1    6000 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X10
-U 1 1 5D0CCECA
-P 6600 4850
-F 0 "X10" H 6650 4750 60  0000 C CNN
-F 1 "5_nand" H 6700 5000 60  0000 C CNN
-F 2 "" H 6600 4850 60  0000 C CNN
-F 3 "" H 6600 4850 60  0000 C CNN
-	1    6600 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X11
-U 1 1 5D0CCF63
-P 7150 4850
-F 0 "X11" H 7200 4750 60  0000 C CNN
-F 1 "5_nand" H 7250 5000 60  0000 C CNN
-F 2 "" H 7150 4850 60  0000 C CNN
-F 3 "" H 7150 4850 60  0000 C CNN
-	1    7150 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X12
-U 1 1 5D0CD07D
-P 7700 4850
-F 0 "X12" H 7750 4750 60  0000 C CNN
-F 1 "5_nand" H 7800 5000 60  0000 C CNN
-F 2 "" H 7700 4850 60  0000 C CNN
-F 3 "" H 7700 4850 60  0000 C CNN
-	1    7700 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X13
-U 1 1 5D0CD124
-P 8250 4850
-F 0 "X13" H 8300 4750 60  0000 C CNN
-F 1 "5_nand" H 8350 5000 60  0000 C CNN
-F 2 "" H 8250 4850 60  0000 C CNN
-F 3 "" H 8250 4850 60  0000 C CNN
-	1    8250 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X14
-U 1 1 5D0CD1C6
-P 8800 4850
-F 0 "X14" H 8850 4750 60  0000 C CNN
-F 1 "5_nand" H 8900 5000 60  0000 C CNN
-F 2 "" H 8800 4850 60  0000 C CNN
-F 3 "" H 8800 4850 60  0000 C CNN
-	1    8800 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X15
-U 1 1 5D0CD348
-P 9350 4850
-F 0 "X15" H 9400 4750 60  0000 C CNN
-F 1 "5_nand" H 9450 5000 60  0000 C CNN
-F 2 "" H 9350 4850 60  0000 C CNN
-F 3 "" H 9350 4850 60  0000 C CNN
-	1    9350 4850
-	0    1    1    0   
-$EndComp
-$Comp
-L 5_nand X16
-U 1 1 5D0CD3EE
-P 9900 4850
-F 0 "X16" H 9950 4750 60  0000 C CNN
-F 1 "5_nand" H 10000 5000 60  0000 C CNN
-F 2 "" H 9900 4850 60  0000 C CNN
-F 3 "" H 9900 4850 60  0000 C CNN
-	1    9900 4850
-	0    1    1    0   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub
deleted file mode 100644
index 4f7595da..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub
+++ /dev/null
@@ -1,43 +0,0 @@
-* Subcircuit 4to16_demux
-.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir
-.include 5_nand.sub
-* u3  net-_u1-pad23_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad22_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad21_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad20_ net-_u6-pad2_ d_inverter
-* u2  net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor
-x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand
-x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand
-x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand
-x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand
-x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand
-x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand
-x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand
-x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand
-x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand
-x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand
-x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand
-x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand
-x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand
-x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand
-x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand
-x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand
-a1 net-_u1-pad23_ net-_u3-pad2_ u3
-a2 net-_u1-pad22_ net-_u4-pad2_ u4
-a3 net-_u1-pad21_ net-_u5-pad2_ u5
-a4 net-_u1-pad20_ net-_u6-pad2_ u6
-a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4to16_demux
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml
deleted file mode 100644
index 93c6f25a..00000000
--- a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x13><x14><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x14><x15><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x15><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x9><x16><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x16><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x12><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib
deleted file mode 100644
index ac396288..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir
deleted file mode 100644
index 6a05b9b5..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out
deleted file mode 100644
index 6a6b126a..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro
deleted file mode 100644
index 7a2f090e..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch
deleted file mode 100644
index e9eb58ee..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and.sch
+++ /dev/null
@@ -1,171 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60  0000 C CNN
-F 1 "3_and" H 4750 3850 60  0000 C CNN
-F 2 "" H 3800 3350 60  0000 C CNN
-F 3 "" H 3800 3350 60  0000 C CNN
-	1    3800 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60  0000 C CNN
-F 1 "d_and" H 4700 3500 60  0000 C CNN
-F 2 "" H 4650 3400 60  0000 C CNN
-F 3 "" H 4650 3400 60  0000 C CNN
-	1    4650 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2791
-P 5550 3200
-F 0 "U3" H 5550 3200 60  0000 C CNN
-F 1 "d_and" H 5600 3300 60  0000 C CNN
-F 2 "" H 5550 3200 60  0000 C CNN
-F 3 "" H 5550 3200 60  0000 C CNN
-	1    5550 3200
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5100 3100 5100 2950
-Wire Wire Line
-	5100 3200 5100 3350
-Wire Wire Line
-	4250 2850 4250 2700
-Wire Wire Line
-	4250 2700 3600 2700
-Wire Wire Line
-	4250 2950 4150 2950
-Wire Wire Line
-	4150 2950 4150 2900
-Wire Wire Line
-	4150 2900 3600 2900
-Wire Wire Line
-	4200 3300 3600 3300
-Wire Wire Line
-	4250 3050 4250 3100
-Wire Wire Line
-	4250 3100 3600 3100
-Wire Wire Line
-	4200 3400 4200 3500
-Wire Wire Line
-	4200 3500 3600 3500
-Wire Wire Line
-	6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30  0000 C CNN
-F 1 "PORT" H 3350 2700 30  0000 C CNN
-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
-	1    3350 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30  0000 C CNN
-F 1 "PORT" H 3350 2900 30  0000 C CNN
-F 2 "" H 3350 2900 60  0000 C CNN
-F 3 "" H 3350 2900 60  0000 C CNN
-	2    3350 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
-F 0 "U1" H 3400 3200 30  0000 C CNN
-F 1 "PORT" H 3350 3100 30  0000 C CNN
-F 2 "" H 3350 3100 60  0000 C CNN
-F 3 "" H 3350 3100 60  0000 C CNN
-	3    3350 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
-P 3350 3300
-F 0 "U1" H 3400 3400 30  0000 C CNN
-F 1 "PORT" H 3350 3300 30  0000 C CNN
-F 2 "" H 3350 3300 60  0000 C CNN
-F 3 "" H 3350 3300 60  0000 C CNN
-	4    3350 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
-P 3350 3500
-F 0 "U1" H 3400 3600 30  0000 C CNN
-F 1 "PORT" H 3350 3500 30  0000 C CNN
-F 2 "" H 3350 3500 60  0000 C CNN
-F 3 "" H 3350 3500 60  0000 C CNN
-	5    3350 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30  0000 C CNN
-F 1 "PORT" H 6750 3150 30  0000 C CNN
-F 2 "" H 6750 3150 60  0000 C CNN
-F 3 "" H 6750 3150 60  0000 C CNN
-	6    6750 3150
-	-1   0    0    1   
-$EndComp
-Text Notes 3800 2700 0    60   ~ 12
-in1
-Text Notes 3800 2900 0    60   ~ 12
-in2
-Text Notes 3800 3100 0    60   ~ 12
-in3
-Text Notes 3800 3300 0    60   ~ 12
-in4
-Text Notes 3800 3500 0    60   ~ 12
-in5
-Text Notes 6150 3150 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub
deleted file mode 100644
index 35b10e17..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib
deleted file mode 100644
index cb517be1..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib
+++ /dev/null
@@ -1,78 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir b/src/SubcircuitLibrary/4to16_demux/5_nand.cir
deleted file mode 100644
index e833d0f4..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out
deleted file mode 100644
index 164de911..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.pro b/src/SubcircuitLibrary/4to16_demux/5_nand.pro
deleted file mode 100644
index b7d23f44..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=Fri Jun 21 16:46:10 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sch b/src/SubcircuitLibrary/4to16_demux/5_nand.sch
deleted file mode 100644
index 86379b08..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand.sch
+++ /dev/null
@@ -1,175 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 5_and X1
-U 1 1 5D0CBD44
-P 4150 3700
-F 0 "X1" H 4200 3600 60  0000 C CNN
-F 1 "5_and" H 4250 3850 60  0000 C CNN
-F 2 "" H 4150 3700 60  0000 C CNN
-F 3 "" H 4150 3700 60  0000 C CNN
-	1    4150 3700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U2
-U 1 1 5D0CBD97
-P 5150 3700
-F 0 "U2" H 5150 3600 60  0000 C CNN
-F 1 "d_inverter" H 5150 3850 60  0000 C CNN
-F 2 "" H 5200 3650 60  0000 C CNN
-F 3 "" H 5200 3650 60  0000 C CNN
-	1    5150 3700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5D0CBDBE
-P 2900 2900
-F 0 "U1" H 2950 3000 30  0000 C CNN
-F 1 "PORT" H 2900 2900 30  0000 C CNN
-F 2 "" H 2900 2900 60  0000 C CNN
-F 3 "" H 2900 2900 60  0000 C CNN
-	1    2900 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5D0CBDF4
-P 2900 3150
-F 0 "U1" H 2950 3250 30  0000 C CNN
-F 1 "PORT" H 2900 3150 30  0000 C CNN
-F 2 "" H 2900 3150 60  0000 C CNN
-F 3 "" H 2900 3150 60  0000 C CNN
-	2    2900 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5D0CBE16
-P 2900 3400
-F 0 "U1" H 2950 3500 30  0000 C CNN
-F 1 "PORT" H 2900 3400 30  0000 C CNN
-F 2 "" H 2900 3400 60  0000 C CNN
-F 3 "" H 2900 3400 60  0000 C CNN
-	3    2900 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5D0CBE3F
-P 2900 3750
-F 0 "U1" H 2950 3850 30  0000 C CNN
-F 1 "PORT" H 2900 3750 30  0000 C CNN
-F 2 "" H 2900 3750 60  0000 C CNN
-F 3 "" H 2900 3750 60  0000 C CNN
-	4    2900 3750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5D0CBE6B
-P 2900 4150
-F 0 "U1" H 2950 4250 30  0000 C CNN
-F 1 "PORT" H 2900 4150 30  0000 C CNN
-F 2 "" H 2900 4150 60  0000 C CNN
-F 3 "" H 2900 4150 60  0000 C CNN
-	5    2900 4150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5D0CBE9C
-P 6200 3700
-F 0 "U1" H 6250 3800 30  0000 C CNN
-F 1 "PORT" H 6200 3700 30  0000 C CNN
-F 2 "" H 6200 3700 60  0000 C CNN
-F 3 "" H 6200 3700 60  0000 C CNN
-	6    6200 3700
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	3150 2900 3700 2900
-Wire Wire Line
-	3700 2900 3700 3500
-Wire Wire Line
-	3700 3600 3500 3600
-Wire Wire Line
-	3500 3600 3500 3150
-Wire Wire Line
-	3500 3150 3150 3150
-Wire Wire Line
-	3150 3400 3350 3400
-Wire Wire Line
-	3350 3400 3350 3700
-Wire Wire Line
-	3350 3700 3700 3700
-Wire Wire Line
-	3700 3800 3250 3800
-Wire Wire Line
-	3250 3800 3250 3750
-Wire Wire Line
-	3250 3750 3150 3750
-Wire Wire Line
-	3150 4150 3350 4150
-Wire Wire Line
-	3350 4150 3350 3900
-Wire Wire Line
-	3350 3900 3700 3900
-Wire Wire Line
-	4700 3700 4850 3700
-Wire Wire Line
-	5450 3700 5950 3700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sub b/src/SubcircuitLibrary/4to16_demux/5_nand.sub
deleted file mode 100644
index c3e041fa..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 5_nand
-.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nand
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml
deleted file mode 100644
index c4b4cde2..00000000
--- a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4to16_demux/analysis b/src/SubcircuitLibrary/4to16_demux/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/4to16_demux/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/556/556-cache.lib b/src/SubcircuitLibrary/556/556-cache.lib
deleted file mode 100644
index 75d610da..00000000
--- a/src/SubcircuitLibrary/556/556-cache.lib
+++ /dev/null
@@ -1,64 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# LM555N
-#
-DEF LM555N X 0 40 Y Y 1 F N
-F0 "X" 0 -50 60 H V C CNN
-F1 "LM555N" 0 100 60 H V C CNN
-F2 "" -50 0 60 H V C CNN
-F3 "" -50 0 60 H V C CNN
-DRAW
-S 350 -400 -350 400 0 1 0 N
-X GND 1 0 -600 200 U 50 50 1 1 W
-X TR 2 -550 250 200 R 50 50 1 1 I
-X Q 3 550 250 200 L 50 50 1 1 O
-X R 4 -550 -250 200 R 50 50 1 1 I I
-X CV 5 -550 0 200 R 50 50 1 1 I
-X THR 6 550 -250 200 L 50 50 1 1 I
-X DIS 7 550 0 200 L 50 50 1 1 I
-X VCC 8 0 600 200 D 50 50 1 1 W
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/556/556.cir b/src/SubcircuitLibrary/556/556.cir
deleted file mode 100644
index 48baa73e..00000000
--- a/src/SubcircuitLibrary/556/556.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N		
-X2  Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/556/556.cir.out b/src/SubcircuitLibrary/556/556.cir.out
deleted file mode 100644
index c74aab7c..00000000
--- a/src/SubcircuitLibrary/556/556.cir.out
+++ /dev/null
@@ -1,15 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\556\556.cir
-
-.include lm555n.sub
-x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n
-x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/556/556.pro b/src/SubcircuitLibrary/556/556.pro
deleted file mode 100644
index a165313d..00000000
--- a/src/SubcircuitLibrary/556/556.pro
+++ /dev/null
@@ -1,72 +0,0 @@
-update=03/18/19 18:13:51
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=regul
-LibName6=74xx
-LibName7=cmos4000
-LibName8=adc-dac
-LibName9=memory
-LibName10=xilinx
-LibName11=microcontrollers
-LibName12=dsp
-LibName13=microchip
-LibName14=analog_switches
-LibName15=motorola
-LibName16=texas
-LibName17=intel
-LibName18=audio
-LibName19=interface
-LibName20=digital-audio
-LibName21=philips
-LibName22=display
-LibName23=cypress
-LibName24=siliconi
-LibName25=opto
-LibName26=atmel
-LibName27=contrib
-LibName28=valves
-LibName29=eSim_User
-LibName30=eSim_Subckt
-LibName31=eSim_Sources
-LibName32=eSim_PSpice
-LibName33=eSim_Power
-LibName34=eSim_Plot
-LibName35=eSim_Miscellaneous
-LibName36=eSim_Hybrid
-LibName37=eSim_Digital
-LibName38=eSim_Devices
-LibName39=eSim_Analog
diff --git a/src/SubcircuitLibrary/556/556.sch b/src/SubcircuitLibrary/556/556.sch
deleted file mode 100644
index af4e1bc9..00000000
--- a/src/SubcircuitLibrary/556/556.sch
+++ /dev/null
@@ -1,275 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:eSim_Sources
-LIBS:eSim_PSpice
-LIBS:eSim_Power
-LIBS:eSim_Plot
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Hybrid
-LIBS:eSim_Digital
-LIBS:eSim_Devices
-LIBS:eSim_Analog
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L LM555N X1
-U 1 1 5C8F9298
-P 4150 3850
-F 0 "X1" H 4150 3800 60  0000 C CNN
-F 1 "LM555N" H 4150 3950 60  0000 C CNN
-F 2 "" H 4100 3850 60  0000 C CNN
-F 3 "" H 4100 3850 60  0000 C CNN
-	1    4150 3850
-	1    0    0    -1  
-$EndComp
-$Comp
-L LM555N X2
-U 1 1 5C8F92E5
-P 7100 3850
-F 0 "X2" H 7100 3800 60  0000 C CNN
-F 1 "LM555N" H 7100 3950 60  0000 C CNN
-F 2 "" H 7050 3850 60  0000 C CNN
-F 3 "" H 7050 3850 60  0000 C CNN
-	1    7100 3850
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4150 3250 4150 3000
-Wire Wire Line
-	4150 3000 7100 3000
-Wire Wire Line
-	4150 4450 4150 4650
-Wire Wire Line
-	4150 4650 7100 4650
-$Comp
-L PORT U1
-U 14 1 5C8F93E6
-P 4650 2600
-F 0 "U1" H 4700 2700 30  0000 C CNN
-F 1 "PORT" H 4650 2600 30  0000 C CNN
-F 2 "" H 4650 2600 60  0000 C CNN
-F 3 "" H 4650 2600 60  0000 C CNN
-	14   4650 2600
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4900 2600 5000 2600
-Wire Wire Line
-	5000 2600 5000 3000
-Connection ~ 5000 3000
-$Comp
-L PORT U1
-U 6 1 5C8F94B6
-P 3050 3600
-F 0 "U1" H 3100 3700 30  0000 C CNN
-F 1 "PORT" H 3050 3600 30  0000 C CNN
-F 2 "" H 3050 3600 60  0000 C CNN
-F 3 "" H 3050 3600 60  0000 C CNN
-	6    3050 3600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C8F95C0
-P 3050 3850
-F 0 "U1" H 3100 3950 30  0000 C CNN
-F 1 "PORT" H 3050 3850 30  0000 C CNN
-F 2 "" H 3050 3850 60  0000 C CNN
-F 3 "" H 3050 3850 60  0000 C CNN
-	3    3050 3850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C8F95E7
-P 3050 4100
-F 0 "U1" H 3100 4200 30  0000 C CNN
-F 1 "PORT" H 3050 4100 30  0000 C CNN
-F 2 "" H 3050 4100 60  0000 C CNN
-F 3 "" H 3050 4100 60  0000 C CNN
-	4    3050 4100
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7100 3000 7100 3250
-Wire Wire Line
-	7100 4650 7100 4450
-$Comp
-L PORT U1
-U 8 1 5C8F9C35
-P 6000 3600
-F 0 "U1" H 6050 3700 30  0000 C CNN
-F 1 "PORT" H 6000 3600 30  0000 C CNN
-F 2 "" H 6000 3600 60  0000 C CNN
-F 3 "" H 6000 3600 60  0000 C CNN
-	8    6000 3600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C8F9C3B
-P 6000 3850
-F 0 "U1" H 6050 3950 30  0000 C CNN
-F 1 "PORT" H 6000 3850 30  0000 C CNN
-F 2 "" H 6000 3850 60  0000 C CNN
-F 3 "" H 6000 3850 60  0000 C CNN
-	11   6000 3850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C8F9C41
-P 6000 4100
-F 0 "U1" H 6050 4200 30  0000 C CNN
-F 1 "PORT" H 6000 4100 30  0000 C CNN
-F 2 "" H 6000 4100 60  0000 C CNN
-F 3 "" H 6000 4100 60  0000 C CNN
-	10   6000 4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C8F9D22
-P 5200 4100
-F 0 "U1" H 5250 4200 30  0000 C CNN
-F 1 "PORT" H 5200 4100 30  0000 C CNN
-F 2 "" H 5200 4100 60  0000 C CNN
-F 3 "" H 5200 4100 60  0000 C CNN
-	2    5200 4100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C8F9D28
-P 5200 3850
-F 0 "U1" H 5250 3950 30  0000 C CNN
-F 1 "PORT" H 5200 3850 30  0000 C CNN
-F 2 "" H 5200 3850 60  0000 C CNN
-F 3 "" H 5200 3850 60  0000 C CNN
-	1    5200 3850
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C8F9D2E
-P 5200 3600
-F 0 "U1" H 5250 3700 30  0000 C CNN
-F 1 "PORT" H 5200 3600 30  0000 C CNN
-F 2 "" H 5200 3600 60  0000 C CNN
-F 3 "" H 5200 3600 60  0000 C CNN
-	5    5200 3600
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5C8FA0FA
-P 8250 4100
-F 0 "U1" H 8300 4200 30  0000 C CNN
-F 1 "PORT" H 8250 4100 30  0000 C CNN
-F 2 "" H 8250 4100 60  0000 C CNN
-F 3 "" H 8250 4100 60  0000 C CNN
-	12   8250 4100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C8FA100
-P 8250 3850
-F 0 "U1" H 8300 3950 30  0000 C CNN
-F 1 "PORT" H 8250 3850 30  0000 C CNN
-F 2 "" H 8250 3850 60  0000 C CNN
-F 3 "" H 8250 3850 60  0000 C CNN
-	13   8250 3850
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C8FA106
-P 8250 3600
-F 0 "U1" H 8300 3700 30  0000 C CNN
-F 1 "PORT" H 8250 3600 30  0000 C CNN
-F 2 "" H 8250 3600 60  0000 C CNN
-F 3 "" H 8250 3600 60  0000 C CNN
-	9    8250 3600
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C8FA319
-P 4950 5050
-F 0 "U1" H 5000 5150 30  0000 C CNN
-F 1 "PORT" H 4950 5050 30  0000 C CNN
-F 2 "" H 4950 5050 60  0000 C CNN
-F 3 "" H 4950 5050 60  0000 C CNN
-	7    4950 5050
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5200 5050 5200 4650
-Connection ~ 5200 4650
-Wire Wire Line
-	3300 3600 3600 3600
-Wire Wire Line
-	3300 3850 3600 3850
-Wire Wire Line
-	3300 4100 3600 4100
-Wire Wire Line
-	4700 3600 4950 3600
-Wire Wire Line
-	4700 3850 4950 3850
-Wire Wire Line
-	4700 4100 4950 4100
-Wire Wire Line
-	6250 3600 6550 3600
-Wire Wire Line
-	6250 3850 6550 3850
-Wire Wire Line
-	6250 4100 6550 4100
-Wire Wire Line
-	8000 3600 7650 3600
-Wire Wire Line
-	8000 3850 7650 3850
-Wire Wire Line
-	8000 4100 7650 4100
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/556/556.sub b/src/SubcircuitLibrary/556/556.sub
deleted file mode 100644
index a370b703..00000000
--- a/src/SubcircuitLibrary/556/556.sub
+++ /dev/null
@@ -1,9 +0,0 @@
-* Subcircuit 556
-.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* c:\esim\esim\src\subcircuitlibrary\556\556.cir
-.include lm555n.sub
-x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n
-x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n
-* Control Statements
-
-.ends 556
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/556/556_Previous_Values.xml b/src/SubcircuitLibrary/556/556_Previous_Values.xml
deleted file mode 100644
index c025c2d1..00000000
--- a/src/SubcircuitLibrary/556/556_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/5_and/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/5_and/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/5_and/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro
deleted file mode 100644
index 76df4655..00000000
--- a/src/SubcircuitLibrary/5_and/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch
deleted file mode 100644
index d6ac89f9..00000000
--- a/src/SubcircuitLibrary/5_and/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
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-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
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-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
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-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
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-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
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-F 0 "U1" H 3100 3200 30  0000 C CNN
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-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
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diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/5_and/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib
deleted file mode 100644
index ac396288..00000000
--- a/src/SubcircuitLibrary/5_and/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir
deleted file mode 100644
index 6a05b9b5..00000000
--- a/src/SubcircuitLibrary/5_and/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out
deleted file mode 100644
index 6a6b126a..00000000
--- a/src/SubcircuitLibrary/5_and/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro
deleted file mode 100644
index 7a2f090e..00000000
--- a/src/SubcircuitLibrary/5_and/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch
deleted file mode 100644
index e9eb58ee..00000000
--- a/src/SubcircuitLibrary/5_and/5_and.sch
+++ /dev/null
@@ -1,171 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-Title ""
-Date ""
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-$EndDescr
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-F 1 "3_and" H 4750 3850 60  0000 C CNN
-F 2 "" H 3800 3350 60  0000 C CNN
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-	1    3800 3350
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-$EndComp
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-F 3 "" H 4650 3400 60  0000 C CNN
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-F 1 "PORT" H 3350 2700 30  0000 C CNN
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-L PORT U1
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-$EndComp
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-L PORT U1
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-$EndComp
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-$EndComp
-$Comp
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-F 0 "U1" H 3400 3600 30  0000 C CNN
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-F 2 "" H 3350 3500 60  0000 C CNN
-F 3 "" H 3350 3500 60  0000 C CNN
-	5    3350 3500
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-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
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-F 3 "" H 6750 3150 60  0000 C CNN
-	6    6750 3150
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-$EndComp
-Text Notes 3800 2700 0    60   ~ 12
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-Text Notes 3800 3100 0    60   ~ 12
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-Text Notes 3800 3300 0    60   ~ 12
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-Text Notes 6150 3150 0    60   ~ 12
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub
deleted file mode 100644
index 35b10e17..00000000
--- a/src/SubcircuitLibrary/5_and/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_and/analysis b/src/SubcircuitLibrary/5_and/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/5_and/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/3_and-cache.lib b/src/SubcircuitLibrary/5_nand/3_and-cache.lib
deleted file mode 100644
index 0a3ccf7f..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir b/src/SubcircuitLibrary/5_nand/3_and.cir
deleted file mode 100644
index 15f8954d..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir.out b/src/SubcircuitLibrary/5_nand/3_and.cir.out
deleted file mode 100644
index e3c96645..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.pro b/src/SubcircuitLibrary/5_nand/3_and.pro
deleted file mode 100644
index 0fdf4d25..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sch b/src/SubcircuitLibrary/5_nand/3_and.sch
deleted file mode 100644
index c853bf49..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sub b/src/SubcircuitLibrary/5_nand/3_and.sub
deleted file mode 100644
index b949ae4f..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and-cache.lib b/src/SubcircuitLibrary/5_nand/5_and-cache.lib
deleted file mode 100644
index 4cf915be..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir b/src/SubcircuitLibrary/5_nand/5_and.cir
deleted file mode 100644
index ca1199bd..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir.out b/src/SubcircuitLibrary/5_nand/5_and.cir.out
deleted file mode 100644
index 20d3f8a5..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.pro b/src/SubcircuitLibrary/5_nand/5_and.pro
deleted file mode 100644
index a9d6304f..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
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diff --git a/src/SubcircuitLibrary/5_nand/5_and.sch b/src/SubcircuitLibrary/5_nand/5_and.sch
deleted file mode 100644
index 0d86cdec..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.sch
+++ /dev/null
@@ -1,171 +0,0 @@
-EESchema Schematic File Version 2
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-LIBS:eSim_Power
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-LIBS:eSim_Sources
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-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
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diff --git a/src/SubcircuitLibrary/5_nand/5_and.sub b/src/SubcircuitLibrary/5_nand/5_and.sub
deleted file mode 100644
index 9d929fcb..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
deleted file mode 100644
index cb517be1..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib
+++ /dev/null
@@ -1,78 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir b/src/SubcircuitLibrary/5_nand/5_nand.cir
deleted file mode 100644
index e833d0f4..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir.out b/src/SubcircuitLibrary/5_nand/5_nand.cir.out
deleted file mode 100644
index 164de911..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.pro b/src/SubcircuitLibrary/5_nand/5_nand.pro
deleted file mode 100644
index b7d23f44..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=Fri Jun 21 16:46:10 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
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-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
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-LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sch b/src/SubcircuitLibrary/5_nand/5_nand.sch
deleted file mode 100644
index 86379b08..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.sch
+++ /dev/null
@@ -1,175 +0,0 @@
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-	3700 3600 3500 3600
-Wire Wire Line
-	3500 3600 3500 3150
-Wire Wire Line
-	3500 3150 3150 3150
-Wire Wire Line
-	3150 3400 3350 3400
-Wire Wire Line
-	3350 3400 3350 3700
-Wire Wire Line
-	3350 3700 3700 3700
-Wire Wire Line
-	3700 3800 3250 3800
-Wire Wire Line
-	3250 3800 3250 3750
-Wire Wire Line
-	3250 3750 3150 3750
-Wire Wire Line
-	3150 4150 3350 4150
-Wire Wire Line
-	3350 4150 3350 3900
-Wire Wire Line
-	3350 3900 3700 3900
-Wire Wire Line
-	4700 3700 4850 3700
-Wire Wire Line
-	5450 3700 5950 3700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sub b/src/SubcircuitLibrary/5_nand/5_nand.sub
deleted file mode 100644
index c3e041fa..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 5_nand
-.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
-.include 5_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
-* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
-a1 net-_u2-pad1_ net-_u1-pad6_ u2
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nand
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
deleted file mode 100644
index c4b4cde2..00000000
--- a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nand/analysis b/src/SubcircuitLibrary/5_nand/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/5_nand/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/3_and-cache.lib b/src/SubcircuitLibrary/5_nor/3_and-cache.lib
deleted file mode 100644
index 0a3ccf7f..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir b/src/SubcircuitLibrary/5_nor/3_and.cir
deleted file mode 100644
index 15f8954d..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir.out b/src/SubcircuitLibrary/5_nor/3_and.cir.out
deleted file mode 100644
index e3c96645..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nor/3_and.pro b/src/SubcircuitLibrary/5_nor/3_and.pro
deleted file mode 100644
index 0fdf4d25..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_nor/3_and.sch b/src/SubcircuitLibrary/5_nor/3_and.sch
deleted file mode 100644
index c853bf49..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and.sch
+++ /dev/null
@@ -1,130 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Text Notes 3500 2600 0    60   ~ 12
-in1
-Text Notes 3450 2800 0    60   ~ 12
-in2\n
-Text Notes 3500 3100 0    60   ~ 12
-in3
-Text Notes 6100 2850 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nor/3_and.sub b/src/SubcircuitLibrary/5_nor/3_and.sub
deleted file mode 100644
index b949ae4f..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/5_and-cache.lib b/src/SubcircuitLibrary/5_nor/5_and-cache.lib
deleted file mode 100644
index 4cf915be..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir b/src/SubcircuitLibrary/5_nor/5_and.cir
deleted file mode 100644
index ca1199bd..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir.out b/src/SubcircuitLibrary/5_nor/5_and.cir.out
deleted file mode 100644
index 20d3f8a5..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_and.pro b/src/SubcircuitLibrary/5_nor/5_and.pro
deleted file mode 100644
index a9d6304f..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_nor/5_and.sch b/src/SubcircuitLibrary/5_nor/5_and.sch
deleted file mode 100644
index 0d86cdec..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and.sch
+++ /dev/null
@@ -1,171 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60  0000 C CNN
-F 1 "3_and" H 4750 3850 60  0000 C CNN
-F 2 "" H 3800 3350 60  0000 C CNN
-F 3 "" H 3800 3350 60  0000 C CNN
-	1    3800 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60  0000 C CNN
-F 1 "d_and" H 4700 3500 60  0000 C CNN
-F 2 "" H 4650 3400 60  0000 C CNN
-F 3 "" H 4650 3400 60  0000 C CNN
-	1    4650 3400
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-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2791
-P 5550 3200
-F 0 "U3" H 5550 3200 60  0000 C CNN
-F 1 "d_and" H 5600 3300 60  0000 C CNN
-F 2 "" H 5550 3200 60  0000 C CNN
-F 3 "" H 5550 3200 60  0000 C CNN
-	1    5550 3200
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-$EndComp
-Wire Wire Line
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-	4200 3500 3600 3500
-Wire Wire Line
-	6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30  0000 C CNN
-F 1 "PORT" H 3350 2700 30  0000 C CNN
-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
-	1    3350 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30  0000 C CNN
-F 1 "PORT" H 3350 2900 30  0000 C CNN
-F 2 "" H 3350 2900 60  0000 C CNN
-F 3 "" H 3350 2900 60  0000 C CNN
-	2    3350 2900
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-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
-F 0 "U1" H 3400 3200 30  0000 C CNN
-F 1 "PORT" H 3350 3100 30  0000 C CNN
-F 2 "" H 3350 3100 60  0000 C CNN
-F 3 "" H 3350 3100 60  0000 C CNN
-	3    3350 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
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-F 0 "U1" H 3400 3400 30  0000 C CNN
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-F 2 "" H 3350 3300 60  0000 C CNN
-F 3 "" H 3350 3300 60  0000 C CNN
-	4    3350 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
-P 3350 3500
-F 0 "U1" H 3400 3600 30  0000 C CNN
-F 1 "PORT" H 3350 3500 30  0000 C CNN
-F 2 "" H 3350 3500 60  0000 C CNN
-F 3 "" H 3350 3500 60  0000 C CNN
-	5    3350 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
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-F 2 "" H 6750 3150 60  0000 C CNN
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-	6    6750 3150
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-$EndComp
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-Text Notes 6150 3150 0    60   ~ 12
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nor/5_and.sub b/src/SubcircuitLibrary/5_nor/5_and.sub
deleted file mode 100644
index 9d929fcb..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/5_nor-cache.lib b/src/SubcircuitLibrary/5_nor/5_nor-cache.lib
deleted file mode 100644
index 7098010f..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir b/src/SubcircuitLibrary/5_nor/5_nor.cir
deleted file mode 100644
index 0e4db1ea..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor.cir
+++ /dev/null
@@ -1,19 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U8  Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
-U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter		
-U6  Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter		
-U7  Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
-X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and		
-
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir.out b/src/SubcircuitLibrary/5_nor/5_nor.cir.out
deleted file mode 100644
index bc90e004..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor.cir.out
+++ /dev/null
@@ -1,42 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir
-
-.include 5_and.sub
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_nor.pro b/src/SubcircuitLibrary/5_nor/5_nor.pro
deleted file mode 100644
index 4716d4ae..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor.pro
+++ /dev/null
@@ -1,73 +0,0 @@
-update=Tue Jun 25 23:32:34 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_User
-LibName37=eSim_Plot
-LibName38=eSim_PSpice
-LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sch b/src/SubcircuitLibrary/5_nor/5_nor.sch
deleted file mode 100644
index 6bb6fcb8..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor.sch
+++ /dev/null
@@ -1,275 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
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diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sub b/src/SubcircuitLibrary/5_nor/5_nor.sub
deleted file mode 100644
index dbcdb750..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor.sub
+++ /dev/null
@@ -1,36 +0,0 @@
-* Subcircuit 5_nor
-.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir
-.include 5_and.sub
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nor
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml
deleted file mode 100644
index 75f5258c..00000000
--- a/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5_nor/analysis b/src/SubcircuitLibrary/5_nor/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/5_nor/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib
deleted file mode 100644
index b75ae867..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# Full-Adder
-#
-DEF Full-Adder X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "Full-Adder" 0 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 200 300 -200 0 1 0 N
-X A 1 -500 150 200 R 50 50 1 1 I
-X B 2 -500 0 200 R 50 50 1 1 I
-X Cin 3 -500 -150 200 R 50 50 1 1 I
-X Out 4 500 100 200 L 50 50 1 1 I
-X Cout 5 500 -100 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir
deleted file mode 100644
index 84b7b723..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\5bit-Ripple_carry_adder\5bit-Ripple_carry_adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 02:16:47
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X4  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X4-Pad3_ Net-_U1-Pad4_ ? Full-Adder		
-X5  Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X5-Pad3_ Net-_U1-Pad7_ Net-_X4-Pad3_ Full-Adder		
-X6  Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X6-Pad3_ Net-_U1-Pad10_ Net-_X5-Pad3_ Full-Adder		
-X7  Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_X7-Pad3_ Net-_U1-Pad13_ Net-_X6-Pad3_ Full-Adder		
-X8  Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X7-Pad3_ Full-Adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out
deleted file mode 100644
index dfda0a3b..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro
deleted file mode 100644
index d3bfc6c4..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Sat Jun 22 12:25:13 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../eSim-1.1.2/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=9bit-BoothMultiplier-cache
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch
deleted file mode 100644
index dd2e9165..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch
+++ /dev/null
@@ -1,386 +0,0 @@
-EESchema Schematic File Version 2
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diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub
deleted file mode 100644
index 675975d9..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 5bit-Ripple_carry_adder
-.subckt 5bit-Ripple_carry_adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ 
-* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* Control Statements
-
-.ends 5bit-Ripple_carry_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml
deleted file mode 100644
index 8fbbb417..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x8><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x8><x6><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x6><x7><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x7><x4><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x4><x5><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x5></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib
deleted file mode 100644
index cba68b20..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib
+++ /dev/null
@@ -1,100 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
deleted file mode 100644
index ea7aed36..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\Full-Adder\Full-Adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/19 17:15:52
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_xor		
-U5  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_xor		
-U4  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and		
-U6  Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_or		
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
deleted file mode 100644
index 086d8b71..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
+++ /dev/null
@@ -1,32 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro
deleted file mode 100644
index 7089d69d..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=03/21/19 17:06:42
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-last_client=eeschema
-[general]
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-RootSch=
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-[pcbnew]
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-PadDrillOvalY=0.600000000000
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-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
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-LibName11=eSim_User
-LibName12=half-adder
-LibName13=power
-LibName14=device
-LibName15=transistors
-LibName16=conn
-LibName17=linear
-LibName18=regul
-LibName19=74xx
-LibName20=cmos4000
-LibName21=adc-dac
-LibName22=memory
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-LibName24=microcontrollers
-LibName25=dsp
-LibName26=microchip
-LibName27=analog_switches
-LibName28=motorola
-LibName29=texas
-LibName30=intel
-LibName31=audio
-LibName32=interface
-LibName33=digital-audio
-LibName34=philips
-LibName35=display
-LibName36=cypress
-LibName37=siliconi
-LibName38=opto
-LibName39=atmel
-LibName40=contrib
-LibName41=valves
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch
deleted file mode 100644
index 981e7cdb..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch
+++ /dev/null
@@ -1,226 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:half-adder
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:Full-Adder-cache
-EELAYER 25 0
-EELAYER END
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-$EndComp
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-L PORT U1
-U 4 1 5C9377F2
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-$EndComp
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-L PORT U1
-U 5 1 5C937851
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-$EndComp
-$Comp
-L d_xor U2
-U 1 1 5C93788C
-P 5150 2900
-F 0 "U2" H 5150 2900 60  0000 C CNN
-F 1 "d_xor" H 5200 3000 47  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
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-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5C9378DF
-P 6400 2950
-F 0 "U5" H 6400 2950 60  0000 C CNN
-F 1 "d_xor" H 6450 3050 47  0000 C CNN
-F 2 "" H 6400 2950 60  0000 C CNN
-F 3 "" H 6400 2950 60  0000 C CNN
-	1    6400 2950
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-$EndComp
-$Comp
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-U 1 1 5C937928
-P 6150 3300
-F 0 "U4" H 6150 3300 60  0000 C CNN
-F 1 "d_and" H 6200 3400 60  0000 C CNN
-F 2 "" H 6150 3300 60  0000 C CNN
-F 3 "" H 6150 3300 60  0000 C CNN
-	1    6150 3300
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-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9379CF
-P 5200 3500
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-F 2 "" H 5200 3500 60  0000 C CNN
-F 3 "" H 5200 3500 60  0000 C CNN
-	1    5200 3500
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-$EndComp
-$Comp
-L d_or U6
-U 1 1 5C937A14
-P 7250 3550
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-	1    7250 3550
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-$EndComp
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-	5650 3450 6800 3450
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub
deleted file mode 100644
index 0ea4496d..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub
+++ /dev/null
@@ -1,26 +0,0 @@
-* Subcircuit Full-Adder
-.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends Full-Adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml
deleted file mode 100644
index c7136641..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_xor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/74153/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
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-X ~ 18 250 0 100 L 30 30 18 1 B
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-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
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-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/74153/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/74153/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro
deleted file mode 100644
index 2c9ac554..00000000
--- a/src/SubcircuitLibrary/74153/3_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
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-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
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-ModuleTextSizeThickness=0.150000000000
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-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch
deleted file mode 100644
index 86be0215..00000000
--- a/src/SubcircuitLibrary/74153/3_and.sch
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
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-LIBS:intel
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-LIBS:digital-audio
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-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/74153/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib
deleted file mode 100644
index 155f5e60..00000000
--- a/src/SubcircuitLibrary/74153/4_OR-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir
deleted file mode 100644
index b338b7b5..00000000
--- a/src/SubcircuitLibrary/74153/4_OR.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
-U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
-U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out
deleted file mode 100644
index adb6b01b..00000000
--- a/src/SubcircuitLibrary/74153/4_OR.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro
deleted file mode 100644
index 2c258cec..00000000
--- a/src/SubcircuitLibrary/74153/4_OR.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=03/28/19 22:43:48
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch
deleted file mode 100644
index 11896865..00000000
--- a/src/SubcircuitLibrary/74153/4_OR.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60  0000 C CNN
-F 1 "d_or" H 4300 3050 60  0000 C CNN
-F 2 "" H 4300 2950 60  0000 C CNN
-F 3 "" H 4300 2950 60  0000 C CNN
-	1    4300 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60  0000 C CNN
-F 1 "d_or" H 4300 3450 60  0000 C CNN
-F 2 "" H 4300 3350 60  0000 C CNN
-F 3 "" H 4300 3350 60  0000 C CNN
-	1    4300 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60  0000 C CNN
-F 1 "d_or" H 5250 3250 60  0000 C CNN
-F 2 "" H 5250 3150 60  0000 C CNN
-F 3 "" H 5250 3150 60  0000 C CNN
-	1    5250 3150
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4800 3050 4800 2900
-Wire Wire Line
-	4800 2900 4750 2900
-Wire Wire Line
-	4800 3150 4800 3300
-Wire Wire Line
-	4800 3300 4750 3300
-Wire Wire Line
-	3350 2850 3850 2850
-Wire Wire Line
-	3850 2950 3600 2950
-Wire Wire Line
-	3850 3250 3350 3250
-Wire Wire Line
-	3600 2950 3600 3000
-Wire Wire Line
-	3600 3000 3350 3000
-Wire Wire Line
-	3850 3350 3850 3400
-Wire Wire Line
-	3850 3400 3350 3400
-Wire Wire Line
-	5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30  0000 C CNN
-F 1 "PORT" H 3100 2850 30  0000 C CNN
-F 2 "" H 3100 2850 60  0000 C CNN
-F 3 "" H 3100 2850 60  0000 C CNN
-	1    3100 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
-P 3100 3000
-F 0 "U1" H 3150 3100 30  0000 C CNN
-F 1 "PORT" H 3100 3000 30  0000 C CNN
-F 2 "" H 3100 3000 60  0000 C CNN
-F 3 "" H 3100 3000 60  0000 C CNN
-	2    3100 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30  0000 C CNN
-F 1 "PORT" H 3100 3250 30  0000 C CNN
-F 2 "" H 3100 3250 60  0000 C CNN
-F 3 "" H 3100 3250 60  0000 C CNN
-	3    3100 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30  0000 C CNN
-F 1 "PORT" H 3100 3400 30  0000 C CNN
-F 2 "" H 3100 3400 60  0000 C CNN
-F 3 "" H 3100 3400 60  0000 C CNN
-	4    3100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30  0000 C CNN
-F 1 "PORT" H 6450 3100 30  0000 C CNN
-F 2 "" H 6450 3100 60  0000 C CNN
-F 3 "" H 6450 3100 60  0000 C CNN
-	5    6450 3100
-	-1   0    0    1   
-$EndComp
-Text Notes 3450 2850 0    60   ~ 12
-in1
-Text Notes 3450 3000 0    60   ~ 12
-in2
-Text Notes 3450 3250 0    60   ~ 12
-in3
-Text Notes 3450 3400 0    60   ~ 12
-in4
-Text Notes 5800 3100 0    60   ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub
deleted file mode 100644
index d1fd3a24..00000000
--- a/src/SubcircuitLibrary/74153/4_OR.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_OR
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml
deleted file mode 100644
index 23698d37..00000000
--- a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib
deleted file mode 100644
index ac396288..00000000
--- a/src/SubcircuitLibrary/74153/4_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/4_and-rescue.lib b/src/SubcircuitLibrary/74153/4_and-rescue.lib
deleted file mode 100644
index 6b2c17f7..00000000
--- a/src/SubcircuitLibrary/74153/4_and-rescue.lib
+++ /dev/null
@@ -1,22 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir
deleted file mode 100644
index 50d490fa..00000000
--- a/src/SubcircuitLibrary/74153/4_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out
deleted file mode 100644
index f40e5bc6..00000000
--- a/src/SubcircuitLibrary/74153/4_and.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro
deleted file mode 100644
index 6eb77fff..00000000
--- a/src/SubcircuitLibrary/74153/4_and.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/26/19 18:58:33
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch
deleted file mode 100644
index 883458e1..00000000
--- a/src/SubcircuitLibrary/74153/4_and.sch
+++ /dev/null
@@ -1,139 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60  0000 C CNN
-F 1 "3_and" H 4650 4000 60  0000 C CNN
-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60  0000 C CNN
-F 1 "d_and" H 5500 3500 60  0000 C CNN
-F 2 "" H 5450 3400 60  0000 C CNN
-F 3 "" H 5450 3400 60  0000 C CNN
-	1    5450 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5000 3100 5000 3300
-Wire Wire Line
-	4150 3000 4150 2700
-Wire Wire Line
-	4150 2700 3200 2700
-Wire Wire Line
-	4150 3100 4000 3100
-Wire Wire Line
-	4000 3100 4000 3000
-Wire Wire Line
-	4000 3000 3200 3000
-Wire Wire Line
-	4150 3200 4150 3300
-Wire Wire Line
-	4150 3300 3250 3300
-Wire Wire Line
-	5000 3400 5000 3550
-Wire Wire Line
-	5000 3550 3250 3550
-Wire Wire Line
-	5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30  0000 C CNN
-F 1 "PORT" H 2950 2700 30  0000 C CNN
-F 2 "" H 2950 2700 60  0000 C CNN
-F 3 "" H 2950 2700 60  0000 C CNN
-	1    2950 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30  0000 C CNN
-F 1 "PORT" H 2950 3000 30  0000 C CNN
-F 2 "" H 2950 3000 60  0000 C CNN
-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30  0000 C CNN
-F 1 "PORT" H 3000 3300 30  0000 C CNN
-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30  0000 C CNN
-F 1 "PORT" H 3000 3550 30  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	4    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30  0000 C CNN
-F 1 "PORT" H 6750 3350 30  0000 C CNN
-F 2 "" H 6750 3350 60  0000 C CNN
-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
-	-1   0    0    1   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub
deleted file mode 100644
index 8663f37e..00000000
--- a/src/SubcircuitLibrary/74153/4_and.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml
deleted file mode 100644
index f2ba0130..00000000
--- a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib
deleted file mode 100644
index 1e85854e..00000000
--- a/src/SubcircuitLibrary/74153/74153-cache.lib
+++ /dev/null
@@ -1,98 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 4_OR
-#
-DEF 4_OR X 0 40 Y Y 1 F N
-F0 "X" 3900 3050 60 H V C CNN
-F1 "4_OR" 3900 3250 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900
-A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150
-A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150
-P 2 0 1 0  3550 2900  3900 2900 N
-P 2 0 1 0  3550 3400  3900 3400 N
-X in1 1 3400 3300 200 R 50 50 1 1 I
-X in2 2 3400 3200 200 R 50 50 1 1 I
-X in3 3 3400 3100 200 R 50 50 1 1 I
-X in4 4 3400 3000 200 R 50 50 1 1 I
-X out 5 4300 3150 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0  1250 1300  1600 1300 N
-P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir
deleted file mode 100644
index b20e6858..00000000
--- a/src/SubcircuitLibrary/74153/74153.cir
+++ /dev/null
@@ -1,25 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-U35  Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter		
-U34  Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter		
-X8  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and		
-X9  Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and		
-X4  Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and		
-X10  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and		
-X5  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and		
-X6  Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and		
-X3  Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and		
-X7  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and		
-X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR		
-X2  Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR		
-
-.end
diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out
deleted file mode 100644
index c95e5ad9..00000000
--- a/src/SubcircuitLibrary/74153/74153.cir.out
+++ /dev/null
@@ -1,40 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir
-
-.include 4_and.sub
-.include 4_OR.sub
-* u2  net-_u1-pad12_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad11_ net-_u3-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-* u35  net-_u1-pad5_ net-_u35-pad2_ d_inverter
-* u34  net-_u1-pad10_ net-_u34-pad2_ d_inverter
-x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and
-x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and
-x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and
-x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and
-x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and
-x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and
-x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and
-x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR
-x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR
-a1 net-_u1-pad12_ net-_u2-pad2_ u2
-a2 net-_u1-pad11_ net-_u3-pad2_ u3
-a3 net-_u1-pad5_ net-_u35-pad2_ u35
-a4 net-_u1-pad10_ net-_u34-pad2_ u34
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro
deleted file mode 100644
index ed8b8bf2..00000000
--- a/src/SubcircuitLibrary/74153/74153.pro
+++ /dev/null
@@ -1,59 +0,0 @@
-update=03/28/19 23:27:36
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=texas
-LibName4=intel
-LibName5=audio
-LibName6=interface
-LibName7=digital-audio
-LibName8=philips
-LibName9=display
-LibName10=cypress
-LibName11=siliconi
-LibName12=opto
-LibName13=atmel
-LibName14=contrib
-LibName15=valves
-LibName16=eSim_Analog
-LibName17=eSim_Devices
-LibName18=eSim_Digital
-LibName19=eSim_Hybrid
-LibName20=eSim_Miscellaneous
-LibName21=eSim_Plot
-LibName22=eSim_Power
-LibName23=eSim_PSpice
-LibName24=eSim_Sources
-LibName25=eSim_User
-LibName26=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch
deleted file mode 100644
index e0bcf950..00000000
--- a/src/SubcircuitLibrary/74153/74153.sch
+++ /dev/null
@@ -1,568 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:74153-cache
-EELAYER 25 0
-EELAYER END
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diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub
deleted file mode 100644
index 6e00261f..00000000
--- a/src/SubcircuitLibrary/74153/74153.sub
+++ /dev/null
@@ -1,34 +0,0 @@
-* Subcircuit 74153
-.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir
-.include 4_and.sub
-.include 4_OR.sub
-* u2  net-_u1-pad12_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad11_ net-_u3-pad2_ d_inverter
-* u35  net-_u1-pad5_ net-_u35-pad2_ d_inverter
-* u34  net-_u1-pad10_ net-_u34-pad2_ d_inverter
-x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and
-x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and
-x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and
-x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and
-x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and
-x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and
-x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and
-x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR
-x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR
-a1 net-_u1-pad12_ net-_u2-pad2_ u2
-a2 net-_u1-pad11_ net-_u3-pad2_ u3
-a3 net-_u1-pad5_ net-_u35-pad2_ u35
-a4 net-_u1-pad10_ net-_u34-pad2_ u34
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 74153
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml
deleted file mode 100644
index ea70e6f3..00000000
--- a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib
deleted file mode 100644
index 10496d63..00000000
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib
+++ /dev/null
@@ -1,94 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir
deleted file mode 100644
index 583c4a00..00000000
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir
+++ /dev/null
@@ -1,45 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U14  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and		
-U25  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and		
-U5  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and		
-U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and		
-U7  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and		
-U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and		
-U18  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and		
-U24  Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and		
-U28  Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or		
-U29  Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or		
-U32  Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or		
-U2  Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter		
-U3  Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter		
-U15  Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and		
-U6  Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and		
-U8  Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and		
-U4  Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and		
-U16  Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and		
-U27  Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and		
-U10  Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and		
-U22  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and		
-U12  Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and		
-U23  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and		
-U19  Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and		
-U26  Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and		
-U30  Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or		
-U31  Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or		
-U33  Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or		
-U17  Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and		
-U11  Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
-U13  Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
-U9  Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-U34  Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter		
-U35  Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter		
-
-.end
diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch
deleted file mode 100644
index 340b1a31..00000000
--- a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch
+++ /dev/null
@@ -1,814 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:74153-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-P 5900 2550
-F 0 "U28" H 5900 2550 60  0000 C CNN
-F 1 "d_or" H 5900 2650 60  0000 C CNN
-F 2 "" H 5900 2550 60  0000 C CNN
-F 3 "" H 5900 2550 60  0000 C CNN
-	1    5900 2550
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U29
-U 1 1 5C9373A8
-P 5900 2800
-F 0 "U29" H 5900 2800 60  0000 C CNN
-F 1 "d_or" H 5900 2900 60  0000 C CNN
-F 2 "" H 5900 2800 60  0000 C CNN
-F 3 "" H 5900 2800 60  0000 C CNN
-	1    5900 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U32
-U 1 1 5C9373FC
-P 6850 2650
-F 0 "U32" H 6850 2650 60  0000 C CNN
-F 1 "d_or" H 6850 2750 60  0000 C CNN
-F 2 "" H 6850 2650 60  0000 C CNN
-F 3 "" H 6850 2650 60  0000 C CNN
-	1    6850 2650
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4400 1850 4400 2050
-Wire Wire Line
-	4400 2500 4400 2400
-Wire Wire Line
-	4400 2400 4300 2400
-Wire Wire Line
-	4350 3100 4350 3000
-Wire Wire Line
-	4350 3000 4250 3000
-Wire Wire Line
-	4350 3600 4350 3500
-Wire Wire Line
-	4350 3500 4250 3500
-Wire Wire Line
-	6400 2550 6400 2500
-Wire Wire Line
-	6400 2500 6350 2500
-Wire Wire Line
-	6400 2650 6400 2750
-Wire Wire Line
-	6400 2750 6350 2750
-Wire Wire Line
-	5450 2450 5350 2450
-Wire Wire Line
-	5350 2450 5350 2100
-Wire Wire Line
-	5350 2100 5300 2100
-Wire Wire Line
-	5300 2550 5450 2550
-Wire Wire Line
-	5450 2700 5300 2700
-Wire Wire Line
-	5300 2700 5300 3150
-Wire Wire Line
-	5300 3150 5250 3150
-Wire Wire Line
-	5250 3650 5400 3650
-Wire Wire Line
-	5400 3650 5400 2800
-Wire Wire Line
-	5400 2800 5450 2800
-$Comp
-L d_inverter U2
-U 1 1 5C9378F6
-P 2650 1350
-F 0 "U2" H 2650 1250 60  0000 C CNN
-F 1 "d_inverter" H 2650 1500 60  0000 C CNN
-F 2 "" H 2700 1300 60  0000 C CNN
-F 3 "" H 2700 1300 60  0000 C CNN
-	1    2650 1350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U3
-U 1 1 5C93798D
-P 2700 950
-F 0 "U3" H 2700 850 60  0000 C CNN
-F 1 "d_inverter" H 2700 1100 60  0000 C CNN
-F 2 "" H 2750 900 60  0000 C CNN
-F 3 "" H 2750 900 60  0000 C CNN
-	1    2700 950 
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3500 1800 3100 1800
-Wire Wire Line
-	3100 1350 3100 5600
-Wire Wire Line
-	3500 1900 3200 1900
-Wire Wire Line
-	3200 950  3200 5100
-Wire Wire Line
-	2950 1350 3100 1350
-Connection ~ 3100 1800
-Wire Wire Line
-	3000 950  3200 950 
-Connection ~ 3200 1900
-Wire Wire Line
-	1800 950  2400 950 
-Wire Wire Line
-	1800 1350 2350 1350
-Wire Wire Line
-	2200 950  2200 6200
-Connection ~ 2200 950 
-Wire Wire Line
-	2300 1350 2300 6100
-$Comp
-L d_and U15
-U 1 1 5C937C96
-P 3850 2700
-F 0 "U15" H 3850 2700 60  0000 C CNN
-F 1 "d_and" H 3900 2800 60  0000 C CNN
-F 2 "" H 3850 2700 60  0000 C CNN
-F 3 "" H 3850 2700 60  0000 C CNN
-	1    3850 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U6
-U 1 1 5C937CEE
-P 3800 3300
-F 0 "U6" H 3800 3300 60  0000 C CNN
-F 1 "d_and" H 3850 3400 60  0000 C CNN
-F 2 "" H 3800 3300 60  0000 C CNN
-F 3 "" H 3800 3300 60  0000 C CNN
-	1    3800 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U8
-U 1 1 5C937D35
-P 3800 3800
-F 0 "U8" H 3800 3800 60  0000 C CNN
-F 1 "d_and" H 3850 3900 60  0000 C CNN
-F 2 "" H 3800 3800 60  0000 C CNN
-F 3 "" H 3800 3800 60  0000 C CNN
-	1    3800 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C937DC5
-P 3800 2150
-F 0 "U4" H 3800 2150 60  0000 C CNN
-F 1 "d_and" H 3850 2250 60  0000 C CNN
-F 2 "" H 3800 2150 60  0000 C CNN
-F 3 "" H 3800 2150 60  0000 C CNN
-	1    3800 2150
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3350 2150 3300 2150
-Wire Wire Line
-	3300 2150 3300 3800
-Wire Wire Line
-	3300 2700 3400 2700
-Wire Wire Line
-	3300 3300 3350 3300
-Connection ~ 3300 2700
-Wire Wire Line
-	3000 3800 3350 3800
-Connection ~ 3300 3300
-Wire Wire Line
-	4350 3200 4350 3250
-Wire Wire Line
-	4350 3250 4250 3250
-Wire Wire Line
-	4400 2600 4400 2650
-Wire Wire Line
-	4400 2650 4300 2650
-Wire Wire Line
-	4400 2150 4300 2150
-Wire Wire Line
-	4300 2150 4300 2100
-Wire Wire Line
-	4300 2100 4250 2100
-Wire Wire Line
-	4350 3700 4250 3700
-Wire Wire Line
-	4250 3700 4250 3750
-Wire Wire Line
-	3350 3700 1600 3700
-Wire Wire Line
-	3350 3200 1600 3200
-Wire Wire Line
-	3400 2600 1600 2600
-Wire Wire Line
-	3350 2050 1600 2050
-Wire Wire Line
-	3000 3950 3000 3800
-Wire Wire Line
-	2950 3950 3000 3950
-Wire Wire Line
-	1600 3950 2350 3950
-Connection ~ 3300 3800
-$Comp
-L d_and U16
-U 1 1 5C9388D0
-P 3850 5100
-F 0 "U16" H 3850 5100 60  0000 C CNN
-F 1 "d_and" H 3900 5200 60  0000 C CNN
-F 2 "" H 3850 5100 60  0000 C CNN
-F 3 "" H 3850 5100 60  0000 C CNN
-	1    3850 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U27
-U 1 1 5C9388D6
-P 4850 5250
-F 0 "U27" H 4850 5250 60  0000 C CNN
-F 1 "d_and" H 4900 5350 60  0000 C CNN
-F 2 "" H 4850 5250 60  0000 C CNN
-F 3 "" H 4850 5250 60  0000 C CNN
-	1    4850 5250
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U10
-U 1 1 5C9388DC
-P 3800 5700
-F 0 "U10" H 3800 5700 60  0000 C CNN
-F 1 "d_and" H 3850 5800 60  0000 C CNN
-F 2 "" H 3800 5700 60  0000 C CNN
-F 3 "" H 3800 5700 60  0000 C CNN
-	1    3800 5700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U22
-U 1 1 5C9388E2
-P 4800 5850
-F 0 "U22" H 4800 5850 60  0000 C CNN
-F 1 "d_and" H 4850 5950 60  0000 C CNN
-F 2 "" H 4800 5850 60  0000 C CNN
-F 3 "" H 4800 5850 60  0000 C CNN
-	1    4800 5850
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U12
-U 1 1 5C9388E8
-P 3800 6200
-F 0 "U12" H 3800 6200 60  0000 C CNN
-F 1 "d_and" H 3850 6300 60  0000 C CNN
-F 2 "" H 3800 6200 60  0000 C CNN
-F 3 "" H 3800 6200 60  0000 C CNN
-	1    3800 6200
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U23
-U 1 1 5C9388EE
-P 4800 6350
-F 0 "U23" H 4800 6350 60  0000 C CNN
-F 1 "d_and" H 4850 6450 60  0000 C CNN
-F 2 "" H 4800 6350 60  0000 C CNN
-F 3 "" H 4800 6350 60  0000 C CNN
-	1    4800 6350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U19
-U 1 1 5C9388F4
-P 3950 4550
-F 0 "U19" H 3950 4550 60  0000 C CNN
-F 1 "d_and" H 4000 4650 60  0000 C CNN
-F 2 "" H 3950 4550 60  0000 C CNN
-F 3 "" H 3950 4550 60  0000 C CNN
-	1    3950 4550
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U26
-U 1 1 5C9388FA
-P 4850 4800
-F 0 "U26" H 4850 4800 60  0000 C CNN
-F 1 "d_and" H 4900 4900 60  0000 C CNN
-F 2 "" H 4850 4800 60  0000 C CNN
-F 3 "" H 4850 4800 60  0000 C CNN
-	1    4850 4800
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U30
-U 1 1 5C938900
-P 5900 5200
-F 0 "U30" H 5900 5200 60  0000 C CNN
-F 1 "d_or" H 5900 5300 60  0000 C CNN
-F 2 "" H 5900 5200 60  0000 C CNN
-F 3 "" H 5900 5200 60  0000 C CNN
-	1    5900 5200
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U31
-U 1 1 5C938906
-P 5900 5450
-F 0 "U31" H 5900 5450 60  0000 C CNN
-F 1 "d_or" H 5900 5550 60  0000 C CNN
-F 2 "" H 5900 5450 60  0000 C CNN
-F 3 "" H 5900 5450 60  0000 C CNN
-	1    5900 5450
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U33
-U 1 1 5C93890C
-P 6850 5300
-F 0 "U33" H 6850 5300 60  0000 C CNN
-F 1 "d_or" H 6850 5400 60  0000 C CNN
-F 2 "" H 6850 5300 60  0000 C CNN
-F 3 "" H 6850 5300 60  0000 C CNN
-	1    6850 5300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4400 4500 4400 4700
-Wire Wire Line
-	4400 5150 4400 5050
-Wire Wire Line
-	4400 5050 4300 5050
-Wire Wire Line
-	4350 5750 4350 5650
-Wire Wire Line
-	4350 5650 4250 5650
-Wire Wire Line
-	4350 6250 4350 6150
-Wire Wire Line
-	4350 6150 4250 6150
-Wire Wire Line
-	6400 5200 6400 5150
-Wire Wire Line
-	6400 5150 6350 5150
-Wire Wire Line
-	6400 5300 6400 5400
-Wire Wire Line
-	6400 5400 6350 5400
-Wire Wire Line
-	5450 5100 5350 5100
-Wire Wire Line
-	5350 5100 5350 4750
-Wire Wire Line
-	5350 4750 5300 4750
-Wire Wire Line
-	5300 5200 5450 5200
-Wire Wire Line
-	5450 5350 5300 5350
-Wire Wire Line
-	5300 5350 5300 5800
-Wire Wire Line
-	5300 5800 5250 5800
-Wire Wire Line
-	5250 6300 5400 6300
-Wire Wire Line
-	5400 6300 5400 5450
-Wire Wire Line
-	5400 5450 5450 5450
-Wire Wire Line
-	3100 4450 3500 4450
-Wire Wire Line
-	3200 4550 3500 4550
-$Comp
-L d_and U17
-U 1 1 5C938937
-P 3850 5350
-F 0 "U17" H 3850 5350 60  0000 C CNN
-F 1 "d_and" H 3900 5450 60  0000 C CNN
-F 2 "" H 3850 5350 60  0000 C CNN
-F 3 "" H 3850 5350 60  0000 C CNN
-	1    3850 5350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U11
-U 1 1 5C93893D
-P 3800 5950
-F 0 "U11" H 3800 5950 60  0000 C CNN
-F 1 "d_and" H 3850 6050 60  0000 C CNN
-F 2 "" H 3800 5950 60  0000 C CNN
-F 3 "" H 3800 5950 60  0000 C CNN
-	1    3800 5950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U13
-U 1 1 5C938943
-P 3800 6450
-F 0 "U13" H 3800 6450 60  0000 C CNN
-F 1 "d_and" H 3850 6550 60  0000 C CNN
-F 2 "" H 3800 6450 60  0000 C CNN
-F 3 "" H 3800 6450 60  0000 C CNN
-	1    3800 6450
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U9
-U 1 1 5C938949
-P 3800 4800
-F 0 "U9" H 3800 4800 60  0000 C CNN
-F 1 "d_and" H 3850 4900 60  0000 C CNN
-F 2 "" H 3800 4800 60  0000 C CNN
-F 3 "" H 3800 4800 60  0000 C CNN
-	1    3800 4800
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3350 4800 3300 4800
-Wire Wire Line
-	3300 4800 3300 6450
-Wire Wire Line
-	3300 5350 3400 5350
-Wire Wire Line
-	3300 5950 3350 5950
-Connection ~ 3300 5350
-Wire Wire Line
-	3200 6450 3350 6450
-Connection ~ 3300 5950
-Wire Wire Line
-	4350 5850 4350 5900
-Wire Wire Line
-	4350 5900 4250 5900
-Wire Wire Line
-	4400 5250 4400 5300
-Wire Wire Line
-	4400 5300 4300 5300
-Wire Wire Line
-	4400 4800 4300 4800
-Wire Wire Line
-	4300 4800 4300 4750
-Wire Wire Line
-	4300 4750 4250 4750
-Wire Wire Line
-	4350 6350 4250 6350
-Wire Wire Line
-	4250 6350 4250 6400
-Wire Wire Line
-	3350 6350 1600 6350
-Wire Wire Line
-	3350 5850 1600 5850
-Wire Wire Line
-	3400 5250 1600 5250
-Wire Wire Line
-	3350 4700 1600 4700
-Wire Wire Line
-	3200 6600 3200 6450
-Wire Wire Line
-	3000 6600 3200 6600
-Wire Wire Line
-	1600 6600 2400 6600
-Connection ~ 3300 6450
-Connection ~ 2300 1350
-Connection ~ 3100 4450
-Connection ~ 3200 4550
-$Comp
-L PORT U1
-U 1 1 5C93A0F9
-P 1350 2050
-F 0 "U1" H 1400 2150 30  0000 C CNN
-F 1 "PORT" H 1350 2050 30  0000 C CNN
-F 2 "" H 1350 2050 60  0000 C CNN
-F 3 "" H 1350 2050 60  0000 C CNN
-	1    1350 2050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C93A174
-P 1350 4700
-F 0 "U1" H 1400 4800 30  0000 C CNN
-F 1 "PORT" H 1350 4700 30  0000 C CNN
-F 2 "" H 1350 4700 60  0000 C CNN
-F 3 "" H 1350 4700 60  0000 C CNN
-	6    1350 4700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C93AA3C
-P 1350 2600
-F 0 "U1" H 1400 2700 30  0000 C CNN
-F 1 "PORT" H 1350 2600 30  0000 C CNN
-F 2 "" H 1350 2600 60  0000 C CNN
-F 3 "" H 1350 2600 60  0000 C CNN
-	2    1350 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C93AACB
-P 1350 3200
-F 0 "U1" H 1400 3300 30  0000 C CNN
-F 1 "PORT" H 1350 3200 30  0000 C CNN
-F 2 "" H 1350 3200 60  0000 C CNN
-F 3 "" H 1350 3200 60  0000 C CNN
-	3    1350 3200
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C93AB5F
-P 1350 3700
-F 0 "U1" H 1400 3800 30  0000 C CNN
-F 1 "PORT" H 1350 3700 30  0000 C CNN
-F 2 "" H 1350 3700 60  0000 C CNN
-F 3 "" H 1350 3700 60  0000 C CNN
-	4    1350 3700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C93AD97
-P 1350 5250
-F 0 "U1" H 1400 5350 30  0000 C CNN
-F 1 "PORT" H 1350 5250 30  0000 C CNN
-F 2 "" H 1350 5250 60  0000 C CNN
-F 3 "" H 1350 5250 60  0000 C CNN
-	7    1350 5250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C93ADFC
-P 1350 5850
-F 0 "U1" H 1400 5950 30  0000 C CNN
-F 1 "PORT" H 1350 5850 30  0000 C CNN
-F 2 "" H 1350 5850 60  0000 C CNN
-F 3 "" H 1350 5850 60  0000 C CNN
-	8    1350 5850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C93AE63
-P 1350 6350
-F 0 "U1" H 1400 6450 30  0000 C CNN
-F 1 "PORT" H 1350 6350 30  0000 C CNN
-F 2 "" H 1350 6350 60  0000 C CNN
-F 3 "" H 1350 6350 60  0000 C CNN
-	9    1350 6350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C93AECA
-P 1350 3950
-F 0 "U1" H 1400 4050 30  0000 C CNN
-F 1 "PORT" H 1350 3950 30  0000 C CNN
-F 2 "" H 1350 3950 60  0000 C CNN
-F 3 "" H 1350 3950 60  0000 C CNN
-	5    1350 3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C93AF79
-P 1350 6600
-F 0 "U1" H 1400 6700 30  0000 C CNN
-F 1 "PORT" H 1350 6600 30  0000 C CNN
-F 2 "" H 1350 6600 60  0000 C CNN
-F 3 "" H 1350 6600 60  0000 C CNN
-	10   1350 6600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C93B10A
-P 1550 950
-F 0 "U1" H 1600 1050 30  0000 C CNN
-F 1 "PORT" H 1550 950 30  0000 C CNN
-F 2 "" H 1550 950 60  0000 C CNN
-F 3 "" H 1550 950 60  0000 C CNN
-	11   1550 950 
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5C93B179
-P 1550 1350
-F 0 "U1" H 1600 1450 30  0000 C CNN
-F 1 "PORT" H 1550 1350 30  0000 C CNN
-F 2 "" H 1550 1350 60  0000 C CNN
-F 3 "" H 1550 1350 60  0000 C CNN
-	12   1550 1350
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7300 2600 7600 2600
-Wire Wire Line
-	7300 5250 7650 5250
-$Comp
-L PORT U1
-U 13 1 5C93B567
-P 7850 2600
-F 0 "U1" H 7900 2700 30  0000 C CNN
-F 1 "PORT" H 7850 2600 30  0000 C CNN
-F 2 "" H 7850 2600 60  0000 C CNN
-F 3 "" H 7850 2600 60  0000 C CNN
-	13   7850 2600
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C93B5DA
-P 7900 5250
-F 0 "U1" H 7950 5350 30  0000 C CNN
-F 1 "PORT" H 7900 5250 30  0000 C CNN
-F 2 "" H 7900 5250 60  0000 C CNN
-F 3 "" H 7900 5250 60  0000 C CNN
-	14   7900 5250
-	-1   0    0    1   
-$EndComp
-Connection ~ 2200 3450
-Wire Wire Line
-	3200 5100 3400 5100
-Wire Wire Line
-	3400 5000 2300 5000
-Connection ~ 2300 5000
-Wire Wire Line
-	3100 5600 3350 5600
-Wire Wire Line
-	2200 5700 3350 5700
-Wire Wire Line
-	2200 6200 3350 6200
-Connection ~ 2200 5700
-Wire Wire Line
-	2300 6100 3350 6100
-Wire Wire Line
-	3400 2450 3200 2450
-Connection ~ 3200 2450
-Wire Wire Line
-	3400 2350 2300 2350
-Connection ~ 2300 2350
-Wire Wire Line
-	3350 3050 2200 3050
-Connection ~ 2200 3050
-Wire Wire Line
-	3350 2950 3100 2950
-Connection ~ 3100 2950
-Wire Wire Line
-	3350 3450 2300 3450
-Wire Wire Line
-	2300 3450 2300 3400
-Connection ~ 2300 3400
-Wire Wire Line
-	3350 3550 2200 3550
-Connection ~ 2200 3550
-$Comp
-L d_inverter U34
-U 1 1 5C95C9D0
-P 2650 3950
-F 0 "U34" H 2650 3850 60  0000 C CNN
-F 1 "d_inverter" H 2650 4100 60  0000 C CNN
-F 2 "" H 2700 3900 60  0000 C CNN
-F 3 "" H 2700 3900 60  0000 C CNN
-	1    2650 3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U35
-U 1 1 5C95CD17
-P 2700 6600
-F 0 "U35" H 2700 6500 60  0000 C CNN
-F 1 "d_inverter" H 2700 6750 60  0000 C CNN
-F 2 "" H 2750 6550 60  0000 C CNN
-F 3 "" H 2750 6550 60  0000 C CNN
-	1    2700 6600
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/74153/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/74157/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/74157/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/74157/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro
deleted file mode 100644
index 2c9ac554..00000000
--- a/src/SubcircuitLibrary/74157/3_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch
deleted file mode 100644
index 86be0215..00000000
--- a/src/SubcircuitLibrary/74157/3_and.sch
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/74157/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib
deleted file mode 100644
index de171255..00000000
--- a/src/SubcircuitLibrary/74157/74157-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/74157-rescue.lib b/src/SubcircuitLibrary/74157/74157-rescue.lib
deleted file mode 100644
index cac27fc1..00000000
--- a/src/SubcircuitLibrary/74157/74157-rescue.lib
+++ /dev/null
@@ -1,22 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-74157
-#
-DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir
deleted file mode 100644
index 6920161c..00000000
--- a/src/SubcircuitLibrary/74157/74157.cir
+++ /dev/null
@@ -1,25 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U20  Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or		
-U21  Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or		
-U22  Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or		
-U23  Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or		
-U3  Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-U2  Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter		
-X2  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and		
-X3  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and		
-X4  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and		
-X5  Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and		
-X6  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and		
-X7  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and		
-X1  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and		
-X8  Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and		
-
-.end
diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out
deleted file mode 100644
index 3a11a42d..00000000
--- a/src/SubcircuitLibrary/74157/74157.cir.out
+++ /dev/null
@@ -1,45 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
-
-.include 3_and.sub
-* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
-* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
-* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
-* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
-* u3  net-_u1-pad10_ net-_u3-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-* u2  net-_u1-pad9_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
-a5 net-_u1-pad10_ net-_u3-pad2_ u3
-a6 net-_u1-pad9_ net-_u2-pad2_ u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro
deleted file mode 100644
index fcbb1fc8..00000000
--- a/src/SubcircuitLibrary/74157/74157.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/28/19 22:30:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_User
-LibName24=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch
deleted file mode 100644
index 7fd3609e..00000000
--- a/src/SubcircuitLibrary/74157/74157.sch
+++ /dev/null
@@ -1,549 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:74157-cache
-EELAYER 25 0
-EELAYER END
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diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub
deleted file mode 100644
index 545741f5..00000000
--- a/src/SubcircuitLibrary/74157/74157.sub
+++ /dev/null
@@ -1,39 +0,0 @@
-* Subcircuit 74157
-.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
-.include 3_and.sub
-* u20  net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
-* u21  net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
-* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
-* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
-* u3  net-_u1-pad10_ net-_u3-pad2_ d_inverter
-* u2  net-_u1-pad9_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
-a5 net-_u1-pad10_ net-_u3-pad2_ u3
-a6 net-_u1-pad9_ net-_u2-pad2_ u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 74157
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
deleted file mode 100644
index 85f14960..00000000
--- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/analysis b/src/SubcircuitLibrary/74157/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/74157/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/7485/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/7485/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/7485/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro
deleted file mode 100644
index 2c9ac554..00000000
--- a/src/SubcircuitLibrary/7485/3_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch
deleted file mode 100644
index 86be0215..00000000
--- a/src/SubcircuitLibrary/7485/3_and.sch
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4700 2650 4700 2800
-Wire Wire Line
-	5600 2850 6650 2850
-Wire Wire Line
-	3800 2600 3300 2600
-Wire Wire Line
-	3800 2700 3300 2700
-Wire Wire Line
-	3300 2700 3300 2800
-Wire Wire Line
-	3300 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/7485/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib
deleted file mode 100644
index ac396288..00000000
--- a/src/SubcircuitLibrary/7485/4_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and-rescue.lib b/src/SubcircuitLibrary/7485/4_and-rescue.lib
deleted file mode 100644
index 6b2c17f7..00000000
--- a/src/SubcircuitLibrary/7485/4_and-rescue.lib
+++ /dev/null
@@ -1,22 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir
deleted file mode 100644
index 50d490fa..00000000
--- a/src/SubcircuitLibrary/7485/4_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
-U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out
deleted file mode 100644
index f40e5bc6..00000000
--- a/src/SubcircuitLibrary/7485/4_and.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro
deleted file mode 100644
index 6eb77fff..00000000
--- a/src/SubcircuitLibrary/7485/4_and.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/26/19 18:58:33
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch
deleted file mode 100644
index 883458e1..00000000
--- a/src/SubcircuitLibrary/7485/4_and.sch
+++ /dev/null
@@ -1,139 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-U 1 1 5C9A2915
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-F 2 "" H 3700 3500 60  0000 C CNN
-F 3 "" H 3700 3500 60  0000 C CNN
-	1    3700 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
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-F 3 "" H 5450 3400 60  0000 C CNN
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-Wire Wire Line
-	5000 3550 3250 3550
-Wire Wire Line
-	5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
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-F 1 "PORT" H 2950 2700 30  0000 C CNN
-F 2 "" H 2950 2700 60  0000 C CNN
-F 3 "" H 2950 2700 60  0000 C CNN
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-$EndComp
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-L PORT U1
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-F 3 "" H 2950 3000 60  0000 C CNN
-	2    2950 3000
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-$EndComp
-$Comp
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-F 2 "" H 3000 3300 60  0000 C CNN
-F 3 "" H 3000 3300 60  0000 C CNN
-	3    3000 3300
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-$EndComp
-$Comp
-L PORT U1
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-$EndComp
-$Comp
-L PORT U1
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-F 3 "" H 6750 3350 60  0000 C CNN
-	5    6750 3350
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-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub
deleted file mode 100644
index 8663f37e..00000000
--- a/src/SubcircuitLibrary/7485/4_and.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml
deleted file mode 100644
index f2ba0130..00000000
--- a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib
deleted file mode 100644
index ac396288..00000000
--- a/src/SubcircuitLibrary/7485/5_and-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir
deleted file mode 100644
index 6a05b9b5..00000000
--- a/src/SubcircuitLibrary/7485/5_and.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out
deleted file mode 100644
index 6a6b126a..00000000
--- a/src/SubcircuitLibrary/7485/5_and.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro
deleted file mode 100644
index c82e4e6d..00000000
--- a/src/SubcircuitLibrary/7485/5_and.pro
+++ /dev/null
@@ -1,50 +0,0 @@
-update=03/26/19 18:50:27
-version=1
-last_client=eeschema
-[general]
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-RootSch=
-BoardNm=
-[pcbnew]
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-DrawSegmentWidth=0.200000000000
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-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
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-LibName2=siliconi
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-LibName5=contrib
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-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch
deleted file mode 100644
index da927b09..00000000
--- a/src/SubcircuitLibrary/7485/5_and.sch
+++ /dev/null
@@ -1,158 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
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-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
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-LIBS:eSim_Power
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-LIBS:eSim_User
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-Wire Wire Line
-	6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30  0000 C CNN
-F 1 "PORT" H 3350 2700 30  0000 C CNN
-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
-	1    3350 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30  0000 C CNN
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-F 2 "" H 3350 2900 60  0000 C CNN
-F 3 "" H 3350 2900 60  0000 C CNN
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-$EndComp
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-L PORT U1
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-$EndComp
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-U 5 1 5C9A2928
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-$EndComp
-$Comp
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-	6    6750 3150
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diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub
deleted file mode 100644
index 35b10e17..00000000
--- a/src/SubcircuitLibrary/7485/5_and.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml
deleted file mode 100644
index ae2c08a7..00000000
--- a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/5_nor-cache.lib b/src/SubcircuitLibrary/7485/5_nor-cache.lib
deleted file mode 100644
index 7098010f..00000000
--- a/src/SubcircuitLibrary/7485/5_nor-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/5_nor.cir b/src/SubcircuitLibrary/7485/5_nor.cir
deleted file mode 100644
index 0e4db1ea..00000000
--- a/src/SubcircuitLibrary/7485/5_nor.cir
+++ /dev/null
@@ -1,19 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U8  Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
-U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter		
-U6  Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter		
-U7  Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
-X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/5_nor.cir.out b/src/SubcircuitLibrary/7485/5_nor.cir.out
deleted file mode 100644
index bc90e004..00000000
--- a/src/SubcircuitLibrary/7485/5_nor.cir.out
+++ /dev/null
@@ -1,42 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir
-
-.include 5_and.sub
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/5_nor.pro b/src/SubcircuitLibrary/7485/5_nor.pro
deleted file mode 100644
index 4716d4ae..00000000
--- a/src/SubcircuitLibrary/7485/5_nor.pro
+++ /dev/null
@@ -1,73 +0,0 @@
-update=Tue Jun 25 23:32:34 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_User
-LibName37=eSim_Plot
-LibName38=eSim_PSpice
-LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/7485/5_nor.sch b/src/SubcircuitLibrary/7485/5_nor.sch
deleted file mode 100644
index 6bb6fcb8..00000000
--- a/src/SubcircuitLibrary/7485/5_nor.sch
+++ /dev/null
@@ -1,275 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:eSim_Subckt
-LIBS:c_gate-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-P 5600 3300
-F 0 "U8" H 5600 3300 60  0000 C CNN
-F 1 "d_and" H 5650 3400 60  0000 C CNN
-F 2 "" H 5600 3300 60  0000 C CNN
-F 3 "" H 5600 3300 60  0000 C CNN
-	1    5600 3300
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-$EndComp
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-Wire Wire Line
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-$Comp
-L d_inverter U2
-U 1 1 5D126276
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-F 0 "U2" H 3300 2250 60  0000 C CNN
-F 1 "d_inverter" H 3300 2500 60  0000 C CNN
-F 2 "" H 3350 2300 60  0000 C CNN
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-$EndComp
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-F 2 "" H 3350 2500 60  0000 C CNN
-F 3 "" H 3350 2500 60  0000 C CNN
-	1    3300 2550
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-$EndComp
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-U 1 1 5D126278
-P 3300 2750
-F 0 "U4" H 3300 2650 60  0000 C CNN
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-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
-	1    3300 2750
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-$EndComp
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-U 1 1 5D126279
-P 3300 2950
-F 0 "U5" H 3300 2850 60  0000 C CNN
-F 1 "d_inverter" H 3300 3100 60  0000 C CNN
-F 2 "" H 3350 2900 60  0000 C CNN
-F 3 "" H 3350 2900 60  0000 C CNN
-	1    3300 2950
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-$EndComp
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-L d_inverter U6
-U 1 1 5D12627A
-P 3300 3150
-F 0 "U6" H 3300 3050 60  0000 C CNN
-F 1 "d_inverter" H 3300 3300 60  0000 C CNN
-F 2 "" H 3350 3100 60  0000 C CNN
-F 3 "" H 3350 3100 60  0000 C CNN
-	1    3300 3150
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-$EndComp
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-L d_inverter U7
-U 1 1 5D12627B
-P 3300 3300
-F 0 "U7" H 3300 3200 60  0000 C CNN
-F 1 "d_inverter" H 3300 3450 60  0000 C CNN
-F 2 "" H 3350 3250 60  0000 C CNN
-F 3 "" H 3350 3250 60  0000 C CNN
-	1    3300 3300
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-	3000 2350 2000 2350
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-	3000 3150 2050 3150
-Wire Wire Line
-	3000 3300 2050 3300
-Wire Wire Line
-	6050 3250 6950 3250
-$Comp
-L PORT U1
-U 1 1 5D12627C
-P 1750 2350
-F 0 "U1" H 1800 2450 30  0000 C CNN
-F 1 "PORT" H 1750 2350 30  0000 C CNN
-F 2 "" H 1750 2350 60  0000 C CNN
-F 3 "" H 1750 2350 60  0000 C CNN
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-$Comp
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-F 3 "" H 1750 2550 60  0000 C CNN
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-L PORT U1
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-F 3 "" H 1800 2750 60  0000 C CNN
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5D12627F
-P 1800 2950
-F 0 "U1" H 1850 3050 30  0000 C CNN
-F 1 "PORT" H 1800 2950 30  0000 C CNN
-F 2 "" H 1800 2950 60  0000 C CNN
-F 3 "" H 1800 2950 60  0000 C CNN
-	4    1800 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5D126280
-P 1800 3150
-F 0 "U1" H 1850 3250 30  0000 C CNN
-F 1 "PORT" H 1800 3150 30  0000 C CNN
-F 2 "" H 1800 3150 60  0000 C CNN
-F 3 "" H 1800 3150 60  0000 C CNN
-	5    1800 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5D126281
-P 1800 3300
-F 0 "U1" H 1850 3400 30  0000 C CNN
-F 1 "PORT" H 1800 3300 30  0000 C CNN
-F 2 "" H 1800 3300 60  0000 C CNN
-F 3 "" H 1800 3300 60  0000 C CNN
-	6    1800 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5D126282
-P 7200 3250
-F 0 "U1" H 7250 3350 30  0000 C CNN
-F 1 "PORT" H 7200 3250 30  0000 C CNN
-F 2 "" H 7200 3250 60  0000 C CNN
-F 3 "" H 7200 3250 60  0000 C CNN
-	7    7200 3250
-	-1   0    0    1   
-$EndComp
-Text Notes 2400 2350 0    60   ~ 12
-in1
-Text Notes 2400 2550 0    60   ~ 12
-in2
-Text Notes 2400 2750 0    60   ~ 12
-in3
-Text Notes 2400 2950 0    60   ~ 12
-in4
-Text Notes 2400 3150 0    60   ~ 12
-in5
-Text Notes 2400 3300 0    60   ~ 12
-in6
-Text Notes 6350 3250 0    60   ~ 12
-out
-$Comp
-L 5_and X1
-U 1 1 5D1262D5
-P 4600 2850
-F 0 "X1" H 4650 2750 60  0000 C CNN
-F 1 "5_and" H 4700 3000 60  0000 C CNN
-F 2 "" H 4600 2850 60  0000 C CNN
-F 3 "" H 4600 2850 60  0000 C CNN
-	1    4600 2850
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/5_nor.sub b/src/SubcircuitLibrary/7485/5_nor.sub
deleted file mode 100644
index dbcdb750..00000000
--- a/src/SubcircuitLibrary/7485/5_nor.sub
+++ /dev/null
@@ -1,36 +0,0 @@
-* Subcircuit 5_nor
-.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir
-.include 5_and.sub
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_nor
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml
deleted file mode 100644
index 75f5258c..00000000
--- a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib
deleted file mode 100644
index 6edb5033..00000000
--- a/src/SubcircuitLibrary/7485/7485-cache.lib
+++ /dev/null
@@ -1,175 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0  1250 1300  1600 1300 N
-P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0  1050 1150  1450 1150 N
-P 3 0 1 0  1050 1150  1050 650  1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# c_gate
-#
-DEF c_gate X 0 40 Y Y 1 F N
-F0 "X" 5900 4450 60 H V C CNN
-F1 "c_gate" 5950 4700 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
-P 2 0 1 0  5550 4850  6100 4850 N
-P 4 0 1 0  5550 4850  5550 4250  6050 4250  6100 4250 N
-X in1 1 5350 4800 200 R 50 50 1 1 I I
-X in2 2 5350 4700 200 R 50 50 1 1 I I
-X in3 3 5350 4600 200 R 50 50 1 1 I I
-X in4 4 5350 4500 200 R 50 50 1 1 I I
-X in5 5 5350 4400 200 R 50 50 1 1 I I
-X in6 6 5350 4300 200 R 50 50 1 1 I I
-X out 7 6500 4550 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_nand
-#
-DEF d_nand U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nand" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir
deleted file mode 100644
index e15a357f..00000000
--- a/src/SubcircuitLibrary/7485/7485.cir
+++ /dev/null
@@ -1,42 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U6  Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and		
-U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand		
-U7  Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and		
-U14  Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor		
-U19  Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and		
-X12  Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and		
-X7  Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and		
-X9  Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and		
-X10  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and		
-X11  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and		
-X13  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and		
-U18  Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and		
-X8  Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and		
-X3  Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and		
-X6  Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and		
-X5  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and		
-X4  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and		
-U8  Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and		
-U3  Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand		
-U9  Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and		
-U15  Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor		
-U12  Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and		
-U5  Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand		
-U13  Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and		
-U17  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor		
-U10  Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
-U4  Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand		
-U11  Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and		
-U16  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor		
-X2  Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate		
-X1  Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out
deleted file mode 100644
index afc7b865..00000000
--- a/src/SubcircuitLibrary/7485/7485.cir.out
+++ /dev/null
@@ -1,101 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir
-
-.include 4_and.sub
-.include 3_and.sub
-.include 5_and.sub
-.include c_gate.sub
-* u6  net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand
-* u7  net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and
-* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
-* u19  net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and
-x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and
-x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and
-x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and
-x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and
-x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and
-x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and
-* u18  net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and
-x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and
-x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and
-x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and
-x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and
-x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and
-* u8  net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and
-* u3  net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand
-* u9  net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and
-* u15  net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
-* u12  net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and
-* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand
-* u13  net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and
-* u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor
-* u10  net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u4  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand
-* u11  net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and
-* u16  net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor
-x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6
-a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2
-a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7
-a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
-a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19
-a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8
-a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3
-a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9
-a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
-a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12
-a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5
-a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13
-a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
-a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4
-a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11
-a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro
deleted file mode 100644
index 8fb4abb4..00000000
--- a/src/SubcircuitLibrary/7485/7485.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 19:27:48
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_User
-LibName25=eSim_Subckt
diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch
deleted file mode 100644
index 0db5f0d6..00000000
--- a/src/SubcircuitLibrary/7485/7485.sch
+++ /dev/null
@@ -1,1127 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:7485-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-Wire Wire Line
-	2800 2800 2800 2900
-Wire Wire Line
-	2800 2900 2800 4600
-Wire Wire Line
-	2800 3000 1650 3000
-Wire Wire Line
-	1650 3000 1650 2850
-Wire Wire Line
-	1200 2850 1600 2850
-Wire Wire Line
-	1600 2850 1650 2850
-Wire Wire Line
-	1650 2850 1750 2850
-Wire Wire Line
-	1200 2750 1450 2750
-Wire Wire Line
-	1450 2750 1650 2750
-Wire Wire Line
-	1650 2750 1750 2750
-Wire Wire Line
-	1650 2750 1650 2500
-Wire Wire Line
-	1650 2500 2800 2500
-Wire Wire Line
-	2650 2800 2800 2800
-Connection ~ 2800 2800
-Connection ~ 1650 2750
-Connection ~ 1650 2850
-Wire Wire Line
-	4050 5050 4050 4900
-Wire Wire Line
-	4050 5150 4050 5300
-Wire Wire Line
-	3150 4950 3150 5000
-Wire Wire Line
-	3150 5000 3150 5150
-Wire Wire Line
-	3150 5150 3150 5250
-Wire Wire Line
-	3150 5250 3150 5850
-Wire Wire Line
-	3150 5350 2000 5350
-Wire Wire Line
-	2000 5350 2000 5200
-Wire Wire Line
-	1250 5200 1500 5200
-Wire Wire Line
-	1500 5200 2000 5200
-Wire Wire Line
-	2000 5200 2100 5200
-Wire Wire Line
-	1250 5100 1800 5100
-Wire Wire Line
-	1800 5100 2000 5100
-Wire Wire Line
-	2000 5100 2100 5100
-Wire Wire Line
-	2000 5100 2000 4850
-Wire Wire Line
-	2000 4850 3150 4850
-Wire Wire Line
-	3000 5150 3150 5150
-Connection ~ 3150 5150
-Connection ~ 2000 5100
-Connection ~ 2000 5200
-Wire Wire Line
-	3850 3850 3850 3700
-Wire Wire Line
-	3850 3950 3850 4100
-Wire Wire Line
-	2950 3200 2950 3750
-Wire Wire Line
-	2950 3750 2950 3950
-Wire Wire Line
-	2950 3950 2950 4050
-Wire Wire Line
-	2950 4050 2950 4350
-Wire Wire Line
-	2950 4150 1800 4150
-Wire Wire Line
-	1800 4150 1800 4000
-Wire Wire Line
-	1350 4000 1750 4000
-Wire Wire Line
-	1750 4000 1800 4000
-Wire Wire Line
-	1800 4000 1900 4000
-Wire Wire Line
-	1200 3900 1600 3900
-Wire Wire Line
-	1600 3900 1800 3900
-Wire Wire Line
-	1800 3900 1900 3900
-Wire Wire Line
-	1800 3900 1800 3650
-Wire Wire Line
-	1800 3650 2950 3650
-Wire Wire Line
-	2800 3950 2950 3950
-Connection ~ 2950 3950
-Connection ~ 1800 3900
-Connection ~ 1800 4000
-Wire Wire Line
-	1400 1350 1400 7000
-Wire Wire Line
-	1400 7000 5900 7000
-Connection ~ 1400 1350
-Wire Wire Line
-	1250 5200 1250 5300
-Wire Wire Line
-	5900 6900 2900 6900
-Wire Wire Line
-	2900 6900 2900 4700
-Wire Wire Line
-	2900 4700 2700 4700
-Connection ~ 2700 1500
-Wire Wire Line
-	5950 6750 1450 6750
-Wire Wire Line
-	1450 6750 1450 2750
-Connection ~ 1450 2750
-Wire Wire Line
-	5950 6650 2950 6650
-Wire Wire Line
-	2950 6650 2950 4600
-Wire Wire Line
-	2950 4600 2800 4600
-Connection ~ 2800 2900
-Wire Wire Line
-	5100 6550 5950 6550
-Wire Wire Line
-	5100 1350 5100 1700
-Wire Wire Line
-	5100 1700 5100 2150
-Wire Wire Line
-	5100 2150 5100 2500
-Wire Wire Line
-	5100 2500 5100 3050
-Wire Wire Line
-	5100 3050 5100 3750
-Wire Wire Line
-	5100 3750 5100 4850
-Wire Wire Line
-	5100 4850 5100 5400
-Wire Wire Line
-	5100 5400 5100 5750
-Wire Wire Line
-	5100 5750 5100 6300
-Wire Wire Line
-	5100 6300 5100 6550
-Wire Wire Line
-	4500 1350 5100 1350
-Wire Wire Line
-	5100 1350 6500 1350
-Wire Wire Line
-	1500 1450 1500 900 
-Wire Wire Line
-	1500 900  6450 900 
-Connection ~ 1500 1450
-Wire Wire Line
-	2700 1000 6450 1000
-Connection ~ 2700 1200
-Wire Wire Line
-	6500 1150 4500 1150
-Wire Wire Line
-	4500 1150 4500 1900
-Wire Wire Line
-	4500 1900 1600 1900
-Wire Wire Line
-	1600 1900 1600 2850
-Connection ~ 1600 2850
-Wire Wire Line
-	6500 1250 4550 1250
-Wire Wire Line
-	4550 1250 4550 2000
-Wire Wire Line
-	4550 2000 2800 2000
-Connection ~ 2800 2600
-Connection ~ 5100 1350
-Wire Wire Line
-	6500 1500 4600 1500
-Wire Wire Line
-	4600 1500 4600 2100
-Wire Wire Line
-	4600 2100 1750 2100
-Wire Wire Line
-	1750 2100 1750 4000
-Connection ~ 1750 4000
-Wire Wire Line
-	6500 1600 4650 1600
-Wire Wire Line
-	4650 1600 4650 3200
-Wire Wire Line
-	4650 3200 2950 3200
-Connection ~ 2950 3750
-Wire Wire Line
-	6500 1700 5100 1700
-Connection ~ 5100 1700
-Wire Wire Line
-	6500 1800 5250 1800
-Wire Wire Line
-	5250 1800 5250 2250
-Wire Wire Line
-	5250 2250 5250 2600
-Wire Wire Line
-	5250 2600 5250 2750
-Wire Wire Line
-	5250 2750 5250 3150
-Wire Wire Line
-	5250 3150 5250 3850
-Wire Wire Line
-	5250 3850 5250 4750
-Wire Wire Line
-	5250 4750 5250 5300
-Wire Wire Line
-	5250 5300 5250 5650
-Wire Wire Line
-	5250 5650 5250 6100
-Wire Wire Line
-	5250 2750 4600 2750
-Wire Wire Line
-	6500 1950 1500 1950
-Wire Wire Line
-	1500 1950 1500 5200
-Connection ~ 1500 5200
-Wire Wire Line
-	6500 2050 4950 2050
-Wire Wire Line
-	4950 2050 4950 4300
-Wire Wire Line
-	4950 4300 3150 4300
-Wire Wire Line
-	3150 4300 3150 5000
-Connection ~ 3150 5000
-Wire Wire Line
-	6500 2150 5100 2150
-Connection ~ 5100 2150
-Wire Wire Line
-	6500 2250 5250 2250
-Connection ~ 5250 2250
-Wire Wire Line
-	6500 2350 5350 2350
-Wire Wire Line
-	5350 2350 5350 2700
-Wire Wire Line
-	5350 2700 5350 3200
-Wire Wire Line
-	5350 3200 5350 3900
-Wire Wire Line
-	5350 3900 5350 4050
-Wire Wire Line
-	5350 4050 5350 4650
-Wire Wire Line
-	5350 4650 5350 5200
-Wire Wire Line
-	5350 5200 5350 5550
-Wire Wire Line
-	5350 3900 4750 3900
-Wire Wire Line
-	6500 2500 5100 2500
-Connection ~ 5100 2500
-Wire Wire Line
-	6500 2600 5250 2600
-Connection ~ 5250 2600
-Wire Wire Line
-	6500 2700 5350 2700
-Connection ~ 5350 2700
-Wire Wire Line
-	6500 2800 5450 2800
-Wire Wire Line
-	5450 2800 5450 3350
-Wire Wire Line
-	5450 3350 5450 4150
-Wire Wire Line
-	5450 4150 5450 4550
-Wire Wire Line
-	5450 4550 5450 5100
-Wire Wire Line
-	4950 5100 5450 5100
-Wire Wire Line
-	5450 5100 5950 5100
-Wire Wire Line
-	6500 2900 5550 2900
-Wire Wire Line
-	5550 2900 5550 3250
-Wire Wire Line
-	5550 3250 1050 3250
-Wire Wire Line
-	6500 3050 5100 3050
-Connection ~ 5100 3050
-Wire Wire Line
-	5250 3150 6500 3150
-Connection ~ 5250 2750
-Wire Wire Line
-	6500 3250 5700 3250
-Wire Wire Line
-	5700 3250 5700 3200
-Wire Wire Line
-	5700 3200 5350 3200
-Connection ~ 5350 3200
-Wire Wire Line
-	6500 3350 5450 3350
-Connection ~ 5450 3350
-Wire Wire Line
-	4800 3450 5950 3450
-Wire Wire Line
-	5950 3450 6500 3450
-Wire Wire Line
-	4800 3450 4800 3400
-Wire Wire Line
-	4800 3400 2600 3400
-Wire Wire Line
-	2050 3400 1050 3400
-Wire Wire Line
-	5950 3450 5950 3950
-Wire Wire Line
-	5950 3950 5950 4450
-Connection ~ 5950 3450
-Wire Wire Line
-	5950 4550 5450 4550
-Connection ~ 5450 4550
-Wire Wire Line
-	5350 4650 5950 4650
-Connection ~ 5350 3900
-Wire Wire Line
-	5250 4750 5950 4750
-Connection ~ 5250 3150
-Wire Wire Line
-	5950 4850 5100 4850
-Connection ~ 5100 4850
-Wire Wire Line
-	5950 5400 5100 5400
-Connection ~ 5100 5400
-Wire Wire Line
-	5950 5750 5100 5750
-Connection ~ 5100 5750
-Wire Wire Line
-	5950 5000 4800 5000
-Wire Wire Line
-	4800 5000 4800 3550
-Wire Wire Line
-	4800 3550 1050 3550
-Connection ~ 5450 5100
-Wire Wire Line
-	5350 5200 5950 5200
-Connection ~ 5350 4650
-Wire Wire Line
-	5250 5300 5950 5300
-Connection ~ 5250 4750
-Wire Wire Line
-	5950 5950 1800 5950
-Wire Wire Line
-	1800 5950 1800 5100
-Connection ~ 1800 5100
-Wire Wire Line
-	5950 6400 1600 6400
-Wire Wire Line
-	1600 6400 1600 3900
-Connection ~ 1600 3900
-Wire Wire Line
-	5950 6300 5100 6300
-Connection ~ 5100 6300
-Wire Wire Line
-	5350 5550 5950 5550
-Connection ~ 5350 5200
-Wire Wire Line
-	5250 5650 5950 5650
-Connection ~ 5250 5300
-Wire Wire Line
-	3150 5850 5950 5850
-Connection ~ 3150 5250
-Wire Wire Line
-	5250 6100 5950 6100
-Connection ~ 5250 5650
-Wire Wire Line
-	5950 6200 3000 6200
-Wire Wire Line
-	3000 6200 3000 4350
-Wire Wire Line
-	3000 4350 2950 4350
-Connection ~ 2950 4050
-Wire Wire Line
-	8400 3950 5950 3950
-Connection ~ 5950 3950
-Wire Wire Line
-	8400 3750 5100 3750
-Connection ~ 5100 3750
-Wire Wire Line
-	8400 3850 5250 3850
-Connection ~ 5250 3850
-Wire Wire Line
-	8400 4050 5350 4050
-Connection ~ 5350 4050
-Wire Wire Line
-	8400 4150 5450 4150
-Connection ~ 5450 4150
-Wire Wire Line
-	8400 1800 8400 950 
-Wire Wire Line
-	8400 950  7350 950 
-Wire Wire Line
-	8400 1900 8200 1900
-Wire Wire Line
-	8200 1900 8200 1250
-Wire Wire Line
-	8200 1250 7350 1250
-Wire Wire Line
-	8400 2000 8050 2000
-Wire Wire Line
-	8050 2000 8050 1650
-Wire Wire Line
-	8050 1650 7400 1650
-Wire Wire Line
-	7500 2150 7800 2150
-Wire Wire Line
-	7800 2150 7800 2100
-Wire Wire Line
-	7800 2100 8400 2100
-Wire Wire Line
-	8400 2200 7900 2200
-Wire Wire Line
-	7900 2200 7900 2700
-Wire Wire Line
-	7900 2700 7500 2700
-Wire Wire Line
-	7500 3250 8050 3250
-Wire Wire Line
-	8050 3250 8050 2300
-Wire Wire Line
-	8050 2300 8400 2300
-Wire Wire Line
-	8200 5200 8200 4650
-Wire Wire Line
-	8200 4650 6950 4650
-Wire Wire Line
-	8200 5300 8050 5300
-Wire Wire Line
-	8050 5300 8050 5200
-Wire Wire Line
-	8050 5200 6950 5200
-Wire Wire Line
-	8200 5400 7250 5400
-Wire Wire Line
-	7250 5400 7250 5750
-Wire Wire Line
-	7250 5750 6950 5750
-Wire Wire Line
-	6850 6250 6850 5850
-Wire Wire Line
-	6850 5850 7350 5850
-Wire Wire Line
-	7350 5850 7350 5500
-Wire Wire Line
-	7350 5500 8200 5500
-Wire Wire Line
-	6800 6950 6950 6950
-Wire Wire Line
-	6950 6950 6950 6200
-Wire Wire Line
-	6950 6200 7950 6200
-Wire Wire Line
-	7950 6200 7950 5700
-Wire Wire Line
-	7950 5700 8200 5700
-$Comp
-L PORT U1
-U 4 1 5C9A8539
-P 850 1350
-F 0 "U1" H 900 1450 30  0000 C CNN
-F 1 "PORT" H 850 1350 30  0000 C CNN
-F 2 "" H 850 1350 60  0000 C CNN
-F 3 "" H 850 1350 60  0000 C CNN
-	4    850  1350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A8668
-P 850 1550
-F 0 "U1" H 900 1650 30  0000 C CNN
-F 1 "PORT" H 850 1550 30  0000 C CNN
-F 2 "" H 850 1550 60  0000 C CNN
-F 3 "" H 850 1550 60  0000 C CNN
-	5    850  1550
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1100 1550 1100 1450
-$Comp
-L PORT U1
-U 6 1 5C9A8815
-P 950 2650
-F 0 "U1" H 1000 2750 30  0000 C CNN
-F 1 "PORT" H 950 2650 30  0000 C CNN
-F 2 "" H 950 2650 60  0000 C CNN
-F 3 "" H 950 2650 60  0000 C CNN
-	6    950  2650
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1200 2650 1200 2750
-$Comp
-L PORT U1
-U 7 1 5C9A8B82
-P 950 2850
-F 0 "U1" H 1000 2950 30  0000 C CNN
-F 1 "PORT" H 950 2850 30  0000 C CNN
-F 2 "" H 950 2850 60  0000 C CNN
-F 3 "" H 950 2850 60  0000 C CNN
-	7    950  2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9A8C46
-P 950 3900
-F 0 "U1" H 1000 4000 30  0000 C CNN
-F 1 "PORT" H 950 3900 30  0000 C CNN
-F 2 "" H 950 3900 60  0000 C CNN
-F 3 "" H 950 3900 60  0000 C CNN
-	8    950  3900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C9A8D2C
-P 950 4100
-F 0 "U1" H 1000 4200 30  0000 C CNN
-F 1 "PORT" H 950 4100 30  0000 C CNN
-F 2 "" H 950 4100 60  0000 C CNN
-F 3 "" H 950 4100 60  0000 C CNN
-	9    950  4100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C9A8DBD
-P 1000 5100
-F 0 "U1" H 1050 5200 30  0000 C CNN
-F 1 "PORT" H 1000 5100 30  0000 C CNN
-F 2 "" H 1000 5100 60  0000 C CNN
-F 3 "" H 1000 5100 60  0000 C CNN
-	10   1000 5100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C9A8E65
-P 1000 5300
-F 0 "U1" H 1050 5400 30  0000 C CNN
-F 1 "PORT" H 1000 5300 30  0000 C CNN
-F 2 "" H 1000 5300 60  0000 C CNN
-F 3 "" H 1000 5300 60  0000 C CNN
-	11   1000 5300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A8EEE
-P 800 3150
-F 0 "U1" H 850 3250 30  0000 C CNN
-F 1 "PORT" H 800 3150 30  0000 C CNN
-F 2 "" H 800 3150 60  0000 C CNN
-F 3 "" H 800 3150 60  0000 C CNN
-	1    800  3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A8F9C
-P 800 3400
-F 0 "U1" H 850 3500 30  0000 C CNN
-F 1 "PORT" H 800 3400 30  0000 C CNN
-F 2 "" H 800 3400 60  0000 C CNN
-F 3 "" H 800 3400 60  0000 C CNN
-	2    800  3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A9031
-P 800 3600
-F 0 "U1" H 850 3700 30  0000 C CNN
-F 1 "PORT" H 800 3600 30  0000 C CNN
-F 2 "" H 800 3600 60  0000 C CNN
-F 3 "" H 800 3600 60  0000 C CNN
-	3    800  3600
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1050 3250 1050 3150
-Wire Wire Line
-	1050 3550 1050 3600
-Wire Wire Line
-	1350 4000 1350 4100
-Wire Wire Line
-	1350 4100 1200 4100
-Wire Wire Line
-	9550 2050 9850 2050
-Wire Wire Line
-	9400 3950 9850 3950
-Wire Wire Line
-	9350 5450 9900 5450
-$Comp
-L PORT U1
-U 12 1 5C9A9B26
-P 10100 2050
-F 0 "U1" H 10150 2150 30  0000 C CNN
-F 1 "PORT" H 10100 2050 30  0000 C CNN
-F 2 "" H 10100 2050 60  0000 C CNN
-F 3 "" H 10100 2050 60  0000 C CNN
-	12   10100 2050
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C9A9BCA
-P 10100 3950
-F 0 "U1" H 10150 4050 30  0000 C CNN
-F 1 "PORT" H 10100 3950 30  0000 C CNN
-F 2 "" H 10100 3950 60  0000 C CNN
-F 3 "" H 10100 3950 60  0000 C CNN
-	13   10100 3950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C9A9CA0
-P 10150 5450
-F 0 "U1" H 10200 5550 30  0000 C CNN
-F 1 "PORT" H 10150 5450 30  0000 C CNN
-F 2 "" H 10150 5450 60  0000 C CNN
-F 3 "" H 10150 5450 60  0000 C CNN
-	14   10150 5450
-	-1   0    0    1   
-$EndComp
-Text Notes 9650 2000 0    60   ~ 12
-A>B
-Text Notes 9600 3900 0    60   ~ 12
-A=B\n
-Text Notes 9600 5400 0    60   ~ 12
-A<B\n
-Text Notes 1250 5100 0    60   ~ 12
-A0
-Text Notes 1200 5400 0    60   ~ 12
-B0
-Text Notes 1300 3900 2    60   ~ 12
-A1
-Text Notes 1300 4200 2    60   ~ 12
-B1
-Text Notes 1250 3250 2    60   ~ 12
-A<B
-Text Notes 1250 3400 2    60   ~ 12
-A=B
-Text Notes 1250 3550 2    60   ~ 12
-A>B
-Text Notes 1350 2750 2    60   ~ 12
-A2
-Text Notes 1350 2950 2    60   ~ 12
-B2
-Text Notes 1300 1350 2    60   ~ 12
-A3
-Text Notes 1300 1550 2    60   ~ 12
-B3
-Wire Wire Line
-	8200 5600 7450 5600
-Wire Wire Line
-	7450 5600 7450 6050
-Wire Wire Line
-	7450 6050 6900 6050
-Wire Wire Line
-	6800 6650 6800 6300
-Wire Wire Line
-	6800 6300 6900 6300
-Wire Wire Line
-	6900 6300 6900 6050
-Wire Notes Line
-	500  3000 1350 3000
-Wire Notes Line
-	1350 3000 1350 3750
-Wire Notes Line
-	1350 3750 500  3750
-Wire Notes Line
-	500  3750 500  3000
-Text Notes 600  3000 3    60   ~ 12
-Cascading Inputs
-Wire Notes Line
-	9500 1550 9500 6050
-Wire Notes Line
-	9500 6050 10550 6050
-Wire Notes Line
-	10550 6050 10550 1550
-Wire Notes Line
-	10550 1550 9500 1550
-Text Notes 9900 3400 0    60   ~ 12
-Outputs
-Wire Wire Line
-	2600 3400 2050 3400
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub
deleted file mode 100644
index 5a45c57c..00000000
--- a/src/SubcircuitLibrary/7485/7485.sub
+++ /dev/null
@@ -1,95 +0,0 @@
-* Subcircuit 7485
-.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir
-.include 4_and.sub
-.include 3_and.sub
-.include 5_and.sub
-.include c_gate.sub
-* u6  net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and
-* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand
-* u7  net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and
-* u14  net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
-* u19  net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and
-x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and
-x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and
-x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and
-x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and
-x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and
-x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and
-* u18  net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and
-x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and
-x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and
-x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and
-x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and
-x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and
-* u8  net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and
-* u3  net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand
-* u9  net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and
-* u15  net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
-* u12  net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and
-* u5  net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand
-* u13  net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and
-* u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor
-* u10  net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u4  net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand
-* u11  net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and
-* u16  net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor
-x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate
-x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate
-a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6
-a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2
-a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7
-a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
-a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19
-a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8
-a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3
-a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9
-a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
-a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12
-a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5
-a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13
-a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
-a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4
-a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11
-a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nand, NgSpice Name: d_nand
-.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 7485
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml
deleted file mode 100644
index 6d8f93b6..00000000
--- a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib
deleted file mode 100644
index 6edb5033..00000000
--- a/src/SubcircuitLibrary/7485/7485mod-cache.lib
+++ /dev/null
@@ -1,175 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0  650 550  1000 550 N
-P 3 0 1 0  650 550  650 250  1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0  1250 1300  1600 1300 N
-P 4 0 1 0  1250 1300  1250 900  1500 900  1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0  1050 1150  1450 1150 N
-P 3 0 1 0  1050 1150  1050 650  1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# c_gate
-#
-DEF c_gate X 0 40 Y Y 1 F N
-F0 "X" 5900 4450 60 H V C CNN
-F1 "c_gate" 5950 4700 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
-P 2 0 1 0  5550 4850  6100 4850 N
-P 4 0 1 0  5550 4850  5550 4250  6050 4250  6100 4250 N
-X in1 1 5350 4800 200 R 50 50 1 1 I I
-X in2 2 5350 4700 200 R 50 50 1 1 I I
-X in3 3 5350 4600 200 R 50 50 1 1 I I
-X in4 4 5350 4500 200 R 50 50 1 1 I I
-X in5 5 5350 4400 200 R 50 50 1 1 I I
-X in6 6 5350 4300 200 R 50 50 1 1 I I
-X out 7 6500 4550 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_nand
-#
-DEF d_nand U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nand" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch
deleted file mode 100644
index f7e537ad..00000000
--- a/src/SubcircuitLibrary/7485/7485mod.sch
+++ /dev/null
@@ -1,1007 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:7485-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-F 3 "" H 3150 1200 60  0000 C CNN
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-$Comp
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-F 2 "" H 2100 1450 60  0000 C CNN
-F 3 "" H 2100 1450 60  0000 C CNN
-	1    2100 1450
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-$EndComp
-$Comp
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-F 2 "" H 3150 1600 60  0000 C CNN
-F 3 "" H 3150 1600 60  0000 C CNN
-	1    3150 1600
-	1    0    0    -1  
-$EndComp
-$Comp
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-U 1 1 5C9A252F
-P 4050 1400
-F 0 "U14" H 4050 1400 60  0000 C CNN
-F 1 "d_nor" H 4100 1500 60  0000 C CNN
-F 2 "" H 4050 1400 60  0000 C CNN
-F 3 "" H 4050 1400 60  0000 C CNN
-	1    4050 1400
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-F 1 "d_and" H 6950 1100 60  0000 C CNN
-F 2 "" H 6900 1000 60  0000 C CNN
-F 3 "" H 6900 1000 60  0000 C CNN
-	1    6900 1000
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-$Comp
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-F 1 "5_and" H 7050 5200 60  0000 C CNN
-F 2 "" H 5650 4150 60  0000 C CNN
-F 3 "" H 5650 4150 60  0000 C CNN
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-F 1 "5_and" H 8950 5900 60  0000 C CNN
-F 2 "" H 7550 4850 60  0000 C CNN
-F 3 "" H 7550 4850 60  0000 C CNN
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-$EndComp
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-F 2 "" H 6350 6900 60  0000 C CNN
-F 3 "" H 6350 6900 60  0000 C CNN
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-F 1 "3_and" H 6450 6750 60  0000 C CNN
-F 2 "" H 5500 6250 60  0000 C CNN
-F 3 "" H 5500 6250 60  0000 C CNN
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-$EndComp
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-F 1 "4_and" H 6450 6350 60  0000 C CNN
-F 2 "" H 4900 5150 60  0000 C CNN
-F 3 "" H 4900 5150 60  0000 C CNN
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-F 1 "5_and" H 6500 5900 60  0000 C CNN
-F 2 "" H 5100 4850 60  0000 C CNN
-F 3 "" H 5100 4850 60  0000 C CNN
-	1    5100 4850
-	1    0    0    1   
-$EndComp
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-F 1 "5_and" H 6500 5350 60  0000 C CNN
-F 2 "" H 5100 4300 60  0000 C CNN
-F 3 "" H 5100 4300 60  0000 C CNN
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-$EndComp
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-F 1 "5_and" H 6500 4800 60  0000 C CNN
-F 2 "" H 5100 3750 60  0000 C CNN
-F 3 "" H 5100 3750 60  0000 C CNN
-	1    5100 3750
-	1    0    0    1   
-$EndComp
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-F 1 "d_and" H 3300 2700 60  0000 C CNN
-F 2 "" H 3250 2600 60  0000 C CNN
-F 3 "" H 3250 2600 60  0000 C CNN
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-$EndComp
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-F 1 "d_nand" H 2250 2950 60  0000 C CNN
-F 2 "" H 2200 2850 60  0000 C CNN
-F 3 "" H 2200 2850 60  0000 C CNN
-	1    2200 2850
-	1    0    0    -1  
-$EndComp
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-F 0 "U9" H 3250 3000 60  0000 C CNN
-F 1 "d_and" H 3300 3100 60  0000 C CNN
-F 2 "" H 3250 3000 60  0000 C CNN
-F 3 "" H 3250 3000 60  0000 C CNN
-	1    3250 3000
-	1    0    0    -1  
-$EndComp
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-P 4150 2800
-F 0 "U15" H 4150 2800 60  0000 C CNN
-F 1 "d_nor" H 4200 2900 60  0000 C CNN
-F 2 "" H 4150 2800 60  0000 C CNN
-F 3 "" H 4150 2800 60  0000 C CNN
-	1    4150 2800
-	1    0    0    -1  
-$EndComp
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-F 0 "U12" H 3600 4950 60  0000 C CNN
-F 1 "d_and" H 3650 5050 60  0000 C CNN
-F 2 "" H 3600 4950 60  0000 C CNN
-F 3 "" H 3600 4950 60  0000 C CNN
-	1    3600 4950
-	1    0    0    -1  
-$EndComp
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-F 1 "d_nand" H 2600 5300 60  0000 C CNN
-F 2 "" H 2550 5200 60  0000 C CNN
-F 3 "" H 2550 5200 60  0000 C CNN
-	1    2550 5200
-	1    0    0    -1  
-$EndComp
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-P 3600 5350
-F 0 "U13" H 3600 5350 60  0000 C CNN
-F 1 "d_and" H 3650 5450 60  0000 C CNN
-F 2 "" H 3600 5350 60  0000 C CNN
-F 3 "" H 3600 5350 60  0000 C CNN
-	1    3600 5350
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A3B68
-P 4500 5150
-F 0 "U17" H 4500 5150 60  0000 C CNN
-F 1 "d_nor" H 4550 5250 60  0000 C CNN
-F 2 "" H 4500 5150 60  0000 C CNN
-F 3 "" H 4500 5150 60  0000 C CNN
-	1    4500 5150
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A3C6D
-P 3400 3750
-F 0 "U10" H 3400 3750 60  0000 C CNN
-F 1 "d_and" H 3450 3850 60  0000 C CNN
-F 2 "" H 3400 3750 60  0000 C CNN
-F 3 "" H 3400 3750 60  0000 C CNN
-	1    3400 3750
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A3C73
-P 2350 4000
-F 0 "U4" H 2350 4000 60  0000 C CNN
-F 1 "d_nand" H 2400 4100 60  0000 C CNN
-F 2 "" H 2350 4000 60  0000 C CNN
-F 3 "" H 2350 4000 60  0000 C CNN
-	1    2350 4000
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A3C79
-P 3400 4150
-F 0 "U11" H 3400 4150 60  0000 C CNN
-F 1 "d_and" H 3450 4250 60  0000 C CNN
-F 2 "" H 3400 4150 60  0000 C CNN
-F 3 "" H 3400 4150 60  0000 C CNN
-	1    3400 4150
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A3C7F
-P 4300 3950
-F 0 "U16" H 4300 3950 60  0000 C CNN
-F 1 "d_nor" H 4350 4050 60  0000 C CNN
-F 2 "" H 4300 3950 60  0000 C CNN
-F 3 "" H 4300 3950 60  0000 C CNN
-	1    4300 3950
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A4498
-P 3050 6600
-F 0 "X2" H 3100 6650 60  0000 C CNN
-F 1 "c_gate" H 9000 11300 60  0000 C CNN
-F 2 "" H 3050 6600 60  0000 C CNN
-F 3 "" H 3050 6600 60  0000 C CNN
-	1    3050 6600
-	1    0    0    -1  
-$EndComp
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-U 1 1 5C9A465F
-P 2850 10000
-F 0 "X1" H 2900 10050 60  0000 C CNN
-F 1 "c_gate" H 8800 14700 60  0000 C CNN
-F 2 "" H 2850 10000 60  0000 C CNN
-F 3 "" H 2850 10000 60  0000 C CNN
-	1    2850 10000
-	1    0    0    -1  
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-Wire Wire Line
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-	1550 1600 1550 1450
-Wire Wire Line
-	1100 1450 1650 1450
-Wire Wire Line
-	1100 1350 1650 1350
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-	1550 1350 1550 1100
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-Wire Wire Line
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-Connection ~ 2700 1400
-Connection ~ 1550 1350
-Connection ~ 1550 1450
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-Wire Wire Line
-	3700 2800 3700 2950
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-Wire Wire Line
-	1650 3000 1650 2850
-Wire Wire Line
-	1200 2850 1750 2850
-Wire Wire Line
-	1200 2750 1750 2750
-Wire Wire Line
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-Connection ~ 1650 2850
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-	4050 5050 4050 4900
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-	4050 5150 4050 5300
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-Wire Wire Line
-	2000 5350 2000 5200
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-Wire Wire Line
-	1250 5100 2100 5100
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-Connection ~ 1800 4000
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-	1400 1350 1400 7000
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-Wire Wire Line
-	5950 6750 1450 6750
-Wire Wire Line
-	1450 6750 1450 2750
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	5100 6550 5950 6550
-Wire Wire Line
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-Wire Wire Line
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-	6500 1500 4600 1500
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-	4600 1500 4600 2100
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-Connection ~ 1750 4000
-Wire Wire Line
-	6500 1600 4650 1600
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-	6500 1800 5250 1800
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-	6500 1950 1500 1950
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-	6500 2050 4950 2050
-Wire Wire Line
-	4950 2050 4950 4300
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-Connection ~ 3150 5000
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-Connection ~ 5100 2150
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-Connection ~ 5250 2250
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-	6500 2350 5350 2350
-Wire Wire Line
-	5350 2350 5350 5550
-Wire Wire Line
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-Wire Wire Line
-	6500 2500 5100 2500
-Connection ~ 5100 2500
-Wire Wire Line
-	6500 2600 5250 2600
-Connection ~ 5250 2600
-Wire Wire Line
-	6500 2700 5350 2700
-Connection ~ 5350 2700
-Wire Wire Line
-	6500 2800 5450 2800
-Wire Wire Line
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-Wire Wire Line
-	4950 5100 5950 5100
-Wire Wire Line
-	6500 2900 5550 2900
-Wire Wire Line
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-Wire Wire Line
-	5550 3250 1050 3250
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-Connection ~ 5100 3050
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-Connection ~ 5250 2750
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-Connection ~ 5450 3350
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-Wire Wire Line
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-Connection ~ 5950 3450
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-Connection ~ 5450 4550
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-Connection ~ 5100 5400
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-Connection ~ 5100 3750
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-P 850 1350
-F 0 "U1" H 900 1450 30  0000 C CNN
-F 1 "PORT" H 850 1350 30  0000 C CNN
-F 2 "" H 850 1350 60  0000 C CNN
-F 3 "" H 850 1350 60  0000 C CNN
-	4    850  1350
-	1    0    0    -1  
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-U 5 1 5C9A8668
-P 850 1550
-F 0 "U1" H 900 1650 30  0000 C CNN
-F 1 "PORT" H 850 1550 30  0000 C CNN
-F 2 "" H 850 1550 60  0000 C CNN
-F 3 "" H 850 1550 60  0000 C CNN
-	5    850  1550
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-$EndComp
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-	1100 1550 1100 1450
-$Comp
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-U 6 1 5C9A8815
-P 950 2650
-F 0 "U1" H 1000 2750 30  0000 C CNN
-F 1 "PORT" H 950 2650 30  0000 C CNN
-F 2 "" H 950 2650 60  0000 C CNN
-F 3 "" H 950 2650 60  0000 C CNN
-	6    950  2650
-	1    0    0    -1  
-$EndComp
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-	1200 2650 1200 2750
-$Comp
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-P 950 2850
-F 0 "U1" H 1000 2950 30  0000 C CNN
-F 1 "PORT" H 950 2850 30  0000 C CNN
-F 2 "" H 950 2850 60  0000 C CNN
-F 3 "" H 950 2850 60  0000 C CNN
-	7    950  2850
-	1    0    0    -1  
-$EndComp
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-P 950 3900
-F 0 "U1" H 1000 4000 30  0000 C CNN
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-F 2 "" H 950 3900 60  0000 C CNN
-F 3 "" H 950 3900 60  0000 C CNN
-	8    950  3900
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-F 0 "U1" H 1000 4200 30  0000 C CNN
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-F 3 "" H 950 4100 60  0000 C CNN
-	9    950  4100
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-P 1000 5100
-F 0 "U1" H 1050 5200 30  0000 C CNN
-F 1 "PORT" H 1000 5100 30  0000 C CNN
-F 2 "" H 1000 5100 60  0000 C CNN
-F 3 "" H 1000 5100 60  0000 C CNN
-	10   1000 5100
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-P 1000 5300
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-F 2 "" H 1000 5300 60  0000 C CNN
-F 3 "" H 1000 5300 60  0000 C CNN
-	11   1000 5300
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-U 1 1 5C9A8EEE
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-F 3 "" H 800 3150 60  0000 C CNN
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-$EndComp
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-U 2 1 5C9A8F9C
-P 800 3400
-F 0 "U1" H 850 3500 30  0000 C CNN
-F 1 "PORT" H 800 3400 30  0000 C CNN
-F 2 "" H 800 3400 60  0000 C CNN
-F 3 "" H 800 3400 60  0000 C CNN
-	2    800  3400
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-$EndComp
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-L PORT U1
-U 3 1 5C9A9031
-P 800 3600
-F 0 "U1" H 850 3700 30  0000 C CNN
-F 1 "PORT" H 800 3600 30  0000 C CNN
-F 2 "" H 800 3600 60  0000 C CNN
-F 3 "" H 800 3600 60  0000 C CNN
-	3    800  3600
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-Wire Wire Line
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-Wire Wire Line
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-	9550 2050 9850 2050
-Wire Wire Line
-	9400 3950 9850 3950
-Wire Wire Line
-	9350 5450 9900 5450
-$Comp
-L PORT U1
-U 12 1 5C9A9B26
-P 10100 2050
-F 0 "U1" H 10150 2150 30  0000 C CNN
-F 1 "PORT" H 10100 2050 30  0000 C CNN
-F 2 "" H 10100 2050 60  0000 C CNN
-F 3 "" H 10100 2050 60  0000 C CNN
-	12   10100 2050
-	-1   0    0    1   
-$EndComp
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-L PORT U1
-U 13 1 5C9A9BCA
-P 10100 3950
-F 0 "U1" H 10150 4050 30  0000 C CNN
-F 1 "PORT" H 10100 3950 30  0000 C CNN
-F 2 "" H 10100 3950 60  0000 C CNN
-F 3 "" H 10100 3950 60  0000 C CNN
-	13   10100 3950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C9A9CA0
-P 10150 5450
-F 0 "U1" H 10200 5550 30  0000 C CNN
-F 1 "PORT" H 10150 5450 30  0000 C CNN
-F 2 "" H 10150 5450 60  0000 C CNN
-F 3 "" H 10150 5450 60  0000 C CNN
-	14   10150 5450
-	-1   0    0    1   
-$EndComp
-Text Notes 9650 2000 0    60   ~ 12
-A>B
-Text Notes 9600 3900 0    60   ~ 12
-A=B\n
-Text Notes 9600 5400 0    60   ~ 12
-A<B\n
-Text Notes 1250 5100 0    60   ~ 12
-A0
-Text Notes 1200 5400 0    60   ~ 12
-B0
-Text Notes 1300 3900 2    60   ~ 12
-A1
-Text Notes 1300 4200 2    60   ~ 12
-B1
-Text Notes 1250 3250 2    60   ~ 12
-A<B
-Text Notes 1250 3400 2    60   ~ 12
-A=B
-Text Notes 1250 3550 2    60   ~ 12
-A>B
-Text Notes 1350 2750 2    60   ~ 12
-A2
-Text Notes 1350 2950 2    60   ~ 12
-B2
-Text Notes 1300 1350 2    60   ~ 12
-A3
-Text Notes 1300 1550 2    60   ~ 12
-B3
-Wire Wire Line
-	8200 5600 7450 5600
-Wire Wire Line
-	7450 5600 7450 6050
-Wire Wire Line
-	7450 6050 6900 6050
-Wire Wire Line
-	6800 6650 6800 6300
-Wire Wire Line
-	6800 6300 6900 6300
-Wire Wire Line
-	6900 6300 6900 6050
-Wire Notes Line
-	500  3000 1350 3000
-Wire Notes Line
-	1350 3000 1350 3750
-Wire Notes Line
-	1350 3750 500  3750
-Wire Notes Line
-	500  3750 500  3000
-Text Notes 600  3000 3    60   ~ 12
-Cascading Inputs
-Wire Notes Line
-	9500 1550 9500 6050
-Wire Notes Line
-	9500 6050 10550 6050
-Wire Notes Line
-	10550 6050 10550 1550
-Wire Notes Line
-	10550 1550 9500 1550
-Text Notes 9900 3400 0    60   ~ 12
-Outputs
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/analysis b/src/SubcircuitLibrary/7485/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/7485/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib
deleted file mode 100644
index 05fb44d7..00000000
--- a/src/SubcircuitLibrary/7485/c_gate-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0  1050 1150  1450 1150 N
-P 3 0 1 0  1050 1150  1050 650  1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir
deleted file mode 100644
index 1ac12515..00000000
--- a/src/SubcircuitLibrary/7485/c_gate.cir
+++ /dev/null
@@ -1,19 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and		
-U8  Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U3  Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter		
-U4  Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter		
-U5  Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter		
-U6  Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter		
-U7  Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out
deleted file mode 100644
index db7bb2f8..00000000
--- a/src/SubcircuitLibrary/7485/c_gate.cir.out
+++ /dev/null
@@ -1,42 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro
deleted file mode 100644
index f0743529..00000000
--- a/src/SubcircuitLibrary/7485/c_gate.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/26/19 19:06:59
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch
deleted file mode 100644
index 5d960c8d..00000000
--- a/src/SubcircuitLibrary/7485/c_gate.sch
+++ /dev/null
@@ -1,246 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:c_gate-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 5_and X1
-U 1 1 5C9A2B0B
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-F 0 "X1" H 4650 4550 60  0000 C CNN
-F 1 "5_and" H 4700 4800 60  0000 C CNN
-F 2 "" H 3300 3750 60  0000 C CNN
-F 3 "" H 3300 3750 60  0000 C CNN
-	1    3300 3750
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U8
-U 1 1 5C9A2B3E
-P 5600 3300
-F 0 "U8" H 5600 3300 60  0000 C CNN
-F 1 "d_and" H 5650 3400 60  0000 C CNN
-F 2 "" H 5600 3300 60  0000 C CNN
-F 3 "" H 5600 3300 60  0000 C CNN
-	1    5600 3300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5150 3200 5150 2850
-Wire Wire Line
-	4150 2650 4150 2350
-Wire Wire Line
-	4150 2350 3600 2350
-Wire Wire Line
-	4150 2750 4050 2750
-Wire Wire Line
-	4050 2750 4050 2550
-Wire Wire Line
-	4050 2550 3600 2550
-Wire Wire Line
-	4150 2850 3700 2850
-Wire Wire Line
-	3700 2850 3700 2750
-Wire Wire Line
-	3700 2750 3600 2750
-Wire Wire Line
-	4150 2950 3600 2950
-Wire Wire Line
-	4150 3050 4150 3150
-Wire Wire Line
-	4150 3150 3600 3150
-Wire Wire Line
-	5150 3300 3600 3300
-$Comp
-L d_inverter U2
-U 1 1 5C9A2CDC
-P 3300 2350
-F 0 "U2" H 3300 2250 60  0000 C CNN
-F 1 "d_inverter" H 3300 2500 60  0000 C CNN
-F 2 "" H 3350 2300 60  0000 C CNN
-F 3 "" H 3350 2300 60  0000 C CNN
-	1    3300 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U3
-U 1 1 5C9A2D06
-P 3300 2550
-F 0 "U3" H 3300 2450 60  0000 C CNN
-F 1 "d_inverter" H 3300 2700 60  0000 C CNN
-F 2 "" H 3350 2500 60  0000 C CNN
-F 3 "" H 3350 2500 60  0000 C CNN
-	1    3300 2550
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U4
-U 1 1 5C9A2D26
-P 3300 2750
-F 0 "U4" H 3300 2650 60  0000 C CNN
-F 1 "d_inverter" H 3300 2900 60  0000 C CNN
-F 2 "" H 3350 2700 60  0000 C CNN
-F 3 "" H 3350 2700 60  0000 C CNN
-	1    3300 2750
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U5
-U 1 1 5C9A2D49
-P 3300 2950
-F 0 "U5" H 3300 2850 60  0000 C CNN
-F 1 "d_inverter" H 3300 3100 60  0000 C CNN
-F 2 "" H 3350 2900 60  0000 C CNN
-F 3 "" H 3350 2900 60  0000 C CNN
-	1    3300 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U6
-U 1 1 5C9A2D73
-P 3300 3150
-F 0 "U6" H 3300 3050 60  0000 C CNN
-F 1 "d_inverter" H 3300 3300 60  0000 C CNN
-F 2 "" H 3350 3100 60  0000 C CNN
-F 3 "" H 3350 3100 60  0000 C CNN
-	1    3300 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U7
-U 1 1 5C9A2D9E
-P 3300 3300
-F 0 "U7" H 3300 3200 60  0000 C CNN
-F 1 "d_inverter" H 3300 3450 60  0000 C CNN
-F 2 "" H 3350 3250 60  0000 C CNN
-F 3 "" H 3350 3250 60  0000 C CNN
-	1    3300 3300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3000 2350 2000 2350
-Wire Wire Line
-	3000 2550 2000 2550
-Wire Wire Line
-	3000 2750 2050 2750
-Wire Wire Line
-	3000 2950 2050 2950
-Wire Wire Line
-	3000 3150 2050 3150
-Wire Wire Line
-	3000 3300 2050 3300
-Wire Wire Line
-	6050 3250 6950 3250
-$Comp
-L PORT U1
-U 1 1 5C9A2F6F
-P 1750 2350
-F 0 "U1" H 1800 2450 30  0000 C CNN
-F 1 "PORT" H 1750 2350 30  0000 C CNN
-F 2 "" H 1750 2350 60  0000 C CNN
-F 3 "" H 1750 2350 60  0000 C CNN
-	1    1750 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A2FAB
-P 1750 2550
-F 0 "U1" H 1800 2650 30  0000 C CNN
-F 1 "PORT" H 1750 2550 30  0000 C CNN
-F 2 "" H 1750 2550 60  0000 C CNN
-F 3 "" H 1750 2550 60  0000 C CNN
-	2    1750 2550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2FDD
-P 1800 2750
-F 0 "U1" H 1850 2850 30  0000 C CNN
-F 1 "PORT" H 1800 2750 30  0000 C CNN
-F 2 "" H 1800 2750 60  0000 C CNN
-F 3 "" H 1800 2750 60  0000 C CNN
-	3    1800 2750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A301A
-P 1800 2950
-F 0 "U1" H 1850 3050 30  0000 C CNN
-F 1 "PORT" H 1800 2950 30  0000 C CNN
-F 2 "" H 1800 2950 60  0000 C CNN
-F 3 "" H 1800 2950 60  0000 C CNN
-	4    1800 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A3052
-P 1800 3150
-F 0 "U1" H 1850 3250 30  0000 C CNN
-F 1 "PORT" H 1800 3150 30  0000 C CNN
-F 2 "" H 1800 3150 60  0000 C CNN
-F 3 "" H 1800 3150 60  0000 C CNN
-	5    1800 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A308D
-P 1800 3300
-F 0 "U1" H 1850 3400 30  0000 C CNN
-F 1 "PORT" H 1800 3300 30  0000 C CNN
-F 2 "" H 1800 3300 60  0000 C CNN
-F 3 "" H 1800 3300 60  0000 C CNN
-	6    1800 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C9A30DD
-P 7200 3250
-F 0 "U1" H 7250 3350 30  0000 C CNN
-F 1 "PORT" H 7200 3250 30  0000 C CNN
-F 2 "" H 7200 3250 60  0000 C CNN
-F 3 "" H 7200 3250 60  0000 C CNN
-	7    7200 3250
-	-1   0    0    1   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub
deleted file mode 100644
index c6eaa478..00000000
--- a/src/SubcircuitLibrary/7485/c_gate.sub
+++ /dev/null
@@ -1,36 +0,0 @@
-* Subcircuit c_gate
-.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends c_gate
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml
deleted file mode 100644
index e51d62de..00000000
--- a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib
deleted file mode 100644
index f5944a63..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib
+++ /dev/null
@@ -1,112 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_dff
-#
-DEF d_dff U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_dff" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 350 450 -350 -400 0 1 0 N
-X Din 1 -550 350 200 R 50 50 1 1 I
-X Clk 2 -550 -300 200 R 50 50 1 1 I C
-X Set 3 0 650 200 D 50 50 1 1 I
-X Reset 4 0 -600 200 U 50 50 1 1 I
-X Dout 5 550 350 200 L 50 50 1 1 O
-X Ndout 6 550 -300 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir
deleted file mode 100644
index 52ab8ff8..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir
+++ /dev/null
@@ -1,56 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\9bit-Right_shift_register\9bit-Right_shift_register.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/19 01:43:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U20-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad2_ ? d_dff		
-U4  Net-_U25-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U30-Pad2_ ? d_dff		
-U6  Net-_U29-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U34-Pad2_ ? d_dff		
-U15  Net-_U15-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U15-Pad5_ ? d_dff		
-U2  Net-_U14-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U2-Pad5_ ? d_dff		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? d_dff		
-U18  Net-_U18-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U18-Pad5_ ? d_dff		
-U11  Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad1_ d_or		
-U14  Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or		
-U20  Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U20-Pad3_ d_or		
-U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and		
-U8  Net-_U7-Pad2_ Net-_U5-Pad1_ Net-_U11-Pad1_ d_and		
-U7  Net-_U10-Pad1_ Net-_U7-Pad2_ d_inverter		
-U13  Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and		
-U16  Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and		
-U12  Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter		
-U19  Net-_U17-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and		
-U21  Net-_U10-Pad1_ Net-_U2-Pad5_ Net-_U20-Pad1_ d_and		
-U17  Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter		
-U25  Net-_U23-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_or		
-U23  Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and		
-U26  Net-_U10-Pad1_ Net-_U26-Pad2_ Net-_U25-Pad2_ d_and		
-U22  Net-_U10-Pad1_ Net-_U22-Pad2_ d_inverter		
-U29  Net-_U28-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_or		
-U28  Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and		
-U30  Net-_U10-Pad1_ Net-_U30-Pad2_ Net-_U29-Pad2_ d_and		
-U27  Net-_U10-Pad1_ Net-_U27-Pad2_ d_inverter		
-U33  Net-_U32-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or		
-U40  Net-_U38-Pad3_ Net-_U40-Pad2_ Net-_U15-Pad1_ d_or		
-U32  Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and		
-U34  Net-_U10-Pad1_ Net-_U34-Pad2_ Net-_U33-Pad2_ d_and		
-U38  Net-_U37-Pad2_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and		
-U42  Net-_U10-Pad1_ Net-_U42-Pad2_ Net-_U40-Pad2_ d_and		
-U31  Net-_U10-Pad1_ Net-_U31-Pad2_ d_inverter		
-U37  Net-_U10-Pad1_ Net-_U37-Pad2_ d_inverter		
-U39  Net-_U36-Pad3_ Net-_U39-Pad2_ Net-_U18-Pad1_ d_or		
-U36  Net-_U36-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad3_ d_and		
-U41  Net-_U15-Pad5_ Net-_U10-Pad1_ Net-_U39-Pad2_ d_and		
-U9  Net-_U33-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U42-Pad2_ ? d_dff		
-U35  Net-_U10-Pad1_ Net-_U35-Pad2_ d_inverter		
-U24  Net-_U24-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U10-Pad2_ ? d_dff		
-U45  Net-_U45-Pad1_ Net-_U44-Pad3_ Net-_U24-Pad1_ d_or		
-U46  Net-_U18-Pad5_ Net-_U10-Pad1_ Net-_U45-Pad1_ d_and		
-U44  Net-_U44-Pad1_ Net-_U43-Pad2_ Net-_U44-Pad3_ d_and		
-U43  Net-_U10-Pad1_ Net-_U43-Pad2_ d_inverter		
-U5  Net-_U5-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad1_ Net-_U19-Pad2_ Net-_U23-Pad2_ Net-_U10-Pad2_ Net-_U2-Pad5_ Net-_U30-Pad2_ Net-_U42-Pad2_ Net-_U18-Pad5_ Net-_U28-Pad2_ Net-_U1-Pad5_ Net-_U26-Pad2_ Net-_U34-Pad2_ Net-_U15-Pad5_ Net-_U36-Pad1_ Net-_U32-Pad2_ Net-_U38-Pad2_ Net-_U10-Pad1_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out
deleted file mode 100644
index cff41387..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out
+++ /dev/null
@@ -1,192 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-
-* u3  net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4  net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6  net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15  net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2  net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18  net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11  net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14  net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20  net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8  net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7  net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13  net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16  net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12  net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19  net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21  net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17  net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25  net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23  net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26  net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22  net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29  net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28  net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30  net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27  net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33  net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40  net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32  net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34  net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38  net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42  net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31  net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37  net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39  net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36  net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41  net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9  net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35  net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24  net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45  net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46  net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44  net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43  net-_u10-pad1_ net-_u43-pad2_ d_inverter
-* u5  net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ port
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro
deleted file mode 100644
index ec294cbd..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro
+++ /dev/null
@@ -1,85 +0,0 @@
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diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch
deleted file mode 100644
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-$Comp
-L d_inverter U17
-U 1 1 5C94722C
-P 5950 8950
-F 0 "U17" H 5950 8850 60  0000 C CNN
-F 1 "d_inverter" H 5950 9100 60  0000 C CNN
-F 2 "" H 6000 8900 60  0000 C CNN
-F 3 "" H 6000 8900 60  0000 C CNN
-	1    5950 8950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U25
-U 1 1 5C94A04A
-P 7950 6250
-F 0 "U25" H 7950 6250 60  0000 C CNN
-F 1 "d_or" H 7950 6350 60  0000 C CNN
-F 2 "" H 7950 6250 60  0000 C CNN
-F 3 "" H 7950 6250 60  0000 C CNN
-	1    7950 6250
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_and U23
-U 1 1 5C94A0C3
-P 7800 7050
-F 0 "U23" H 7800 7050 60  0000 C CNN
-F 1 "d_and" H 7850 7150 60  0000 C CNN
-F 2 "" H 7800 7050 60  0000 C CNN
-F 3 "" H 7800 7050 60  0000 C CNN
-	1    7800 7050
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U26
-U 1 1 5C94A14D
-P 8150 7050
-F 0 "U26" H 8150 7050 60  0000 C CNN
-F 1 "d_and" H 8200 7150 60  0000 C CNN
-F 2 "" H 8150 7050 60  0000 C CNN
-F 3 "" H 8150 7050 60  0000 C CNN
-	1    8150 7050
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_inverter U22
-U 1 1 5C94A510
-P 7700 8000
-F 0 "U22" H 7700 7900 60  0000 C CNN
-F 1 "d_inverter" H 7700 8150 60  0000 C CNN
-F 2 "" H 7750 7950 60  0000 C CNN
-F 3 "" H 7750 7950 60  0000 C CNN
-	1    7700 8000
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_or U29
-U 1 1 5C94E1FD
-P 9900 5850
-F 0 "U29" H 9900 5850 60  0000 C CNN
-F 1 "d_or" H 9900 5950 60  0000 C CNN
-F 2 "" H 9900 5850 60  0000 C CNN
-F 3 "" H 9900 5850 60  0000 C CNN
-	1    9900 5850
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_and U28
-U 1 1 5C94E286
-P 9750 6650
-F 0 "U28" H 9750 6650 60  0000 C CNN
-F 1 "d_and" H 9800 6750 60  0000 C CNN
-F 2 "" H 9750 6650 60  0000 C CNN
-F 3 "" H 9750 6650 60  0000 C CNN
-	1    9750 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U30
-U 1 1 5C94E302
-P 10100 6650
-F 0 "U30" H 10100 6650 60  0000 C CNN
-F 1 "d_and" H 10150 6750 60  0000 C CNN
-F 2 "" H 10100 6650 60  0000 C CNN
-F 3 "" H 10100 6650 60  0000 C CNN
-	1    10100 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_inverter U27
-U 1 1 5C94E385
-P 9650 7600
-F 0 "U27" H 9650 7500 60  0000 C CNN
-F 1 "d_inverter" H 9650 7750 60  0000 C CNN
-F 2 "" H 9700 7550 60  0000 C CNN
-F 3 "" H 9700 7550 60  0000 C CNN
-	1    9650 7600
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_or U33
-U 1 1 5C94FC0A
-P 11150 5850
-F 0 "U33" H 11150 5850 60  0000 C CNN
-F 1 "d_or" H 11150 5950 60  0000 C CNN
-F 2 "" H 11150 5850 60  0000 C CNN
-F 3 "" H 11150 5850 60  0000 C CNN
-	1    11150 5850
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_or U40
-U 1 1 5C94FC89
-P 12450 5850
-F 0 "U40" H 12450 5850 60  0000 C CNN
-F 1 "d_or" H 12450 5950 60  0000 C CNN
-F 2 "" H 12450 5850 60  0000 C CNN
-F 3 "" H 12450 5850 60  0000 C CNN
-	1    12450 5850
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_and U32
-U 1 1 5C94FD1B
-P 11000 6650
-F 0 "U32" H 11000 6650 60  0000 C CNN
-F 1 "d_and" H 11050 6750 60  0000 C CNN
-F 2 "" H 11000 6650 60  0000 C CNN
-F 3 "" H 11000 6650 60  0000 C CNN
-	1    11000 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U34
-U 1 1 5C94FDA6
-P 11350 6650
-F 0 "U34" H 11350 6650 60  0000 C CNN
-F 1 "d_and" H 11400 6750 60  0000 C CNN
-F 2 "" H 11350 6650 60  0000 C CNN
-F 3 "" H 11350 6650 60  0000 C CNN
-	1    11350 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U38
-U 1 1 5C94FE38
-P 12300 6650
-F 0 "U38" H 12300 6650 60  0000 C CNN
-F 1 "d_and" H 12350 6750 60  0000 C CNN
-F 2 "" H 12300 6650 60  0000 C CNN
-F 3 "" H 12300 6650 60  0000 C CNN
-	1    12300 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_and U42
-U 1 1 5C94FEC5
-P 12600 6650
-F 0 "U42" H 12600 6650 60  0000 C CNN
-F 1 "d_and" H 12650 6750 60  0000 C CNN
-F 2 "" H 12600 6650 60  0000 C CNN
-F 3 "" H 12600 6650 60  0000 C CNN
-	1    12600 6650
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_inverter U31
-U 1 1 5C95027B
-P 10900 7600
-F 0 "U31" H 10900 7500 60  0000 C CNN
-F 1 "d_inverter" H 10900 7750 60  0000 C CNN
-F 2 "" H 10950 7550 60  0000 C CNN
-F 3 "" H 10950 7550 60  0000 C CNN
-	1    10900 7600
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_inverter U37
-U 1 1 5C950310
-P 12200 7600
-F 0 "U37" H 12200 7500 60  0000 C CNN
-F 1 "d_inverter" H 12200 7750 60  0000 C CNN
-F 2 "" H 12250 7550 60  0000 C CNN
-F 3 "" H 12250 7550 60  0000 C CNN
-	1    12200 7600
-	0    -1   -1   0   
-$EndComp
-$Comp
-L d_or U39
-U 1 1 5C956491
-P 12350 3100
-F 0 "U39" H 12350 3100 60  0000 C CNN
-F 1 "d_or" H 12350 3200 60  0000 C CNN
-F 2 "" H 12350 3100 60  0000 C CNN
-F 3 "" H 12350 3100 60  0000 C CNN
-	1    12350 3100
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_and U36
-U 1 1 5C956C09
-P 12200 2550
-F 0 "U36" H 12200 2550 60  0000 C CNN
-F 1 "d_and" H 12250 2650 60  0000 C CNN
-F 2 "" H 12200 2550 60  0000 C CNN
-F 3 "" H 12200 2550 60  0000 C CNN
-	1    12200 2550
-	0    1    1    0   
-$EndComp
-$Comp
-L d_and U41
-U 1 1 5C95766B
-P 12500 2550
-F 0 "U41" H 12500 2550 60  0000 C CNN
-F 1 "d_and" H 12550 2650 60  0000 C CNN
-F 2 "" H 12500 2550 60  0000 C CNN
-F 3 "" H 12500 2550 60  0000 C CNN
-	1    12500 2550
-	0    1    1    0   
-$EndComp
-Text Notes 10300 2100 0    60   ~ 0
-IN0
-Text Notes 12050 9000 0    60   ~ 0
-IN1
-Text Notes 10700 9000 0    60   ~ 0
-IN2
-Text Notes 9500 9000 0    60   ~ 0
-IN3
-Text Notes 7500 9050 0    60   ~ 0
-IN4
-Text Notes 6150 9050 0    60   ~ 0
-IN5
-Text Notes 4050 9100 0    60   ~ 0
-IN6
-Text Notes 2750 9050 0    60   ~ 0
-IN7
-Text Notes 12850 8650 0    60   ~ 0
-CI
-Text Notes 8700 2850 0    60   ~ 0
-O0
-Text Notes 8500 2750 0    60   ~ 0
-O1
-Text Notes 8700 2650 0    60   ~ 0
-O2
-Text Notes 8500 2550 0    60   ~ 0
-O3
-Text Notes 8700 2450 0    60   ~ 0
-O4
-Text Notes 8500 2350 0    60   ~ 0
-O5
-Text Notes 8700 2250 0    60   ~ 0
-O6
-Text Notes 8500 2150 0    60   ~ 0
-O7
-$Comp
-L d_dff U9
-U 1 1 5C92973B
-P 9850 4850
-F 0 "U9" H 9850 4850 60  0000 C CNN
-F 1 "d_dff" H 9850 5000 60  0000 C CNN
-F 2 "" H 9850 4850 60  0000 C CNN
-F 3 "" H 9850 4850 60  0000 C CNN
-	1    9850 4850
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U35
-U 1 1 5C9582C3
-P 11500 2550
-F 0 "U35" H 11500 2450 60  0000 C CNN
-F 1 "d_inverter" H 11500 2700 60  0000 C CNN
-F 2 "" H 11550 2500 60  0000 C CNN
-F 3 "" H 11550 2500 60  0000 C CNN
-	1    11500 2550
-	0    1    1    0   
-$EndComp
-$Comp
-L d_dff U24
-U 1 1 5C95D8E8
-P 3350 3000
-F 0 "U24" H 3350 3000 60  0000 C CNN
-F 1 "d_dff" H 3350 3150 60  0000 C CNN
-F 2 "" H 3350 3000 60  0000 C CNN
-F 3 "" H 3350 3000 60  0000 C CNN
-	1    3350 3000
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3350 3600 3350 4200
-Wire Wire Line
-	2600 4000 12450 4000
-Wire Wire Line
-	12450 4000 12450 4200
-Connection ~ 11150 4000
-Wire Wire Line
-	11150 4200 11150 4000
-Wire Wire Line
-	9850 4200 9850 4000
-Connection ~ 9850 4000
-Wire Wire Line
-	8550 4200 8550 4000
-Connection ~ 8550 4000
-Wire Wire Line
-	5950 4200 5950 4000
-Connection ~ 5950 4000
-Wire Wire Line
-	7250 4200 7250 4000
-Connection ~ 7250 4000
-Wire Wire Line
-	4650 4200 4650 4000
-Connection ~ 4650 4000
-Wire Wire Line
-	3350 5450 3350 5600
-Wire Wire Line
-	2600 5600 12450 5600
-Wire Wire Line
-	4650 5600 4650 5450
-Wire Wire Line
-	5950 5600 5950 5450
-Connection ~ 4650 5600
-Wire Wire Line
-	7250 5600 7250 5450
-Connection ~ 5950 5600
-Wire Wire Line
-	8550 5600 8550 5450
-Connection ~ 7250 5600
-Wire Wire Line
-	9850 5600 9850 5450
-Connection ~ 8550 5600
-Wire Wire Line
-	11150 5600 11150 5450
-Connection ~ 9850 5600
-Wire Wire Line
-	12450 5600 12450 5450
-Connection ~ 11150 5600
-Wire Wire Line
-	2600 2050 2600 5600
-Connection ~ 3350 4000
-Connection ~ 3350 5600
-Connection ~ 2600 4000
-Wire Wire Line
-	3350 2350 3350 2250
-Wire Wire Line
-	3350 2250 2600 2250
-Wire Wire Line
-	2600 2050 2850 2050
-Connection ~ 2600 2250
-Wire Wire Line
-	2800 3300 2650 3300
-Wire Wire Line
-	2650 3300 2650 5500
-Wire Wire Line
-	2650 5150 2800 5150
-Wire Wire Line
-	2650 5500 11850 5500
-Wire Wire Line
-	4050 5500 4050 5150
-Wire Wire Line
-	4050 5150 4100 5150
-Connection ~ 2650 5150
-Wire Wire Line
-	5400 5150 5350 5150
-Wire Wire Line
-	5350 5150 5350 5500
-Connection ~ 4050 5500
-Wire Wire Line
-	6650 5500 6650 5150
-Wire Wire Line
-	6650 5150 6700 5150
-Connection ~ 5350 5500
-Wire Wire Line
-	7950 5500 7950 5150
-Wire Wire Line
-	7950 5150 8000 5150
-Connection ~ 6650 5500
-Wire Wire Line
-	9250 5500 9250 5150
-Wire Wire Line
-	9250 5150 9300 5150
-Connection ~ 7950 5500
-Wire Wire Line
-	10550 5500 10550 5150
-Wire Wire Line
-	10550 5150 10600 5150
-Connection ~ 9250 5500
-Wire Wire Line
-	11850 5500 11850 5150
-Wire Wire Line
-	11850 5150 11900 5150
-Connection ~ 10550 5500
-Wire Wire Line
-	2650 3500 3150 3500
-Wire Wire Line
-	3150 3500 3150 3650
-Connection ~ 2650 3500
-Wire Wire Line
-	3950 2650 3900 2650
-Wire Wire Line
-	3950 2250 3950 2650
-Wire Wire Line
-	3950 2250 3750 2250
-Wire Wire Line
-	3750 2250 3750 1950
-Text Notes 8700 2050 0    60   ~ 0
-O8
-Wire Wire Line
-	13000 4500 13100 4500
-Wire Wire Line
-	13100 4500 13100 3500
-Wire Wire Line
-	13100 3500 8200 3500
-Wire Wire Line
-	8100 3600 11750 3600
-Wire Wire Line
-	11750 3600 11750 4500
-Wire Wire Line
-	11750 4500 11700 4500
-Wire Wire Line
-	8000 3700 10450 3700
-Wire Wire Line
-	10450 3700 10450 4500
-Wire Wire Line
-	10450 4500 10400 4500
-Wire Wire Line
-	7900 3800 9150 3800
-Wire Wire Line
-	9150 3800 9150 4500
-Wire Wire Line
-	9150 4500 9100 4500
-Wire Wire Line
-	7800 2350 7800 4300
-Wire Wire Line
-	7800 4300 7850 4300
-Wire Wire Line
-	7850 4300 7850 4500
-Wire Wire Line
-	7850 4500 7800 4500
-Wire Wire Line
-	6500 2250 6500 4300
-Wire Wire Line
-	6500 4300 6550 4300
-Wire Wire Line
-	6550 4300 6550 4500
-Wire Wire Line
-	6550 4500 6500 4500
-Wire Wire Line
-	3900 2050 3900 2150
-Wire Wire Line
-	3900 2150 4100 2150
-Wire Wire Line
-	4100 2150 4100 4250
-Wire Wire Line
-	4100 4250 3950 4250
-Wire Wire Line
-	3950 4250 3950 4500
-Wire Wire Line
-	3950 4500 3900 4500
-$Comp
-L d_or U45
-U 1 1 5C9948BA
-P 4650 3350
-F 0 "U45" H 4650 3350 60  0000 C CNN
-F 1 "d_or" H 4650 3450 60  0000 C CNN
-F 2 "" H 4650 3350 60  0000 C CNN
-F 3 "" H 4650 3350 60  0000 C CNN
-	1    4650 3350
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_and U46
-U 1 1 5C994A8D
-P 4850 2700
-F 0 "U46" H 4850 2700 60  0000 C CNN
-F 1 "d_and" H 4900 2800 60  0000 C CNN
-F 2 "" H 4850 2700 60  0000 C CNN
-F 3 "" H 4850 2700 60  0000 C CNN
-	1    4850 2700
-	0    1    1    0   
-$EndComp
-$Comp
-L d_and U44
-U 1 1 5C994B61
-P 4550 2700
-F 0 "U44" H 4550 2700 60  0000 C CNN
-F 1 "d_and" H 4600 2800 60  0000 C CNN
-F 2 "" H 4550 2700 60  0000 C CNN
-F 3 "" H 4550 2700 60  0000 C CNN
-	1    4550 2700
-	0    1    1    0   
-$EndComp
-$Comp
-L d_inverter U43
-U 1 1 5C994C4E
-P 4300 2650
-F 0 "U43" H 4300 2550 60  0000 C CNN
-F 1 "d_inverter" H 4300 2800 60  0000 C CNN
-F 2 "" H 4350 2600 60  0000 C CNN
-F 3 "" H 4350 2600 60  0000 C CNN
-	1    4300 2650
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	4300 2950 4400 2950
-Wire Wire Line
-	4400 2950 4400 2200
-Wire Wire Line
-	4400 2200 4550 2200
-Wire Wire Line
-	4550 2200 4550 2250
-Wire Wire Line
-	2850 7550 2850 7400
-Wire Wire Line
-	2850 8150 2850 8700
-Wire Wire Line
-	2850 8700 13000 8700
-Wire Wire Line
-	12200 7900 12200 8700
-Connection ~ 12200 8700
-Wire Wire Line
-	12200 7300 12200 7100
-Wire Wire Line
-	12500 7100 12500 8700
-Connection ~ 12500 8700
-Wire Wire Line
-	10900 7300 10900 7100
-Wire Wire Line
-	10900 7900 10900 8700
-Connection ~ 10900 8700
-Wire Wire Line
-	11250 7100 11250 8700
-Connection ~ 11250 8700
-Wire Wire Line
-	9650 7100 9650 7300
-Wire Wire Line
-	10000 7100 10000 8700
-Connection ~ 10000 8700
-Wire Wire Line
-	9650 7900 9650 8700
-Connection ~ 9650 8700
-Wire Wire Line
-	7700 7700 7700 7500
-Wire Wire Line
-	7700 8300 7700 8700
-Connection ~ 7700 8700
-Wire Wire Line
-	8050 7500 8050 8700
-Connection ~ 8050 8700
-Wire Wire Line
-	5650 8950 5650 8700
-Connection ~ 5650 8700
-Wire Wire Line
-	6250 8950 6250 8650
-Wire Wire Line
-	6600 8650 6600 8700
-Connection ~ 6600 8700
-Wire Wire Line
-	3200 7400 3200 8700
-Connection ~ 3200 8700
-Wire Wire Line
-	4250 8700 4250 8150
-Connection ~ 4250 8700
-Wire Wire Line
-	4250 7550 4250 7300
-Wire Wire Line
-	4600 7300 4600 8700
-Connection ~ 4600 8700
-Wire Wire Line
-	11500 2850 11500 2950
-Wire Wire Line
-	11500 2950 12050 2950
-Wire Wire Line
-	12050 2950 12050 2050
-Wire Wire Line
-	12050 2050 12200 2050
-Wire Wire Line
-	12200 2050 12200 2100
-Wire Wire Line
-	11500 2250 11300 2250
-Wire Wire Line
-	11300 1900 11300 3450
-Wire Wire Line
-	5650 3450 13250 3450
-Wire Wire Line
-	13250 3450 13250 8500
-Wire Wire Line
-	13250 8500 12750 8500
-Wire Wire Line
-	12750 8500 12750 8700
-Connection ~ 12750 8700
-Wire Wire Line
-	11300 1900 12500 1900
-Wire Wire Line
-	12500 1900 12500 2100
-Connection ~ 11300 2250
-Wire Wire Line
-	5650 2000 5650 3450
-Connection ~ 11300 3450
-Wire Wire Line
-	3750 1950 8900 1950
-Wire Wire Line
-	4300 2350 4300 2000
-Wire Wire Line
-	4300 2000 5650 2000
-Wire Wire Line
-	4850 2250 4850 2000
-Connection ~ 4850 2000
-Wire Wire Line
-	2800 2300 2800 2650
-Wire Wire Line
-	2800 2300 4050 2300
-Wire Wire Line
-	4050 2300 4050 3400
-Wire Wire Line
-	4050 3400 4200 3400
-Wire Wire Line
-	4600 3150 4600 3250
-Wire Wire Line
-	4600 3250 5100 3250
-Wire Wire Line
-	5100 3250 5100 3350
-Wire Wire Line
-	4900 3150 5150 3150
-Wire Wire Line
-	5150 3150 5150 3450
-Wire Wire Line
-	5150 3450 5100 3450
-Wire Wire Line
-	4650 2250 4650 2100
-Wire Wire Line
-	4650 2100 5450 2100
-Wire Wire Line
-	5450 2100 5450 2500
-Wire Wire Line
-	4950 2250 5100 2250
-Wire Wire Line
-	5100 2250 5100 3000
-Wire Wire Line
-	5100 3000 8200 3000
-Connection ~ 8200 3000
-Wire Wire Line
-	3950 2550 4000 2550
-Wire Wire Line
-	4000 2550 4000 7450
-Wire Wire Line
-	4000 7450 3300 7450
-Wire Wire Line
-	3300 7450 3300 7400
-Connection ~ 3950 2550
-Wire Wire Line
-	2800 4500 2750 4500
-Wire Wire Line
-	2750 4500 2750 6150
-Wire Wire Line
-	2750 6150 3000 6150
-Wire Wire Line
-	2900 6500 2900 6300
-Wire Wire Line
-	2900 6300 3900 6300
-Wire Wire Line
-	3900 6300 3900 6200
-Wire Wire Line
-	3900 6100 3950 6100
-Wire Wire Line
-	3950 6100 3950 6450
-Wire Wire Line
-	3950 6450 3250 6450
-Wire Wire Line
-	3250 6450 3250 6500
-Wire Wire Line
-	2950 7400 2950 9100
-Wire Wire Line
-	2950 9100 2700 9100
-Wire Wire Line
-	2700 9100 2700 9050
-Wire Wire Line
-	3950 9100 4350 9100
-Wire Wire Line
-	4350 9100 4350 7300
-Wire Wire Line
-	4100 4150 4400 4150
-Wire Wire Line
-	4400 4150 4400 5850
-Connection ~ 4100 4150
-Wire Wire Line
-	4400 5850 5300 5850
-Wire Wire Line
-	5300 5850 5300 7450
-Wire Wire Line
-	5300 7450 4700 7450
-Wire Wire Line
-	4700 7450 4700 7300
-Wire Wire Line
-	4650 6400 5150 6400
-Wire Wire Line
-	5150 6400 5150 6200
-Wire Wire Line
-	5150 6200 5000 6200
-Wire Wire Line
-	4100 6150 4100 5300
-Wire Wire Line
-	4100 5300 4200 5300
-Wire Wire Line
-	4200 5300 4200 4600
-Wire Wire Line
-	4200 4600 4050 4600
-Wire Wire Line
-	4050 4600 4050 4500
-Wire Wire Line
-	4050 4500 4100 4500
-Wire Wire Line
-	4300 6400 4300 6300
-Wire Wire Line
-	4300 6300 5100 6300
-Wire Wire Line
-	5100 6300 5100 6100
-Wire Wire Line
-	5100 6100 5000 6100
-Wire Wire Line
-	6350 8650 6350 9100
-Wire Wire Line
-	6350 9100 5850 9100
-Wire Wire Line
-	5400 4500 5350 4500
-Wire Wire Line
-	5350 4500 5350 5100
-Wire Wire Line
-	5350 5100 5300 5100
-Wire Wire Line
-	5300 5100 5300 5350
-Wire Wire Line
-	5300 5350 5600 5350
-Wire Wire Line
-	5600 5350 5600 7500
-Wire Wire Line
-	5600 7500 6000 7500
-Wire Wire Line
-	5250 4500 5200 4500
-Wire Wire Line
-	5200 2150 8900 2150
-Wire Wire Line
-	5200 2150 5200 4250
-Wire Wire Line
-	5200 4250 5250 4250
-Wire Wire Line
-	5250 4250 5250 4500
-Wire Wire Line
-	5250 4350 5750 4350
-Wire Wire Line
-	5750 4350 5750 7250
-Wire Wire Line
-	5750 7250 7250 7250
-Connection ~ 5250 4350
-Wire Wire Line
-	7250 7250 7250 8850
-Wire Wire Line
-	7250 8850 6700 8850
-Wire Wire Line
-	6700 8850 6700 8650
-Wire Wire Line
-	6650 7750 6650 7700
-Wire Wire Line
-	6650 7700 7050 7700
-Wire Wire Line
-	7050 7700 7050 7550
-Wire Wire Line
-	7050 7550 6900 7550
-Wire Wire Line
-	6300 7750 6300 7650
-Wire Wire Line
-	6300 7650 7150 7650
-Wire Wire Line
-	7150 7650 7150 7450
-Wire Wire Line
-	7150 7450 6900 7450
-Wire Wire Line
-	7450 9050 7800 9050
-Wire Wire Line
-	7800 9050 7800 7500
-Wire Wire Line
-	7750 6600 7750 6450
-Wire Wire Line
-	7750 6450 8550 6450
-Wire Wire Line
-	8550 6450 8550 6350
-Wire Wire Line
-	8550 6350 8400 6350
-Wire Wire Line
-	8400 6250 8600 6250
-Wire Wire Line
-	8600 6250 8600 6500
-Wire Wire Line
-	8600 6500 8100 6500
-Wire Wire Line
-	8100 6500 8100 6600
-Wire Wire Line
-	6600 4500 6700 4500
-Wire Wire Line
-	6600 4500 6600 6300
-Wire Wire Line
-	6600 6300 7500 6300
-Wire Wire Line
-	6500 4150 7100 4150
-Wire Wire Line
-	7100 4150 7100 6050
-Wire Wire Line
-	7100 6050 8800 6050
-Wire Wire Line
-	8800 6050 8800 7600
-Wire Wire Line
-	8800 7600 8150 7600
-Wire Wire Line
-	8150 7600 8150 7500
-Connection ~ 6500 4150
-Wire Wire Line
-	9750 7100 9750 9050
-Wire Wire Line
-	9750 9050 9400 9050
-Wire Wire Line
-	11000 7100 11000 9050
-Wire Wire Line
-	11000 9050 10650 9050
-Wire Wire Line
-	12300 7100 12300 9050
-Wire Wire Line
-	12300 9050 12050 9050
-Wire Wire Line
-	12250 6200 12250 6100
-Wire Wire Line
-	12250 6100 13000 6100
-Wire Wire Line
-	13000 6100 13000 5950
-Wire Wire Line
-	13000 5950 12900 5950
-Wire Wire Line
-	12900 5850 13100 5850
-Wire Wire Line
-	13100 5850 13100 6150
-Wire Wire Line
-	13100 6150 12550 6150
-Wire Wire Line
-	12550 6150 12550 6200
-Wire Wire Line
-	8000 4500 7900 4500
-Wire Wire Line
-	7900 4500 7900 5900
-Wire Wire Line
-	7900 5900 9450 5900
-Wire Wire Line
-	7800 4150 8400 4150
-Wire Wire Line
-	8400 4150 8400 5700
-Wire Wire Line
-	8400 5700 10550 5700
-Wire Wire Line
-	10550 5700 10550 7250
-Wire Wire Line
-	10550 7250 10100 7250
-Wire Wire Line
-	10100 7250 10100 7100
-Connection ~ 7800 4150
-Wire Wire Line
-	9700 6200 9700 6100
-Wire Wire Line
-	9700 6100 10450 6100
-Wire Wire Line
-	10450 6100 10450 5950
-Wire Wire Line
-	10450 5950 10350 5950
-Wire Wire Line
-	10350 5850 10500 5850
-Wire Wire Line
-	10500 5850 10500 6150
-Wire Wire Line
-	10500 6150 10050 6150
-Wire Wire Line
-	10050 6150 10050 6200
-Wire Wire Line
-	9300 4500 9200 4500
-Wire Wire Line
-	9200 4500 9200 5300
-Wire Wire Line
-	9200 5300 10650 5300
-Wire Wire Line
-	10650 5300 10650 5900
-Wire Wire Line
-	10650 5900 10700 5900
-Wire Wire Line
-	9150 4200 9650 4200
-Wire Wire Line
-	9650 4200 9650 4850
-Wire Wire Line
-	9650 4850 10450 4850
-Wire Wire Line
-	10450 4850 10450 5650
-Wire Wire Line
-	10450 5650 11750 5650
-Connection ~ 9150 4200
-Wire Wire Line
-	11750 5650 11750 7300
-Wire Wire Line
-	11750 7300 11350 7300
-Wire Wire Line
-	11350 7300 11350 7100
-Wire Wire Line
-	10950 6200 10950 6100
-Wire Wire Line
-	10950 6100 11650 6100
-Wire Wire Line
-	11650 6100 11650 5950
-Wire Wire Line
-	11650 5950 11600 5950
-Wire Wire Line
-	11600 5850 11700 5850
-Wire Wire Line
-	11700 5850 11700 6150
-Wire Wire Line
-	11700 6150 11300 6150
-Wire Wire Line
-	11300 6150 11300 6200
-Wire Wire Line
-	10600 4500 10600 4950
-Wire Wire Line
-	10600 4950 11350 4950
-Wire Wire Line
-	11350 4950 11350 5450
-Wire Wire Line
-	11350 5450 11950 5450
-Wire Wire Line
-	11950 5450 11950 5900
-Wire Wire Line
-	11950 5900 12000 5900
-Wire Wire Line
-	10450 4200 11000 4200
-Wire Wire Line
-	11000 4200 11000 4700
-Wire Wire Line
-	11000 4700 11800 4700
-Wire Wire Line
-	11800 4700 11800 5350
-Wire Wire Line
-	11800 5350 13150 5350
-Wire Wire Line
-	13150 5350 13150 7250
-Connection ~ 10450 4200
-Wire Wire Line
-	13150 7250 12600 7250
-Wire Wire Line
-	12600 7250 12600 7100
-Wire Wire Line
-	11900 4500 11800 4500
-Wire Wire Line
-	11800 4500 11800 3150
-Wire Wire Line
-	11800 3150 11900 3150
-Wire Wire Line
-	12550 3000 12900 3000
-Wire Wire Line
-	12900 3000 12900 3100
-Wire Wire Line
-	12900 3100 12800 3100
-Wire Wire Line
-	12250 3000 12400 3000
-Wire Wire Line
-	12400 3000 12400 2850
-Wire Wire Line
-	12400 2850 13200 2850
-Wire Wire Line
-	13200 2850 13200 3200
-Wire Wire Line
-	13200 3200 12800 3200
-Wire Wire Line
-	10200 2000 12300 2000
-Wire Wire Line
-	12300 2000 12300 2100
-Wire Wire Line
-	11650 3600 11650 1950
-Wire Wire Line
-	11650 1950 12600 1950
-Wire Wire Line
-	12600 1950 12600 2100
-Connection ~ 11650 3600
-$Comp
-L PORT U5
-U 12 1 5C982725
-P 9150 2750
-F 0 "U5" H 9200 2850 30  0000 C CNN
-F 1 "PORT" H 9150 2750 30  0000 C CNN
-F 2 "" H 9150 2750 60  0000 C CNN
-F 3 "" H 9150 2750 60  0000 C CNN
-	12   9150 2750
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 17 1 5C9827C2
-P 9550 2650
-F 0 "U5" H 9600 2750 30  0000 C CNN
-F 1 "PORT" H 9550 2650 30  0000 C CNN
-F 2 "" H 9550 2650 60  0000 C CNN
-F 3 "" H 9550 2650 60  0000 C CNN
-	17   9550 2650
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 11 1 5C98283D
-P 9150 2550
-F 0 "U5" H 9200 2650 30  0000 C CNN
-F 1 "PORT" H 9150 2550 30  0000 C CNN
-F 2 "" H 9150 2550 60  0000 C CNN
-F 3 "" H 9150 2550 60  0000 C CNN
-	11   9150 2550
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 16 1 5C9828CC
-P 9550 2450
-F 0 "U5" H 9600 2550 30  0000 C CNN
-F 1 "PORT" H 9550 2450 30  0000 C CNN
-F 2 "" H 9550 2450 60  0000 C CNN
-F 3 "" H 9550 2450 60  0000 C CNN
-	16   9550 2450
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 10 1 5C982957
-P 9150 2350
-F 0 "U5" H 9200 2450 30  0000 C CNN
-F 1 "PORT" H 9150 2350 30  0000 C CNN
-F 2 "" H 9150 2350 60  0000 C CNN
-F 3 "" H 9150 2350 60  0000 C CNN
-	10   9150 2350
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 15 1 5C9829D6
-P 9550 2250
-F 0 "U5" H 9600 2350 30  0000 C CNN
-F 1 "PORT" H 9550 2250 30  0000 C CNN
-F 2 "" H 9550 2250 60  0000 C CNN
-F 3 "" H 9550 2250 60  0000 C CNN
-	15   9550 2250
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 9 1 5C982A5D
-P 9150 2150
-F 0 "U5" H 9200 2250 30  0000 C CNN
-F 1 "PORT" H 9150 2150 30  0000 C CNN
-F 2 "" H 9150 2150 60  0000 C CNN
-F 3 "" H 9150 2150 60  0000 C CNN
-	9    9150 2150
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 14 1 5C982AE0
-P 9550 2050
-F 0 "U5" H 9600 2150 30  0000 C CNN
-F 1 "PORT" H 9550 2050 30  0000 C CNN
-F 2 "" H 9550 2050 60  0000 C CNN
-F 3 "" H 9550 2050 60  0000 C CNN
-	14   9550 2050
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 8 1 5C982B81
-P 9150 1950
-F 0 "U5" H 9200 2050 30  0000 C CNN
-F 1 "PORT" H 9150 1950 30  0000 C CNN
-F 2 "" H 9150 1950 60  0000 C CNN
-F 3 "" H 9150 1950 60  0000 C CNN
-	8    9150 1950
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 21 1 5C983602
-P 13250 8700
-F 0 "U5" H 13300 8800 30  0000 C CNN
-F 1 "PORT" H 13250 8700 30  0000 C CNN
-F 2 "" H 13250 8700 60  0000 C CNN
-F 3 "" H 13250 8700 60  0000 C CNN
-	21   13250 8700
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 18 1 5C983C2F
-P 9950 2000
-F 0 "U5" H 10000 2100 30  0000 C CNN
-F 1 "PORT" H 9950 2000 30  0000 C CNN
-F 2 "" H 9950 2000 60  0000 C CNN
-F 3 "" H 9950 2000 60  0000 C CNN
-	18   9950 2000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 20 1 5C984048
-P 11800 9050
-F 0 "U5" H 11850 9150 30  0000 C CNN
-F 1 "PORT" H 11800 9050 30  0000 C CNN
-F 2 "" H 11800 9050 60  0000 C CNN
-F 3 "" H 11800 9050 60  0000 C CNN
-	20   11800 9050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 19 1 5C9840D3
-P 10400 9050
-F 0 "U5" H 10450 9150 30  0000 C CNN
-F 1 "PORT" H 10400 9050 30  0000 C CNN
-F 2 "" H 10400 9050 60  0000 C CNN
-F 3 "" H 10400 9050 60  0000 C CNN
-	19   10400 9050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 13 1 5C984164
-P 9150 9050
-F 0 "U5" H 9200 9150 30  0000 C CNN
-F 1 "PORT" H 9150 9050 30  0000 C CNN
-F 2 "" H 9150 9050 60  0000 C CNN
-F 3 "" H 9150 9050 60  0000 C CNN
-	13   9150 9050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 7 1 5C985678
-P 7200 9050
-F 0 "U5" H 7250 9150 30  0000 C CNN
-F 1 "PORT" H 7200 9050 30  0000 C CNN
-F 2 "" H 7200 9050 60  0000 C CNN
-F 3 "" H 7200 9050 60  0000 C CNN
-	7    7200 9050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 6 1 5C985709
-P 5600 9100
-F 0 "U5" H 5650 9200 30  0000 C CNN
-F 1 "PORT" H 5600 9100 30  0000 C CNN
-F 2 "" H 5600 9100 60  0000 C CNN
-F 3 "" H 5600 9100 60  0000 C CNN
-	6    5600 9100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 4 1 5C98579A
-P 3700 9100
-F 0 "U5" H 3750 9200 30  0000 C CNN
-F 1 "PORT" H 3700 9100 30  0000 C CNN
-F 2 "" H 3700 9100 60  0000 C CNN
-F 3 "" H 3700 9100 60  0000 C CNN
-	4    3700 9100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U5
-U 1 1 5C98582D
-P 2700 8800
-F 0 "U5" H 2750 8900 30  0000 C CNN
-F 1 "PORT" H 2700 8800 30  0000 C CNN
-F 2 "" H 2700 8800 60  0000 C CNN
-F 3 "" H 2700 8800 60  0000 C CNN
-	1    2700 8800
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U5
-U 5 1 5C98694B
-P 5450 2750
-F 0 "U5" H 5500 2850 30  0000 C CNN
-F 1 "PORT" H 5450 2750 30  0000 C CNN
-F 2 "" H 5450 2750 60  0000 C CNN
-F 3 "" H 5450 2750 60  0000 C CNN
-	5    5450 2750
-	0    -1   -1   0   
-$EndComp
-Text Notes 5400 2450 1    60   ~ 0
-IN8
-Text Notes 2650 2000 0    60   ~ 0
-GND
-$Comp
-L PORT U5
-U 2 1 5C986B72
-P 3100 2050
-F 0 "U5" H 3150 2150 30  0000 C CNN
-F 1 "PORT" H 3100 2050 30  0000 C CNN
-F 2 "" H 3100 2050 60  0000 C CNN
-F 3 "" H 3100 2050 60  0000 C CNN
-	2    3100 2050
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U5
-U 3 1 5C986C25
-P 3150 3900
-F 0 "U5" H 3200 4000 30  0000 C CNN
-F 1 "PORT" H 3150 3900 30  0000 C CNN
-F 2 "" H 3150 3900 60  0000 C CNN
-F 3 "" H 3150 3900 60  0000 C CNN
-	3    3150 3900
-	0    -1   -1   0   
-$EndComp
-Text Notes 2850 3600 0    60   ~ 0
-CLK
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub
deleted file mode 100644
index e94cb0f4..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub
+++ /dev/null
@@ -1,186 +0,0 @@
-* Subcircuit 9bit-Right_shift_register
-.subckt 9bit-Right_shift_register net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ 
-* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-* u3  net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4  net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6  net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15  net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2  net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18  net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11  net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14  net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20  net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8  net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7  net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13  net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16  net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12  net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19  net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21  net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17  net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25  net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23  net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26  net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22  net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29  net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28  net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30  net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27  net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33  net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40  net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32  net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34  net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38  net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42  net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31  net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37  net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39  net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36  net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41  net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9  net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35  net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24  net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45  net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46  net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44  net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43  net-_u10-pad1_ net-_u43-pad2_ d_inverter
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 9bit-Right_shift_register
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml
deleted file mode 100644
index 28c290d4..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u3 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u4><u6 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u6><u15 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u15><u2 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u2><u1 name="type">d_dff<field51 name="Enter IC (default=0)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter value for Set Load (default=1.0e-12)" /><field54 name="Enter Clk Delay (default=1.0e-9)" /><field55 name="Enter value for Clk Load (default=1.0e-12)" /><field56 name="Enter Reset Delay (default=1.0)" /><field57 name="Enter value for Data Load (default=1.0e-12)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter value for Reset Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u1><u18 name="type">d_dff<field61 name="Enter IC (default=0)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter value for Set Load (default=1.0e-12)" /><field64 name="Enter Clk Delay (default=1.0e-9)" /><field65 name="Enter value for Clk Load (default=1.0e-12)" /><field66 name="Enter Reset Delay (default=1.0)" /><field67 name="Enter value for Data Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter value for Reset Load (default=1.0e-12)" /><field70 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_or<field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /><field73 name="Enter Rise Delay (default=1.0e-9)" /></u11><u14 name="type">d_or<field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /><field76 name="Enter Rise Delay (default=1.0e-9)" /></u14><u20 name="type">d_or<field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /></u20><u10 name="type">d_and<field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /><field82 name="Enter Rise Delay (default=1.0e-9)" /></u10><u8 name="type">d_and<field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /><field85 name="Enter Rise Delay (default=1.0e-9)" /></u8><u7 name="type">d_inverter<field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /><field88 name="Enter Rise Delay (default=1.0e-9)" /></u7><u13 name="type">d_and<field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /><field91 name="Enter Rise Delay (default=1.0e-9)" /></u13><u16 name="type">d_and<field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /><field94 name="Enter Rise Delay (default=1.0e-9)" /></u16><u12 name="type">d_inverter<field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /><field97 name="Enter Rise Delay (default=1.0e-9)" /></u12><u19 name="type">d_and<field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /></u19><u21 name="type">d_and<field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /></u21><u17 name="type">d_inverter<field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /><field106 name="Enter Rise Delay (default=1.0e-9)" /></u17><u25 name="type">d_or<field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /></u25><u23 name="type">d_and<field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /><field112 name="Enter Rise Delay (default=1.0e-9)" /></u23><u26 name="type">d_and<field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /><field115 name="Enter Rise Delay (default=1.0e-9)" /></u26><u22 name="type">d_inverter<field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /><field118 name="Enter Rise Delay (default=1.0e-9)" /></u22><u29 name="type">d_or<field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /><field121 name="Enter Rise Delay (default=1.0e-9)" /></u29><u28 name="type">d_and<field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /><field124 name="Enter Rise Delay (default=1.0e-9)" /></u28><u30 name="type">d_and<field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /><field127 name="Enter Rise Delay (default=1.0e-9)" /></u30><u27 name="type">d_inverter<field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /><field130 name="Enter Rise Delay (default=1.0e-9)" /></u27><u33 name="type">d_or<field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /></u33><u40 name="type">d_or<field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /><field136 name="Enter Rise Delay (default=1.0e-9)" /></u40><u32 name="type">d_and<field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /></u32><u34 name="type">d_and<field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /><field142 name="Enter Rise Delay (default=1.0e-9)" /></u34><u38 name="type">d_and<field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /><field145 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_and<field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /><field148 name="Enter Rise Delay (default=1.0e-9)" /></u42><u31 name="type">d_inverter<field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /></u31><u37 name="type">d_inverter<field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /><field154 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_or<field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /><field157 name="Enter Rise Delay (default=1.0e-9)" /></u39><u36 name="type">d_and<field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /><field160 name="Enter Rise Delay (default=1.0e-9)" /></u36><u41 name="type">d_and<field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /><field163 name="Enter Rise Delay (default=1.0e-9)" /></u41><u9 name="type">d_dff<field164 name="Enter IC (default=0)" /><field165 name="Enter Set Delay (default=1.0e-9)" /><field166 name="Enter value for Set Load (default=1.0e-12)" /><field167 name="Enter Clk Delay (default=1.0e-9)" /><field168 name="Enter value for Clk Load (default=1.0e-12)" /><field169 name="Enter Reset Delay (default=1.0)" /><field170 name="Enter value for Data Load (default=1.0e-12)" /><field171 name="Enter Fall Delay (default=1.0e-9)" /><field172 name="Enter value for Reset Load (default=1.0e-12)" /><field173 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field174 name="Enter Fall Delay (default=1.0e-9)" /><field175 name="Enter Input Load (default=1.0e-12)" /><field176 name="Enter Rise Delay (default=1.0e-9)" /></u35><u24 name="type">d_dff<field177 name="Enter IC (default=0)" /><field178 name="Enter Set Delay (default=1.0e-9)" /><field179 name="Enter value for Set Load (default=1.0e-12)" /><field180 name="Enter Clk Delay (default=1.0e-9)" /><field181 name="Enter value for Clk Load (default=1.0e-12)" /><field182 name="Enter Reset Delay (default=1.0)" /><field183 name="Enter value for Data Load (default=1.0e-12)" /><field184 name="Enter Fall Delay (default=1.0e-9)" /><field185 name="Enter value for Reset Load (default=1.0e-12)" /><field186 name="Enter Rise Delay (default=1.0e-9)" /></u24><u45 name="type">d_or<field187 name="Enter Fall Delay (default=1.0e-9)" /><field188 name="Enter Input Load (default=1.0e-12)" /><field189 name="Enter Rise Delay (default=1.0e-9)" /></u45><u46 name="type">d_and<field190 name="Enter Fall Delay (default=1.0e-9)" /><field191 name="Enter Input Load (default=1.0e-12)" /><field192 name="Enter Rise Delay (default=1.0e-9)" /></u46><u44 name="type">d_and<field193 name="Enter Fall Delay (default=1.0e-9)" /><field194 name="Enter Input Load (default=1.0e-12)" /><field195 name="Enter Rise Delay (default=1.0e-9)" /></u44><u43 name="type">d_inverter<field196 name="Enter Fall Delay (default=1.0e-9)" /><field197 name="Enter Input Load (default=1.0e-12)" /><field198 name="Enter Rise Delay (default=1.0e-9)" /></u43></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis b/src/SubcircuitLibrary/9bit-Right_shift_register/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/AD620-cache.lib b/src/SubcircuitLibrary/AD620/AD620-cache.lib
deleted file mode 100644
index b2ef0045..00000000
--- a/src/SubcircuitLibrary/AD620/AD620-cache.lib
+++ /dev/null
@@ -1,82 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# lm_741
-#
-DEF lm_741 X 0 40 Y Y 1 F N
-F0 "X" -200 0 60 H V C CNN
-F1 "lm_741" -350 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
-X off_null 1 -50 400 200 D 50 38 1 1 I
-X in- 2 -550 150 200 R 50 38 1 1 I
-X in+ 3 -550 -100 200 R 50 38 1 1 I
-X V- 4 -150 -450 200 U 50 38 1 1 I
-X off_null 5 50 350 200 D 50 38 1 1 I
-X out 6 550 0 200 L 50 38 1 1 O
-X V+ 7 -150 450 200 D 50 38 1 1 I
-X NC 8 150 -300 200 U 50 38 1 1 N
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-ENDDEF
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-#End Library
diff --git a/src/SubcircuitLibrary/AD620/AD620.cir b/src/SubcircuitLibrary/AD620/AD620.cir
deleted file mode 100644
index c82fdfd6..00000000
--- a/src/SubcircuitLibrary/AD620/AD620.cir
+++ /dev/null
@@ -1,26 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\AD620\AD620.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/19 16:16:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X2  Net-_R8-Pad1_ Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_R10-Pad2_ Net-_R10-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad7_ ? lm_741		
-X1  Net-_R7-Pad2_ Net-_R2-Pad1_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R9-Pad2_ Net-_R2-Pad2_ Net-_U1-Pad7_ ? lm_741		
-X3  Net-_R11-Pad2_ Net-_R4-Pad1_ Net-_R3-Pad1_ Net-_R10-Pad2_ Net-_R12-Pad2_ Net-_R6-Pad1_ Net-_U1-Pad7_ ? lm_741		
-R1  Net-_R1-Pad1_ Net-_R1-Pad2_ 24.7k		
-R2  Net-_R2-Pad1_ Net-_R2-Pad2_ 24.7k		
-R4  Net-_R4-Pad1_ Net-_R1-Pad1_ 10k		
-R3  Net-_R3-Pad1_ Net-_R2-Pad2_ 10k		
-R6  Net-_R6-Pad1_ Net-_R4-Pad1_ 10k		
-R5  Net-_R5-Pad1_ Net-_R3-Pad1_ 10k		
-U1  Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R5-Pad1_ Net-_R6-Pad1_ Net-_U1-Pad7_ Net-_R2-Pad1_ PORT		
-R8  Net-_R8-Pad1_ Net-_R10-Pad2_ 0.297k		
-R10  Net-_R10-Pad1_ Net-_R10-Pad2_ 1k		
-R7  Net-_R10-Pad2_ Net-_R7-Pad2_ 0.297k		
-R9  Net-_R10-Pad2_ Net-_R9-Pad2_ 1k		
-R12  Net-_R10-Pad2_ Net-_R12-Pad2_ 1k		
-R11  Net-_R10-Pad2_ Net-_R11-Pad2_ 0.75732k		
-
-.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.cir.out b/src/SubcircuitLibrary/AD620/AD620.cir.out
deleted file mode 100644
index 082780e2..00000000
--- a/src/SubcircuitLibrary/AD620/AD620.cir.out
+++ /dev/null
@@ -1,28 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
-
-.include lm_741.sub
-x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
-x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
-x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
-r1  net-_r1-pad1_ net-_r1-pad2_ 24.7k
-r2  net-_r2-pad1_ net-_r2-pad2_ 24.7k
-r4  net-_r4-pad1_ net-_r1-pad1_ 10k
-r3  net-_r3-pad1_ net-_r2-pad2_ 10k
-r6  net-_r6-pad1_ net-_r4-pad1_ 10k
-r5  net-_r5-pad1_ net-_r3-pad1_ 10k
-* u1  net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ port
-r8  net-_r8-pad1_ net-_r10-pad2_ 0.297k
-r10  net-_r10-pad1_ net-_r10-pad2_ 1k
-r7  net-_r10-pad2_ net-_r7-pad2_ 0.297k
-r9  net-_r10-pad2_ net-_r9-pad2_ 1k
-r12  net-_r10-pad2_ net-_r12-pad2_ 1k
-r11  net-_r10-pad2_ net-_r11-pad2_ 0.75732k
-.tran 0e-03 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.pro b/src/SubcircuitLibrary/AD620/AD620.pro
deleted file mode 100644
index 21e55e98..00000000
--- a/src/SubcircuitLibrary/AD620/AD620.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Thu Jun 27 12:48:03 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_User
-LibName11=eSim_Subckt
diff --git a/src/SubcircuitLibrary/AD620/AD620.sch b/src/SubcircuitLibrary/AD620/AD620.sch
deleted file mode 100644
index 8724fe19..00000000
--- a/src/SubcircuitLibrary/AD620/AD620.sch
+++ /dev/null
@@ -1,424 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:AD620-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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diff --git a/src/SubcircuitLibrary/AD620/AD620.sub b/src/SubcircuitLibrary/AD620/AD620.sub
deleted file mode 100644
index 1be97dbd..00000000
--- a/src/SubcircuitLibrary/AD620/AD620.sub
+++ /dev/null
@@ -1,22 +0,0 @@
-* Subcircuit AD620
-.subckt AD620 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ 
-* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
-.include lm_741.sub
-x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
-x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
-x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
-r1  net-_r1-pad1_ net-_r1-pad2_ 24.7k
-r2  net-_r2-pad1_ net-_r2-pad2_ 24.7k
-r4  net-_r4-pad1_ net-_r1-pad1_ 10k
-r3  net-_r3-pad1_ net-_r2-pad2_ 10k
-r6  net-_r6-pad1_ net-_r4-pad1_ 10k
-r5  net-_r5-pad1_ net-_r3-pad1_ 10k
-r8  net-_r8-pad1_ net-_r10-pad2_ 0.297k
-r10  net-_r10-pad1_ net-_r10-pad2_ 1k
-r7  net-_r10-pad2_ net-_r7-pad2_ 0.297k
-r9  net-_r10-pad2_ net-_r9-pad2_ 1k
-r12  net-_r10-pad2_ net-_r12-pad2_ 1k
-r11  net-_r10-pad2_ net-_r11-pad2_ 0.75732k
-* Control Statements
-
-.ends AD620
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml
deleted file mode 100644
index 3a4f8217..00000000
--- a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/NPN.lib b/src/SubcircuitLibrary/AD620/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/AD620/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/AD620/PNP.lib b/src/SubcircuitLibrary/AD620/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/AD620/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/AD620/analysis b/src/SubcircuitLibrary/AD620/analysis
deleted file mode 100644
index cf94dd7f..00000000
--- a/src/SubcircuitLibrary/AD620/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-03 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/lm_741-cache.lib b/src/SubcircuitLibrary/AD620/lm_741-cache.lib
deleted file mode 100644
index 6e908886..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741-cache.lib
+++ /dev/null
@@ -1,119 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20  -80 -30  80 -30 N
-P 2 0 1 20  -80 30  80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir b/src/SubcircuitLibrary/AD620/lm_741.cir
deleted file mode 100644
index b7989199..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741.cir
+++ /dev/null
@@ -1,43 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q6  Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP		
-Q5  Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP		
-Q3  Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
-Q4  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q9  Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q8  Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN		
-Q7  Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
-R1  Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k		
-R2  Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k		
-R3  Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k		
-Q12  Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
-Q13  Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-R4  Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k		
-R11  Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q11  Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q14  Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
-R8  Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k		
-R7  Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
-Q16  Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN		
-Q15  Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN		
-R5  Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k		
-R6  Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50		
-Q17  Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN		
-Q18  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN		
-Q20  Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN		
-R9  Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25		
-R10  Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50		
-Q19  Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP		
-U1  Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir.out b/src/SubcircuitLibrary/AD620/lm_741.cir.out
deleted file mode 100644
index 0184209e..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741.cir.out
+++ /dev/null
@@ -1,46 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1  net-_q7-pad3_ net-_q12-pad3_ 1k
-r2  net-_q3-pad3_ net-_q12-pad3_ 50k
-r3  net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4  net-_q13-pad3_ net-_q12-pad3_ 5k
-r11  net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5  net-_q15-pad2_ net-_q12-pad3_ 50k
-r6  net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9  net-_q18-pad3_ net-_q20-pad3_ 25
-r10  net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* u1  net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.pro b/src/SubcircuitLibrary/AD620/lm_741.pro
deleted file mode 100644
index d7d4217f..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=05/25/19 14:52:30
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/AD620/lm_741.sch b/src/SubcircuitLibrary/AD620/lm_741.sch
deleted file mode 100644
index 6a74cf22..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741.sch
+++ /dev/null
@@ -1,697 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:lm_741-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_NPN Q1
-U 1 1 5CE90A7B
-P 2650 2700
-F 0 "Q1" H 2550 2750 50  0000 R CNN
-F 1 "eSim_NPN" H 2600 2850 50  0000 R CNN
-F 2 "" H 2850 2800 29  0000 C CNN
-F 3 "" H 2650 2700 60  0000 C CNN
-	1    2650 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q2
-U 1 1 5CE90A7C
-P 4300 2700
-F 0 "Q2" H 4200 2750 50  0000 R CNN
-F 1 "eSim_NPN" H 4250 2850 50  0000 R CNN
-F 2 "" H 4500 2800 29  0000 C CNN
-F 3 "" H 4300 2700 60  0000 C CNN
-	1    4300 2700
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_PNP Q6
-U 1 1 5CE90A7D
-P 3000 3200
-F 0 "Q6" H 2900 3250 50  0000 R CNN
-F 1 "eSim_PNP" H 2950 3350 50  0000 R CNN
-F 2 "" H 3200 3300 29  0000 C CNN
-F 3 "" H 3000 3200 60  0000 C CNN
-	1    3000 3200
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q5
-U 1 1 5CE90A7E
-P 3950 3200
-F 0 "Q5" H 3850 3250 50  0000 R CNN
-F 1 "eSim_PNP" H 3900 3350 50  0000 R CNN
-F 2 "" H 4150 3300 29  0000 C CNN
-F 3 "" H 3950 3200 60  0000 C CNN
-	1    3950 3200
-	1    0    0    1   
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5CE90A7F
-P 3300 4000
-F 0 "Q3" H 3200 4050 50  0000 R CNN
-F 1 "eSim_NPN" H 3250 4150 50  0000 R CNN
-F 2 "" H 3500 4100 29  0000 C CNN
-F 3 "" H 3300 4000 60  0000 C CNN
-	1    3300 4000
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_PNP Q4
-U 1 1 5CE90A80
-P 3850 2000
-F 0 "Q4" H 3750 2050 50  0000 R CNN
-F 1 "eSim_PNP" H 3800 2150 50  0000 R CNN
-F 2 "" H 4050 2100 29  0000 C CNN
-F 3 "" H 3850 2000 60  0000 C CNN
-	1    3850 2000
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q9
-U 1 1 5CE90A81
-P 5200 2000
-F 0 "Q9" H 5100 2050 50  0000 R CNN
-F 1 "eSim_PNP" H 5150 2150 50  0000 R CNN
-F 2 "" H 5400 2100 29  0000 C CNN
-F 3 "" H 5200 2000 60  0000 C CNN
-	1    5200 2000
-	1    0    0    1   
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 5CE90A82
-P 3950 4600
-F 0 "Q8" H 3850 4650 50  0000 R CNN
-F 1 "eSim_NPN" H 3900 4750 50  0000 R CNN
-F 2 "" H 4150 4700 29  0000 C CNN
-F 3 "" H 3950 4600 60  0000 C CNN
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-	5    1850 4850
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-	2550 4850 2550 4900
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-	8    9600 6050
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diff --git a/src/SubcircuitLibrary/AD620/lm_741.sub b/src/SubcircuitLibrary/AD620/lm_741.sub
deleted file mode 100644
index 3842c902..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741.sub
+++ /dev/null
@@ -1,40 +0,0 @@
-* Subcircuit lm_741
-.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1  net-_q7-pad3_ net-_q12-pad3_ 1k
-r2  net-_q3-pad3_ net-_q12-pad3_ 50k
-r3  net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4  net-_q13-pad3_ net-_q12-pad3_ 5k
-r11  net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5  net-_q15-pad2_ net-_q12-pad3_ 50k
-r6  net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9  net-_q18-pad3_ net-_q20-pad3_ 25
-r10  net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* Control Statements
-
-.ends lm_741
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml
deleted file mode 100644
index b61322bb..00000000
--- a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/npn_1.lib b/src/SubcircuitLibrary/AD620/npn_1.lib
deleted file mode 100644
index 4a863e3e..00000000
--- a/src/SubcircuitLibrary/AD620/npn_1.lib
+++ /dev/null
@@ -1,29 +0,0 @@
-.model npn_1 NPN(
-+ Vtf=1.7 
-+ Cjc=0.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.5p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=500
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=125
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/AD620/pnp_1.lib b/src/SubcircuitLibrary/AD620/pnp_1.lib
deleted file mode 100644
index c486429f..00000000
--- a/src/SubcircuitLibrary/AD620/pnp_1.lib
+++ /dev/null
@@ -1,29 +0,0 @@
-.model pnp_1 PNP(
-+ Vtf=1.7 
-+ Cjc=1.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.3p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=250
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=25
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CA3096/CA3096-cache.lib b/src/SubcircuitLibrary/CA3096/CA3096-cache.lib
deleted file mode 100644
index 16f09ee3..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096-cache.lib
+++ /dev/null
@@ -1,83 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir b/src/SubcircuitLibrary/CA3096/CA3096.cir
deleted file mode 100644
index 5a3af0fb..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CA3096/CA3096.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 12:00:17 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q5  Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP		
-Q4  Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP		
-U1  Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_Q2-Pad2_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q4-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad1_ Net-_Q5-Pad3_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ ? PORT		
-Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
-
-.end
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir.out b/src/SubcircuitLibrary/CA3096/CA3096.cir.out
deleted file mode 100644
index 89c57845..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.cir.out
+++ /dev/null
@@ -1,19 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir
-
-.include PNP.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A
-* u1  net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? port
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.pro b/src/SubcircuitLibrary/CA3096/CA3096.pro
deleted file mode 100644
index d91a953f..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.pro
+++ /dev/null
@@ -1,82 +0,0 @@
-update=Sat Jun 22 11:58:40 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_Sources
-LibName38=eSim_Subckt
-LibName39=eSim_User
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sch b/src/SubcircuitLibrary/CA3096/CA3096.sch
deleted file mode 100644
index 3c08258c..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.sch
+++ /dev/null
@@ -1,328 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:CA3096-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
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-	1    4150 4250
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-$EndComp
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-$EndComp
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-$EndComp
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-Wire Wire Line
-	5200 4950 5900 4950
-Wire Wire Line
-	5500 4650 5900 4650
-Wire Wire Line
-	5200 4200 5900 4200
-Wire Wire Line
-	4050 4050 3200 4050
-$Comp
-L PORT U1
-U 7 1 5C9CB60F
-P 2950 5650
-F 0 "U1" H 3000 5750 30  0000 C CNN
-F 1 "PORT" H 2950 5650 30  0000 C CNN
-F 2 "" H 2950 5650 60  0000 C CNN
-F 3 "" H 2950 5650 60  0000 C CNN
-	7    2950 5650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9CB58F
-P 2950 4750
-F 0 "U1" H 3000 4850 30  0000 C CNN
-F 1 "PORT" H 2950 4750 30  0000 C CNN
-F 2 "" H 2950 4750 60  0000 C CNN
-F 3 "" H 2950 4750 60  0000 C CNN
-	4    2950 4750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9CB511
-P 2950 4050
-F 0 "U1" H 3000 4150 30  0000 C CNN
-F 1 "PORT" H 2950 4050 30  0000 C CNN
-F 2 "" H 2950 4050 60  0000 C CNN
-F 3 "" H 2950 4050 60  0000 C CNN
-	2    2950 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9CBE1D
-P 2950 5850
-F 0 "U1" H 3000 5950 30  0000 C CNN
-F 1 "PORT" H 2950 5850 30  0000 C CNN
-F 2 "" H 2950 5850 60  0000 C CNN
-F 3 "" H 2950 5850 60  0000 C CNN
-	8    2950 5850
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 16 1 5D0DDF9F
-P 6200 3950
-F 0 "U1" H 6250 4050 30  0000 C CNN
-F 1 "PORT" H 6200 3950 30  0000 C CNN
-F 2 "" H 6200 3950 60  0000 C CNN
-F 3 "" H 6200 3950 60  0000 C CNN
-	16   6200 3950
-	-1   0    0    1   
-$EndComp
-NoConn ~ 5950 3950
-$Comp
-L eSim_NPN Q3
-U 1 1 5C98F006
-P 4250 5850
-F 0 "Q3" H 4150 5900 50  0000 R CNN
-F 1 "eSim_NPN" H 4200 6000 50  0000 R CNN
-F 2 "" H 4450 5950 29  0000 C CNN
-F 3 "" H 4250 5850 60  0000 C CNN
-	1    4250 5850
-	1    0    0    1   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sub b/src/SubcircuitLibrary/CA3096/CA3096.sub
deleted file mode 100644
index f79667b7..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.sub
+++ /dev/null
@@ -1,13 +0,0 @@
-* Subcircuit CA3096
-.subckt CA3096 net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir
-.include PNP.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-* Control Statements
-
-.ends CA3096
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CA3096/CA3096.xml b/src/SubcircuitLibrary/CA3096/CA3096.xml
deleted file mode 100644
index 24f50baa..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096.xml
+++ /dev/null
@@ -1,191 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<export version="D">
-  <design>
-    <source>C:/esim_1/eSim/src/SubcircuitLibrary/CA3096/CA3096.sch</source>
-    <date>03/31/19 09:48:27</date>
-    <tool>Eeschema 4.0.2-stable</tool>
-    <sheet number="1" name="/" tstamps="/">
-      <title_block>
-        <title/>
-        <company/>
-        <rev/>
-        <date/>
-        <source>CA3096.sch</source>
-        <comment number="1" value=""/>
-        <comment number="2" value=""/>
-        <comment number="3" value=""/>
-        <comment number="4" value=""/>
-      </title_block>
-    </sheet>
-  </design>
-  <components>
-    <comp ref="Q1">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EEF5</tstamp>
-    </comp>
-    <comp ref="Q2">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EFC9</tstamp>
-    </comp>
-    <comp ref="Q3">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98F006</tstamp>
-    </comp>
-    <comp ref="Q5">
-      <value>eSim_PNP</value>
-      <libsource lib="eSim_Devices" part="eSim_PNP"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98F076</tstamp>
-    </comp>
-    <comp ref="Q4">
-      <value>eSim_PNP</value>
-      <libsource lib="eSim_Devices" part="eSim_PNP"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98F0A7</tstamp>
-    </comp>
-    <comp ref="U1">
-      <value>PORT</value>
-      <libsource lib="eSim_Miscellaneous" part="PORT"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98F1D4</tstamp>
-    </comp>
-  </components>
-  <libparts>
-    <libpart lib="eSim_Miscellaneous" part="PORT">
-      <fields>
-        <field name="Reference">U</field>
-        <field name="Value">PORT</field>
-      </fields>
-      <pins>
-        <pin num="1" name="~" type="input"/>
-        <pin num="2" name="~" type="input"/>
-        <pin num="3" name="~" type="input"/>
-        <pin num="4" name="~" type="input"/>
-        <pin num="5" name="~" type="input"/>
-        <pin num="6" name="~" type="input"/>
-        <pin num="7" name="~" type="input"/>
-        <pin num="8" name="~" type="input"/>
-        <pin num="9" name="~" type="input"/>
-        <pin num="10" name="~" type="input"/>
-        <pin num="11" name="~" type="input"/>
-        <pin num="12" name="~" type="input"/>
-        <pin num="13" name="~" type="input"/>
-        <pin num="14" name="~" type="input"/>
-        <pin num="15" name="~" type="input"/>
-        <pin num="16" name="~" type="input"/>
-        <pin num="17" name="~" type="input"/>
-        <pin num="18" name="~" type="input"/>
-        <pin num="19" name="~" type="input"/>
-        <pin num="20" name="~" type="input"/>
-        <pin num="21" name="~" type="input"/>
-        <pin num="22" name="~" type="input"/>
-        <pin num="23" name="~" type="input"/>
-        <pin num="24" name="~" type="input"/>
-        <pin num="25" name="~" type="input"/>
-        <pin num="26" name="~" type="input"/>
-      </pins>
-    </libpart>
-    <libpart lib="eSim_Devices" part="eSim_NPN">
-      <aliases>
-        <alias>BC547</alias>
-        <alias>Q2N2222</alias>
-      </aliases>
-      <fields>
-        <field name="Reference">Q</field>
-        <field name="Value">eSim_NPN</field>
-      </fields>
-      <pins>
-        <pin num="1" name="C" type="openCol"/>
-        <pin num="2" name="B" type="input"/>
-        <pin num="3" name="E" type="openEm"/>
-      </pins>
-    </libpart>
-    <libpart lib="eSim_Devices" part="eSim_PNP">
-      <fields>
-        <field name="Reference">Q</field>
-        <field name="Value">eSim_PNP</field>
-      </fields>
-      <pins>
-        <pin num="1" name="C" type="openCol"/>
-        <pin num="2" name="B" type="input"/>
-        <pin num="3" name="E" type="openEm"/>
-      </pins>
-    </libpart>
-  </libparts>
-  <libraries>
-    <library logical="eSim_Devices">
-      <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri>
-    </library>
-    <library logical="eSim_Miscellaneous">
-      <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri>
-    </library>
-  </libraries>
-  <nets>
-    <net code="1" name="Net-(Q5-Pad2)">
-      <node ref="U1" pin="11"/>
-      <node ref="Q5" pin="2"/>
-    </net>
-    <net code="2" name="Net-(Q2-Pad2)">
-      <node ref="U1" pin="5"/>
-      <node ref="Q2" pin="2"/>
-    </net>
-    <net code="3" name="Net-(Q3-Pad2)">
-      <node ref="U1" pin="8"/>
-      <node ref="Q3" pin="2"/>
-    </net>
-    <net code="4" name="Net-(Q4-Pad2)">
-      <node ref="U1" pin="14"/>
-      <node ref="Q4" pin="2"/>
-    </net>
-    <net code="5" name="Net-(Q1-Pad1)">
-      <node ref="U1" pin="3"/>
-      <node ref="Q1" pin="1"/>
-    </net>
-    <net code="6" name="Net-(Q2-Pad3)">
-      <node ref="Q2" pin="3"/>
-      <node ref="U1" pin="4"/>
-    </net>
-    <net code="7" name="Net-(Q3-Pad3)">
-      <node ref="Q3" pin="3"/>
-      <node ref="U1" pin="7"/>
-    </net>
-    <net code="8" name="Net-(Q3-Pad1)">
-      <node ref="U1" pin="9"/>
-      <node ref="Q3" pin="1"/>
-    </net>
-    <net code="9" name="Net-(Q5-Pad1)">
-      <node ref="U1" pin="12"/>
-      <node ref="Q5" pin="1"/>
-    </net>
-    <net code="10" name="Net-(Q1-Pad2)">
-      <node ref="U1" pin="1"/>
-      <node ref="Q1" pin="2"/>
-    </net>
-    <net code="11" name="Net-(Q1-Pad3)">
-      <node ref="U1" pin="2"/>
-      <node ref="Q1" pin="3"/>
-    </net>
-    <net code="12" name="Net-(Q2-Pad1)">
-      <node ref="Q2" pin="1"/>
-      <node ref="U1" pin="6"/>
-    </net>
-    <net code="13" name="Net-(Q5-Pad3)">
-      <node ref="Q5" pin="3"/>
-      <node ref="U1" pin="13"/>
-    </net>
-    <net code="14" name="Net-(Q4-Pad1)">
-      <node ref="U1" pin="15"/>
-      <node ref="Q4" pin="1"/>
-    </net>
-    <net code="15" name="Net-(Q4-Pad3)">
-      <node ref="Q4" pin="3"/>
-      <node ref="U1" pin="10"/>
-    </net>
-  </nets>
-</export>
diff --git a/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml b/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml
deleted file mode 100644
index 82a40fb6..00000000
--- a/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CA3096/D.lib b/src/SubcircuitLibrary/CA3096/D.lib
deleted file mode 100644
index 8a7fb4da..00000000
--- a/src/SubcircuitLibrary/CA3096/D.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
diff --git a/src/SubcircuitLibrary/CA3096/NPN.lib b/src/SubcircuitLibrary/CA3096/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/CA3096/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/CA3096/PNP.lib b/src/SubcircuitLibrary/CA3096/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/CA3096/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/CA3096/analysis b/src/SubcircuitLibrary/CA3096/analysis
deleted file mode 100644
index d5e13546..00000000
--- a/src/SubcircuitLibrary/CA3096/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib
deleted file mode 100644
index f7d63760..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib
+++ /dev/null
@@ -1,185 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Logic_adder
-#
-DEF Logic_adder X 0 40 Y Y 1 F N
-F0 "X" 0 -250 60 H V C CNN
-F1 "Logic_adder" 50 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -550 550 550 -600 0 1 0 N
-X IN1 1 -750 350 200 R 50 50 1 1 I
-X IN2 2 -750 -50 200 R 50 50 1 1 I
-X CIN 3 -750 -450 200 R 50 50 1 1 I
-X SUM 4 750 350 200 L 50 50 1 1 O
-X COUT 5 750 -300 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# MUX
-#
-DEF MUX X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "MUX" 0 100 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 350 250 -150 0 1 0 N
-X sel 1 0 550 200 D 50 50 1 1 I
-X a0 2 -500 150 200 R 50 50 1 1 I
-X a1 3 -500 -50 200 R 50 50 1 1 I
-X y 4 450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 75 50 H I C CNN
-F1 "PWR_FLAG" 0 150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
-ENDDRAW
-ENDDEF
-#
-# adc_bridge_1
-#
-DEF adc_bridge_1 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "adc_bridge_1" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -50 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X OUT1 2 550 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-# eSim_GND
-#
-DEF eSim_GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "eSim_GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir
deleted file mode 100644
index fee511ed..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir
+++ /dev/null
@@ -1,29 +0,0 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun  8 18:40:34 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_and		
-U5  Net-_U2-Pad2_ Net-_U2-Pad1_ Net-_U5-Pad3_ d_xor		
-U6  Net-_U2-Pad3_ Net-_U3-Pad1_ Net-_U6-Pad3_ d_xor		
-U7  Net-_U3-Pad3_ Net-_U7-Pad2_ Net-_U7-Pad3_ d_xor		
-U8  Net-_U3-Pad3_ Net-_U8-Pad2_ Net-_U8-Pad3_ d_xor		
-U4  Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
-X3  Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U9-Pad2_ Net-_U2-Pad2_ Net-_X1-Pad3_ Logic_adder		
-X1  Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_X1-Pad3_ Net-_U2-Pad1_ Net-_X1-Pad5_ Logic_adder		
-X2  Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_X1-Pad5_ Net-_U3-Pad1_ Net-_X2-Pad5_ Logic_adder		
-X4  Net-_U1-Pad4_ Net-_U1-Pad8_ Net-_X2-Pad5_ Net-_U7-Pad2_ Net-_U8-Pad2_ Logic_adder		
-X7  Net-_U1-Pad9_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad10_ MUX		
-X5  Net-_U1-Pad9_ Net-_U2-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad11_ MUX		
-X8  Net-_U1-Pad9_ Net-_U3-Pad1_ Net-_U6-Pad3_ Net-_U1-Pad12_ MUX		
-X6  Net-_U1-Pad9_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U1-Pad13_ MUX		
-X9  Net-_U1-Pad9_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U1-Pad14_ MUX		
-v1  Net-_U9-Pad1_ GND 0		
-U9  Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1		
-
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out
deleted file mode 100644
index 9bfd2402..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out
+++ /dev/null
@@ -1,56 +0,0 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir
-
-.include LOGIC_ADDER.sub
-.include MUX.sub
-* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and
-* u5  net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor
-* u6  net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor
-* u7  net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor
-* u8  net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor
-* u4  net-_u2-pad2_ net-_u4-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER
-x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER
-x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER
-x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER
-x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX
-x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX
-x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX
-x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX
-x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX
-v1  net-_u9-pad1_ gnd 0
-* u9  net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1
-a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5
-a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6
-a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7
-a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8
-a7 net-_u2-pad2_ net-_u4-pad2_ u4
-a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
-.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro
deleted file mode 100644
index a546f71d..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro
+++ /dev/null
@@ -1,46 +0,0 @@
-update=Sat Jun  8 13:24:24 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-LibName11=eSim_Subckt
-LibName12=power
-
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch
deleted file mode 100644
index e7eac906..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch
+++ /dev/null
@@ -1,654 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_PSpice
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:power
-LIBS:CSLA_BEC1_logic-cache
-EELAYER 25 0
-EELAYER END
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-F 2 "" H 800 2450 50  0001 C CNN
-F 3 "" H 800 2450 50  0001 C CNN
-	1    800  2450
-	1    0    0    -1  
-$EndComp
-$Comp
-L DC v1
-U 1 1 5CFBBABC
-P 1300 2300
-F 0 "v1" H 1100 2400 60  0000 C CNN
-F 1 "0" H 1100 2250 60  0000 C CNN
-F 2 "R1" H 1000 2300 60  0000 C CNN
-F 3 "" H 1300 2300 60  0000 C CNN
-	1    1300 2300
-	0    1    1    0   
-$EndComp
-$Comp
-L adc_bridge_1 U9
-U 1 1 5CFBB81E
-P 2500 2350
-F 0 "U9" H 2500 2350 60  0000 C CNN
-F 1 "adc_bridge_1" H 2500 2500 60  0000 C CNN
-F 2 "" H 2500 2350 60  0000 C CNN
-F 3 "" H 2500 2350 60  0000 C CNN
-	1    2500 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PWR_FLAG #FLG02
-U 1 1 5CFBBCDC
-P 750 2350
-F 0 "#FLG02" H 750 2425 50  0001 C CNN
-F 1 "PWR_FLAG" H 750 2500 50  0000 C CNN
-F 2 "" H 750 2350 50  0001 C CNN
-F 3 "" H 750 2350 50  0001 C CNN
-	1    750  2350
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	1750 2300 1900 2300
-Wire Wire Line
-	750  2400 850  2400
-Wire Wire Line
-	850  2300 850  2450
-Connection ~ 850  2400
-Wire Wire Line
-	850  2450 800  2450
-Wire Wire Line
-	750  2350 750  2400
-Wire Wire Line
-	3050 2300 3050 2100
-Wire Wire Line
-	3050 2100 3100 2100
-Connection ~ 6600 2100
-Connection ~ 6600 600 
-Wire Wire Line
-	6600 600  6600 5650
-Connection ~ 6600 3550
-Wire Wire Line
-	6600 2100 7450 2100
-Wire Wire Line
-	6600 3550 7500 3550
-Wire Wire Line
-	6600 4700 7450 4700
-Wire Wire Line
-	4600 3700 4550 3700
-Wire Wire Line
-	4700 2100 4650 2100
-Wire Wire Line
-	7050 6300 7050 6250
-Wire Wire Line
-	7050 6000 7050 6050
-Wire Wire Line
-	6950 5350 6950 5300
-Wire Wire Line
-	6950 5050 6950 5100
-Wire Wire Line
-	7000 4150 6900 4150
-Wire Wire Line
-	6900 3950 6900 3900
-Wire Wire Line
-	7000 3950 6900 3950
-Wire Wire Line
-	8150 4000 7950 4000
-Wire Wire Line
-	6950 3050 6850 3050
-Wire Wire Line
-	6950 3000 6950 3050
-Wire Wire Line
-	6950 2750 6950 2800
-Wire Wire Line
-	6950 1550 6900 1550
-Wire Wire Line
-	6950 1500 6950 1550
-Wire Wire Line
-	7000 1500 6950 1500
-Wire Wire Line
-	7000 1250 6900 1250
-Wire Wire Line
-	7000 1300 7000 1250
-Wire Wire Line
-	4500 3550 4600 3550
-Wire Wire Line
-	4700 6550 4600 6550
-Wire Wire Line
-	4550 5100 4650 5100
-Wire Wire Line
-	4700 1950 4600 1950
-Wire Wire Line
-	6600 5650 7550 5650
-Wire Wire Line
-	5400 6000 7050 6000
-Wire Wire Line
-	5350 5050 6950 5050
-Wire Wire Line
-	5350 5900 5350 5050
-Wire Wire Line
-	6400 5350 6950 5350
-Wire Wire Line
-	6400 5200 6400 5350
-Wire Wire Line
-	6650 6650 6650 6300
-Wire Wire Line
-	5400 6700 5400 6000
-Wire Wire Line
-	6900 3900 5350 3900
-Wire Wire Line
-	6900 4150 6900 4400
-Wire Wire Line
-	6900 4400 6250 4400
-Connection ~ 5200 2900
-Wire Wire Line
-	5200 2900 5200 2600
-Wire Wire Line
-	5200 2600 6350 2600
-Wire Wire Line
-	6350 2600 6350 2750
-Wire Wire Line
-	6350 2750 6950 2750
-Wire Wire Line
-	6850 3050 6850 2850
-Wire Wire Line
-	6850 2850 6200 2850
-Wire Wire Line
-	4550 4450 5350 4450
-Wire Wire Line
-	4600 1300 5300 1300
-Wire Wire Line
-	4500 2900 5300 2900
-Wire Wire Line
-	4700 1950 4700 2100
-Wire Wire Line
-	4600 3550 4600 3700
-Wire Wire Line
-	4650 5250 4600 5250
-Wire Wire Line
-	4650 5100 4650 5250
-Wire Wire Line
-	4600 5900 5450 5900
-Wire Wire Line
-	4700 6700 5450 6700
-Wire Wire Line
-	4700 6550 4700 6700
-Wire Wire Line
-	2200 1300 3100 1300
-Wire Wire Line
-	2200 1700 3100 1700
-Wire Wire Line
-	2700 2100 2700 600 
-Wire Wire Line
-	2550 3300 3000 3300
-Wire Wire Line
-	2400 2900 3000 2900
-Wire Wire Line
-	2200 2100 2700 2100
-Wire Wire Line
-	8000 6100 8450 6100
-Wire Wire Line
-	8450 6100 8450 3800
-Wire Wire Line
-	8300 3500 8450 3500
-Wire Wire Line
-	8300 5150 8300 3500
-Wire Wire Line
-	7900 5150 8300 5150
-Wire Wire Line
-	8150 3200 8450 3200
-Wire Wire Line
-	8300 2600 8450 2600
-Wire Wire Line
-	8300 2850 8300 2600
-Wire Wire Line
-	7900 2850 8300 2850
-Wire Wire Line
-	8450 1350 8450 2250
-Wire Wire Line
-	7950 1350 8450 1350
-Wire Wire Line
-	8150 3200 8150 4000
-Wire Wire Line
-	6650 6300 7050 6300
-Wire Wire Line
-	5350 4450 5350 3900
-Wire Wire Line
-	7450 2100 7450 2400
-Wire Wire Line
-	6900 1550 6900 1300
-Wire Wire Line
-	6900 1300 5900 1300
-Wire Wire Line
-	6900 1250 6900 1050
-Wire Wire Line
-	7500 600  7500 900 
-Wire Wire Line
-	6350 5200 6400 5200
-Wire Wire Line
-	2700 600  7500 600 
-Wire Wire Line
-	2250 5900 3100 5900
-Wire Wire Line
-	2550 6300 3100 6300
-Wire Wire Line
-	2400 4850 3050 4850
-Wire Wire Line
-	2150 4450 3050 4450
-Wire Wire Line
-	5450 5900 5450 5250
-Wire Wire Line
-	5400 5150 5450 5150
-Wire Wire Line
-	5400 5800 5400 5150
-Wire Wire Line
-	6350 6650 6650 6650
-Connection ~ 5350 5900
-Connection ~ 5400 6700
-Wire Wire Line
-	4900 6600 5450 6600
-Wire Wire Line
-	4900 5800 4900 6600
-Wire Wire Line
-	4900 5800 5400 5800
-Connection ~ 4950 4450
-Wire Wire Line
-	4950 4450 4950 4900
-Wire Wire Line
-	4850 3950 4850 4900
-Wire Wire Line
-	2800 6700 3100 6700
-Wire Wire Line
-	2800 5600 2800 6700
-Wire Wire Line
-	4600 5600 2800 5600
-Wire Wire Line
-	4600 5250 4600 5600
-Wire Wire Line
-	2750 5250 3050 5250
-Wire Wire Line
-	2750 4100 2750 5250
-Wire Wire Line
-	4550 4100 2750 4100
-Wire Wire Line
-	4550 3700 4550 4100
-Connection ~ 4850 4350
-Wire Wire Line
-	4850 4350 5350 4350
-Connection ~ 4900 2900
-Wire Wire Line
-	4900 2900 4900 3050
-Connection ~ 4800 2750
-Wire Wire Line
-	5300 2750 5300 2800
-Wire Wire Line
-	4800 2750 5300 2750
-Connection ~ 4800 1300
-Wire Wire Line
-	4800 1300 4800 3050
-Wire Wire Line
-	2700 3700 3000 3700
-Wire Wire Line
-	2700 2500 2700 3700
-Wire Wire Line
-	4650 2500 2700 2500
-Wire Wire Line
-	4650 2100 4650 2500
-Wire Wire Line
-	6900 1050 5300 1050
-Wire Wire Line
-	5300 1050 5300 1300
-Connection ~ 6600 4700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub
deleted file mode 100644
index fd844be7..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub
+++ /dev/null
@@ -1,50 +0,0 @@
-* Subcircuit CSLA_BEC1_logic
-.subckt CSLA_BEC1_logic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir
-.include LOGIC_ADDER.sub
-.include MUX.sub
-* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and
-* u5  net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor
-* u6  net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor
-* u7  net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor
-* u8  net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor
-* u4  net-_u2-pad2_ net-_u4-pad2_ d_inverter
-x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER
-x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER
-x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER
-x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER
-x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX
-x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX
-x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX
-x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX
-x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX
-v1  net-_u9-pad1_ gnd 0
-* u9  net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1
-a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5
-a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6
-a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7
-a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8
-a7 net-_u2-pad2_ net-_u4-pad2_ u4
-a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
-.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
-* Control Statements
-
-.ends CSLA_BEC1_logic
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml
deleted file mode 100644
index 55dd75da..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">0</v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u4><u9 name="type">adc_bridge<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter value for in_high (default=2.0)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter value for in_low (default=1.0)" /></u9></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x9><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib
deleted file mode 100644
index 34588988..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib
+++ /dev/null
@@ -1,82 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir
deleted file mode 100644
index ec177d39..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  A B Net-_U2-Pad3_ d_and		
-U4  Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and		
-U3  A B Net-_U3-Pad3_ d_xor		
-U5  Net-_U3-Pad3_ CIN SUM d_xor		
-U6  Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or		
-U1  A B CIN SUM CARRY PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out
deleted file mode 100644
index df9bcde6..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out
+++ /dev/null
@@ -1,32 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-
-* u2  a b net-_u2-pad3_ d_and
-* u4  net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3  a b net-_u3-pad3_ d_xor
-* u5  net-_u3-pad3_ cin sum d_xor
-* u6  net-_u2-pad3_ net-_u4-pad3_ carry d_or
-* u1  a b cin sum carry port
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro
deleted file mode 100644
index a2b9fa1f..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Sat Jun  8 13:01:54 2019
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-LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch
deleted file mode 100644
index d39a1b78..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch
+++ /dev/null
@@ -1,245 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
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-LIBS:microcontrollers
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-LIBS:analog_switches
-LIBS:motorola
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-LIBS:intel
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-LIBS:digital-audio
-LIBS:philips
-LIBS:display
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-LIBS:siliconi
-LIBS:opto
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-LIBS:contrib
-LIBS:valves
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-U 1 1 5AB6498F
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-$EndComp
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-U 1 1 5AB64A11
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-$EndComp
-$Comp
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-F 3 "" H 2650 2100 60  0000 C CNN
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-L PORT U1
-U 2 1 5AB64BE9
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-$EndComp
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-$EndComp
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-$EndComp
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-L PORT U1
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diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub
deleted file mode 100644
index a1e1cfac..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub
+++ /dev/null
@@ -1,26 +0,0 @@
-* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry 
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2  a b net-_u2-pad3_ d_and
-* u4  net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3  a b net-_u3-pad3_ d_xor
-* u5  net-_u3-pad3_ cin sum d_xor
-* u6  net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml
deleted file mode 100644
index ab59f216..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib
deleted file mode 100644
index 9fa4b3f9..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib
+++ /dev/null
@@ -1,76 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0  -100 50  -100 -50  100 0  -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir
deleted file mode 100644
index 8d97f9a1..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir
+++ /dev/null
@@ -1,15 +0,0 @@
-* C:\eSim\eSim\src\SubcircuitLibrary\MUX\MUX.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:29:10 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and		
-U4  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U5  Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out
deleted file mode 100644
index 342293e7..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out
+++ /dev/null
@@ -1,28 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
-
-* u3  net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
-* u4  net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u5  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
-a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
-a4 net-_u1-pad1_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro
deleted file mode 100644
index 07f53b67..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro
+++ /dev/null
@@ -1,43 +0,0 @@
-update=Sat Jun  8 12:53:13 2019
-version=1
-last_client=eeschema
-[general]
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-BoardNm=
-[pcbnew]
-version=1
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-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
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-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
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-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
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diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch
deleted file mode 100644
index eb095e0e..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch
+++ /dev/null
@@ -1,172 +0,0 @@
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diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub
deleted file mode 100644
index 473dc907..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub
+++ /dev/null
@@ -1,22 +0,0 @@
-* Subcircuit MUX
-.subckt MUX net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
-* u3  net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
-* u4  net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u5  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
-a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
-a4 net-_u1-pad1_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends MUX
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml
deleted file mode 100644
index 6f43d20b..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u2 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/IB3858/IB3858-cache.lib b/src/SubcircuitLibrary/IB3858/IB3858-cache.lib
deleted file mode 100644
index df4966f4..00000000
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+++ /dev/null
@@ -1,79 +0,0 @@
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- C_*
-$ENDFPLIST
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-F2 "" 1950 550 60 V V C CNN
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-F0 "R" 50 130 50 H V C CNN
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diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir b/src/SubcircuitLibrary/IB3858/IB3858.cir
deleted file mode 100644
index e89f69e1..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/IB3858/IB3858.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 24 16:30:15 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1  Net-_R1-Pad1_ Net-_L1-Pad1_ 5.2		
-L1  Net-_L1-Pad1_ Net-_C1-Pad1_ 3.08m		
-L2  Net-_C1-Pad1_ Net-_C1-Pad2_ 61.100458m		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 896.8481u		
-R2  Net-_C1-Pad1_ Net-_C1-Pad2_ 73.6254		
-U1  Net-_R1-Pad1_ Net-_C1-Pad2_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir.out b/src/SubcircuitLibrary/IB3858/IB3858.cir.out
deleted file mode 100644
index 3b84dfd6..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858.cir.out
+++ /dev/null
@@ -1,17 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir
-
-r1  net-_r1-pad1_ net-_l1-pad1_ 5.2
-l1  net-_l1-pad1_ net-_c1-pad1_ 3.08m
-l2  net-_c1-pad1_ net-_c1-pad2_ 61.100458m
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-* u1  net-_r1-pad1_ net-_c1-pad2_ port
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/IB3858/IB3858.pro b/src/SubcircuitLibrary/IB3858/IB3858.pro
deleted file mode 100644
index 148e9ed5..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858.pro
+++ /dev/null
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diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sch b/src/SubcircuitLibrary/IB3858/IB3858.sch
deleted file mode 100644
index bbc79e75..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858.sch
+++ /dev/null
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-$EndComp
-Wire Wire Line
-	5950 3100 5500 3100
-Connection ~ 7350 4350
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sub b/src/SubcircuitLibrary/IB3858/IB3858.sub
deleted file mode 100644
index cc9a9809..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858.sub
+++ /dev/null
@@ -1,11 +0,0 @@
-* Subcircuit IB3858
-.subckt IB3858 net-_r1-pad1_ net-_c1-pad2_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir
-r1  net-_r1-pad1_ net-_l1-pad1_ 5.2
-l1  net-_l1-pad1_ net-_c1-pad1_ 3.08m
-l2  net-_c1-pad1_ net-_c1-pad2_ 61.100458m
-c1  net-_c1-pad1_ net-_c1-pad2_ 896.8481u
-r2  net-_c1-pad1_ net-_c1-pad2_ 73.6254
-* Control Statements
-
-.ends IB3858
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml b/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml
deleted file mode 100644
index 56ce5d3f..00000000
--- a/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/IB3858/analysis b/src/SubcircuitLibrary/IB3858/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/IB3858/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib
deleted file mode 100644
index cc25b0c9..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib
+++ /dev/null
@@ -1,146 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 w
-X - 2 0 -450 300 U 50 50 1 1 w
-ENDDRAW
-ENDDEF
-#
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_MOS_N
-#
-DEF eSim_MOS_N M 0 0 Y N 1 F N
-F0 "M" 0 -150 50 H V R CNN
-F1 "eSim_MOS_N" 100 -50 50 H V R CNN
-F2 "" 300 -300 29 H V C CNN
-F3 "" 100 -200 60 H V C CNN
-DRAW
-C 150 -200 111 0 1 10 N
-P 2 0 1 10 130 -290 130 -250 N
-P 2 0 1 0 130 -270 200 -270 N
-P 2 0 1 10 130 -220 130 -180 N
-P 2 0 1 0 130 -200 200 -200 N
-P 2 0 1 10 130 -150 130 -110 N
-P 2 0 1 0 130 -130 200 -130 N
-P 2 0 1 0 200 -300 200 -270 N
-P 2 0 1 0 200 -130 200 -100 N
-P 3 0 1 10 110 -275 110 -125 110 -125 N
-P 3 0 1 0 200 -200 300 -200 300 -250 N
-P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
-X D 1 200 0 100 D 50 50 1 1 P
-X G 2 -100 -200 210 R 50 50 1 1 P
-X S 3 200 -400 100 U 50 50 1 1 P
-X B 4 300 -350 98 U 47 47 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_MOS_P
-#
-DEF eSim_MOS_P M 0 0 Y N 1 F N
-F0 "M" -50 50 50 H V R CNN
-F1 "eSim_MOS_P" 50 150 50 H V R CNN
-F2 "" 250 100 29 H V C CNN
-F3 "" 50 0 60 H V C CNN
-DRAW
-C 100 0 111 0 1 10 N
-P 2 0 1 0 80 -70 150 -70 N
-P 2 0 1 10 80 -50 80 -90 N
-P 2 0 1 0 80 0 150 0 N
-P 2 0 1 10 80 20 80 -20 N
-P 2 0 1 0 80 70 150 70 N
-P 2 0 1 10 80 90 80 50 N
-P 2 0 1 0 150 -70 150 -100 N
-P 2 0 1 0 150 100 150 70 N
-P 3 0 1 10 60 75 60 -75 60 -75 N
-P 3 0 1 0 150 0 250 0 250 -50 N
-P 4 0 1 0 140 0 100 -15 100 15 140 0 F
-X D 1 150 200 100 D 50 50 1 1 P
-X G 2 -150 0 210 R 50 50 1 1 P
-X S 3 150 -200 100 U 50 50 1 1 P
-X B 4 250 -150 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
deleted file mode 100644
index 44f1df81..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
+++ /dev/null
@@ -1,15 +0,0 @@
-* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U1  Net-_M1-Pad2_ Net-_C1-Pad1_ PORT		
-M1  Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
-M2  Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P		
-v1  Net-_M2-Pad1_ GND 5		
-C1  Net-_C1-Pad1_ GND 1u		
-
-.end
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out
deleted file mode 100644
index cb2b6641..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
-
-.include NMOS-180nm.lib
-.include PMOS-180nm.lib
-* u1  net-_m1-pad2_ net-_c1-pad1_ port
-m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
-m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
-v1  net-_m2-pad1_ gnd 5
-c1  net-_c1-pad1_ gnd 1u
-.tran 0e-03 0e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro
deleted file mode 100644
index b3f410b6..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro
+++ /dev/null
@@ -1,73 +0,0 @@
-update=Sun Aug 25 15:54:56 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_User
-LibName37=eSim_Plot
-LibName38=eSim_PSpice
-LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch
deleted file mode 100644
index 13a7fc09..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch
+++ /dev/null
@@ -1,189 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:eSim_Subckt
-LIBS:INVCMOS-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "29 apr 2015"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
-	5900 4000 5900 4150
-Connection ~ 5800 2450
-Connection ~ 5800 4150
-Wire Wire Line
-	5900 4150 5800 4150
-Connection ~ 5050 3350
-Wire Wire Line
-	4000 3350 5050 3350
-Wire Wire Line
-	5050 3850 5500 3850
-Wire Wire Line
-	5050 2700 5050 3850
-Wire Wire Line
-	5050 2700 5500 2700
-Wire Wire Line
-	5800 3650 5800 2900
-Wire Wire Line
-	5800 2500 5800 2300
-Connection ~ 4200 3350
-$Comp
-L PORT U1
-U 1 1 5D6263BC
-P 3750 3350
-F 0 "U1" H 3800 3450 30  0000 C CNN
-F 1 "PORT" H 3750 3350 30  0000 C CNN
-F 2 "" H 3750 3350 60  0000 C CNN
-F 3 "" H 3750 3350 60  0000 C CNN
-	1    3750 3350
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6050 3250 5800 3250
-Connection ~ 5800 3250
-Wire Wire Line
-	5800 4050 5800 4550
-$Comp
-L eSim_MOS_N M1
-U 1 1 5D6265DB
-P 5600 3650
-F 0 "M1" H 5600 3500 50  0000 R CNN
-F 1 "eSim_MOS_N" H 5700 3600 50  0000 R CNN
-F 2 "" H 5900 3350 29  0000 C CNN
-F 3 "" H 5700 3450 60  0000 C CNN
-	1    5600 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_MOS_P M2
-U 1 1 5D626659
-P 5650 2700
-F 0 "M2" H 5600 2750 50  0000 R CNN
-F 1 "eSim_MOS_P" H 5700 2850 50  0000 R CNN
-F 2 "" H 5900 2800 29  0000 C CNN
-F 3 "" H 5700 2700 60  0000 C CNN
-	1    5650 2700
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5900 2850 6050 2850
-Wire Wire Line
-	6050 2850 6050 2450
-Wire Wire Line
-	6050 2450 5800 2450
-Connection ~ 6000 3250
-Connection ~ 5800 4300
-$Comp
-L GND #PWR1
-U 1 1 5D626C59
-P 5800 4550
-F 0 "#PWR1" H 5800 4300 50  0001 C CNN
-F 1 "GND" H 5800 4400 50  0000 C CNN
-F 2 "" H 5800 4550 50  0001 C CNN
-F 3 "" H 5800 4550 50  0001 C CNN
-	1    5800 4550
-	1    0    0    -1  
-$EndComp
-$Comp
-L DC v1
-U 1 1 5D626C7F
-P 6250 2300
-F 0 "v1" H 6050 2400 60  0000 C CNN
-F 1 "5" H 6050 2250 60  0000 C CNN
-F 2 "R1" H 5950 2300 60  0000 C CNN
-F 3 "" H 6250 2300 60  0000 C CNN
-	1    6250 2300
-	0    -1   -1   0   
-$EndComp
-$Comp
-L GND #PWR2
-U 1 1 5D626CF6
-P 6850 2300
-F 0 "#PWR2" H 6850 2050 50  0001 C CNN
-F 1 "GND" H 6850 2150 50  0000 C CNN
-F 2 "" H 6850 2300 50  0001 C CNN
-F 3 "" H 6850 2300 50  0001 C CNN
-	1    6850 2300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6850 2300 6700 2300
-$Comp
-L PORT U1
-U 2 1 5D626DCB
-P 6300 3250
-F 0 "U1" H 6350 3350 30  0000 C CNN
-F 1 "PORT" H 6300 3250 30  0000 C CNN
-F 2 "" H 6300 3250 60  0000 C CNN
-F 3 "" H 6300 3250 60  0000 C CNN
-	2    6300 3250
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_C C1
-U 1 1 5D62796C
-P 6050 3850
-F 0 "C1" H 6075 3950 50  0000 L CNN
-F 1 "1u" H 6075 3750 50  0000 L CNN
-F 2 "" H 6088 3700 30  0000 C CNN
-F 3 "" H 6050 3850 60  0000 C CNN
-	1    6050 3850
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6050 3700 6050 3400
-Wire Wire Line
-	6050 3400 6000 3400
-Wire Wire Line
-	6000 3400 6000 3250
-Wire Wire Line
-	6050 4000 6050 4300
-Wire Wire Line
-	6050 4300 5800 4300
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub
deleted file mode 100644
index 2319995c..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit INVCMOS
-.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ 
-* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
-.include NMOS-180nm.lib
-.include PMOS-180nm.lib
-m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
-m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
-v1  net-_m2-pad1_ gnd 5
-c1  net-_c1-pad1_ gnd 1u
-* Control Statements
-
-.ends INVCMOS
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml
deleted file mode 100644
index e5bb98c7..00000000
--- a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib
deleted file mode 100644
index 51e9b119..00000000
--- a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib
+++ /dev/null
@@ -1,13 +0,0 @@
-.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
-+            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
-+            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
-+            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
-+            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
-+            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
-+            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
-+            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
-+            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
-+            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
-+            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
-+            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
-+            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib
deleted file mode 100644
index 032b5b95..00000000
--- a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
-+            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
-+            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
-+            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
-+            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
-+            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
-+            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
-+            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
-+            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
-+            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
-+            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/SubcircuitLibrary/INVCMOS/analysis b/src/SubcircuitLibrary/INVCMOS/analysis
deleted file mode 100644
index 334c5333..00000000
--- a/src/SubcircuitLibrary/INVCMOS/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-03 0e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM108/LM108-cache.lib b/src/SubcircuitLibrary/LM108/LM108-cache.lib
deleted file mode 100644
index 1d0c038e..00000000
--- a/src/SubcircuitLibrary/LM108/LM108-cache.lib
+++ /dev/null
@@ -1,120 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# eSim_NJF
-#
-DEF eSim_NJF J 0 0 Y N 1 F N
-F0 "J" -100 50 50 H V R CNN
-F1 "eSim_NJF" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 3 0 1 10  10 75  10 -75  10 -75 N
-P 3 0 1 0  100 -100  100 -50  10 -50 N
-P 3 0 1 0  100 100  100 55  10 55 N
-P 4 0 1 0  0 0  -40 15  -40 -15  0 0 F
-X D 1 100 200 100 D 50 50 1 1 C
-X G 2 -200 0 210 R 50 50 1 1 I
-X S 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM108/LM108.cir b/src/SubcircuitLibrary/LM108/LM108.cir
deleted file mode 100644
index f8d793b5..00000000
--- a/src/SubcircuitLibrary/LM108/LM108.cir
+++ /dev/null
@@ -1,59 +0,0 @@
-* C:\esim_1\eSim\src\SubcircuitLibrary\LM108\LM108.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 16:57:39
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R2  v+ Net-_Q2-Pad3_ 20k		
-Q2  Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q2-Pad3_ eSim_PNP		
-Q5  Net-_Q13-Pad1_ Net-_Q2-Pad1_ Net-_Q11-Pad3_ eSim_PNP		
-Q3  Net-_Q2-Pad1_ Net-_Q14-Pad1_ Net-_Q1-Pad1_ eSim_NPN		
-Q7  CompensationA Net-_Q14-Pad1_ Net-_Q7-Pad3_ eSim_NPN		
-Q9  CompensationA CompensationA Net-_Q9-Pad3_ eSim_PNP		
-Q11  Net-_Q11-Pad1_ CompensationA Net-_Q11-Pad3_ eSim_PNP		
-R3  v+ Net-_Q9-Pad3_ 20K		
-R7  v+ Net-_Q11-Pad3_ 10K		
-Q1  Net-_Q1-Pad1_ Input- Net-_Q1-Pad3_ eSim_NPN		
-Q4  Net-_Q4-Pad1_ Input+ Input- eSim_NPN		
-Q6  Net-_Q4-Pad1_ Input- Input+ eSim_NPN		
-R1  Net-_Q1-Pad3_ Net-_Q10-Pad1_ 2K		
-R5  Net-_Q4-Pad1_ Net-_Q12-Pad3_ 50K		
-Q8  Net-_Q7-Pad3_ Input+ Net-_Q8-Pad3_ eSim_NPN		
-R8  v+ Net-_Q15-Pad3_ 10K		
-Q15  Net-_Q14-Pad1_ Net-_J1-Pad3_ Net-_Q15-Pad3_ eSim_PNP		
-R12  CompensationB Net-_Q11-Pad1_ 5.6k		
-Q13  Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-Q17  Net-_Q11-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-Q14  Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
-R4  Net-_Q8-Pad3_ Net-_Q10-Pad1_ 2k		
-Q12  V- Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_PNP		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
-Q18  Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q18-Pad3_ eSim_NPN		
-J1  Net-_J1-Pad1_ V- Net-_J1-Pad3_ eSim_NJF		
-R13  Net-_J1-Pad1_ Net-_Q16-Pad2_ 940		
-R14  Net-_Q18-Pad3_ Net-_Q24-Pad2_ 20k		
-Q24  Net-_Q13-Pad3_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_NPN		
-R6  Net-_Q10-Pad3_ Net-_R10-Pad1_ 6.4K		
-R9  Net-_Q10-Pad2_ Net-_R10-Pad1_ 60K		
-R11  Net-_Q18-Pad3_ Net-_Q19-Pad3_ 20K		
-R10  Net-_R10-Pad1_ Net-_Q19-Pad3_ 500		
-R15  Net-_Q19-Pad3_ V- 1K		
-Q19  Net-_Q16-Pad2_ Net-_Q18-Pad3_ Net-_Q19-Pad3_ eSim_NPN		
-R17  Net-_Q24-Pad3_ V- 820		
-Q21  v+ Net-_J1-Pad3_ Net-_Q20-Pad1_ eSim_NPN		
-Q20  Net-_Q20-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-R16  Net-_J1-Pad3_ Net-_Q23-Pad1_ 2K		
-Q23  Net-_Q23-Pad1_ Net-_J1-Pad3_ Net-_Q22-Pad3_ eSim_NPN		
-Q26  v+ Net-_Q23-Pad1_ Net-_Q25-Pad2_ eSim_NPN		
-Q25  Net-_Q23-Pad1_ Net-_Q25-Pad2_ Output eSim_NPN		
-Q22  V- Net-_Q13-Pad3_ Net-_Q22-Pad3_ eSim_PNP		
-Q27  V- Net-_Q13-Pad3_ Net-_Q27-Pad3_ eSim_PNP		
-R18  Net-_Q25-Pad2_ Net-_Q27-Pad3_ 240		
-R19  Net-_Q25-Pad2_ Output 90		
-U1  CompensationA Input+ Input- V- Output v+ CompensationB PORT		
-Q29  Net-_J1-Pad3_ Net-_J1-Pad3_ v+ eSim_PNP		
-Q16  Net-_J1-Pad3_ Net-_Q16-Pad2_ Net-_Q10-Pad2_ eSim_NPN		
-
-.end
diff --git a/src/SubcircuitLibrary/LM108/LM108.cir.out b/src/SubcircuitLibrary/LM108/LM108.cir.out
deleted file mode 100644
index 6e2ff4a1..00000000
--- a/src/SubcircuitLibrary/LM108/LM108.cir.out
+++ /dev/null
@@ -1,63 +0,0 @@
-* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir
-
-.include PNP.lib
-.include NJF.lib
-.include NPN.lib
-r2  v+ net-_q2-pad3_ 20k
-q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A
-q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A
-q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222
-q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222
-q9 compensationa compensationa net-_q9-pad3_ Q2N2907A
-q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A
-r3  v+ net-_q9-pad3_ 20k
-r7  v+ net-_q11-pad3_ 10k
-q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222
-q4 net-_q4-pad1_ input+ input- Q2N2222
-q6 net-_q4-pad1_ input- input+ Q2N2222
-r1  net-_q1-pad3_ net-_q10-pad1_ 2k
-r5  net-_q4-pad1_ net-_q12-pad3_ 50k
-q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222
-r8  v+ net-_q15-pad3_ 10k
-q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A
-r12  compensationb net-_q11-pad1_ 5.6k
-q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222
-r4  net-_q8-pad3_ net-_q10-pad1_ 2k
-q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222
-j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819
-r13  net-_j1-pad1_ net-_q16-pad2_ 940
-r14  net-_q18-pad3_ net-_q24-pad2_ 20k
-q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222
-r6  net-_q10-pad3_ net-_r10-pad1_ 6.4k
-r9  net-_q10-pad2_ net-_r10-pad1_ 60k
-r11  net-_q18-pad3_ net-_q19-pad3_ 20k
-r10  net-_r10-pad1_ net-_q19-pad3_ 500
-r15  net-_q19-pad3_ v- 1k
-q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222
-r17  net-_q24-pad3_ v- 820
-q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222
-q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-r16  net-_j1-pad3_ net-_q23-pad1_ 2k
-q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222
-q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222
-q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222
-q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A
-q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A
-r18  net-_q25-pad2_ net-_q27-pad3_ 240
-r19  net-_q25-pad2_ output 90
-* u1  compensationa input+ input- v- output v+ compensationb port
-q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A
-q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM108/LM108.pro b/src/SubcircuitLibrary/LM108/LM108.pro
deleted file mode 100644
index c76222d6..00000000
--- a/src/SubcircuitLibrary/LM108/LM108.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=03/31/19 17:48:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Program Files (x86)/KiCad/share/library
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_User
-LibName40=eSim_Subckt
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Spice
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/LM108/LM108.sch b/src/SubcircuitLibrary/LM108/LM108.sch
deleted file mode 100644
index a9735ce5..00000000
--- a/src/SubcircuitLibrary/LM108/LM108.sch
+++ /dev/null
@@ -1,1013 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:LM108-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_R R2
-U 1 1 5C9DB838
-P 2750 1400
-F 0 "R2" H 2800 1530 50  0000 C CNN
-F 1 "20k" H 2800 1450 50  0000 C CNN
-F 2 "" H 2800 1380 30  0000 C CNN
-F 3 "" V 2800 1450 30  0000 C CNN
-	1    2750 1400
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_PNP Q2
-U 1 1 5C9DB867
-P 2900 1975
-F 0 "Q2" H 2800 2025 50  0000 R CNN
-F 1 "eSim_PNP" H 2850 2125 50  0000 R CNN
-F 2 "" H 3100 2075 29  0000 C CNN
-F 3 "" H 2900 1975 60  0000 C CNN
-	1    2900 1975
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q5
-U 1 1 5C9DB8A6
-P 3350 1975
-F 0 "Q5" H 3250 2025 50  0000 R CNN
-F 1 "eSim_PNP" H 3300 2125 50  0000 R CNN
-F 2 "" H 3550 2075 29  0000 C CNN
-F 3 "" H 3350 1975 60  0000 C CNN
-	1    3350 1975
-	1    0    0    1   
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5C9DB912
-P 2900 2625
-F 0 "Q3" H 2800 2675 50  0000 R CNN
-F 1 "eSim_NPN" H 2850 2775 50  0000 R CNN
-F 2 "" H 3100 2725 29  0000 C CNN
-F 3 "" H 2900 2625 60  0000 C CNN
-	1    2900 2625
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5C9DB94B
-P 3600 2625
-F 0 "Q7" H 3500 2675 50  0000 R CNN
-F 1 "eSim_NPN" H 3550 2775 50  0000 R CNN
-F 2 "" H 3800 2725 29  0000 C CNN
-F 3 "" H 3600 2625 60  0000 C CNN
-	1    3600 2625
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_PNP Q9
-U 1 1 5C9DB994
-P 3800 2075
-F 0 "Q9" H 3700 2125 50  0000 R CNN
-F 1 "eSim_PNP" H 3750 2225 50  0000 R CNN
-F 2 "" H 4000 2175 29  0000 C CNN
-F 3 "" H 3800 2075 60  0000 C CNN
-	1    3800 2075
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q11
-U 1 1 5C9DB9EF
-P 4275 2075
-F 0 "Q11" H 4175 2125 50  0000 R CNN
-F 1 "eSim_PNP" H 4225 2225 50  0000 R CNN
-F 2 "" H 4475 2175 29  0000 C CNN
-F 3 "" H 4275 2075 60  0000 C CNN
-	1    4275 2075
-	1    0    0    1   
-$EndComp
-Wire Wire Line
-	2800 1600 2800 1775
-Wire Wire Line
-	3100 1975 3150 1975
-Wire Wire Line
-	3125 1975 3125 2225
-Wire Wire Line
-	3125 2225 2800 2225
-Wire Wire Line
-	2800 2175 2800 2425
-Connection ~ 3125 1975
-Wire Wire Line
-	4000 2075 4075 2075
-Wire Wire Line
-	3700 2275 3700 2425
-Wire Wire Line
-	4050 1100 4050 2325
-Wire Wire Line
-	4050 2325 3700 2325
-Connection ~ 3700 2325
-Connection ~ 4050 2075
-Connection ~ 2800 2225
-Wire Wire Line
-	3100 2625 3400 2625
-$Comp
-L eSim_R R3
-U 1 1 5C9DBD46
-P 3650 1400
-F 0 "R3" H 3700 1530 50  0000 C CNN
-F 1 "20K" H 3700 1450 50  0000 C CNN
-F 2 "" H 3700 1380 30  0000 C CNN
-F 3 "" V 3700 1450 30  0000 C CNN
-	1    3650 1400
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R7
-U 1 1 5C9DBD83
-P 4325 1400
-F 0 "R7" H 4375 1530 50  0000 C CNN
-F 1 "10K" H 4375 1450 50  0000 C CNN
-F 2 "" H 4375 1380 30  0000 C CNN
-F 3 "" V 4375 1450 30  0000 C CNN
-	1    4325 1400
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	3700 1600 3700 1875
-Wire Wire Line
-	4375 1600 4375 1875
-Wire Wire Line
-	3450 1775 3450 1700
-Wire Wire Line
-	3450 1700 4375 1700
-Connection ~ 4375 1700
-Wire Wire Line
-	2800 1300 2800 1225
-Wire Wire Line
-	2800 1225 7575 1225
-Wire Wire Line
-	3700 1225 3700 1300
-Wire Wire Line
-	4375 1225 4375 1300
-Connection ~ 3700 1225
-$Comp
-L eSim_NPN Q1
-U 1 1 5C9DBEE9
-P 2650 3375
-F 0 "Q1" H 2550 3425 50  0000 R CNN
-F 1 "eSim_NPN" H 2600 3525 50  0000 R CNN
-F 2 "" H 2850 3475 29  0000 C CNN
-F 3 "" H 2650 3375 60  0000 C CNN
-	1    2650 3375
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2750 3175 2750 2825
-Wire Wire Line
-	2750 2825 2800 2825
-Wire Wire Line
-	2450 3375 2375 3375
-$Comp
-L eSim_NPN Q4
-U 1 1 5C9DBF74
-P 2950 3975
-F 0 "Q4" H 2850 4025 50  0000 R CNN
-F 1 "eSim_NPN" H 2900 4125 50  0000 R CNN
-F 2 "" H 3150 4075 29  0000 C CNN
-F 3 "" H 2950 3975 60  0000 C CNN
-	1    2950 3975
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q6
-U 1 1 5C9DBFBB
-P 3500 3975
-F 0 "Q6" H 3400 4025 50  0000 R CNN
-F 1 "eSim_NPN" H 3450 4125 50  0000 R CNN
-F 2 "" H 3700 4075 29  0000 C CNN
-F 3 "" H 3500 3975 60  0000 C CNN
-	1    3500 3975
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3600 3775 3600 3650
-Wire Wire Line
-	2850 3650 4050 3650
-Wire Wire Line
-	2850 3650 2850 3775
-Wire Wire Line
-	3150 3975 3150 4175
-Wire Wire Line
-	3150 4175 3600 4175
-Wire Wire Line
-	3300 4250 3300 3975
-Wire Wire Line
-	2450 4250 3300 4250
-Wire Wire Line
-	2850 4250 2850 4175
-Wire Wire Line
-	2450 4250 2450 3375
-Connection ~ 2850 4250
-$Comp
-L eSim_R R1
-U 1 1 5C9DC222
-P 2700 5000
-F 0 "R1" H 2750 5130 50  0000 C CNN
-F 1 "2K" H 2750 5050 50  0000 C CNN
-F 2 "" H 2750 4980 30  0000 C CNN
-F 3 "" V 2750 5050 30  0000 C CNN
-	1    2700 5000
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	2750 3575 2750 4900
-$Comp
-L eSim_R R5
-U 1 1 5C9DC2A7
-P 4150 3700
-F 0 "R5" H 4200 3830 50  0000 C CNN
-F 1 "50K" H 4200 3750 50  0000 C CNN
-F 2 "" H 4200 3680 30  0000 C CNN
-F 3 "" V 4200 3750 30  0000 C CNN
-	1    4150 3700
-	1    0    0    -1  
-$EndComp
-Connection ~ 3600 3650
-$Comp
-L eSim_NPN Q8
-U 1 1 5C9DC459
-P 3625 4425
-F 0 "Q8" H 3525 4475 50  0000 R CNN
-F 1 "eSim_NPN" H 3575 4575 50  0000 R CNN
-F 2 "" H 3825 4525 29  0000 C CNN
-F 3 "" H 3625 4425 60  0000 C CNN
-	1    3625 4425
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3400 4425 3400 4175
-Wire Wire Line
-	2400 4425 3425 4425
-Connection ~ 3400 4175
-Wire Wire Line
-	3725 4225 3725 2825
-Wire Wire Line
-	3725 2825 3700 2825
-$Comp
-L eSim_R R8
-U 1 1 5C9DCB0B
-P 4575 1400
-F 0 "R8" H 4625 1530 50  0000 C CNN
-F 1 "10K" H 4625 1450 50  0000 C CNN
-F 2 "" H 4625 1380 30  0000 C CNN
-F 3 "" V 4625 1450 30  0000 C CNN
-	1    4575 1400
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	4625 1225 4625 1300
-Connection ~ 4375 1225
-$Comp
-L eSim_PNP Q15
-U 1 1 5C9DCBA9
-P 4775 1850
-F 0 "Q15" H 4675 1900 50  0000 R CNN
-F 1 "eSim_PNP" H 4725 2000 50  0000 R CNN
-F 2 "" H 4975 1950 29  0000 C CNN
-F 3 "" H 4775 1850 60  0000 C CNN
-	1    4775 1850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	4675 1650 4625 1650
-Wire Wire Line
-	4625 1650 4625 1600
-Connection ~ 4625 1225
-$Comp
-L eSim_R R12
-U 1 1 5C9DC058
-P 5550 1925
-F 0 "R12" H 5600 2055 50  0000 C CNN
-F 1 "5.6k" H 5600 1975 50  0000 C CNN
-F 2 "" H 5600 1905 30  0000 C CNN
-F 3 "" V 5600 1975 30  0000 C CNN
-	1    5550 1925
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	5600 2125 5600 2550
-Wire Wire Line
-	4375 2275 5725 2275
-$Comp
-L eSim_NPN Q13
-U 1 1 5C9DC257
-P 4525 2750
-F 0 "Q13" H 4425 2800 50  0000 R CNN
-F 1 "eSim_NPN" H 4475 2900 50  0000 R CNN
-F 2 "" H 4725 2850 29  0000 C CNN
-F 3 "" H 4525 2750 60  0000 C CNN
-	1    4525 2750
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q17
-U 1 1 5C9DC2B6
-P 5500 2750
-F 0 "Q17" H 5400 2800 50  0000 R CNN
-F 1 "eSim_NPN" H 5450 2900 50  0000 R CNN
-F 2 "" H 5700 2850 29  0000 C CNN
-F 3 "" H 5500 2750 60  0000 C CNN
-	1    5500 2750
-	1    0    0    -1  
-$EndComp
-Connection ~ 5600 2275
-Wire Wire Line
-	4725 2750 5300 2750
-Wire Wire Line
-	3450 2175 3450 2400
-Wire Wire Line
-	3450 2400 5050 2400
-Wire Wire Line
-	4425 2400 4425 2550
-Wire Wire Line
-	5050 2400 5050 2750
-Connection ~ 5050 2750
-Connection ~ 4425 2400
-Wire Wire Line
-	4425 2950 4425 3075
-Wire Wire Line
-	4425 3075 7275 3075
-Wire Wire Line
-	5600 3075 5600 2950
-$Comp
-L eSim_NPN Q14
-U 1 1 5C9DC732
-P 4525 3400
-F 0 "Q14" H 4425 3450 50  0000 R CNN
-F 1 "eSim_NPN" H 4475 3550 50  0000 R CNN
-F 2 "" H 4725 3500 29  0000 C CNN
-F 3 "" H 4525 3400 60  0000 C CNN
-	1    4525 3400
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	3200 3200 4725 3200
-Wire Wire Line
-	4725 2225 4725 3400
-Wire Wire Line
-	4725 2225 4675 2225
-Wire Wire Line
-	4675 2225 4675 2050
-Connection ~ 4725 3200
-Wire Wire Line
-	3200 3200 3200 2625
-Connection ~ 3200 2625
-Connection ~ 4425 3200
-Wire Wire Line
-	4425 3600 4425 5125
-Wire Wire Line
-	4425 3650 4350 3650
-$Comp
-L eSim_R R4
-U 1 1 5C9DCD74
-P 3675 5000
-F 0 "R4" H 3725 5130 50  0000 C CNN
-F 1 "2k" H 3725 5050 50  0000 C CNN
-F 2 "" H 3725 4980 30  0000 C CNN
-F 3 "" V 3725 5050 30  0000 C CNN
-	1    3675 5000
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	3725 4625 3725 4900
-Wire Wire Line
-	3725 5200 3725 5600
-Wire Wire Line
-	2750 5325 4125 5325
-Wire Wire Line
-	2750 5325 2750 5200
-$Comp
-L eSim_PNP Q12
-U 1 1 5C9DD197
-P 4325 5325
-F 0 "Q12" H 4225 5375 50  0000 R CNN
-F 1 "eSim_PNP" H 4275 5475 50  0000 R CNN
-F 2 "" H 4525 5425 29  0000 C CNN
-F 3 "" H 4325 5325 60  0000 C CNN
-	1    4325 5325
-	1    0    0    1   
-$EndComp
-Connection ~ 3725 5325
-Connection ~ 4425 3650
-$Comp
-L eSim_NPN Q10
-U 1 1 5C9DD5DD
-P 3825 5800
-F 0 "Q10" H 3725 5850 50  0000 R CNN
-F 1 "eSim_NPN" H 3775 5950 50  0000 R CNN
-F 2 "" H 4025 5900 29  0000 C CNN
-F 3 "" H 3825 5800 60  0000 C CNN
-	1    3825 5800
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	4825 5225 4825 5875
-Wire Wire Line
-	4825 5800 4025 5800
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9DDBBA
-P 5650 4175
-F 0 "Q18" H 5550 4225 50  0000 R CNN
-F 1 "eSim_NPN" H 5600 4325 50  0000 R CNN
-F 2 "" H 5850 4275 29  0000 C CNN
-F 3 "" H 5650 4175 60  0000 C CNN
-	1    5650 4175
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NJF J1
-U 1 1 5C9DDDE9
-P 6400 4100
-F 0 "J1" H 6300 4150 50  0000 R CNN
-F 1 "eSim_NJF" H 6350 4250 50  0000 R CNN
-F 2 "" H 6600 4200 29  0000 C CNN
-F 3 "" H 6400 4100 60  0000 C CNN
-	1    6400 4100
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_R R13
-U 1 1 5C9DFBCC
-P 6250 4625
-F 0 "R13" H 6300 4755 50  0000 C CNN
-F 1 "940" H 6300 4675 50  0000 C CNN
-F 2 "" H 6300 4605 30  0000 C CNN
-F 3 "" V 6300 4675 30  0000 C CNN
-	1    6250 4625
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	6300 4300 6300 4525
-Wire Wire Line
-	5125 5025 6300 5025
-Wire Wire Line
-	6300 4825 6300 5475
-$Comp
-L eSim_R R14
-U 1 1 5C9DFE3D
-P 6500 4550
-F 0 "R14" H 6550 4680 50  0000 C CNN
-F 1 "20k" H 6550 4600 50  0000 C CNN
-F 2 "" H 6550 4530 30  0000 C CNN
-F 3 "" V 6550 4600 30  0000 C CNN
-	1    6500 4550
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6400 4500 5550 4500
-Wire Wire Line
-	5550 4375 5550 5875
-Wire Wire Line
-	4425 5525 6850 5525
-Wire Wire Line
-	6850 4100 6850 6250
-Wire Wire Line
-	6850 4100 6600 4100
-$Comp
-L eSim_NPN Q24
-U 1 1 5C9E055D
-P 7225 4500
-F 0 "Q24" H 7125 4550 50  0000 R CNN
-F 1 "eSim_NPN" H 7175 4650 50  0000 R CNN
-F 2 "" H 7425 4600 29  0000 C CNN
-F 3 "" H 7225 4500 60  0000 C CNN
-	1    7225 4500
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7025 4500 6700 4500
-$Comp
-L eSim_R R6
-U 1 1 5C9E0948
-P 4225 6300
-F 0 "R6" H 4275 6430 50  0000 C CNN
-F 1 "6.4K" H 4275 6350 50  0000 C CNN
-F 2 "" H 4275 6280 30  0000 C CNN
-F 3 "" V 4275 6350 30  0000 C CNN
-	1    4225 6300
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5C9E09B9
-P 4775 5975
-F 0 "R9" H 4825 6105 50  0000 C CNN
-F 1 "60K" H 4825 6025 50  0000 C CNN
-F 2 "" H 4825 5955 30  0000 C CNN
-F 3 "" V 4825 6025 30  0000 C CNN
-	1    4775 5975
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9E0B22
-P 5500 5975
-F 0 "R11" H 5550 6105 50  0000 C CNN
-F 1 "20K" H 5550 6025 50  0000 C CNN
-F 2 "" H 5550 5955 30  0000 C CNN
-F 3 "" V 5550 6025 30  0000 C CNN
-	1    5500 5975
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5C9E0B8F
-P 5125 6300
-F 0 "R10" H 5175 6430 50  0000 C CNN
-F 1 "500" H 5175 6350 50  0000 C CNN
-F 2 "" H 5175 6280 30  0000 C CNN
-F 3 "" V 5175 6350 30  0000 C CNN
-	1    5125 6300
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_R R15
-U 1 1 5C9E0BFA
-P 6500 6300
-F 0 "R15" H 6550 6430 50  0000 C CNN
-F 1 "1K" H 6550 6350 50  0000 C CNN
-F 2 "" H 6550 6280 30  0000 C CNN
-F 3 "" V 6550 6350 30  0000 C CNN
-	1    6500 6300
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9E0C83
-P 5750 5675
-F 0 "Q19" H 5650 5725 50  0000 R CNN
-F 1 "eSim_NPN" H 5700 5825 50  0000 R CNN
-F 2 "" H 5950 5775 29  0000 C CNN
-F 3 "" H 5750 5675 60  0000 C CNN
-	1    5750 5675
-	1    0    0    -1  
-$EndComp
-Connection ~ 5550 4500
-Connection ~ 5550 5675
-Wire Wire Line
-	5550 6175 5550 6250
-Wire Wire Line
-	5325 6250 6400 6250
-Wire Wire Line
-	4425 6250 5025 6250
-Wire Wire Line
-	4825 6250 4825 6175
-Connection ~ 4825 6250
-Connection ~ 4825 5800
-Wire Wire Line
-	4125 6250 3725 6250
-Wire Wire Line
-	3725 6250 3725 6000
-Connection ~ 5550 6250
-Wire Wire Line
-	5850 5875 6225 5875
-Wire Wire Line
-	6225 5875 6225 6250
-Connection ~ 6225 6250
-Wire Wire Line
-	6700 6250 8600 6250
-Connection ~ 6850 5525
-Wire Wire Line
-	6300 5475 5850 5475
-Connection ~ 6300 5025
-$Comp
-L eSim_R R17
-U 1 1 5C9E17A1
-P 7275 5325
-F 0 "R17" H 7325 5455 50  0000 C CNN
-F 1 "820" H 7325 5375 50  0000 C CNN
-F 2 "" H 7325 5305 30  0000 C CNN
-F 3 "" V 7325 5375 30  0000 C CNN
-	1    7275 5325
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	7325 4700 7325 5225
-Wire Wire Line
-	7325 6250 7325 5525
-Connection ~ 6850 6250
-$Comp
-L eSim_NPN Q21
-U 1 1 5C9E2938
-P 6125 1525
-F 0 "Q21" H 6025 1575 50  0000 R CNN
-F 1 "eSim_NPN" H 6075 1675 50  0000 R CNN
-F 2 "" H 6325 1625 29  0000 C CNN
-F 3 "" H 6125 1525 60  0000 C CNN
-	1    6125 1525
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q20
-U 1 1 5C9E29AB
-P 5925 2275
-F 0 "Q20" H 5825 2325 50  0000 R CNN
-F 1 "eSim_NPN" H 5875 2425 50  0000 R CNN
-F 2 "" H 6125 2375 29  0000 C CNN
-F 3 "" H 5925 2275 60  0000 C CNN
-	1    5925 2275
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6025 1725 6025 2075
-Wire Wire Line
-	5700 1300 5700 1675
-Wire Wire Line
-	7575 1300 8450 1300
-Wire Wire Line
-	6375 1300 6375 1800
-Wire Wire Line
-	6325 1525 6675 1525
-$Comp
-L eSim_R R16
-U 1 1 5C9E2CC0
-P 6775 1575
-F 0 "R16" H 6825 1705 50  0000 C CNN
-F 1 "2K" H 6825 1625 50  0000 C CNN
-F 2 "" H 6825 1555 30  0000 C CNN
-F 3 "" V 6825 1625 30  0000 C CNN
-	1    6775 1575
-	1    0    0    -1  
-$EndComp
-Connection ~ 6375 1525
-$Comp
-L eSim_NPN Q23
-U 1 1 5C9E2F0C
-P 6875 1800
-F 0 "Q23" H 6775 1850 50  0000 R CNN
-F 1 "eSim_NPN" H 6825 1950 50  0000 R CNN
-F 2 "" H 7075 1900 29  0000 C CNN
-F 3 "" H 6875 1800 60  0000 C CNN
-	1    6875 1800
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6975 1525 6975 1600
-Wire Wire Line
-	6375 1800 6675 1800
-$Comp
-L eSim_NPN Q26
-U 1 1 5C9E318C
-P 7475 1525
-F 0 "Q26" H 7375 1575 50  0000 R CNN
-F 1 "eSim_NPN" H 7425 1675 50  0000 R CNN
-F 2 "" H 7675 1625 29  0000 C CNN
-F 3 "" H 7475 1525 60  0000 C CNN
-	1    7475 1525
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6975 1525 7275 1525
-$Comp
-L eSim_NPN Q25
-U 1 1 5C9E32C5
-P 7300 1800
-F 0 "Q25" H 7200 1850 50  0000 R CNN
-F 1 "eSim_NPN" H 7250 1950 50  0000 R CNN
-F 2 "" H 7500 1900 29  0000 C CNN
-F 3 "" H 7300 1800 60  0000 C CNN
-	1    7300 1800
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	7200 1600 7200 1525
-Connection ~ 7200 1525
-Wire Wire Line
-	7575 1725 7575 2275
-Wire Wire Line
-	7500 1800 7825 1800
-Wire Wire Line
-	7575 1225 7575 1325
-$Comp
-L eSim_PNP Q22
-U 1 1 5C9E36C9
-P 6850 2775
-F 0 "Q22" H 6750 2825 50  0000 R CNN
-F 1 "eSim_PNP" H 6800 2925 50  0000 R CNN
-F 2 "" H 7050 2875 29  0000 C CNN
-F 3 "" H 6850 2775 60  0000 C CNN
-	1    6850 2775
-	1    0    0    1   
-$EndComp
-Wire Wire Line
-	6975 2000 6975 2575
-Wire Wire Line
-	6975 2575 6950 2575
-Connection ~ 5600 3075
-Wire Wire Line
-	6025 3075 6025 2475
-Wire Wire Line
-	6650 2775 6650 3325
-Connection ~ 6025 3075
-$Comp
-L eSim_PNP Q27
-U 1 1 5C9E3F8C
-P 7475 3075
-F 0 "Q27" H 7375 3125 50  0000 R CNN
-F 1 "eSim_PNP" H 7425 3225 50  0000 R CNN
-F 2 "" H 7675 3175 29  0000 C CNN
-F 3 "" H 7475 3075 60  0000 C CNN
-	1    7475 3075
-	1    0    0    1   
-$EndComp
-Connection ~ 6650 3075
-$Comp
-L eSim_R R18
-U 1 1 5C9E431A
-P 7525 2375
-F 0 "R18" H 7575 2505 50  0000 C CNN
-F 1 "240" H 7575 2425 50  0000 C CNN
-F 2 "" H 7575 2355 30  0000 C CNN
-F 3 "" V 7575 2425 30  0000 C CNN
-	1    7525 2375
-	0    1    1    0   
-$EndComp
-Connection ~ 7575 1800
-Wire Wire Line
-	7575 2575 7575 2875
-$Comp
-L eSim_R R19
-U 1 1 5C9E45DF
-P 7925 1850
-F 0 "R19" H 7975 1980 50  0000 C CNN
-F 1 "90" H 7975 1900 50  0000 C CNN
-F 2 "" H 7975 1830 30  0000 C CNN
-F 3 "" V 7975 1900 30  0000 C CNN
-	1    7925 1850
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7200 2000 8250 2000
-Wire Wire Line
-	8250 2000 8250 1800
-Wire Wire Line
-	8125 1800 8475 1800
-Wire Wire Line
-	7325 4300 7325 3325
-Wire Wire Line
-	7325 3325 6650 3325
-Wire Wire Line
-	6950 2975 7300 2975
-Wire Wire Line
-	7300 2975 7300 2750
-Wire Wire Line
-	7300 2750 7875 2750
-Wire Wire Line
-	7875 2750 7875 6250
-Connection ~ 7325 6250
-Wire Wire Line
-	7575 3275 7575 6250
-Connection ~ 7575 6250
-Connection ~ 7875 6250
-Connection ~ 8250 1800
-Connection ~ 7575 1300
-$Comp
-L PORT U1
-U 7 1 5C9EBDC2
-P 8700 1300
-F 0 "U1" H 8750 1400 30  0000 C CNN
-F 1 "PORT" H 8700 1300 30  0000 C CNN
-F 2 "" H 8700 1300 60  0000 C CNN
-F 3 "" H 8700 1300 60  0000 C CNN
-	7    8700 1300
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9EBE57
-P 8725 1800
-F 0 "U1" H 8775 1900 30  0000 C CNN
-F 1 "PORT" H 8725 1800 30  0000 C CNN
-F 2 "" H 8725 1800 60  0000 C CNN
-F 3 "" H 8725 1800 60  0000 C CNN
-	6    8725 1800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9EC714
-P 8850 6250
-F 0 "U1" H 8900 6350 30  0000 C CNN
-F 1 "PORT" H 8850 6250 30  0000 C CNN
-F 2 "" H 8850 6250 60  0000 C CNN
-F 3 "" H 8850 6250 60  0000 C CNN
-	4    8850 6250
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9ED09C
-P 2125 3375
-F 0 "U1" H 2175 3475 30  0000 C CNN
-F 1 "PORT" H 2125 3375 30  0000 C CNN
-F 2 "" H 2125 3375 60  0000 C CNN
-F 3 "" H 2125 3375 60  0000 C CNN
-	2    2125 3375
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9ED12F
-P 2150 4425
-F 0 "U1" H 2200 4525 30  0000 C CNN
-F 1 "PORT" H 2150 4425 30  0000 C CNN
-F 2 "" H 2150 4425 60  0000 C CNN
-F 3 "" H 2150 4425 60  0000 C CNN
-	3    2150 4425
-	1    0    0    -1  
-$EndComp
-Connection ~ 3400 4425
-Text GLabel 8425 1075 0    60   Input ~ 0
-v+
-Wire Wire Line
-	8425 1075 8450 1075
-Wire Wire Line
-	8450 1075 8450 1300
-Text GLabel 8475 1675 0    60   Input ~ 0
-Output
-Wire Wire Line
-	8475 1800 8475 1675
-Text GLabel 8600 6150 0    60   Input ~ 0
-V-
-Wire Wire Line
-	8600 6250 8600 6150
-Text GLabel 2375 4600 0    60   Input ~ 0
-Input+
-Wire Wire Line
-	2375 4600 2450 4600
-Wire Wire Line
-	2450 4600 2450 4425
-Connection ~ 2450 4425
-Text GLabel 2350 3525 0    60   Input ~ 0
-Input-
-Wire Wire Line
-	2350 3525 2375 3525
-Wire Wire Line
-	2375 3525 2375 3375
-Wire Wire Line
-	6025 1225 6025 1325
-Connection ~ 6025 1225
-Wire Wire Line
-	5700 1300 6375 1300
-Wire Wire Line
-	5600 1825 5600 1125
-$Comp
-L PORT U1
-U 1 1 5C9FE719
-P 4050 850
-F 0 "U1" H 4100 950 30  0000 C CNN
-F 1 "PORT" H 4050 850 30  0000 C CNN
-F 2 "" H 4050 850 60  0000 C CNN
-F 3 "" H 4050 850 60  0000 C CNN
-	1    4050 850 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9FF058
-P 5600 875
-F 0 "U1" H 5650 975 30  0000 C CNN
-F 1 "PORT" H 5600 875 30  0000 C CNN
-F 2 "" H 5600 875 60  0000 C CNN
-F 3 "" H 5600 875 60  0000 C CNN
-	8    5600 875 
-	0    1    1    0   
-$EndComp
-Text GLabel 5500 1125 0    60   Input ~ 0
-CompensationB
-Wire Wire Line
-	5600 1125 5500 1125
-Text GLabel 3875 1075 0    60   Input ~ 0
-CompensationA
-Wire Wire Line
-	3875 1075 3975 1075
-Wire Wire Line
-	3975 1075 3975 1150
-Wire Wire Line
-	3975 1150 4050 1150
-Connection ~ 4050 1150
-Wire Wire Line
-	5850 4175 5850 4375
-Wire Wire Line
-	5850 4375 6300 4375
-Connection ~ 6300 4375
-$Comp
-L eSim_PNP Q28
-U 1 1 5CA09126
-P 5075 1475
-F 0 "Q28" H 4975 1525 50  0000 R CNN
-F 1 "eSim_PNP" H 5025 1625 50  0000 R CNN
-F 2 "" H 5275 1575 29  0000 C CNN
-F 3 "" H 5075 1475 60  0000 C CNN
-	1    5075 1475
-	1    0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q29
-U 1 1 5CA091C3
-P 5400 1475
-F 0 "Q29" H 5300 1525 50  0000 R CNN
-F 1 "eSim_PNP" H 5350 1625 50  0000 R CNN
-F 2 "" H 5600 1575 29  0000 C CNN
-F 3 "" H 5400 1475 60  0000 C CNN
-	1    5400 1475
-	1    0    0    1   
-$EndComp
-Wire Wire Line
-	5500 1275 5500 1225
-Connection ~ 5500 1225
-Wire Wire Line
-	4875 1475 4875 1675
-Wire Wire Line
-	4875 1675 4975 1675
-Wire Wire Line
-	5175 1675 5175 1850
-Wire Wire Line
-	5700 1675 5500 1675
-$Comp
-L eSim_NPN Q16
-U 1 1 5CA0B93F
-P 4925 5025
-F 0 "Q16" H 4825 5075 50  0000 R CNN
-F 1 "eSim_NPN" H 4875 5175 50  0000 R CNN
-F 2 "" H 5125 5125 29  0000 C CNN
-F 3 "" H 4925 5025 60  0000 C CNN
-	1    4925 5025
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	5200 1475 5200 1275
-Wire Wire Line
-	5200 1275 5175 1275
-Wire Wire Line
-	5175 1850 4975 1850
-Wire Wire Line
-	4975 1675 4975 3975
-Wire Wire Line
-	4825 3975 6100 3975
-Connection ~ 4975 1850
-Wire Wire Line
-	6100 3975 6100 3900
-Wire Wire Line
-	6100 3900 6300 3900
-Connection ~ 5550 3975
-Wire Wire Line
-	4825 3975 4825 4825
-Connection ~ 4975 3975
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM108/LM108.sub b/src/SubcircuitLibrary/LM108/LM108.sub
deleted file mode 100644
index b04676f7..00000000
--- a/src/SubcircuitLibrary/LM108/LM108.sub
+++ /dev/null
@@ -1,57 +0,0 @@
-* Subcircuit LM108
-.subckt LM108 compensationa input+ input- v- output v+ compensationb 
-* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir
-.include PNP.lib
-.include NJF.lib
-.include NPN.lib
-r2  v+ net-_q2-pad3_ 20k
-q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A
-q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A
-q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222
-q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222
-q9 compensationa compensationa net-_q9-pad3_ Q2N2907A
-q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A
-r3  v+ net-_q9-pad3_ 20k
-r7  v+ net-_q11-pad3_ 10k
-q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222
-q4 net-_q4-pad1_ input+ input- Q2N2222
-q6 net-_q4-pad1_ input- input+ Q2N2222
-r1  net-_q1-pad3_ net-_q10-pad1_ 2k
-r5  net-_q4-pad1_ net-_q12-pad3_ 50k
-q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222
-r8  v+ net-_q15-pad3_ 10k
-q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A
-r12  compensationb net-_q11-pad1_ 5.6k
-q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222
-r4  net-_q8-pad3_ net-_q10-pad1_ 2k
-q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222
-j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819
-r13  net-_j1-pad1_ net-_q16-pad2_ 940
-r14  net-_q18-pad3_ net-_q24-pad2_ 20k
-q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222
-r6  net-_q10-pad3_ net-_r10-pad1_ 6.4k
-r9  net-_q10-pad2_ net-_r10-pad1_ 60k
-r11  net-_q18-pad3_ net-_q19-pad3_ 20k
-r10  net-_r10-pad1_ net-_q19-pad3_ 500
-r15  net-_q19-pad3_ v- 1k
-q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222
-r17  net-_q24-pad3_ v- 820
-q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222
-q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-r16  net-_j1-pad3_ net-_q23-pad1_ 2k
-q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222
-q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222
-q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222
-q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A
-q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A
-r18  net-_q25-pad2_ net-_q27-pad3_ 240
-r19  net-_q25-pad2_ output 90
-q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A
-q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222
-* Control Statements
-
-.ends LM108
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml b/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml
deleted file mode 100644
index c3161654..00000000
--- a/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><j1><field>C:/esim_1/eSim/src/deviceModelLibrary/JFET/NJF.lib</field></j1><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q27><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q12><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM108/NJF.lib b/src/SubcircuitLibrary/LM108/NJF.lib
deleted file mode 100644
index dbb2cbae..00000000
--- a/src/SubcircuitLibrary/LM108/NJF.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model J2N3819	NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+		Af=1)
diff --git a/src/SubcircuitLibrary/LM108/NPN.lib b/src/SubcircuitLibrary/LM108/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/LM108/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/LM108/PNP.lib b/src/SubcircuitLibrary/LM108/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/LM108/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib
deleted file mode 100644
index 27505ab7..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib
+++ /dev/null
@@ -1,77 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 75 50 H I C CNN
-F1 "PWR_FLAG" 0 150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir b/src/SubcircuitLibrary/LM3046/LM3046.cir
deleted file mode 100644
index f9716c63..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM3046/LM3046.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:57:18 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q4  Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN		
-Q5  Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN		
-Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-U1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ Net-_Q5-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ Net-_Q4-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ Net-_Q2-Pad1_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir.out b/src/SubcircuitLibrary/LM3046/LM3046.cir.out
deleted file mode 100644
index 801e68d2..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir
-
-.include NPN.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222
-q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-* u1  net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ port
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM3046/LM3046.pro b/src/SubcircuitLibrary/LM3046/LM3046.pro
deleted file mode 100644
index 38ae7a8e..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.pro
+++ /dev/null
@@ -1,73 +0,0 @@
-update=Fri Jun 21 16:28:59 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
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-UseCmpFile=1
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-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../eSim-1.1.2/kicadSchematicLibrary
-[eeschema/libraries]
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-LibName3=transistors
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-LibName8=cmos4000
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-LibName12=microcontrollers
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-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Plot
-LibName35=eSim_Power
-LibName36=eSim_PSpice
-LibName37=eSim_Sources
-LibName38=eSim_Subckt
-LibName39=eSim_User
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sch b/src/SubcircuitLibrary/LM3046/LM3046.sch
deleted file mode 100644
index 3ba1a18a..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.sch
+++ /dev/null
@@ -1,326 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
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-LIBS:eSim_Hybrid
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-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Miscellaneous
-LIBS:LM3046-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sub b/src/SubcircuitLibrary/LM3046/LM3046.sub
deleted file mode 100644
index 251364bb..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit LM3046
-.subckt LM3046 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir
-.include NPN.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222
-q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-* Control Statements
-
-.ends LM3046
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM3046/LM3046.xml b/src/SubcircuitLibrary/LM3046/LM3046.xml
deleted file mode 100644
index 94884e43..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046.xml
+++ /dev/null
@@ -1,177 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<export version="D">
-  <design>
-    <source>C:/esim_1/eSim/src/SubcircuitLibrary/LM3046/LM3046.sch</source>
-    <date>03/27/19 23:15:04</date>
-    <tool>Eeschema 4.0.2-stable</tool>
-    <sheet number="1" name="/" tstamps="/">
-      <title_block>
-        <title/>
-        <company/>
-        <rev/>
-        <date/>
-        <source>LM3046.sch</source>
-        <comment number="1" value=""/>
-        <comment number="2" value=""/>
-        <comment number="3" value=""/>
-        <comment number="4" value=""/>
-      </title_block>
-    </sheet>
-  </design>
-  <components>
-    <comp ref="Q1">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EC0E</tstamp>
-    </comp>
-    <comp ref="Q2">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EC83</tstamp>
-    </comp>
-    <comp ref="Q4">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98ECC0</tstamp>
-    </comp>
-    <comp ref="Q5">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98ED6B</tstamp>
-    </comp>
-    <comp ref="Q3">
-      <value>eSim_NPN</value>
-      <libsource lib="eSim_Devices" part="eSim_NPN"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EDA0</tstamp>
-    </comp>
-    <comp ref="U1">
-      <value>PORT</value>
-      <libsource lib="eSim_Miscellaneous" part="PORT"/>
-      <sheetpath names="/" tstamps="/"/>
-      <tstamp>5C98EEE0</tstamp>
-    </comp>
-  </components>
-  <libparts>
-    <libpart lib="eSim_Miscellaneous" part="PORT">
-      <fields>
-        <field name="Reference">U</field>
-        <field name="Value">PORT</field>
-      </fields>
-      <pins>
-        <pin num="1" name="~" type="BiDi"/>
-        <pin num="2" name="~" type="BiDi"/>
-        <pin num="3" name="~" type="BiDi"/>
-        <pin num="4" name="~" type="BiDi"/>
-        <pin num="5" name="~" type="BiDi"/>
-        <pin num="6" name="~" type="BiDi"/>
-        <pin num="7" name="~" type="BiDi"/>
-        <pin num="8" name="~" type="BiDi"/>
-        <pin num="9" name="~" type="BiDi"/>
-        <pin num="10" name="~" type="BiDi"/>
-        <pin num="11" name="~" type="BiDi"/>
-        <pin num="12" name="~" type="BiDi"/>
-        <pin num="13" name="~" type="BiDi"/>
-        <pin num="14" name="~" type="BiDi"/>
-        <pin num="15" name="~" type="BiDi"/>
-        <pin num="16" name="~" type="BiDi"/>
-        <pin num="17" name="~" type="BiDi"/>
-        <pin num="18" name="~" type="BiDi"/>
-        <pin num="19" name="~" type="BiDi"/>
-        <pin num="20" name="~" type="BiDi"/>
-        <pin num="21" name="~" type="BiDi"/>
-        <pin num="22" name="~" type="BiDi"/>
-        <pin num="23" name="~" type="BiDi"/>
-        <pin num="24" name="~" type="BiDi"/>
-        <pin num="25" name="~" type="BiDi"/>
-        <pin num="26" name="~" type="BiDi"/>
-      </pins>
-    </libpart>
-    <libpart lib="eSim_Devices" part="eSim_NPN">
-      <aliases>
-        <alias>BC547</alias>
-        <alias>Q2N2222</alias>
-      </aliases>
-      <fields>
-        <field name="Reference">Q</field>
-        <field name="Value">eSim_NPN</field>
-      </fields>
-      <pins>
-        <pin num="1" name="C" type="openCol"/>
-        <pin num="2" name="B" type="input"/>
-        <pin num="3" name="E" type="openEm"/>
-      </pins>
-    </libpart>
-  </libparts>
-  <libraries>
-    <library logical="eSim_Miscellaneous">
-      <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri>
-    </library>
-    <library logical="eSim_Devices">
-      <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri>
-    </library>
-  </libraries>
-  <nets>
-    <net code="1" name="Net-(Q1-Pad1)">
-      <node ref="Q1" pin="1"/>
-      <node ref="U1" pin="1"/>
-    </net>
-    <net code="2" name="Net-(Q2-Pad3)">
-      <node ref="Q2" pin="3"/>
-      <node ref="U1" pin="13"/>
-    </net>
-    <net code="3" name="Net-(Q2-Pad1)">
-      <node ref="Q2" pin="1"/>
-      <node ref="U1" pin="14"/>
-    </net>
-    <net code="4" name="Net-(Q2-Pad2)">
-      <node ref="Q2" pin="2"/>
-      <node ref="U1" pin="12"/>
-    </net>
-    <net code="5" name="Net-(Q4-Pad3)">
-      <node ref="Q4" pin="3"/>
-      <node ref="U1" pin="10"/>
-    </net>
-    <net code="6" name="Net-(Q4-Pad1)">
-      <node ref="Q4" pin="1"/>
-      <node ref="U1" pin="11"/>
-    </net>
-    <net code="7" name="Net-(Q4-Pad2)">
-      <node ref="Q4" pin="2"/>
-      <node ref="U1" pin="9"/>
-    </net>
-    <net code="8" name="Net-(Q1-Pad3)">
-      <node ref="Q3" pin="3"/>
-      <node ref="Q1" pin="3"/>
-      <node ref="U1" pin="3"/>
-    </net>
-    <net code="9" name="Net-(Q3-Pad2)">
-      <node ref="Q3" pin="2"/>
-      <node ref="U1" pin="4"/>
-    </net>
-    <net code="10" name="Net-(Q1-Pad2)">
-      <node ref="Q1" pin="2"/>
-      <node ref="U1" pin="2"/>
-    </net>
-    <net code="11" name="Net-(Q5-Pad1)">
-      <node ref="Q5" pin="1"/>
-      <node ref="U1" pin="8"/>
-    </net>
-    <net code="12" name="Net-(Q5-Pad2)">
-      <node ref="U1" pin="6"/>
-      <node ref="Q5" pin="2"/>
-    </net>
-    <net code="13" name="Net-(Q5-Pad3)">
-      <node ref="U1" pin="7"/>
-      <node ref="Q5" pin="3"/>
-    </net>
-    <net code="14" name="Net-(Q3-Pad1)">
-      <node ref="U1" pin="5"/>
-      <node ref="Q3" pin="1"/>
-    </net>
-  </nets>
-</export>
diff --git a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml
deleted file mode 100644
index 0b34a8e5..00000000
--- a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM3046/NPN.lib b/src/SubcircuitLibrary/LM3046/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/LM3046/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/LM3046/analysis b/src/SubcircuitLibrary/LM3046/analysis
deleted file mode 100644
index d5e13546..00000000
--- a/src/SubcircuitLibrary/LM3046/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM565/LM565-cache.lib b/src/SubcircuitLibrary/LM565/LM565-cache.lib
deleted file mode 100644
index dd2449b9..00000000
--- a/src/SubcircuitLibrary/LM565/LM565-cache.lib
+++ /dev/null
@@ -1,114 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
-F3 "" 0 0 50 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM565/LM565.cir b/src/SubcircuitLibrary/LM565/LM565.cir
deleted file mode 100644
index c1f63f94..00000000
--- a/src/SubcircuitLibrary/LM565/LM565.cir
+++ /dev/null
@@ -1,78 +0,0 @@
-* C:\esim_1\eSim\src\SubcircuitLibrary\LM565\LM565.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 18:47:10
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1  +Vcc Net-_Q1-Pad1_ 7.2k		
-R3  +Vcc Net-_Q14-Pad2_ 7.2k		
-Q4  Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q1-Pad1_ eSim_NPN		
-Q5  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q14-Pad2_ eSim_NPN		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad1_ +Vcc eSim_NPN		
-R4  +Vcc Net-_Q3-Pad2_ 5.7k		
-R6  +Vcc Reference_output 1.75k		
-R7  Reference_output Net-_Q1-Pad2_ 3.8k		
-Q12  +Vcc Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
-Q14  Vco_control_voltage Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
-R12  +Vcc Vco_control_voltage 3.6K		
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q3  Net-_Q14-Pad2_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q7  Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN		
-Q9  Net-_Q14-Pad2_ Net-_Q1-Pad2_ Net-_Q7-Pad3_ eSim_NPN		
-R5  Net-_Q3-Pad2_ -Vcc 13k		
-Q2  Net-_Q1-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN		
-Q8  Net-_Q7-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN		
-Q6  Net-_Q2-Pad3_ Net-_Q11-Pad1_ Net-_Q6-Pad3_ eSim_NPN		
-R2  Net-_Q6-Pad3_ -Vcc 200		
-R8  Net-_Q1-Pad2_ Net-_Q11-Pad1_ 8.1K		
-R10  Net-_Q12-Pad3_ Net-_Q13-Pad1_ 1K		
-R13  Net-_Q14-Pad3_ Net-_Q13-Pad1_ 1K		
-Q13  Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-Q11  Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_NPN		
-R9  Net-_Q11-Pad3_ -Vcc 200		
-R11  Net-_Q13-Pad3_ -Vcc 205		
-Q16  Timming_resistor Vco_control_voltage Net-_Q15-Pad2_ eSim_NPN		
-Q18  Net-_Q15-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN		
-Q20  Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN		
-Q17  Net-_Q17-Pad1_ Net-_Q17-Pad1_ Net-_Q17-Pad3_ eSim_NPN		
-Q21  Timing_capacitor Timing_capacitor Net-_Q17-Pad1_ eSim_PNP		
-Q22  Timing_capacitor Net-_Q17-Pad3_ Net-_Q19-Pad2_ eSim_NPN		
-Q19  Net-_Q17-Pad3_ Net-_Q19-Pad2_ Net-_Q19-Pad3_ eSim_NPN		
-Q23  Net-_Q19-Pad2_ Net-_Q19-Pad2_ Net-_Q23-Pad3_ eSim_NPN		
-R14  Net-_Q19-Pad3_ Net-_Q24-Pad1_ 530		
-R15  Net-_Q23-Pad3_ Net-_Q24-Pad1_ 530		
-Q25  +Vcc Timing_capacitor Net-_Q25-Pad3_ eSim_NPN		
-R17  +Vcc Net-_Q28-Pad1_ 6.5K		
-Q28  Net-_Q28-Pad1_ Net-_Q28-Pad1_ Net-_Q25-Pad3_ eSim_PNP		
-Q27  ? Net-_Q25-Pad3_ Net-_Q27-Pad3_ eSim_NPN		
-Q30  Net-_Q28-Pad1_ Net-_Q27-Pad3_ Net-_Q30-Pad3_ eSim_NPN		
-Q31  ? Net-_Q28-Pad1_ Net-_Q31-Pad3_ eSim_NPN		
-Q32  Net-_Q32-Pad1_ Net-_Q32-Pad1_ Net-_Q28-Pad1_ eSim_PNP		
-R19  +Vcc Net-_Q32-Pad1_ 4.7k		
-Q33  Net-_Q32-Pad1_ Net-_Q31-Pad3_ Net-_Q30-Pad3_ eSim_NPN		
-R18  Net-_Q31-Pad3_ Net-_Q30-Pad3_ 8.4K		
-Q35  +Vcc Net-_Q32-Pad1_ Vco_output eSim_NPN		
-R20  Net-_Q30-Pad3_ -Vcc 2.6K		
-R22  Vco_output -Vcc 4.8K		
-Q24  Net-_Q24-Pad1_ Net-_Q24-Pad2_ -Vcc eSim_NPN		
-Q26  Net-_Q24-Pad1_ Net-_Q24-Pad1_ Net-_Q26-Pad3_ eSim_PNP		
-R16  Net-_Q24-Pad2_ -Vcc 7K		
-Q29  Net-_Q26-Pad3_ Net-_Q26-Pad3_ Net-_Q24-Pad2_ eSim_NPN		
-Q34  Net-_Q25-Pad3_ Net-_Q11-Pad1_ Net-_Q34-Pad3_ eSim_NPN		
-R21  Net-_Q34-Pad3_ -Vcc 2.4K		
-Q36  -Vcc Vco_output Net-_Q36-Pad3_ eSim_PNP		
-Q38  Net-_Q37-Pad2_ Net-_Q38-Pad2_ Net-_Q36-Pad3_ eSim_PNP		
-R23  +Vcc Net-_Q36-Pad3_ 16K		
-R24  Net-_Q37-Pad2_ Net-_Q26-Pad3_ 5.8k		
-Q37  Net-_Q36-Pad3_ Net-_Q37-Pad2_ Net-_Q26-Pad3_ eSim_NPN		
-Q40  Net-_Q38-Pad2_ Net-_Q11-Pad1_ Net-_Q40-Pad3_ eSim_NPN		
-R26  Net-_Q40-Pad3_ -Vcc 200		
-R25  +Vcc Net-_Q38-Pad2_ 4.3k		
-Q39  ? Net-_Q38-Pad2_ +Vcc eSim_NPN		
-U1  -Vcc Input Input Vco_output +Vcc Reference_output Vco_control_voltage Timming_resistor Timing_capacitor +Vcc PORT		
-Q15  ? Net-_Q15-Pad2_ Vco_control_voltage eSim_NPN		
-Q41  Net-_Q18-Pad2_ Net-_Q15-Pad2_ Timming_resistor eSim_PNP		
-
-.end
diff --git a/src/SubcircuitLibrary/LM565/LM565.cir.out b/src/SubcircuitLibrary/LM565/LM565.cir.out
deleted file mode 100644
index e39ed5f4..00000000
--- a/src/SubcircuitLibrary/LM565/LM565.cir.out
+++ /dev/null
@@ -1,81 +0,0 @@
-* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir
-
-.include PNP.lib
-.include NPN.lib
-r1  +vcc net-_q1-pad1_ 7.2k
-r3  +vcc net-_q14-pad2_ 7.2k
-q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222
-q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222
-r4  +vcc net-_q3-pad2_ 5.7k
-r6  +vcc reference_output 1.75k
-r7  reference_output net-_q1-pad2_ 3.8k
-q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222
-q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222
-r12  +vcc vco_control_voltage 3.6k
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222
-r5  net-_q3-pad2_ -vcc 13k
-q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222
-q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222
-q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222
-r2  net-_q6-pad3_ -vcc 200
-r8  net-_q1-pad2_ net-_q11-pad1_ 8.1k
-r10  net-_q12-pad3_ net-_q13-pad1_ 1k
-r13  net-_q14-pad3_ net-_q13-pad1_ 1k
-q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222
-r9  net-_q11-pad3_ -vcc 200
-r11  net-_q13-pad3_ -vcc 205
-q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222
-q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222
-q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A
-q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222
-q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
-q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222
-r14  net-_q19-pad3_ net-_q24-pad1_ 530
-r15  net-_q23-pad3_ net-_q24-pad1_ 530
-q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222
-r17  +vcc net-_q28-pad1_ 6.5k
-q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A
-q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222
-q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222
-q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222
-q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A
-r19  +vcc net-_q32-pad1_ 4.7k
-q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222
-r18  net-_q31-pad3_ net-_q30-pad3_ 8.4k
-q35 +vcc net-_q32-pad1_ vco_output Q2N2222
-r20  net-_q30-pad3_ -vcc 2.6k
-r22  vco_output -vcc 4.8k
-q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222
-q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A
-r16  net-_q24-pad2_ -vcc 7k
-q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222
-q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222
-r21  net-_q34-pad3_ -vcc 2.4k
-q36 -vcc vco_output net-_q36-pad3_ Q2N2907A
-q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A
-r23  +vcc net-_q36-pad3_ 16k
-r24  net-_q37-pad2_ net-_q26-pad3_ 5.8k
-q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222
-q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222
-r26  net-_q40-pad3_ -vcc 200
-r25  +vcc net-_q38-pad2_ 4.3k
-q39 ? net-_q38-pad2_ +vcc Q2N2222
-* u1  -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc port
-q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222
-q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM565/LM565.pro b/src/SubcircuitLibrary/LM565/LM565.pro
deleted file mode 100644
index 94072b3e..00000000
--- a/src/SubcircuitLibrary/LM565/LM565.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=03/31/19 19:39:59
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Program Files (x86)/KiCad/share/library
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_Subckt
-LibName40=eSim_User
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/LM565/LM565.sch b/src/SubcircuitLibrary/LM565/LM565.sch
deleted file mode 100644
index 9f5ad21c..00000000
--- a/src/SubcircuitLibrary/LM565/LM565.sch
+++ /dev/null
@@ -1,1365 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LM565-cache
-EELAYER 25 0
-EELAYER END
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-F 1 "7.2k" H 900 1025 50  0000 C CNN
-F 2 "" H 900 955 30  0000 C CNN
-F 3 "" V 900 1025 30  0000 C CNN
-	1    850  975 
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-F 0 "R3" H 1600 1105 50  0000 C CNN
-F 1 "7.2k" H 1600 1025 50  0000 C CNN
-F 2 "" H 1600 955 30  0000 C CNN
-F 3 "" V 1600 1025 30  0000 C CNN
-	1    1550 975 
-	0    1    1    0   
-$EndComp
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-U 1 1 5C9DA013
-P 1250 1500
-F 0 "Q4" H 1150 1550 50  0000 R CNN
-F 1 "eSim_NPN" H 1200 1650 50  0000 R CNN
-F 2 "" H 1450 1600 29  0000 C CNN
-F 3 "" H 1250 1500 60  0000 C CNN
-	1    1250 1500
-	0    1    -1   0   
-$EndComp
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-L eSim_NPN Q5
-U 1 1 5C9DA091
-P 1250 2200
-F 0 "Q5" H 1150 2250 50  0000 R CNN
-F 1 "eSim_NPN" H 1200 2350 50  0000 R CNN
-F 2 "" H 1450 2300 29  0000 C CNN
-F 3 "" H 1250 2200 60  0000 C CNN
-	1    1250 2200
-	0    -1   1    0   
-$EndComp
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-L eSim_NPN Q10
-U 1 1 5C9DA0EA
-P 2125 1075
-F 0 "Q10" H 2025 1125 50  0000 R CNN
-F 1 "eSim_NPN" H 2075 1225 50  0000 R CNN
-F 2 "" H 2325 1175 29  0000 C CNN
-F 3 "" H 2125 1075 60  0000 C CNN
-	1    2125 1075
-	1    0    0    1   
-$EndComp
-$Comp
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-U 1 1 5C9DA12E
-P 2425 975
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-F 1 "5.7k" H 2475 1025 50  0000 C CNN
-F 2 "" H 2475 955 30  0000 C CNN
-F 3 "" V 2475 1025 30  0000 C CNN
-	1    2425 975 
-	0    1    1    0   
-$EndComp
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-U 1 1 5C9DA17B
-P 2925 975
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-F 1 "1.75k" H 2975 1025 50  0000 C CNN
-F 2 "" H 2975 955 30  0000 C CNN
-F 3 "" V 2975 1025 30  0000 C CNN
-	1    2925 975 
-	0    1    1    0   
-$EndComp
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-P 2925 2100
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-F 1 "3.8k" H 2975 2150 50  0000 C CNN
-F 2 "" H 2975 2080 30  0000 C CNN
-F 3 "" V 2975 2150 30  0000 C CNN
-	1    2925 2100
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q12
-U 1 1 5C9DA38D
-P 3175 2525
-F 0 "Q12" H 3075 2575 50  0000 R CNN
-F 1 "eSim_NPN" H 3125 2675 50  0000 R CNN
-F 2 "" H 3375 2625 29  0000 C CNN
-F 3 "" H 3175 2525 60  0000 C CNN
-	1    3175 2525
-	1    0    0    -1  
-$EndComp
-$Comp
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-U 1 1 5C9DA3C8
-P 3850 2525
-F 0 "Q14" H 3750 2575 50  0000 R CNN
-F 1 "eSim_NPN" H 3800 2675 50  0000 R CNN
-F 2 "" H 4050 2625 29  0000 C CNN
-F 3 "" H 3850 2525 60  0000 C CNN
-	1    3850 2525
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_R R12
-U 1 1 5C9DA421
-P 3700 1000
-F 0 "R12" H 3750 1130 50  0000 C CNN
-F 1 "3.6K" H 3750 1050 50  0000 C CNN
-F 2 "" H 3750 980 30  0000 C CNN
-F 3 "" V 3750 1050 30  0000 C CNN
-	1    3700 1000
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q1
-U 1 1 5C9DA843
-P 800 3100
-F 0 "Q1" H 700 3150 50  0000 R CNN
-F 1 "eSim_NPN" H 750 3250 50  0000 R CNN
-F 2 "" H 1000 3200 29  0000 C CNN
-F 3 "" H 800 3100 60  0000 C CNN
-	1    800  3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5C9DA87E
-P 1200 3100
-F 0 "Q3" H 1100 3150 50  0000 R CNN
-F 1 "eSim_NPN" H 1150 3250 50  0000 R CNN
-F 2 "" H 1400 3200 29  0000 C CNN
-F 3 "" H 1200 3100 60  0000 C CNN
-	1    1200 3100
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5C9DA8BB
-P 1625 3100
-F 0 "Q7" H 1525 3150 50  0000 R CNN
-F 1 "eSim_NPN" H 1575 3250 50  0000 R CNN
-F 2 "" H 1825 3200 29  0000 C CNN
-F 3 "" H 1625 3100 60  0000 C CNN
-	1    1625 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q9
-U 1 1 5C9DAACB
-P 2050 3100
-F 0 "Q9" H 1950 3150 50  0000 R CNN
-F 1 "eSim_NPN" H 2000 3250 50  0000 R CNN
-F 2 "" H 2250 3200 29  0000 C CNN
-F 3 "" H 2050 3100 60  0000 C CNN
-	1    2050 3100
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_R R5
-U 1 1 5C9DAE75
-P 2425 3300
-F 0 "R5" H 2475 3430 50  0000 C CNN
-F 1 "13k" H 2475 3350 50  0000 C CNN
-F 2 "" H 2475 3280 30  0000 C CNN
-F 3 "" V 2475 3350 30  0000 C CNN
-	1    2425 3300
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q2
-U 1 1 5C9DBA96
-P 925 3950
-F 0 "Q2" H 825 4000 50  0000 R CNN
-F 1 "eSim_NPN" H 875 4100 50  0000 R CNN
-F 2 "" H 1125 4050 29  0000 C CNN
-F 3 "" H 925 3950 60  0000 C CNN
-	1    925  3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 5C9DBADD
-P 1950 3950
-F 0 "Q8" H 1850 4000 50  0000 R CNN
-F 1 "eSim_NPN" H 1900 4100 50  0000 R CNN
-F 2 "" H 2150 4050 29  0000 C CNN
-F 3 "" H 1950 3950 60  0000 C CNN
-	1    1950 3950
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q6
-U 1 1 5C9DBDEB
-P 1525 4850
-F 0 "Q6" H 1425 4900 50  0000 R CNN
-F 1 "eSim_NPN" H 1475 5000 50  0000 R CNN
-F 2 "" H 1725 4950 29  0000 C CNN
-F 3 "" H 1525 4850 60  0000 C CNN
-	1    1525 4850
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5C9DBE93
-P 1375 5300
-F 0 "R2" H 1425 5430 50  0000 C CNN
-F 1 "200" H 1425 5350 50  0000 C CNN
-F 2 "" H 1425 5280 30  0000 C CNN
-F 3 "" V 1425 5350 30  0000 C CNN
-	1    1375 5300
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R8
-U 1 1 5C9DC899
-P 2925 3200
-F 0 "R8" H 2975 3330 50  0000 C CNN
-F 1 "8.1K" H 2975 3250 50  0000 C CNN
-F 2 "" H 2975 3180 30  0000 C CNN
-F 3 "" V 2975 3250 30  0000 C CNN
-	1    2925 3200
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5C9DD1D1
-P 3225 3150
-F 0 "R10" H 3275 3280 50  0000 C CNN
-F 1 "1K" H 3275 3200 50  0000 C CNN
-F 2 "" H 3275 3130 30  0000 C CNN
-F 3 "" V 3275 3200 30  0000 C CNN
-	1    3225 3150
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R13
-U 1 1 5C9DD2D0
-P 3700 3150
-F 0 "R13" H 3750 3280 50  0000 C CNN
-F 1 "1K" H 3750 3200 50  0000 C CNN
-F 2 "" H 3750 3130 30  0000 C CNN
-F 3 "" V 3750 3200 30  0000 C CNN
-	1    3700 3150
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q13
-U 1 1 5C9DCD03
-P 3450 4850
-F 0 "Q13" H 3350 4900 50  0000 R CNN
-F 1 "eSim_NPN" H 3400 5000 50  0000 R CNN
-F 2 "" H 3650 4950 29  0000 C CNN
-F 3 "" H 3450 4850 60  0000 C CNN
-	1    3450 4850
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q11
-U 1 1 5C9DCCAE
-P 2875 4850
-F 0 "Q11" H 2775 4900 50  0000 R CNN
-F 1 "eSim_NPN" H 2825 5000 50  0000 R CNN
-F 2 "" H 3075 4950 29  0000 C CNN
-F 3 "" H 2875 4850 60  0000 C CNN
-	1    2875 4850
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5C9DDAF5
-P 2925 5375
-F 0 "R9" H 2975 5505 50  0000 C CNN
-F 1 "200" H 2975 5425 50  0000 C CNN
-F 2 "" H 2975 5355 30  0000 C CNN
-F 3 "" V 2975 5425 30  0000 C CNN
-	1    2925 5375
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9DDB52
-P 3500 5400
-F 0 "R11" H 3550 5530 50  0000 C CNN
-F 1 "205" H 3550 5450 50  0000 C CNN
-F 2 "" H 3550 5380 30  0000 C CNN
-F 3 "" V 3550 5450 30  0000 C CNN
-	1    3500 5400
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q16
-U 1 1 5C9DE652
-P 4525 1150
-F 0 "Q16" H 4425 1200 50  0000 R CNN
-F 1 "eSim_NPN" H 4475 1300 50  0000 R CNN
-F 2 "" H 4725 1250 29  0000 C CNN
-F 3 "" H 4525 1150 60  0000 C CNN
-	1    4525 1150
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9DF30A
-P 4725 2200
-F 0 "Q18" H 4625 2250 50  0000 R CNN
-F 1 "eSim_NPN" H 4675 2350 50  0000 R CNN
-F 2 "" H 4925 2300 29  0000 C CNN
-F 3 "" H 4725 2200 60  0000 C CNN
-	1    4725 2200
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q20
-U 1 1 5C9DF387
-P 5150 2200
-F 0 "Q20" H 5050 2250 50  0000 R CNN
-F 1 "eSim_NPN" H 5100 2350 50  0000 R CNN
-F 2 "" H 5350 2300 29  0000 C CNN
-F 3 "" H 5150 2200 60  0000 C CNN
-	1    5150 2200
-	1    0    0    -1  
-$EndComp
-NoConn ~ 4200 1550
-$Comp
-L eSim_NPN Q17
-U 1 1 5C9E05DE
-P 4525 2900
-F 0 "Q17" H 4425 2950 50  0000 R CNN
-F 1 "eSim_NPN" H 4475 3050 50  0000 R CNN
-F 2 "" H 4725 3000 29  0000 C CNN
-F 3 "" H 4525 2900 60  0000 C CNN
-	1    4525 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_PNP Q21
-U 1 1 5C9E063F
-P 5150 2900
-F 0 "Q21" H 5050 2950 50  0000 R CNN
-F 1 "eSim_PNP" H 5100 3050 50  0000 R CNN
-F 2 "" H 5350 3000 29  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    1   
-$EndComp
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-	900  1175 900  2900
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-	900  1400 1050 1400
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-	1450 1400 4050 1400
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-	1600 1400 1600 1175
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-	900  2000 1250 2000
-Connection ~ 900  1400
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-	900  2300 1050 2300
-Connection ~ 900  2000
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-	900  875  2975 875 
-Connection ~ 2475 875 
-Connection ~ 2225 875 
-Connection ~ 1600 875 
-Wire Wire Line
-	1925 1075 1925 1275
-Wire Wire Line
-	1925 1275 2475 1275
-Wire Wire Line
-	2475 1175 2475 3200
-Connection ~ 2225 1275
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-	2975 1175 2975 2000
-Wire Wire Line
-	2975 1325 2725 1325
-Wire Wire Line
-	2725 1325 2725 775 
-Connection ~ 2975 1325
-Wire Wire Line
-	2225 875  2225 775 
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-	3275 2325 3275 875 
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-	2950 875  9575 875 
-Connection ~ 2950 875 
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-	3750 875  3750 900 
-Connection ~ 3275 875 
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-	3750 1200 3750 2325
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-	4050 1400 4050 2525
-Connection ~ 1600 1400
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-	1250 1700 1800 1700
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-	1800 1400 1800 2650
-Connection ~ 1800 1400
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-	1800 2300 1450 2300
-Connection ~ 1800 1700
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-	900  2525 2975 2525
-Connection ~ 900  2300
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-	1425 3100 1400 3100
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-	1725 3300 1950 3300
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-	900  3300 1100 3300
-Connection ~ 900  2525
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-	1800 2650 1950 2650
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-	1950 2650 1950 2900
-Connection ~ 1800 2300
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-	1800 2600 1100 2600
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-	1100 2600 1100 2900
-Connection ~ 1800 2600
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-	1725 2900 1725 2525
-Connection ~ 1725 2525
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-	1425 2800 2475 2800
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-	1425 2800 1425 3100
-Connection ~ 2475 2800
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-	2250 3100 2350 3100
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-	2350 2975 2350 3525
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-	2350 3525 525  3525
-Wire Wire Line
-	525  3525 525  3100
-Wire Wire Line
-	525  3100 600  3100
-Wire Wire Line
-	1025 3750 1025 3300
-Connection ~ 1025 3300
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-	1850 3750 1850 3300
-Connection ~ 1850 3300
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-	1025 4150 1850 4150
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-	2150 3950 2150 4425
-Wire Wire Line
-	1425 4650 1425 4150
-Connection ~ 1425 4150
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-	1425 5050 1425 5200
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-	2475 3500 2475 6000
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-	1425 6000 9575 6000
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-	1425 6000 1425 5500
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-	2975 2300 2975 3100
-Wire Wire Line
-	2975 2975 2350 2975
-Connection ~ 2350 3100
-Connection ~ 2975 2975
-Wire Wire Line
-	3750 3050 3750 2725
-Wire Wire Line
-	3275 2725 3275 3050
-Wire Wire Line
-	3275 3350 3275 3450
-Wire Wire Line
-	3275 3450 3750 3450
-Wire Wire Line
-	3750 3450 3750 3350
-Connection ~ 3550 3450
-Wire Wire Line
-	3550 3450 3550 4650
-Connection ~ 2975 4525
-Wire Wire Line
-	2675 4850 2675 4525
-Wire Wire Line
-	2675 4525 2975 4525
-Wire Wire Line
-	2975 3400 2975 4650
-Connection ~ 2675 4850
-Wire Wire Line
-	1725 4850 3250 4850
-Wire Wire Line
-	2975 5050 2975 5275
-Wire Wire Line
-	3550 5050 3550 5300
-Wire Wire Line
-	2975 6000 2975 5575
-Connection ~ 2475 6000
-Wire Wire Line
-	3550 6000 3550 5600
-Connection ~ 2975 6000
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-	4500 1350 4950 1350
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-	3950 1150 4325 1150
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-	3950 800  3950 1225
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-	3950 1225 3750 1225
-Connection ~ 3750 1225
-Connection ~ 4200 1150
-Connection ~ 3950 1150
-Wire Wire Line
-	4625 950  5250 950 
-Connection ~ 4625 1350
-Wire Wire Line
-	4900 950  4900 800 
-Connection ~ 4900 950 
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-	4950 2200 4925 2200
-Wire Wire Line
-	5250 950  5250 1150
-Wire Wire Line
-	5250 1550 5250 2000
-Wire Wire Line
-	4625 1350 4625 2000
-Wire Wire Line
-	5250 1800 4925 1800
-Wire Wire Line
-	4925 1800 4925 2200
-Connection ~ 5250 1800
-Wire Wire Line
-	4625 2400 4625 2700
-Wire Wire Line
-	5250 2400 5250 2700
-Wire Wire Line
-	4225 2550 5250 2550
-Connection ~ 4625 2550
-Connection ~ 5250 2550
-Wire Wire Line
-	4225 2550 4225 2900
-Wire Wire Line
-	4225 2900 4325 2900
-Wire Wire Line
-	5250 3100 5250 3525
-Wire Wire Line
-	5575 3200 4900 3200
-Wire Wire Line
-	4900 3200 4900 2900
-Wire Wire Line
-	4900 2900 4950 2900
-Wire Wire Line
-	5575 800  5575 3200
-Connection ~ 5250 3200
-$Comp
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-U 1 1 5C9E12AB
-P 5150 3725
-F 0 "Q22" H 5050 3775 50  0000 R CNN
-F 1 "eSim_NPN" H 5100 3875 50  0000 R CNN
-F 2 "" H 5350 3825 29  0000 C CNN
-F 3 "" H 5150 3725 60  0000 C CNN
-	1    5150 3725
-	1    0    0    -1  
-$EndComp
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-	4950 3725 4625 3725
-Wire Wire Line
-	4625 3100 4625 4625
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9E1696
-P 4725 4825
-F 0 "Q19" H 4625 4875 50  0000 R CNN
-F 1 "eSim_NPN" H 4675 4975 50  0000 R CNN
-F 2 "" H 4925 4925 29  0000 C CNN
-F 3 "" H 4725 4825 60  0000 C CNN
-	1    4725 4825
-	-1   0    0    -1  
-$EndComp
-Connection ~ 4625 3725
-$Comp
-L eSim_NPN Q23
-U 1 1 5C9E190B
-P 5150 4825
-F 0 "Q23" H 5050 4875 50  0000 R CNN
-F 1 "eSim_NPN" H 5100 4975 50  0000 R CNN
-F 2 "" H 5350 4925 29  0000 C CNN
-F 3 "" H 5150 4825 60  0000 C CNN
-	1    5150 4825
-	1    0    0    -1  
-$EndComp
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-	4950 4825 4925 4825
-Wire Wire Line
-	5250 3925 5250 4625
-Wire Wire Line
-	5250 4275 4925 4275
-Wire Wire Line
-	4925 4275 4925 4825
-Connection ~ 5250 4275
-$Comp
-L eSim_R R14
-U 1 1 5C9E1F6D
-P 4575 5350
-F 0 "R14" H 4625 5480 50  0000 C CNN
-F 1 "530" H 4625 5400 50  0000 C CNN
-F 2 "" H 4625 5330 30  0000 C CNN
-F 3 "" V 4625 5400 30  0000 C CNN
-	1    4575 5350
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R15
-U 1 1 5C9E219A
-P 5200 5350
-F 0 "R15" H 5250 5480 50  0000 C CNN
-F 1 "530" H 5250 5400 50  0000 C CNN
-F 2 "" H 5250 5330 30  0000 C CNN
-F 3 "" V 5250 5400 30  0000 C CNN
-	1    5200 5350
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q25
-U 1 1 5C9E2EDE
-P 6050 1400
-F 0 "Q25" H 5950 1450 50  0000 R CNN
-F 1 "eSim_NPN" H 6000 1550 50  0000 R CNN
-F 2 "" H 6250 1500 29  0000 C CNN
-F 3 "" H 6050 1400 60  0000 C CNN
-	1    6050 1400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5850 1400 5575 1400
-Connection ~ 5575 1400
-$Comp
-L eSim_R R17
-U 1 1 5C9E3164
-P 6800 1350
-F 0 "R17" H 6850 1480 50  0000 C CNN
-F 1 "6.5K" H 6850 1400 50  0000 C CNN
-F 2 "" H 6850 1330 30  0000 C CNN
-F 3 "" V 6850 1400 30  0000 C CNN
-	1    6800 1350
-	0    1    1    0   
-$EndComp
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-	6850 800  6850 1250
-Wire Wire Line
-	6850 975  6150 975 
-Wire Wire Line
-	6150 975  6150 1200
-Connection ~ 6850 975 
-Connection ~ 6850 875 
-Connection ~ 3750 875 
-$Comp
-L eSim_PNP Q28
-U 1 1 5C9E3F7F
-P 6525 1875
-F 0 "Q28" H 6425 1925 50  0000 R CNN
-F 1 "eSim_PNP" H 6475 2025 50  0000 R CNN
-F 2 "" H 6725 1975 29  0000 C CNN
-F 3 "" H 6525 1875 60  0000 C CNN
-	1    6525 1875
-	0    1    -1   0   
-$EndComp
-Wire Wire Line
-	6325 1775 6150 1775
-Wire Wire Line
-	6150 1600 6150 4625
-$Comp
-L eSim_NPN Q27
-U 1 1 5C9E4448
-P 6350 2500
-F 0 "Q27" H 6250 2550 50  0000 R CNN
-F 1 "eSim_NPN" H 6300 2650 50  0000 R CNN
-F 2 "" H 6550 2600 29  0000 C CNN
-F 3 "" H 6350 2500 60  0000 C CNN
-	1    6350 2500
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q30
-U 1 1 5C9E4653
-P 6750 2750
-F 0 "Q30" H 6650 2800 50  0000 R CNN
-F 1 "eSim_NPN" H 6700 2900 50  0000 R CNN
-F 2 "" H 6950 2850 29  0000 C CNN
-F 3 "" H 6750 2750 60  0000 C CNN
-	1    6750 2750
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6550 2750 6450 2750
-Wire Wire Line
-	6450 2750 6450 2700
-Connection ~ 6150 1775
-$Comp
-L eSim_NPN Q31
-U 1 1 5C9E49F3
-P 7075 2350
-F 0 "Q31" H 6975 2400 50  0000 R CNN
-F 1 "eSim_NPN" H 7025 2500 50  0000 R CNN
-F 2 "" H 7275 2450 29  0000 C CNN
-F 3 "" H 7075 2350 60  0000 C CNN
-	1    7075 2350
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_PNP Q32
-U 1 1 5C9E4B46
-P 7125 1875
-F 0 "Q32" H 7025 1925 50  0000 R CNN
-F 1 "eSim_PNP" H 7075 2025 50  0000 R CNN
-F 2 "" H 7325 1975 29  0000 C CNN
-F 3 "" H 7125 1875 60  0000 C CNN
-	1    7125 1875
-	0    1    -1   0   
-$EndComp
-Wire Wire Line
-	6850 1550 6850 2550
-Wire Wire Line
-	6725 1775 6925 1775
-Connection ~ 6850 1775
-$Comp
-L eSim_R R19
-U 1 1 5C9E5284
-P 7400 1225
-F 0 "R19" H 7450 1355 50  0000 C CNN
-F 1 "4.7k" H 7450 1275 50  0000 C CNN
-F 2 "" H 7450 1205 30  0000 C CNN
-F 3 "" V 7450 1275 30  0000 C CNN
-	1    7400 1225
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	7450 1425 7450 2350
-Wire Wire Line
-	7325 1775 7625 1775
-Wire Wire Line
-	7450 2075 7125 2075
-Connection ~ 7450 1775
-$Comp
-L eSim_NPN Q33
-U 1 1 5C9E59CA
-P 7375 2725
-F 0 "Q33" H 7275 2775 50  0000 R CNN
-F 1 "eSim_NPN" H 7325 2875 50  0000 R CNN
-F 2 "" H 7575 2825 29  0000 C CNN
-F 3 "" H 7375 2725 60  0000 C CNN
-	1    7375 2725
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7450 2350 7475 2350
-Wire Wire Line
-	7475 2350 7475 2525
-Connection ~ 7450 2075
-Wire Wire Line
-	7175 2550 7175 3000
-$Comp
-L eSim_R R18
-U 1 1 5C9E62BC
-P 7125 3100
-F 0 "R18" H 7175 3230 50  0000 C CNN
-F 1 "8.4K" H 7175 3150 50  0000 C CNN
-F 2 "" H 7175 3080 30  0000 C CNN
-F 3 "" V 7175 3150 30  0000 C CNN
-	1    7125 3100
-	0    1    1    0   
-$EndComp
-Connection ~ 7175 2725
-Wire Wire Line
-	6850 2950 6850 3300
-Wire Wire Line
-	6850 3300 7475 3300
-Wire Wire Line
-	7475 2925 7475 3600
-Connection ~ 7175 3300
-Wire Wire Line
-	7450 875  7450 1125
-$Comp
-L eSim_NPN Q35
-U 1 1 5C9E6F03
-P 7825 1775
-F 0 "Q35" H 7725 1825 50  0000 R CNN
-F 1 "eSim_NPN" H 7775 1925 50  0000 R CNN
-F 2 "" H 8025 1875 29  0000 C CNN
-F 3 "" H 7825 1775 60  0000 C CNN
-	1    7825 1775
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7925 875  7925 1575
-Connection ~ 7450 875 
-$Comp
-L eSim_R R20
-U 1 1 5C9E7FB4
-P 7425 3700
-F 0 "R20" H 7475 3830 50  0000 C CNN
-F 1 "2.6K" H 7475 3750 50  0000 C CNN
-F 2 "" H 7475 3680 30  0000 C CNN
-F 3 "" V 7475 3750 30  0000 C CNN
-	1    7425 3700
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R22
-U 1 1 5C9E803D
-P 7875 3675
-F 0 "R22" H 7925 3805 50  0000 C CNN
-F 1 "4.8K" H 7925 3725 50  0000 C CNN
-F 2 "" H 7925 3655 30  0000 C CNN
-F 3 "" V 7925 3725 30  0000 C CNN
-	1    7875 3675
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	7925 1975 7925 3575
-Connection ~ 7475 3300
-$Comp
-L eSim_NPN Q24
-U 1 1 5C9E8FD5
-P 5650 5800
-F 0 "Q24" H 5550 5850 50  0000 R CNN
-F 1 "eSim_NPN" H 5600 5950 50  0000 R CNN
-F 2 "" H 5850 5900 29  0000 C CNN
-F 3 "" H 5650 5800 60  0000 C CNN
-	1    5650 5800
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	5250 5025 5250 5250
-Wire Wire Line
-	4625 5025 4625 5250
-Wire Wire Line
-	5250 5550 5250 5650
-Wire Wire Line
-	5250 5650 4625 5650
-Wire Wire Line
-	4625 5650 4625 5550
-Connection ~ 3550 6000
-Wire Wire Line
-	5550 5600 5250 5600
-Connection ~ 5250 5600
-$Comp
-L eSim_PNP Q26
-U 1 1 5C9EA5DE
-P 6150 4925
-F 0 "Q26" H 6050 4975 50  0000 R CNN
-F 1 "eSim_PNP" H 6100 5075 50  0000 R CNN
-F 2 "" H 6350 5025 29  0000 C CNN
-F 3 "" H 6150 4925 60  0000 C CNN
-	1    6150 4925
-	0    -1   -1   0   
-$EndComp
-Wire Wire Line
-	5950 4825 5550 4825
-Wire Wire Line
-	5550 4825 5550 5600
-Wire Wire Line
-	6150 5125 6150 5250
-Wire Wire Line
-	6150 5250 5550 5250
-Connection ~ 5550 5250
-$Comp
-L eSim_R R16
-U 1 1 5C9EA881
-P 6100 5800
-F 0 "R16" H 6150 5930 50  0000 C CNN
-F 1 "7K" H 6150 5850 50  0000 C CNN
-F 2 "" H 6150 5780 30  0000 C CNN
-F 3 "" V 6150 5850 30  0000 C CNN
-	1    6100 5800
-	0    1    1    0   
-$EndComp
-Connection ~ 5550 6000
-Wire Wire Line
-	5850 5800 5850 5575
-Wire Wire Line
-	5850 5575 6150 5575
-Wire Wire Line
-	6150 5575 6150 5700
-$Comp
-L eSim_NPN Q29
-U 1 1 5C9EAB2D
-P 6725 5400
-F 0 "Q29" H 6625 5450 50  0000 R CNN
-F 1 "eSim_NPN" H 6675 5550 50  0000 R CNN
-F 2 "" H 6925 5500 29  0000 C CNN
-F 3 "" H 6725 5400 60  0000 C CNN
-	1    6725 5400
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	6625 5600 6150 5600
-Connection ~ 6150 5600
-Wire Wire Line
-	6625 5200 6625 4825
-Wire Wire Line
-	6350 4825 9075 4825
-Wire Wire Line
-	6925 5400 7000 5400
-Wire Wire Line
-	7000 5400 7000 4825
-Connection ~ 6625 4825
-$Comp
-L eSim_NPN Q34
-U 1 1 5C9EB3F8
-P 7625 5075
-F 0 "Q34" H 7525 5125 50  0000 R CNN
-F 1 "eSim_NPN" H 7575 5225 50  0000 R CNN
-F 2 "" H 7825 5175 29  0000 C CNN
-F 3 "" H 7625 5075 60  0000 C CNN
-	1    7625 5075
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_R R21
-U 1 1 5C9EB4C7
-P 7475 5750
-F 0 "R21" H 7525 5880 50  0000 C CNN
-F 1 "2.4K" H 7525 5800 50  0000 C CNN
-F 2 "" H 7525 5730 30  0000 C CNN
-F 3 "" V 7525 5800 30  0000 C CNN
-	1    7475 5750
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	7525 5275 7525 5650
-Wire Wire Line
-	7525 6000 7525 5950
-Connection ~ 6150 6000
-Wire Wire Line
-	7525 4875 7525 4625
-Wire Wire Line
-	7525 4625 6150 4625
-Connection ~ 6150 2500
-NoConn ~ 6450 2300
-NoConn ~ 7175 2150
-Wire Wire Line
-	7475 3900 7475 4425
-Wire Wire Line
-	7475 4425 7875 4425
-Wire Wire Line
-	7875 4425 7875 6000
-Connection ~ 7525 6000
-Wire Wire Line
-	7925 6000 7925 3875
-Connection ~ 7875 6000
-$Comp
-L eSim_PNP Q36
-U 1 1 5C9EEDA4
-P 8475 2300
-F 0 "Q36" H 8375 2350 50  0000 R CNN
-F 1 "eSim_PNP" H 8425 2450 50  0000 R CNN
-F 2 "" H 8675 2400 29  0000 C CNN
-F 3 "" H 8475 2300 60  0000 C CNN
-	1    8475 2300
-	1    0    0    1   
-$EndComp
-Wire Wire Line
-	7925 2300 8275 2300
-Connection ~ 7925 2300
-Wire Wire Line
-	8575 2500 8575 6275
-Connection ~ 7925 6000
-$Comp
-L eSim_PNP Q38
-U 1 1 5C9F04CE
-P 9175 2300
-F 0 "Q38" H 9075 2350 50  0000 R CNN
-F 1 "eSim_PNP" H 9125 2450 50  0000 R CNN
-F 2 "" H 9375 2400 29  0000 C CNN
-F 3 "" H 9175 2300 60  0000 C CNN
-	1    9175 2300
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	8575 2100 9075 2100
-$Comp
-L eSim_R R23
-U 1 1 5C9F0909
-P 8800 1275
-F 0 "R23" H 8850 1405 50  0000 C CNN
-F 1 "16K" H 8850 1325 50  0000 C CNN
-F 2 "" H 8850 1255 30  0000 C CNN
-F 3 "" V 8850 1325 30  0000 C CNN
-	1    8800 1275
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	8850 1475 8850 2625
-Connection ~ 8850 2100
-Wire Wire Line
-	8850 875  8850 1175
-Connection ~ 7925 875 
-Wire Wire Line
-	8175 2300 8175 800 
-Connection ~ 8175 2300
-$Comp
-L eSim_R R24
-U 1 1 5C9F1F80
-P 9025 3775
-F 0 "R24" H 9075 3905 50  0000 C CNN
-F 1 "5.8k" H 9075 3825 50  0000 C CNN
-F 2 "" H 9075 3755 30  0000 C CNN
-F 3 "" V 9075 3825 30  0000 C CNN
-	1    9025 3775
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	9075 2500 9075 3675
-Connection ~ 8575 6000
-$Comp
-L eSim_NPN Q37
-U 1 1 5C9F3715
-P 8850 3025
-F 0 "Q37" H 8750 3075 50  0000 R CNN
-F 1 "eSim_NPN" H 8800 3175 50  0000 R CNN
-F 2 "" H 9050 3125 29  0000 C CNN
-F 3 "" H 8850 3025 60  0000 C CNN
-	1    8850 3025
-	-1   0    0    -1  
-$EndComp
-Wire Wire Line
-	8750 2825 8750 2625
-Wire Wire Line
-	8750 2625 8850 2625
-Wire Wire Line
-	9075 3025 9050 3025
-Connection ~ 9075 3025
-Wire Wire Line
-	9075 4825 9075 3975
-Connection ~ 7000 4825
-Wire Wire Line
-	8750 3225 8750 4825
-Connection ~ 8750 4825
-$Comp
-L eSim_NPN Q40
-U 1 1 5C9F5A03
-P 9475 5100
-F 0 "Q40" H 9375 5150 50  0000 R CNN
-F 1 "eSim_NPN" H 9425 5250 50  0000 R CNN
-F 2 "" H 9675 5200 29  0000 C CNN
-F 3 "" H 9475 5100 60  0000 C CNN
-	1    9475 5100
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	7825 5100 9275 5100
-Wire Wire Line
-	7825 5100 7825 5075
-$Comp
-L eSim_R R26
-U 1 1 5C9F5D68
-P 9525 5600
-F 0 "R26" H 9575 5730 50  0000 C CNN
-F 1 "200" H 9575 5650 50  0000 C CNN
-F 2 "" H 9575 5580 30  0000 C CNN
-F 3 "" V 9575 5650 30  0000 C CNN
-	1    9525 5600
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	9575 5300 9575 5500
-Wire Wire Line
-	9575 6000 9575 5800
-Wire Wire Line
-	9575 1300 9575 4900
-Wire Wire Line
-	9575 2300 9375 2300
-$Comp
-L eSim_R R25
-U 1 1 5C9F78A7
-P 9525 1100
-F 0 "R25" H 9575 1230 50  0000 C CNN
-F 1 "4.3k" H 9575 1150 50  0000 C CNN
-F 2 "" H 9575 1080 30  0000 C CNN
-F 3 "" V 9575 1150 30  0000 C CNN
-	1    9525 1100
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	9575 875  9575 1000
-Connection ~ 8850 875 
-Connection ~ 9575 2300
-$Comp
-L eSim_NPN Q39
-U 1 1 5C9F7E6C
-P 9300 1325
-F 0 "Q39" H 9200 1375 50  0000 R CNN
-F 1 "eSim_NPN" H 9250 1475 50  0000 R CNN
-F 2 "" H 9500 1425 29  0000 C CNN
-F 3 "" H 9300 1325 60  0000 C CNN
-	1    9300 1325
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	9200 1125 9200 875 
-Connection ~ 9200 875 
-Wire Wire Line
-	9500 1325 9575 1325
-Connection ~ 9575 1325
-NoConn ~ 9200 1525
-Wire Wire Line
-	8375 5100 8375 6275
-Wire Wire Line
-	8375 6275 1975 6275
-Wire Wire Line
-	1975 6275 1975 4850
-Connection ~ 1975 4850
-Connection ~ 8375 5100
-$Comp
-L PORT U1
-U 1 1 5C9FA174
-P 8575 6525
-F 0 "U1" H 8625 6625 30  0000 C CNN
-F 1 "PORT" H 8575 6525 30  0000 C CNN
-F 2 "" H 8575 6525 60  0000 C CNN
-F 3 "" H 8575 6525 60  0000 C CNN
-	1    8575 6525
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9FBFA4
-P 475 3950
-F 0 "U1" H 525 4050 30  0000 C CNN
-F 1 "PORT" H 475 3950 30  0000 C CNN
-F 2 "" H 475 3950 60  0000 C CNN
-F 3 "" H 475 3950 60  0000 C CNN
-	3    475  3950
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9FC1B0
-P 600 4425
-F 0 "U1" H 650 4525 30  0000 C CNN
-F 1 "PORT" H 600 4425 30  0000 C CNN
-F 2 "" H 600 4425 60  0000 C CNN
-F 3 "" H 600 4425 60  0000 C CNN
-	2    600  4425
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2150 4425 850  4425
-$Comp
-L PORT U1
-U 5 1 5C9FD8AC
-P 2225 525
-F 0 "U1" H 2275 625 30  0000 C CNN
-F 1 "PORT" H 2225 525 30  0000 C CNN
-F 2 "" H 2225 525 60  0000 C CNN
-F 3 "" H 2225 525 60  0000 C CNN
-	5    2225 525 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9FD96B
-P 2725 525
-F 0 "U1" H 2775 625 30  0000 C CNN
-F 1 "PORT" H 2725 525 30  0000 C CNN
-F 2 "" H 2725 525 60  0000 C CNN
-F 3 "" H 2725 525 60  0000 C CNN
-	6    2725 525 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C9FDA44
-P 3950 550
-F 0 "U1" H 4000 650 30  0000 C CNN
-F 1 "PORT" H 3950 550 30  0000 C CNN
-F 2 "" H 3950 550 60  0000 C CNN
-F 3 "" H 3950 550 60  0000 C CNN
-	7    3950 550 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9FDAFF
-P 4900 550
-F 0 "U1" H 4950 650 30  0000 C CNN
-F 1 "PORT" H 4900 550 30  0000 C CNN
-F 2 "" H 4900 550 60  0000 C CNN
-F 3 "" H 4900 550 60  0000 C CNN
-	8    4900 550 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C9FDBB4
-P 5575 550
-F 0 "U1" H 5625 650 30  0000 C CNN
-F 1 "PORT" H 5575 550 30  0000 C CNN
-F 2 "" H 5575 550 60  0000 C CNN
-F 3 "" H 5575 550 60  0000 C CNN
-	9    5575 550 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C9FDC77
-P 6850 550
-F 0 "U1" H 6900 650 30  0000 C CNN
-F 1 "PORT" H 6850 550 30  0000 C CNN
-F 2 "" H 6850 550 60  0000 C CNN
-F 3 "" H 6850 550 60  0000 C CNN
-	10   6850 550 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9FE0D8
-P 8175 550
-F 0 "U1" H 8225 650 30  0000 C CNN
-F 1 "PORT" H 8175 550 30  0000 C CNN
-F 2 "" H 8175 550 60  0000 C CNN
-F 3 "" H 8175 550 60  0000 C CNN
-	4    8175 550 
-	0    1    1    0   
-$EndComp
-Text GLabel 2125 775  0    60   Input ~ 0
-Phase_comparator_vco_input
-Wire Wire Line
-	2225 775  2125 775 
-Text GLabel 2775 775  2    60   Input ~ 0
-Reference_output
-Wire Wire Line
-	2725 775  2775 775 
-Text GLabel 3975 800  2    55   Input ~ 0
-Vco_control_voltage
-Wire Wire Line
-	3975 800  3950 800 
-Text GLabel 4900 800  2    39   Input ~ 0
-Timming_resistor
-Text GLabel 5575 800  2    39   Input ~ 0
-Timing_capacitor
-Text GLabel 6850 800  0    39   Input ~ 0
-+Vcc
-Text GLabel 8175 800  0    39   Input ~ 0
-Vco_output
-Text GLabel 8575 6275 2    39   Input ~ 0
--Vcc
-Text GLabel 675  4075 0    39   Input ~ 0
-Input
-Wire Wire Line
-	675  4075 725  4075
-Wire Wire Line
-	725  4075 725  3950
-Text GLabel 850  4250 0    39   Input ~ 0
-Input
-Wire Wire Line
-	850  4250 875  4250
-Wire Wire Line
-	875  4250 875  4425
-Connection ~ 875  4425
-Wire Wire Line
-	6525 2350 6525 2075
-Wire Wire Line
-	6525 2350 6875 2350
-Connection ~ 6850 2350
-$Comp
-L eSim_NPN Q15
-U 1 1 5CA0DF1A
-P 4300 1350
-F 0 "Q15" H 4200 1400 50  0000 R CNN
-F 1 "eSim_NPN" H 4250 1500 50  0000 R CNN
-F 2 "" H 4500 1450 29  0000 C CNN
-F 3 "" H 4300 1350 60  0000 C CNN
-	1    4300 1350
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_PNP Q41
-U 1 1 5CA0E6BE
-P 5150 1350
-F 0 "Q41" H 5050 1400 50  0000 R CNN
-F 1 "eSim_PNP" H 5100 1500 50  0000 R CNN
-F 2 "" H 5350 1450 29  0000 C CNN
-F 3 "" H 5150 1350 60  0000 C CNN
-	1    5150 1350
-	1    0    0    1   
-$EndComp
-$Comp
-L PWR_FLAG #FLG01
-U 1 1 5CA131E0
-P 2300 3950
-F 0 "#FLG01" H 2300 4045 50  0001 C CNN
-F 1 "PWR_FLAG" H 2300 4130 50  0000 C CNN
-F 2 "" H 2300 3950 50  0000 C CNN
-F 3 "" H 2300 3950 50  0000 C CNN
-	1    2300 3950
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2150 3950 2300 3950
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM565/LM565.sub b/src/SubcircuitLibrary/LM565/LM565.sub
deleted file mode 100644
index 31747d1e..00000000
--- a/src/SubcircuitLibrary/LM565/LM565.sub
+++ /dev/null
@@ -1,75 +0,0 @@
-* Subcircuit LM565
-.subckt LM565 -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc 
-* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir
-.include PNP.lib
-.include NPN.lib
-r1  +vcc net-_q1-pad1_ 7.2k
-r3  +vcc net-_q14-pad2_ 7.2k
-q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222
-q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222
-r4  +vcc net-_q3-pad2_ 5.7k
-r6  +vcc reference_output 1.75k
-r7  reference_output net-_q1-pad2_ 3.8k
-q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222
-q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222
-r12  +vcc vco_control_voltage 3.6k
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222
-r5  net-_q3-pad2_ -vcc 13k
-q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222
-q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222
-q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222
-r2  net-_q6-pad3_ -vcc 200
-r8  net-_q1-pad2_ net-_q11-pad1_ 8.1k
-r10  net-_q12-pad3_ net-_q13-pad1_ 1k
-r13  net-_q14-pad3_ net-_q13-pad1_ 1k
-q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222
-r9  net-_q11-pad3_ -vcc 200
-r11  net-_q13-pad3_ -vcc 205
-q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222
-q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222
-q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A
-q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222
-q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
-q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222
-r14  net-_q19-pad3_ net-_q24-pad1_ 530
-r15  net-_q23-pad3_ net-_q24-pad1_ 530
-q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222
-r17  +vcc net-_q28-pad1_ 6.5k
-q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A
-q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222
-q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222
-q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222
-q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A
-r19  +vcc net-_q32-pad1_ 4.7k
-q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222
-r18  net-_q31-pad3_ net-_q30-pad3_ 8.4k
-q35 +vcc net-_q32-pad1_ vco_output Q2N2222
-r20  net-_q30-pad3_ -vcc 2.6k
-r22  vco_output -vcc 4.8k
-q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222
-q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A
-r16  net-_q24-pad2_ -vcc 7k
-q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222
-q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222
-r21  net-_q34-pad3_ -vcc 2.4k
-q36 -vcc vco_output net-_q36-pad3_ Q2N2907A
-q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A
-r23  +vcc net-_q36-pad3_ 16k
-r24  net-_q37-pad2_ net-_q26-pad3_ 5.8k
-q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222
-q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222
-r26  net-_q40-pad3_ -vcc 200
-r25  +vcc net-_q38-pad2_ 4.3k
-q39 ? net-_q38-pad2_ +vcc Q2N2222
-q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222
-q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A
-* Control Statements
-
-.ends LM565
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml b/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml
deleted file mode 100644
index c60f46f5..00000000
--- a/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q35><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q35><q40><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q40><q41><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q41><q34><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q34><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q27><q28><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q28><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q33><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q33><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><q39><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q39><q38><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q38><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q32><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q32><q31><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q31><q30><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q30><q37><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q37><q36><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q36></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM565/NPN.lib b/src/SubcircuitLibrary/LM565/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/LM565/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/LM565/PNP.lib b/src/SubcircuitLibrary/LM565/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/LM565/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib
deleted file mode 100644
index c02b3211..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib
+++ /dev/null
@@ -1,135 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-F2 "" -70 0 50 V V C CNN
-F3 "" 0 0 50 H V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S -40 -100 40 100 0 1 10 N
-X ~ 1 0 150 50 D 50 50 1 1 P
-X ~ 2 0 -150 50 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN-RESCUE-LM7812
-#
-DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP-RESCUE-LM7812
-#
-DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# zener
-#
-DEF zener U 0 40 Y Y 1 F N
-F0 "U" -50 -100 60 H V C CNN
-F1 "zener" 0 100 60 H V C CNN
-F2 "" 50 0 60 H V C CNN
-F3 "" 50 0 60 H V C CNN
-DRAW
-P 2 0 1 0 100 -50 50 -100 N
-P 2 0 1 0 100 50 100 -50 N
-P 2 0 1 0 100 50 150 100 N
-P 4 0 1 0 0 50 0 -50 100 0 0 50 N
-X ~ IN -200 0 200 R 50 43 1 1 I
-X ~ OUT 300 0 200 L 50 43 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib
deleted file mode 100644
index e6cfa7d6..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib
+++ /dev/null
@@ -1,42 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# eSim_NPN-RESCUE-LM7812
-#
-DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP-RESCUE-LM7812
-#
-DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir b/src/SubcircuitLibrary/LM7812/LM7812.cir
deleted file mode 100644
index 3f0d3adf..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812.cir
+++ /dev/null
@@ -1,51 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1  Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k		
-R2  Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500		
-R3  Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k		
-R4  Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k		
-U1  Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener		
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-R5  Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500		
-Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q4  Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN		
-R6  Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k		
-Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
-R7  Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k		
-Q6  Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN		
-R10  Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k		
-Q7  Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN		
-Q8  Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN		
-Q12  Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
-R12  Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k		
-R9  Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k		
-Q5  Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP		
-Q9  Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP		
-R8  Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100		
-R11  Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
-Q11  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN		
-Q13  Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN		
-R13  Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
-R14  Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k		
-Q14  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP		
-Q15  Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN		
-R17  Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k		
-R16  Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k		
-R15  Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k		
-U2  Net-_Q15-Pad2_ Net-_R15-Pad2_ zener		
-Q16  Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN		
-Q17  Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN		
-R18  Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200		
-R20  Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3		
-R19  Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240		
-U3  Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir.out b/src/SubcircuitLibrary/LM7812/LM7812.cir.out
deleted file mode 100644
index 73404965..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812.cir.out
+++ /dev/null
@@ -1,60 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir
-
-.include PNP.lib
-.include NPN.lib
-r1  net-_q16-pad1_ net-_q1-pad2_ 100k
-r2  net-_q16-pad1_ net-_q1-pad1_ 500
-r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
-r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
-* u1  net-_q10-pad3_ net-_q1-pad2_ zener
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-r5  net-_q10-pad2_ net-_q10-pad3_ 500
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
-r6  net-_q2-pad3_ net-_q3-pad1_ 1k
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
-r7  net-_q3-pad2_ net-_q10-pad3_ 6k
-q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
-r10  net-_q6-pad3_ net-_q10-pad3_ 1k
-q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
-q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
-q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
-r12  net-_q12-pad3_ net-_q2-pad3_ 6k
-r9  net-_q2-pad3_ net-_c1-pad2_ 20k
-q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
-q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
-r8  net-_q16-pad1_ net-_q5-pad3_ 100
-r11  net-_q16-pad1_ net-_q9-pad3_ 50
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
-q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
-r13  net-_q11-pad3_ net-_q10-pad3_ 6k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-r14  net-_q10-pad1_ net-_c1-pad1_ 6k
-q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
-q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
-r17  net-_q12-pad2_ net-_q10-pad3_ 5k
-r16  net-_q12-pad1_ net-_q12-pad2_ 10.38k
-r15  net-_q16-pad1_ net-_r15-pad2_ 10k
-* u2  net-_q15-pad2_ net-_r15-pad2_ zener
-q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
-q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
-r18  net-_q16-pad3_ net-_q12-pad1_ 200
-r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
-r19  net-_q17-pad3_ net-_q15-pad2_ 240
-* u3  net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port
-a1 net-_q10-pad3_ net-_q1-pad2_ u1
-a2 net-_q15-pad2_ net-_r15-pad2_ u2
-* Schematic Name: zener, NgSpice Name: zener
-.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
-* Schematic Name: zener, NgSpice Name: zener
-.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.pro b/src/SubcircuitLibrary/LM7812/LM7812.pro
deleted file mode 100644
index 12d08139..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812.pro
+++ /dev/null
@@ -1,46 +0,0 @@
-update=Mon Aug 26 14:09:03 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=LM7812-rescue
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
-
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sch b/src/SubcircuitLibrary/LM7812/LM7812.sch
deleted file mode 100644
index ca95c2ca..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812.sch
+++ /dev/null
@@ -1,758 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:LM7812-rescue
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LM7812-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
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-U 1 1 5CE4942E
-P 7300 1950
-F 0 "Q17" H 7200 2000 50  0000 R CNN
-F 1 "eSim_NPN" H 7250 2100 50  0000 R CNN
-F 2 "" H 7500 2050 29  0000 C CNN
-F 3 "" H 7300 1950 60  0000 C CNN
-	1    7300 1950
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	6650 1800 6650 2300
-Wire Wire Line
-	6650 1950 7100 1950
-Wire Wire Line
-	7400 1050 7400 1750
-Connection ~ 5850 1050
-Wire Wire Line
-	6650 1400 6650 1050
-Connection ~ 6650 1050
-$Comp
-L R R18
-U 1 1 5CE498BA
-P 6650 2450
-F 0 "R18" V 6730 2450 50  0000 C CNN
-F 1 "200" V 6650 2450 50  0000 C CNN
-F 2 "" V 6580 2450 50  0001 C CNN
-F 3 "" H 6650 2450 50  0001 C CNN
-	1    6650 2450
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R20
-U 1 1 5CE4999A
-P 7400 2450
-F 0 "R20" V 7480 2450 50  0000 C CNN
-F 1 "0.3" V 7400 2450 50  0000 C CNN
-F 2 "" V 7330 2450 50  0001 C CNN
-F 3 "" H 7400 2450 50  0001 C CNN
-	1    7400 2450
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R19
-U 1 1 5CE49AF5
-P 7000 2250
-F 0 "R19" V 7080 2250 50  0000 C CNN
-F 1 "240" V 7000 2250 50  0000 C CNN
-F 2 "" V 6930 2250 50  0001 C CNN
-F 3 "" H 7000 2250 50  0001 C CNN
-	1    7000 2250
-	0    1    1    0   
-$EndComp
-Connection ~ 6650 1950
-Wire Wire Line
-	5850 2250 6850 2250
-Connection ~ 5850 2150
-Wire Wire Line
-	7400 2150 7400 2300
-Wire Wire Line
-	7150 2250 7400 2250
-Connection ~ 7400 2250
-Wire Wire Line
-	6100 2600 6100 2650
-Wire Wire Line
-	6100 2650 7400 2650
-Wire Wire Line
-	7400 2650 7400 2600
-Connection ~ 6050 2600
-Wire Wire Line
-	6650 2600 6650 2650
-Connection ~ 6650 2650
-$Comp
-L PORT U3
-U 1 1 5CE4AAF6
-P 8050 1050
-F 0 "U3" H 8100 1150 30  0000 C CNN
-F 1 "PORT" H 8050 1050 30  0000 C CNN
-F 2 "" H 8050 1050 60  0000 C CNN
-F 3 "" H 8050 1050 60  0000 C CNN
-	1    8050 1050
-	-1   0    0    1   
-$EndComp
-Connection ~ 7400 1050
-$Comp
-L PORT U3
-U 3 1 5CE4B13E
-P 7700 3000
-F 0 "U3" H 7750 3100 30  0000 C CNN
-F 1 "PORT" H 7700 3000 30  0000 C CNN
-F 2 "" H 7700 3000 60  0000 C CNN
-F 3 "" H 7700 3000 60  0000 C CNN
-	3    7700 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U3
-U 2 1 5CE4B701
-P 6650 5300
-F 0 "U3" H 6700 5400 30  0000 C CNN
-F 1 "PORT" H 6650 5300 30  0000 C CNN
-F 2 "" H 6650 5300 60  0000 C CNN
-F 3 "" H 6650 5300 60  0000 C CNN
-	2    6650 5300
-	-1   0    0    1   
-$EndComp
-Connection ~ 6050 5300
-Wire Wire Line
-	6350 1600 5950 1600
-Wire Wire Line
-	5950 1600 5950 1550
-Wire Wire Line
-	5950 1550 5000 1550
-Wire Wire Line
-	5000 1550 5000 1950
-Connection ~ 5000 1950
-Wire Wire Line
-	7300 2650 7300 3000
-Wire Wire Line
-	7300 3000 7450 3000
-Connection ~ 7300 2650
-Connection ~ 2500 5200
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sub b/src/SubcircuitLibrary/LM7812/LM7812.sub
deleted file mode 100644
index 0dd95154..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812.sub
+++ /dev/null
@@ -1,54 +0,0 @@
-* Subcircuit LM7812
-.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir
-.include PNP.lib
-.include NPN.lib
-r1  net-_q16-pad1_ net-_q1-pad2_ 100k
-r2  net-_q16-pad1_ net-_q1-pad1_ 500
-r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
-r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
-* u1  net-_q10-pad3_ net-_q1-pad2_ zener
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-r5  net-_q10-pad2_ net-_q10-pad3_ 500
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
-r6  net-_q2-pad3_ net-_q3-pad1_ 1k
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
-r7  net-_q3-pad2_ net-_q10-pad3_ 6k
-q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
-r10  net-_q6-pad3_ net-_q10-pad3_ 1k
-q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
-q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
-q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
-r12  net-_q12-pad3_ net-_q2-pad3_ 6k
-r9  net-_q2-pad3_ net-_c1-pad2_ 20k
-q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
-q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
-r8  net-_q16-pad1_ net-_q5-pad3_ 100
-r11  net-_q16-pad1_ net-_q9-pad3_ 50
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
-q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
-r13  net-_q11-pad3_ net-_q10-pad3_ 6k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-r14  net-_q10-pad1_ net-_c1-pad1_ 6k
-q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
-q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
-r17  net-_q12-pad2_ net-_q10-pad3_ 5k
-r16  net-_q12-pad1_ net-_q12-pad2_ 10.38k
-r15  net-_q16-pad1_ net-_r15-pad2_ 10k
-* u2  net-_q15-pad2_ net-_r15-pad2_ zener
-q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
-q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
-r18  net-_q16-pad3_ net-_q12-pad1_ 200
-r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
-r19  net-_q17-pad3_ net-_q15-pad2_ 240
-a1 net-_q10-pad3_ net-_q1-pad2_ u1
-a2 net-_q15-pad2_ net-_r15-pad2_ u2
-* Schematic Name: zener, NgSpice Name: zener
-.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
-* Schematic Name: zener, NgSpice Name: zener
-.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
-* Control Statements
-
-.ends LM7812
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml
deleted file mode 100644
index 263f360c..00000000
--- a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/NPN.lib b/src/SubcircuitLibrary/LM7812/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/LM7812/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/LM7812/PNP.lib b/src/SubcircuitLibrary/LM7812/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/LM7812/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/LM7812/Q_PNP.lib b/src/SubcircuitLibrary/LM7812/Q_PNP.lib
deleted file mode 100644
index 154ed2d8..00000000
--- a/src/SubcircuitLibrary/LM7812/Q_PNP.lib
+++ /dev/null
@@ -1 +0,0 @@
-.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LM7812/analysis b/src/SubcircuitLibrary/LM7812/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/LM7812/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib
deleted file mode 100644
index 34588988..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib
+++ /dev/null
@@ -1,82 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir
deleted file mode 100644
index ec177d39..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  A B Net-_U2-Pad3_ d_and		
-U4  Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and		
-U3  A B Net-_U3-Pad3_ d_xor		
-U5  Net-_U3-Pad3_ CIN SUM d_xor		
-U6  Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or		
-U1  A B CIN SUM CARRY PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out
deleted file mode 100644
index df9bcde6..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out
+++ /dev/null
@@ -1,32 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-
-* u2  a b net-_u2-pad3_ d_and
-* u4  net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3  a b net-_u3-pad3_ d_xor
-* u5  net-_u3-pad3_ cin sum d_xor
-* u6  net-_u2-pad3_ net-_u4-pad3_ carry d_or
-* u1  a b cin sum carry port
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro
deleted file mode 100644
index a2b9fa1f..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Sat Jun  8 13:01:54 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch
deleted file mode 100644
index d39a1b78..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch
+++ /dev/null
@@ -1,245 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LOGIC_ADDER-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5AB647D1
-P 4100 2200
-F 0 "U2" H 4100 2200 60  0000 C CNN
-F 1 "d_and" H 4150 2300 60  0000 C CNN
-F 2 "" H 4100 2200 60  0000 C CNN
-F 3 "" H 4100 2200 60  0000 C CNN
-	1    4100 2200
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5AB648AD
-P 5250 2300
-F 0 "U4" H 5250 2300 60  0000 C CNN
-F 1 "d_and" H 5300 2400 60  0000 C CNN
-F 2 "" H 5250 2300 60  0000 C CNN
-F 3 "" H 5250 2300 60  0000 C CNN
-	1    5250 2300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_xor U3
-U 1 1 5AB648E7
-P 4100 2750
-F 0 "U3" H 4100 2750 60  0000 C CNN
-F 1 "d_xor" H 4150 2850 47  0000 C CNN
-F 2 "" H 4100 2750 60  0000 C CNN
-F 3 "" H 4100 2750 60  0000 C CNN
-	1    4100 2750
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5AB6498F
-P 5250 2600
-F 0 "U5" H 5250 2600 60  0000 C CNN
-F 1 "d_xor" H 5300 2700 47  0000 C CNN
-F 2 "" H 5250 2600 60  0000 C CNN
-F 3 "" H 5250 2600 60  0000 C CNN
-	1    5250 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5AB64A11
-P 6250 2250
-F 0 "U6" H 6250 2250 60  0000 C CNN
-F 1 "d_or" H 6250 2350 60  0000 C CNN
-F 2 "" H 6250 2250 60  0000 C CNN
-F 3 "" H 6250 2250 60  0000 C CNN
-	1    6250 2250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5AB64A78
-P 2650 2100
-F 0 "U1" H 2700 2200 30  0000 C CNN
-F 1 "PORT" H 2650 2100 30  0000 C CNN
-F 2 "" H 2650 2100 60  0000 C CNN
-F 3 "" H 2650 2100 60  0000 C CNN
-	1    2650 2100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5AB64BE9
-P 2650 2300
-F 0 "U1" H 2700 2400 30  0000 C CNN
-F 1 "PORT" H 2650 2300 30  0000 C CNN
-F 2 "" H 2650 2300 60  0000 C CNN
-F 3 "" H 2650 2300 60  0000 C CNN
-	2    2650 2300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5AB64C18
-P 6300 2550
-F 0 "U1" H 6350 2650 30  0000 C CNN
-F 1 "PORT" H 6300 2550 30  0000 C CNN
-F 2 "" H 6300 2550 60  0000 C CNN
-F 3 "" H 6300 2550 60  0000 C CNN
-	4    6300 2550
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5AB64C59
-P 2650 2900
-F 0 "U1" H 2700 3000 30  0000 C CNN
-F 1 "PORT" H 2650 2900 30  0000 C CNN
-F 2 "" H 2650 2900 60  0000 C CNN
-F 3 "" H 2650 2900 60  0000 C CNN
-	3    2650 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5AB64C94
-P 7150 2200
-F 0 "U1" H 7200 2300 30  0000 C CNN
-F 1 "PORT" H 7150 2200 30  0000 C CNN
-F 2 "" H 7150 2200 60  0000 C CNN
-F 3 "" H 7150 2200 60  0000 C CNN
-	5    7150 2200
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	2900 2100 3650 2100
-Wire Wire Line
-	2900 2250 3650 2250
-Wire Wire Line
-	3650 2250 3650 2200
-Wire Wire Line
-	3400 2100 3400 2650
-Wire Wire Line
-	3400 2650 3650 2650
-Connection ~ 3400 2100
-Wire Wire Line
-	3150 2250 3150 2750
-Wire Wire Line
-	3150 2750 3650 2750
-Connection ~ 3150 2250
-Wire Wire Line
-	4550 2700 4550 2500
-Wire Wire Line
-	4550 2500 4800 2500
-Wire Wire Line
-	2900 2900 4800 2900
-Wire Wire Line
-	4800 2900 4800 2600
-Wire Wire Line
-	4700 2500 4700 2200
-Wire Wire Line
-	4700 2200 4800 2200
-Connection ~ 4700 2500
-Wire Wire Line
-	4800 2300 4600 2300
-Wire Wire Line
-	4600 2300 4600 2900
-Connection ~ 4600 2900
-Wire Wire Line
-	5700 2250 5800 2250
-Wire Wire Line
-	4550 2150 4550 2000
-Wire Wire Line
-	4550 2000 5800 2000
-Wire Wire Line
-	5800 2000 5800 2150
-Wire Wire Line
-	5700 2550 6050 2550
-Wire Wire Line
-	6700 2200 6900 2200
-Wire Wire Line
-	2900 2250 2900 2300
-Text GLabel 3000 1850 0    60   Input ~ 0
-A
-Text GLabel 3000 2500 0    60   Input ~ 0
-B
-Text GLabel 3000 3250 0    60   Input ~ 0
-CIN
-Wire Wire Line
-	3000 3250 3050 3250
-Wire Wire Line
-	3050 3250 3050 2900
-Connection ~ 3050 2900
-Wire Wire Line
-	3000 1850 3100 1850
-Wire Wire Line
-	3100 1850 3100 2100
-Connection ~ 3100 2100
-Wire Wire Line
-	3000 2500 3000 2250
-Connection ~ 3000 2250
-Text GLabel 6750 1700 0    60   Output ~ 0
-CARRY
-Text GLabel 5950 2800 0    60   Output ~ 0
-SUM
-Wire Wire Line
-	6750 1700 6800 1700
-Wire Wire Line
-	6800 1700 6800 2200
-Connection ~ 6800 2200
-Wire Wire Line
-	5950 2550 5950 2800
-Connection ~ 5950 2550
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub
deleted file mode 100644
index a1e1cfac..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub
+++ /dev/null
@@ -1,26 +0,0 @@
-* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry 
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2  a b net-_u2-pad3_ d_and
-* u4  net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3  a b net-_u3-pad3_ d_xor
-* u5  net-_u3-pad3_ cin sum d_xor
-* u6  net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml
deleted file mode 100644
index ab59f216..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/analysis b/src/SubcircuitLibrary/LOGIC_ADDER/analysis
deleted file mode 100644
index d5e13546..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/NE566/NE566-cache.lib b/src/SubcircuitLibrary/NE566/NE566-cache.lib
deleted file mode 100644
index db4e06a4..00000000
--- a/src/SubcircuitLibrary/NE566/NE566-cache.lib
+++ /dev/null
@@ -1,125 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# eSim_Diode
-#
-DEF eSim_Diode D 0 40 N N 1 F N
-F0 "D" 0 100 50 H V C CNN
-F1 "eSim_Diode" 0 -100 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- TO-???*
- *SingleDiode
- *_Diode_*
- *SingleDiode*
- D_*
-$ENDFPLIST
-DRAW
-T 0 -100 50 60 0 0 0 A  Normal 0 C C
-T 0 100 50 60 0 0 0 K  Normal 0 C C
-P 2 0 1 6  50 50  50 -50 N
-P 3 0 1 0  -50 50  50 0  -50 -50 F
-X A 1 -150 0 100 R 40 40 1 1 P
-X K 2 150 0 100 L 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/NE566/NE566.cir b/src/SubcircuitLibrary/NE566/NE566.cir
deleted file mode 100644
index 4d52179b..00000000
--- a/src/SubcircuitLibrary/NE566/NE566.cir
+++ /dev/null
@@ -1,57 +0,0 @@
-* C:\esim_1\eSim\src\SubcircuitLibrary\NE566\NE566.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 13:55:47
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_D10-Pad2_ Net-_D10-Pad1_ eSim_NPN		
-Q2  Net-_D10-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN		
-Q5  Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN		
-D1  Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode		
-D3  Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode		
-Q6  Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_Q3-Pad2_ eSim_NPN		
-Q8  Net-_D9-Pad2_ Net-_D3-Pad2_ Net-_D5-Pad1_ eSim_NPN		
-Q7  Net-_Q3-Pad2_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN		
-Q3  Net-_D1-Pad2_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
-R1  Net-_Q3-Pad3_ Net-_D4-Pad2_ 5k		
-R3  Net-_Q7-Pad3_ Net-_D4-Pad2_ 5k		
-D4  Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode		
-Q4  Net-_D4-Pad2_ Net-_D2-Pad2_ Net-_Q15-Pad1_ eSim_NPN		
-D2  Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode		
-R2  Net-_D2-Pad2_ Net-_Q15-Pad1_ 5k		
-R4  Net-_Q9-Pad3_ Net-_Q15-Pad1_ 5k		
-Q10  Net-_D9-Pad2_ Net-_D5-Pad1_ Net-_Q10-Pad3_ eSim_NPN		
-Q9  Net-_D5-Pad1_ Net-_Q11-Pad2_ Net-_Q9-Pad3_ eSim_NPN		
-Q11  Net-_Q10-Pad3_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN		
-D5  Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode		
-D6  Net-_D5-Pad1_ Net-_D6-Pad2_ eSim_Diode		
-Q12  Net-_D5-Pad2_ Net-_D6-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
-D8  Net-_D5-Pad2_ Net-_D8-Pad2_ eSim_Diode		
-D7  Net-_D5-Pad2_ Net-_D7-Pad2_ eSim_Diode		
-R6  Net-_D9-Pad2_ Net-_D5-Pad2_ 5k		
-R8  Net-_D9-Pad2_ Net-_D8-Pad2_ 5k		
-Q14  Net-_D9-Pad2_ Net-_D8-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
-Q13  Net-_D8-Pad2_ Net-_D7-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
-R7  Net-_D7-Pad2_ Net-_Q12-Pad3_ 5k		
-Q15  Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_PNP		
-Q16  Net-_Q15-Pad3_ Net-_Q16-Pad2_ Net-_D2-Pad1_ eSim_PNP		
-Q17  Net-_Q16-Pad2_ Net-_D9-Pad1_ Net-_Q15-Pad3_ eSim_PNP		
-R13  Net-_D9-Pad2_ Net-_D9-Pad1_ 5k		
-D9  Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode		
-R15  Net-_D9-Pad2_ Net-_Q11-Pad2_ 5k		
-R12  Net-_Q16-Pad2_ Net-_D2-Pad1_ 5k		
-R5  Net-_Q11-Pad3_ Net-_Q15-Pad1_ 5k		
-R9  Net-_Q12-Pad3_ Net-_Q15-Pad1_ 5k		
-R10  Net-_Q14-Pad3_ Net-_Q15-Pad1_ 5k		
-Q18  Net-_D9-Pad1_ Net-_Q11-Pad2_ Net-_Q18-Pad3_ eSim_NPN		
-Q19  Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q19-Pad3_ eSim_NPN		
-R14  Net-_Q18-Pad3_ Net-_Q15-Pad1_ 5k		
-R16  Net-_Q19-Pad3_ Net-_Q15-Pad1_ 5k		
-U1  Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q10-Pad3_ Net-_D10-Pad2_ Net-_Q1-Pad1_ Net-_D3-Pad2_ Net-_D9-Pad2_ PORT		
-R11  Net-_D9-Pad2_ Net-_Q15-Pad3_ 5k		
-D10  Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode		
-Q20  Net-_Q2-Pad2_ Net-_D10-Pad1_ Net-_Q1-Pad1_ eSim_PNP		
-
-.end
diff --git a/src/SubcircuitLibrary/NE566/NE566.cir.out b/src/SubcircuitLibrary/NE566/NE566.cir.out
deleted file mode 100644
index c83f8b00..00000000
--- a/src/SubcircuitLibrary/NE566/NE566.cir.out
+++ /dev/null
@@ -1,61 +0,0 @@
-* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir
-
-.include PNP.lib
-.include D.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222
-q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
-d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
-q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222
-q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222
-q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-r1  net-_q3-pad3_ net-_d4-pad2_ 5k
-r3  net-_q7-pad3_ net-_d4-pad2_ 5k
-d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
-q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222
-d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
-r2  net-_d2-pad2_ net-_q15-pad1_ 5k
-r4  net-_q9-pad3_ net-_q15-pad1_ 5k
-q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222
-q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222
-q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
-d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
-d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148
-q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
-d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148
-d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148
-r6  net-_d9-pad2_ net-_d5-pad2_ 5k
-r8  net-_d9-pad2_ net-_d8-pad2_ 5k
-q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222
-q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222
-r7  net-_d7-pad2_ net-_q12-pad3_ 5k
-q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A
-q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222
-q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222
-r13  net-_d9-pad2_ net-_d9-pad1_ 5k
-d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
-r15  net-_d9-pad2_ net-_q11-pad2_ 5k
-r12  net-_q16-pad2_ net-_d2-pad1_ 5k
-r5  net-_q11-pad3_ net-_q15-pad1_ 5k
-r9  net-_q12-pad3_ net-_q15-pad1_ 5k
-r10  net-_q14-pad3_ net-_q15-pad1_ 5k
-q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222
-q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222
-r14  net-_q18-pad3_ net-_q15-pad1_ 5k
-r16  net-_q19-pad3_ net-_q15-pad1_ 5k
-* u1  net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_ port
-r11  net-_d9-pad2_ net-_q15-pad3_ 5k
-d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
-q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/NE566/NE566.pro b/src/SubcircuitLibrary/NE566/NE566.pro
deleted file mode 100644
index 4b1e556f..00000000
--- a/src/SubcircuitLibrary/NE566/NE566.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=03/31/19 14:14:07
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Users/hp/AppData/Roaming/SPB_Data/eSim-Workspace/Function_generator_using_NE566
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_Subckt
-LibName40=eSim_User
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/NE566/NE566.sch b/src/SubcircuitLibrary/NE566/NE566.sch
deleted file mode 100644
index f4c9144d..00000000
--- a/src/SubcircuitLibrary/NE566/NE566.sch
+++ /dev/null
@@ -1,920 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:NE566-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
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-Comment1 ""
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-P 6450 6750
-F 0 "R10" H 6500 6880 50  0000 C CNN
-F 1 "5k" H 6500 6800 50  0000 C CNN
-F 2 "" H 6500 6730 30  0000 C CNN
-F 3 "" V 6500 6800 30  0000 C CNN
-	1    6450 6750
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9D24BF
-P 9650 5900
-F 0 "Q18" H 9550 5950 50  0000 R CNN
-F 1 "eSim_NPN" H 9600 6050 50  0000 R CNN
-F 2 "" H 9850 6000 29  0000 C CNN
-F 3 "" H 9650 5900 60  0000 C CNN
-	1    9650 5900
-	-1   0    0    -1  
-$EndComp
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9D2540
-P 10350 5900
-F 0 "Q19" H 10250 5950 50  0000 R CNN
-F 1 "eSim_NPN" H 10300 6050 50  0000 R CNN
-F 2 "" H 10550 6000 29  0000 C CNN
-F 3 "" H 10350 5900 60  0000 C CNN
-	1    10350 5900
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_R R14
-U 1 1 5C9D25BD
-P 9500 6750
-F 0 "R14" H 9550 6880 50  0000 C CNN
-F 1 "5k" H 9550 6800 50  0000 C CNN
-F 2 "" H 9550 6730 30  0000 C CNN
-F 3 "" V 9550 6800 30  0000 C CNN
-	1    9500 6750
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R16
-U 1 1 5C9D2650
-P 10450 6750
-F 0 "R16" H 10500 6880 50  0000 C CNN
-F 1 "5k" H 10500 6800 50  0000 C CNN
-F 2 "" H 10500 6730 30  0000 C CNN
-F 3 "" V 10500 6800 30  0000 C CNN
-	1    10450 6750
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D2BB3
-P 650 1650
-F 0 "U1" H 700 1750 30  0000 C CNN
-F 1 "PORT" H 650 1650 30  0000 C CNN
-F 2 "" H 650 1650 60  0000 C CNN
-F 3 "" H 650 1650 60  0000 C CNN
-	5    650  1650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9D68D0
-P 2100 800
-F 0 "U1" H 2150 900 30  0000 C CNN
-F 1 "PORT" H 2100 800 30  0000 C CNN
-F 2 "" H 2100 800 60  0000 C CNN
-F 3 "" H 2100 800 60  0000 C CNN
-	6    2100 800 
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9D8B9B
-P 7150 1350
-F 0 "R11" H 7200 1480 50  0000 C CNN
-F 1 "5k" H 7200 1400 50  0000 C CNN
-F 2 "" H 7200 1330 30  0000 C CNN
-F 3 "" V 7200 1400 30  0000 C CNN
-	1    7150 1350
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9D98CB
-P 3650 550
-F 0 "U1" H 3700 650 30  0000 C CNN
-F 1 "PORT" H 3650 550 30  0000 C CNN
-F 2 "" H 3650 550 60  0000 C CNN
-F 3 "" H 3650 550 60  0000 C CNN
-	8    3650 550 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C9E5DF3
-P 3150 3950
-F 0 "U1" H 3200 4050 30  0000 C CNN
-F 1 "PORT" H 3150 3950 30  0000 C CNN
-F 2 "" H 3150 3950 60  0000 C CNN
-F 3 "" H 3150 3950 60  0000 C CNN
-	7    3150 3950
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9E625B
-P 4950 5150
-F 0 "U1" H 5000 5250 30  0000 C CNN
-F 1 "PORT" H 4950 5150 30  0000 C CNN
-F 2 "" H 4950 5150 60  0000 C CNN
-F 3 "" H 4950 5150 60  0000 C CNN
-	4    4950 5150
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9E6ECC
-P 6800 5100
-F 0 "U1" H 6850 5200 30  0000 C CNN
-F 1 "PORT" H 6800 5100 30  0000 C CNN
-F 2 "" H 6800 5100 60  0000 C CNN
-F 3 "" H 6800 5100 60  0000 C CNN
-	3    6800 5100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9E7FDD
-P 11100 7250
-F 0 "U1" H 11150 7350 30  0000 C CNN
-F 1 "PORT" H 11100 7250 30  0000 C CNN
-F 2 "" H 11100 7250 60  0000 C CNN
-F 3 "" H 11100 7250 60  0000 C CNN
-	1    11100 7250
-	0    -1   -1   0   
-$EndComp
-Text Notes 500  1450 0    79   ~ 0
-Modulation Input\n
-Text Notes 2200 800  0    79   ~ 0
-R1(External)
-Text Notes 3300 5750 1    79   ~ 0
-C1(External)\n
-Text Notes 4500 5050 0    79   ~ 0
-Triangle Wave Output
-Text Notes 6500 5000 0    79   ~ 0
-Square Wave Output\n
-Text Notes 10950 7000 0    79   ~ 0
-GND\n
-Text Notes 3425 625  0    79   ~ 0
-V+\n
-$Comp
-L eSim_Diode D10
-U 1 1 5C9F4364
-P 1300 1850
-F 0 "D10" H 1300 1950 50  0000 C CNN
-F 1 "eSim_Diode" H 1300 1750 50  0000 C CNN
-F 2 "" H 1300 1850 60  0000 C CNN
-F 3 "" H 1300 1850 60  0000 C CNN
-	1    1300 1850
-	0    -1   -1   0   
-$EndComp
-Text Notes 950  1650 0    79   ~ 0
-Vc\n
-Wire Wire Line
-	1750 1850 1750 2250
-Wire Wire Line
-	900  1650 1450 1650
-Wire Wire Line
-	2750 2000 2750 2250
-Wire Wire Line
-	2050 2450 2450 2450
-Wire Wire Line
-	2750 2200 2250 2200
-Wire Wire Line
-	2250 2200 2250 2450
-Connection ~ 2250 2450
-Connection ~ 2750 2200
-Wire Wire Line
-	2100 1800 2450 1800
-Wire Wire Line
-	2100 2000 2100 1800
-Wire Wire Line
-	1300 2000 2100 2000
-Connection ~ 1750 2000
-Wire Wire Line
-	2750 1450 1750 1450
-Wire Wire Line
-	2750 2650 2750 3000
-Wire Wire Line
-	1750 2650 1750 3000
-Wire Wire Line
-	2750 2850 1750 2850
-Connection ~ 1750 2850
-Connection ~ 2750 2850
-Wire Wire Line
-	2750 3300 2750 3900
-Wire Wire Line
-	2450 4100 1750 4100
-Wire Wire Line
-	1750 3300 1750 4700
-Connection ~ 1750 4100
-Wire Wire Line
-	2750 4300 2750 4700
-Wire Wire Line
-	2050 4900 2450 4900
-Wire Wire Line
-	2750 3550 3350 3550
-Connection ~ 2750 3550
-Wire Wire Line
-	2750 4500 2250 4500
-Wire Wire Line
-	2250 4500 2250 4900
-Connection ~ 2250 4900
-Connection ~ 2750 4500
-Wire Wire Line
-	2750 5100 2750 5400
-Wire Wire Line
-	2750 5700 2750 5950
-Wire Wire Line
-	1750 5100 1750 5450
-Wire Wire Line
-	1750 5750 1750 6300
-Wire Wire Line
-	1750 5900 2750 5900
-Connection ~ 2750 5900
-Connection ~ 1750 5900
-Wire Wire Line
-	2750 6250 2750 6500
-Wire Wire Line
-	2650 6500 8550 6500
-Wire Wire Line
-	1750 6700 1750 7000
-Wire Wire Line
-	2050 6500 2350 6500
-Wire Wire Line
-	2200 6500 2200 6650
-Connection ~ 2200 6500
-Wire Wire Line
-	1750 7000 11100 7000
-Wire Wire Line
-	2200 7000 2200 6950
-Connection ~ 2200 7000
-Wire Wire Line
-	4500 6950 4500 7000
-Connection ~ 4500 7000
-Wire Wire Line
-	6000 7000 6000 6950
-Wire Wire Line
-	9550 6950 9550 7000
-Connection ~ 9550 7000
-Wire Wire Line
-	10500 6950 10500 7000
-Connection ~ 10500 7000
-Wire Wire Line
-	4500 6100 4500 6650
-Wire Wire Line
-	3650 3750 3650 5700
-Connection ~ 3650 4600
-Wire Wire Line
-	3950 4800 4500 4800
-Wire Wire Line
-	4500 4800 4500 5700
-Wire Wire Line
-	1750 1450 1750 800 
-Wire Wire Line
-	1750 800  1850 800 
-Wire Wire Line
-	3650 800  10500 800 
-Wire Wire Line
-	10500 1950 10500 5700
-Wire Wire Line
-	10500 5700 10450 5700
-Wire Wire Line
-	9850 5900 10150 5900
-Wire Wire Line
-	10500 5550 10000 5550
-Wire Wire Line
-	10000 5550 10000 5900
-Connection ~ 10000 5900
-Connection ~ 10500 5550
-Wire Wire Line
-	10450 6100 10450 6650
-Wire Wire Line
-	10450 6650 10500 6650
-Wire Wire Line
-	9550 6100 9550 6650
-Wire Wire Line
-	9550 1600 9550 5700
-Wire Wire Line
-	8500 1600 9550 1600
-Wire Wire Line
-	9050 800  9050 1300
-Connection ~ 9050 800 
-Connection ~ 9050 1600
-Wire Wire Line
-	8500 1300 8500 800 
-Connection ~ 8500 800 
-Wire Wire Line
-	9550 2650 8850 2650
-Connection ~ 9550 2650
-Wire Wire Line
-	7200 2450 8550 2450
-Wire Wire Line
-	7900 2450 7900 2550
-Wire Wire Line
-	7200 1550 7200 2550
-Connection ~ 7900 2450
-Wire Wire Line
-	7200 800  7200 1250
-Connection ~ 7200 800 
-Connection ~ 7200 2450
-Wire Wire Line
-	3650 3350 3650 800 
-Connection ~ 3650 800 
-Wire Wire Line
-	3950 4400 3950 800 
-Connection ~ 3950 800 
-Wire Wire Line
-	4950 1150 4950 800 
-Connection ~ 4950 800 
-Wire Wire Line
-	5950 1150 5950 800 
-Connection ~ 5950 800 
-Wire Wire Line
-	6200 1850 5950 1850
-Wire Wire Line
-	5950 1450 5950 3100
-Wire Wire Line
-	4950 1450 4950 3750
-Wire Wire Line
-	4950 2350 5000 2350
-Wire Wire Line
-	5950 2350 5300 2350
-Connection ~ 5950 1850
-Wire Wire Line
-	3650 3950 4150 3950
-Connection ~ 3650 3950
-Wire Wire Line
-	4150 2950 3850 2950
-Wire Wire Line
-	3850 2950 3850 3950
-Connection ~ 3850 3950
-Wire Wire Line
-	4950 2950 4450 2950
-Connection ~ 4950 2350
-Connection ~ 4950 2950
-Wire Wire Line
-	4650 3950 4450 3950
-Wire Wire Line
-	3650 6950 3650 7000
-Connection ~ 3650 7000
-Wire Wire Line
-	3650 6650 3650 6100
-Wire Wire Line
-	10000 5900 3950 5900
-Connection ~ 4800 5900
-Wire Wire Line
-	8550 6500 8550 4400
-Connection ~ 2750 6500
-Wire Wire Line
-	8550 2850 8550 4100
-Wire Wire Line
-	8200 2750 8350 2750
-Wire Wire Line
-	8350 2750 8350 3000
-Wire Wire Line
-	8350 3000 8550 3000
-Connection ~ 8550 3000
-Wire Wire Line
-	7900 2950 7900 6500
-Connection ~ 7900 6500
-Wire Wire Line
-	7200 2950 7200 7000
-Wire Wire Line
-	6500 1650 6500 800 
-Connection ~ 6500 800 
-Connection ~ 7200 7000
-Connection ~ 6000 7000
-Wire Wire Line
-	6500 6950 6500 7000
-Connection ~ 6500 7000
-Wire Wire Line
-	5350 3300 5650 3300
-Wire Wire Line
-	5500 3300 5500 3450
-Connection ~ 5500 3300
-Wire Wire Line
-	4950 4150 6000 4150
-Wire Wire Line
-	5950 4150 5950 3500
-Wire Wire Line
-	5500 3750 5500 4150
-Connection ~ 5500 4150
-Wire Wire Line
-	6000 4150 6000 6650
-Connection ~ 5950 4150
-Connection ~ 5950 2350
-Wire Wire Line
-	3150 3550 3150 3700
-Connection ~ 3150 3550
-Wire Wire Line
-	4700 5150 4500 5150
-Connection ~ 4500 5150
-Wire Notes Line
-	2200 800  2900 800 
-Wire Notes Line
-	3150 4050 3150 7000
-Wire Wire Line
-	1300 1700 1300 1650
-Connection ~ 1300 1650
-Wire Wire Line
-	5050 3300 4950 3300
-Connection ~ 4950 3300
-$Comp
-L eSim_PNP Q20
-U 1 1 5CA087B6
-P 2650 1800
-F 0 "Q20" H 2550 1850 50  0000 R CNN
-F 1 "eSim_PNP" H 2600 1950 50  0000 R CNN
-F 2 "" H 2850 1900 29  0000 C CNN
-F 3 "" H 2650 1800 60  0000 C CNN
-	1    2650 1800
-	1    0    0    1   
-$EndComp
-Wire Wire Line
-	2750 1450 2750 1600
-Wire Notes Line
-	2925 800  3600 800 
-Wire Wire Line
-	10500 800  10500 1650
-Wire Wire Line
-	6500 2050 6500 6650
-Wire Wire Line
-	6500 5100 6550 5100
-Connection ~ 6500 5100
-Wire Wire Line
-	6900 2750 6500 2750
-Connection ~ 6500 2750
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/NE566/NE566.sub b/src/SubcircuitLibrary/NE566/NE566.sub
deleted file mode 100644
index 5b2fc943..00000000
--- a/src/SubcircuitLibrary/NE566/NE566.sub
+++ /dev/null
@@ -1,55 +0,0 @@
-* Subcircuit NE566
-.subckt NE566 net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_ 
-* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir
-.include PNP.lib
-.include D.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222
-q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
-d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
-q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222
-q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222
-q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-r1  net-_q3-pad3_ net-_d4-pad2_ 5k
-r3  net-_q7-pad3_ net-_d4-pad2_ 5k
-d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
-q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222
-d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
-r2  net-_d2-pad2_ net-_q15-pad1_ 5k
-r4  net-_q9-pad3_ net-_q15-pad1_ 5k
-q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222
-q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222
-q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
-d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
-d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148
-q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
-d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148
-d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148
-r6  net-_d9-pad2_ net-_d5-pad2_ 5k
-r8  net-_d9-pad2_ net-_d8-pad2_ 5k
-q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222
-q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222
-r7  net-_d7-pad2_ net-_q12-pad3_ 5k
-q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A
-q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222
-q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222
-r13  net-_d9-pad2_ net-_d9-pad1_ 5k
-d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
-r15  net-_d9-pad2_ net-_q11-pad2_ 5k
-r12  net-_q16-pad2_ net-_d2-pad1_ 5k
-r5  net-_q11-pad3_ net-_q15-pad1_ 5k
-r9  net-_q12-pad3_ net-_q15-pad1_ 5k
-r10  net-_q14-pad3_ net-_q15-pad1_ 5k
-q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222
-q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222
-r14  net-_q18-pad3_ net-_q15-pad1_ 5k
-r16  net-_q19-pad3_ net-_q15-pad1_ 5k
-r11  net-_d9-pad2_ net-_q15-pad3_ 5k
-d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
-q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222
-* Control Statements
-
-.ends NE566
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml b/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml
deleted file mode 100644
index cd7c0b08..00000000
--- a/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q20><d8><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d8><d9><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d9><d6><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d6><d7><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d7><d4><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d5><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d5><d2><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><d10><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d10><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/diac/analysis b/src/SubcircuitLibrary/diac/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/diac/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/diac/diac.cir b/src/SubcircuitLibrary/diac/diac.cir
deleted file mode 100644
index 91629b91..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* /opt/eSim/src/SubcircuitLibrary/diac/diac.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec  8 15:35:49 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  1 2 PORT		
-U1  1 1 2 aswitch		
-U2  1 1 2 aswitch		
-
-.end
diff --git a/src/SubcircuitLibrary/diac/diac.cir.out b/src/SubcircuitLibrary/diac/diac.cir.out
deleted file mode 100644
index a1e31f14..00000000
--- a/src/SubcircuitLibrary/diac/diac.cir.out
+++ /dev/null
@@ -1,21 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-
-* u3  1 2 port
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 (1 2)  u1
-a2 1 (1 2)  u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
- 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/diac/diac.pro b/src/SubcircuitLibrary/diac/diac.pro
deleted file mode 100644
index c8563047..00000000
--- a/src/SubcircuitLibrary/diac/diac.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=Tue Dec  8 14:06:36 2015
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=analogSpice
-LibName32=eSim_Analog
-LibName33=eSim_Devices
-LibName34=eSim_Digital
-LibName35=eSim_Hybrid
-LibName36=eSim_Miscellaneous
-LibName37=eSim_Sources
-LibName38=eSim_Subckt
-LibName39=eSim_User
diff --git a/src/SubcircuitLibrary/diac/diac.sch b/src/SubcircuitLibrary/diac/diac.sch
deleted file mode 100644
index 163665e7..00000000
--- a/src/SubcircuitLibrary/diac/diac.sch
+++ /dev/null
@@ -1,148 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "22 sep 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
-	4150 2750 4150 4300
-Connection ~ 4400 3750
-Wire Wire Line
-	4400 4450 5050 4450
-Wire Wire Line
-	4400 4450 4400 3450
-Wire Wire Line
-	5500 3350 5500 4050
-Connection ~ 4600 3400
-Wire Wire Line
-	4600 4050 4600 2750
-Wire Wire Line
-	4600 2750 4150 2750
-Wire Wire Line
-	4400 3450 4150 3450
-Connection ~ 4150 3450
-Wire Wire Line
-	4400 3750 5050 3750
-$Comp
-L PWR_FLAG #FLG01
-U 1 1 5417D647
-P 4150 4300
-F 0 "#FLG01" H 4150 4570 30  0001 C CNN
-F 1 "PWR_FLAG" H 4150 4530 30  0000 C CNN
-F 2 "" H 4150 4300 60  0001 C CNN
-F 3 "" H 4150 4300 60  0001 C CNN
-	1    4150 4300
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U3
-U 2 1 5417D62C
-P 5750 3350
-F 0 "U3" H 5750 3300 30  0000 C CNN
-F 1 "PORT" H 5750 3350 30  0000 C CNN
-F 2 "" H 5750 3350 60  0001 C CNN
-F 3 "" H 5750 3350 60  0001 C CNN
-	2    5750 3350
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U3
-U 1 1 5417D624
-P 4150 2500
-F 0 "U3" H 4150 2450 30  0000 C CNN
-F 1 "PORT" H 4150 2500 30  0000 C CNN
-F 2 "" H 4150 2500 60  0001 C CNN
-F 3 "" H 4150 2500 60  0001 C CNN
-	1    4150 2500
-	0    1    1    0   
-$EndComp
-$Comp
-L GND #PWR02
-U 1 1 5417D5DC
-P 4150 4300
-F 0 "#PWR02" H 4150 4300 30  0001 C CNN
-F 1 "GND" H 4150 4230 30  0001 C CNN
-F 2 "" H 4150 4300 60  0001 C CNN
-F 3 "" H 4150 4300 60  0001 C CNN
-	1    4150 4300
-	1    0    0    -1  
-$EndComp
-$Comp
-L aswitch U1
-U 1 1 56669812
-P 4600 3550
-F 0 "U1" H 5050 3850 60  0000 C CNN
-F 1 "aswitch" H 5050 3750 60  0000 C CNN
-F 2 "" H 5050 3650 60  0000 C CNN
-F 3 "" H 5050 3650 60  0000 C CNN
-	1    4600 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L aswitch U2
-U 1 1 5666987C
-P 4600 4200
-F 0 "U2" H 5050 4500 60  0000 C CNN
-F 1 "aswitch" H 5050 4400 60  0000 C CNN
-F 2 "" H 5050 4300 60  0000 C CNN
-F 3 "" H 5050 4300 60  0000 C CNN
-	1    4600 4200
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5050 4450 5050 4300
-Wire Wire Line
-	5050 3750 5050 3650
-Wire Wire Line
-	5500 4050 5450 4050
-Wire Wire Line
-	5500 3400 5450 3400
-Connection ~ 5500 3400
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/diac/diac.sub b/src/SubcircuitLibrary/diac/diac.sub
deleted file mode 100644
index 7f28ecc2..00000000
--- a/src/SubcircuitLibrary/diac/diac.sub
+++ /dev/null
@@ -1,15 +0,0 @@
-* Subcircuit diac
-.subckt diac 1 2 
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-* u1  1 1 2 aswitch
-* u2  1 1 2 aswitch
-a1 1 (1 2)  u1
-a2 1 (1 2)  u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-
-* Control Statements
-
-.ends diac
diff --git a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml
deleted file mode 100644
index 96df431c..00000000
--- a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">25</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-25</field10></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/analysis b/src/SubcircuitLibrary/full_adder/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/full_adder/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
deleted file mode 100644
index 623a7f41..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir b/src/SubcircuitLibrary/full_adder/full_adder.cir
deleted file mode 100644
index 6461b5b6..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder.cir
+++ /dev/null
@@ -1,12 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-X1  8 7 6 2 half_adder		
-X2  5 6 4 3 half_adder		
-U1  8 7 5 4 1 PORT		
-U2  3 2 1 d_or		
-
-.end
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out
deleted file mode 100644
index b90ce70d..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder.cir.out
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
-
-.include half_adder.sub
-x1 8 7 6 2 half_adder
-x2 5 6 4 3 half_adder
-* u1  8 7 5 4 1 port
-* u2  3 2 1 d_or
-a1 [3 2 ] 1 u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro
deleted file mode 100644
index c0db0775..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 12:19:16 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sch b/src/SubcircuitLibrary/full_adder/full_adder.sch
deleted file mode 100644
index 8bd400f2..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder.sch
+++ /dev/null
@@ -1,180 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
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-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L half_adder X1
-U 1 1 558AA064
-P 3800 3350
-F 0 "X1" H 4700 3850 60  0000 C CNN
-F 1 "half_adder" H 4700 3750 60  0000 C CNN
-F 2 "" H 3800 3350 60  0000 C CNN
-F 3 "" H 3800 3350 60  0000 C CNN
-	1    3800 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L half_adder X2
-U 1 1 558AA0C1
-P 5700 3350
-F 0 "X2" H 6600 3850 60  0000 C CNN
-F 1 "half_adder" H 6600 3750 60  0000 C CNN
-F 2 "" H 5700 3350 60  0000 C CNN
-F 3 "" H 5700 3350 60  0000 C CNN
-	1    5700 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558AA277
-P 3450 2650
-F 0 "U1" H 3500 2750 30  0000 C CNN
-F 1 "PORT" H 3450 2650 30  0000 C CNN
-F 2 "" H 3450 2650 60  0000 C CNN
-F 3 "" H 3450 2650 60  0000 C CNN
-	1    3450 2650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558AA29E
-P 3450 3250
-F 0 "U1" H 3500 3350 30  0000 C CNN
-F 1 "PORT" H 3450 3250 30  0000 C CNN
-F 2 "" H 3450 3250 60  0000 C CNN
-F 3 "" H 3450 3250 60  0000 C CNN
-	2    3450 3250
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558AA2D8
-P 5650 2300
-F 0 "U1" H 5700 2400 30  0000 C CNN
-F 1 "PORT" H 5650 2300 30  0000 C CNN
-F 2 "" H 5650 2300 60  0000 C CNN
-F 3 "" H 5650 2300 60  0000 C CNN
-	3    5650 2300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558AA378
-P 7900 2650
-F 0 "U1" H 7950 2750 30  0000 C CNN
-F 1 "PORT" H 7900 2650 30  0000 C CNN
-F 2 "" H 7900 2650 60  0000 C CNN
-F 3 "" H 7900 2650 60  0000 C CNN
-	4    7900 2650
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 558AA3E0
-P 8700 3400
-F 0 "U1" H 8750 3500 30  0000 C CNN
-F 1 "PORT" H 8700 3400 30  0000 C CNN
-F 2 "" H 8700 3400 60  0000 C CNN
-F 3 "" H 8700 3400 60  0000 C CNN
-	5    8700 3400
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_or U2
-U 1 1 558AA43B
-P 7900 3450
-F 0 "U2" H 7900 3450 60  0000 C CNN
-F 1 "d_or" H 7900 3550 60  0000 C CNN
-F 2 "" H 7900 3450 60  0000 C CNN
-F 3 "" H 7900 3450 60  0000 C CNN
-	1    7900 3450
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3700 2650 4100 2650
-Wire Wire Line
-	3700 3250 4100 3250
-Wire Wire Line
-	5250 2650 5650 2650
-Wire Wire Line
-	5650 2650 5650 3250
-Wire Wire Line
-	5650 3250 6000 3250
-Wire Wire Line
-	5900 2300 5900 2650
-Wire Wire Line
-	5900 2650 6000 2650
-Wire Wire Line
-	7150 2650 7650 2650
-Wire Wire Line
-	7150 3250 7350 3250
-Wire Wire Line
-	7350 3250 7350 3350
-Wire Wire Line
-	7350 3350 7450 3350
-Wire Wire Line
-	5250 3250 5400 3250
-Wire Wire Line
-	5400 3250 5400 3450
-Wire Wire Line
-	5400 3450 7450 3450
-Wire Wire Line
-	8350 3400 8450 3400
-Text Notes 3850 2500 0    60   ~ 0
-IN1
-Text Notes 3850 3150 0    60   ~ 0
-IN2
-Text Notes 6000 2350 0    60   ~ 0
-CIN
-Text Notes 7350 2550 0    60   ~ 0
-SUM
-Text Notes 8300 3200 0    60   ~ 0
-COUT
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sub b/src/SubcircuitLibrary/full_adder/full_adder.sub
deleted file mode 100644
index 5f261f78..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder.sub
+++ /dev/null
@@ -1,13 +0,0 @@
-* Subcircuit full_adder
-.subckt full_adder 8 7 5 4 1 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
-.include half_adder.sub
-x1 8 7 6 2 half_adder
-x2 5 6 4 3 half_adder
-* u2  3 2 1 d_or
-a1 [3 2 ] 1 u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends full_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml
deleted file mode 100644
index b63184d6..00000000
--- a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir b/src/SubcircuitLibrary/full_adder/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder.cir
+++ /dev/null
@@ -1,11 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2  1 4 3 d_xor		
-U3  1 4 2 d_and		
-U1  1 4 3 2 PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir.out b/src/SubcircuitLibrary/full_adder/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro
deleted file mode 100644
index 695ae0f6..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 11:27:22 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sch b/src/SubcircuitLibrary/full_adder/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder.sch
+++ /dev/null
@@ -1,152 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U2
-U 1 1 558A946A
-P 5650 3050
-F 0 "U2" H 5650 3050 60  0000 C CNN
-F 1 "d_xor" H 5700 3150 47  0000 C CNN
-F 2 "" H 5650 3050 60  0000 C CNN
-F 3 "" H 5650 3050 60  0000 C CNN
-	1    5650 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 558A94D5
-P 5700 3800
-F 0 "U3" H 5700 3800 60  0000 C CNN
-F 1 "d_and" H 5750 3900 60  0000 C CNN
-F 2 "" H 5700 3800 60  0000 C CNN
-F 3 "" H 5700 3800 60  0000 C CNN
-	1    5700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558A94F6
-P 4150 3000
-F 0 "U1" H 4200 3100 30  0000 C CNN
-F 1 "PORT" H 4150 3000 30  0000 C CNN
-F 2 "" H 4150 3000 60  0000 C CNN
-F 3 "" H 4150 3000 60  0000 C CNN
-	1    4150 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558A9543
-P 4150 3450
-F 0 "U1" H 4200 3550 30  0000 C CNN
-F 1 "PORT" H 4150 3450 30  0000 C CNN
-F 2 "" H 4150 3450 60  0000 C CNN
-F 3 "" H 4150 3450 60  0000 C CNN
-	2    4150 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558A9573
-P 6650 3000
-F 0 "U1" H 6700 3100 30  0000 C CNN
-F 1 "PORT" H 6650 3000 30  0000 C CNN
-F 2 "" H 6650 3000 60  0000 C CNN
-F 3 "" H 6650 3000 60  0000 C CNN
-	3    6650 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558A9606
-P 6700 3750
-F 0 "U1" H 6750 3850 30  0000 C CNN
-F 1 "PORT" H 6700 3750 30  0000 C CNN
-F 2 "" H 6700 3750 60  0000 C CNN
-F 3 "" H 6700 3750 60  0000 C CNN
-	4    6700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5200 2950 4450 2950
-Wire Wire Line
-	4450 2950 4450 3000
-Wire Wire Line
-	4450 3000 4400 3000
-Wire Wire Line
-	4400 3450 4550 3450
-Wire Wire Line
-	4550 3450 4550 3050
-Wire Wire Line
-	4550 3050 5200 3050
-Wire Wire Line
-	5250 3700 5000 3700
-Wire Wire Line
-	5000 3700 5000 2950
-Connection ~ 5000 2950
-Wire Wire Line
-	5250 3800 4850 3800
-Wire Wire Line
-	4850 3800 4850 3050
-Connection ~ 4850 3050
-Wire Wire Line
-	6100 3000 6400 3000
-Wire Wire Line
-	6150 3750 6450 3750
-Text Notes 4550 2950 0    60   ~ 0
-IN1\n\n
-Text Notes 4600 3150 0    60   ~ 0
-IN2
-Text Notes 6200 2950 0    60   ~ 0
-SUM\n
-Text Notes 6200 3650 0    60   ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sub b/src/SubcircuitLibrary/full_adder/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml
deleted file mode 100644
index b915f0da..00000000
--- a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/analysis b/src/SubcircuitLibrary/full_sub/analysis
deleted file mode 100644
index 660a46cc..00000000
--- a/src/SubcircuitLibrary/full_sub/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
deleted file mode 100644
index 6949ac1a..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib
+++ /dev/null
@@ -1,79 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_sub
-#
-DEF half_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 300 300 -300 0 1 0 N
-X A 1 -500 200 200 R 50 50 1 1 I
-X B 2 -500 -100 200 R 50 50 1 1 I
-X D 3 500 150 200 L 50 50 1 1 O
-X BORROW 4 500 -100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
deleted file mode 100644
index 803b5ece..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# half_sub-RESCUE-full_sub
-#
-DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -1450 850 1550 -1050 0 1 0 N
-X A 1 -1100 850 200 R 50 50 1 1 I
-X B 2 -350 850 200 R 50 50 1 1 I
-X D 3 -800 -1050 200 L 50 50 1 1 O
-X BORROW 4 0 -1050 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir
deleted file mode 100644
index 67359421..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or		
-U5  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT		
-X1  Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub		
-X2  Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub		
-
-.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out
deleted file mode 100644
index 5e58cc0a..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out
+++ /dev/null
@@ -1,19 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-* u5  net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro
deleted file mode 100644
index 1a0c3543..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=03/07/19 10:55:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=full_sub-rescue
-LibName2=adc-dac
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-LibName20=atmel
-LibName21=contrib
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-LibName26=linear
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-LibName29=cmos4000
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-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
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-LibName36=eSim_Sources
-LibName37=eSim_Subckt
-LibName38=eSim_User
-LibName39=eSim_Plot
-LibName40=eSim_PSpice
-
diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch
deleted file mode 100644
index 99ca85e5..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub.sch
+++ /dev/null
@@ -1,211 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:full_sub-rescue
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-LIBS:microcontrollers
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-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
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-LIBS:full_sub-cache
-EELAYER 25 0
-EELAYER END
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diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub
deleted file mode 100644
index 9c9dcc5a..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub.sub
+++ /dev/null
@@ -1,13 +0,0 @@
-* Subcircuit full_sub
-.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-.include half_sub.sub
-* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends full_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml
deleted file mode 100644
index fcdb63e0..00000000
--- a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib
deleted file mode 100644
index bd15e664..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir b/src/SubcircuitLibrary/full_sub/half_sub.cir
deleted file mode 100644
index f20f0368..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U4  Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out
deleted file mode 100644
index 91816956..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.pro b/src/SubcircuitLibrary/full_sub/half_sub.pro
deleted file mode 100644
index 90e3ded9..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=Wed 06 Mar 2019 11:10:38 PM IST
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
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-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
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-LibName12=interface
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-LibName14=philips
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-LibName16=cypress
-LibName17=siliconi
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-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
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-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sch b/src/SubcircuitLibrary/full_sub/half_sub.sch
deleted file mode 100644
index e70b1675..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
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-EELAYER END
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-$Comp
-L PORT U1
-U 3 1 5C7FE00A
-P 5300 3100
-F 0 "U1" H 5350 3200 30  0000 C CNN
-F 1 "PORT" H 5300 3100 30  0000 C CNN
-F 2 "" H 5300 3100 60  0000 C CNN
-F 3 "" H 5300 3100 60  0000 C CNN
-	3    5300 3100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C7FE064
-P 5350 3700
-F 0 "U1" H 5400 3800 30  0000 C CNN
-F 1 "PORT" H 5350 3700 30  0000 C CNN
-F 2 "" H 5350 3700 60  0000 C CNN
-F 3 "" H 5350 3700 60  0000 C CNN
-	4    5350 3700
-	-1   0    0    1   
-$EndComp
-Connection ~ 3100 3050
-Wire Wire Line
-	3750 3350 3950 3350
-Connection ~ 3950 3350
-Wire Wire Line
-	4850 3100 5050 3100
-Wire Wire Line
-	4900 3700 5100 3700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub
deleted file mode 100644
index a61a3409..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml
deleted file mode 100644
index 115ba703..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/analysis b/src/SubcircuitLibrary/half_adder/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/half_adder/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir b/src/SubcircuitLibrary/half_adder/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder.cir
+++ /dev/null
@@ -1,11 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2  1 4 3 d_xor		
-U3  1 4 2 d_and		
-U1  1 4 3 2 PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir.out b/src/SubcircuitLibrary/half_adder/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro
deleted file mode 100644
index 695ae0f6..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 11:27:22 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sch b/src/SubcircuitLibrary/half_adder/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder.sch
+++ /dev/null
@@ -1,152 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U2
-U 1 1 558A946A
-P 5650 3050
-F 0 "U2" H 5650 3050 60  0000 C CNN
-F 1 "d_xor" H 5700 3150 47  0000 C CNN
-F 2 "" H 5650 3050 60  0000 C CNN
-F 3 "" H 5650 3050 60  0000 C CNN
-	1    5650 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 558A94D5
-P 5700 3800
-F 0 "U3" H 5700 3800 60  0000 C CNN
-F 1 "d_and" H 5750 3900 60  0000 C CNN
-F 2 "" H 5700 3800 60  0000 C CNN
-F 3 "" H 5700 3800 60  0000 C CNN
-	1    5700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558A94F6
-P 4150 3000
-F 0 "U1" H 4200 3100 30  0000 C CNN
-F 1 "PORT" H 4150 3000 30  0000 C CNN
-F 2 "" H 4150 3000 60  0000 C CNN
-F 3 "" H 4150 3000 60  0000 C CNN
-	1    4150 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558A9543
-P 4150 3450
-F 0 "U1" H 4200 3550 30  0000 C CNN
-F 1 "PORT" H 4150 3450 30  0000 C CNN
-F 2 "" H 4150 3450 60  0000 C CNN
-F 3 "" H 4150 3450 60  0000 C CNN
-	2    4150 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558A9573
-P 6650 3000
-F 0 "U1" H 6700 3100 30  0000 C CNN
-F 1 "PORT" H 6650 3000 30  0000 C CNN
-F 2 "" H 6650 3000 60  0000 C CNN
-F 3 "" H 6650 3000 60  0000 C CNN
-	3    6650 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558A9606
-P 6700 3750
-F 0 "U1" H 6750 3850 30  0000 C CNN
-F 1 "PORT" H 6700 3750 30  0000 C CNN
-F 2 "" H 6700 3750 60  0000 C CNN
-F 3 "" H 6700 3750 60  0000 C CNN
-	4    6700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5200 2950 4450 2950
-Wire Wire Line
-	4450 2950 4450 3000
-Wire Wire Line
-	4450 3000 4400 3000
-Wire Wire Line
-	4400 3450 4550 3450
-Wire Wire Line
-	4550 3450 4550 3050
-Wire Wire Line
-	4550 3050 5200 3050
-Wire Wire Line
-	5250 3700 5000 3700
-Wire Wire Line
-	5000 3700 5000 2950
-Connection ~ 5000 2950
-Wire Wire Line
-	5250 3800 4850 3800
-Wire Wire Line
-	4850 3800 4850 3050
-Connection ~ 4850 3050
-Wire Wire Line
-	6100 3000 6400 3000
-Wire Wire Line
-	6150 3750 6450 3750
-Text Notes 4550 2950 0    60   ~ 0
-IN1\n\n
-Text Notes 4600 3150 0    60   ~ 0
-IN2
-Text Notes 6200 2950 0    60   ~ 0
-SUM\n
-Text Notes 6200 3650 0    60   ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sub b/src/SubcircuitLibrary/half_adder/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml
deleted file mode 100644
index b915f0da..00000000
--- a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_sub/analysis b/src/SubcircuitLibrary/half_sub/analysis
deleted file mode 100644
index 660a46cc..00000000
--- a/src/SubcircuitLibrary/half_sub/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib
deleted file mode 100644
index bd15e664..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir b/src/SubcircuitLibrary/half_sub/half_sub.cir
deleted file mode 100644
index f20f0368..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub.cir
+++ /dev/null
@@ -1,14 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor		
-U2  Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter		
-U4  Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out
deleted file mode 100644
index 91816956..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.pro b/src/SubcircuitLibrary/half_sub/half_sub.pro
deleted file mode 100644
index 90e3ded9..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=Wed 06 Mar 2019 11:10:38 PM IST
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sch b/src/SubcircuitLibrary/half_sub/half_sub.sch
deleted file mode 100644
index e70b1675..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub.sch
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U3
-U 1 1 5C7FDDA3
-P 4400 3150
-F 0 "U3" H 4400 3150 60  0000 C CNN
-F 1 "d_xor" H 4450 3250 47  0000 C CNN
-F 2 "" H 4400 3150 60  0000 C CNN
-F 3 "" H 4400 3150 60  0000 C CNN
-	1    4400 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_inverter U2
-U 1 1 5C7FDDD8
-P 3400 3750
-F 0 "U2" H 3400 3650 60  0000 C CNN
-F 1 "d_inverter" H 3400 3900 60  0000 C CNN
-F 2 "" H 3450 3700 60  0000 C CNN
-F 3 "" H 3450 3700 60  0000 C CNN
-	1    3400 3750
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C7FDE57
-P 4450 3750
-F 0 "U4" H 4450 3750 60  0000 C CNN
-F 1 "d_and" H 4500 3850 60  0000 C CNN
-F 2 "" H 4450 3750 60  0000 C CNN
-F 3 "" H 4450 3750 60  0000 C CNN
-	1    4450 3750
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3950 3150 3950 3650
-Wire Wire Line
-	3950 3650 4000 3650
-Wire Wire Line
-	3700 3750 4000 3750
-Wire Wire Line
-	3100 3750 3100 3050
-Wire Wire Line
-	2950 3050 3950 3050
-$Comp
-L PORT U1
-U 1 1 5C7FDF5A
-P 2700 3050
-F 0 "U1" H 2750 3150 30  0000 C CNN
-F 1 "PORT" H 2700 3050 30  0000 C CNN
-F 2 "" H 2700 3050 60  0000 C CNN
-F 3 "" H 2700 3050 60  0000 C CNN
-	1    2700 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C7FDF97
-P 3500 3350
-F 0 "U1" H 3550 3450 30  0000 C CNN
-F 1 "PORT" H 3500 3350 30  0000 C CNN
-F 2 "" H 3500 3350 60  0000 C CNN
-F 3 "" H 3500 3350 60  0000 C CNN
-	2    3500 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C7FE00A
-P 5300 3100
-F 0 "U1" H 5350 3200 30  0000 C CNN
-F 1 "PORT" H 5300 3100 30  0000 C CNN
-F 2 "" H 5300 3100 60  0000 C CNN
-F 3 "" H 5300 3100 60  0000 C CNN
-	3    5300 3100
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C7FE064
-P 5350 3700
-F 0 "U1" H 5400 3800 30  0000 C CNN
-F 1 "PORT" H 5350 3700 30  0000 C CNN
-F 2 "" H 5350 3700 60  0000 C CNN
-F 3 "" H 5350 3700 60  0000 C CNN
-	4    5350 3700
-	-1   0    0    1   
-$EndComp
-Connection ~ 3100 3050
-Wire Wire Line
-	3750 3350 3950 3350
-Connection ~ 3950 3350
-Wire Wire Line
-	4850 3100 5050 3100
-Wire Wire Line
-	4900 3700 5100 3700
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub
deleted file mode 100644
index a61a3409..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_sub
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml
deleted file mode 100644
index 115ba703..00000000
--- a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/NPN.lib b/src/SubcircuitLibrary/lm555n/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/lm555n/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis
deleted file mode 100644
index a0953567..00000000
--- a/src/SubcircuitLibrary/lm555n/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib
deleted file mode 100644
index 824af11e..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib
+++ /dev/null
@@ -1,205 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND-RESCUE-lm555n
-#
-DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 75 50 H I C CNN
-F1 "PWR_FLAG" 0 150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
-ENDDRAW
-ENDDEF
-#
-# R-RESCUE-lm555n
-#
-DEF R-RESCUE-lm555n R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-$FPLIST
- R?
- SM0603
- SM0805
- R?-*
-$ENDFPLIST
-DRAW
-S -40 150 40 -150 0 1 12 N
-X ~ 1 0 250 100 D 60 60 1 1 P
-X ~ 2 0 -250 100 U 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# VCVS
-#
-DEF VCVS E 0 40 Y Y 1 F N
-F0 "E" 0 150 50 H V C CNN
-F1 "VCVS" -200 -50 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-# adc_bridge_1
-#
-DEF adc_bridge_1 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "adc_bridge_1" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -50 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X OUT1 2 550 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_srlatch
-#
-DEF d_srlatch U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_srlatch" 50 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 600 550 -600 -600 0 1 0 N
-X S 1 -800 400 200 R 50 50 1 1 I
-X R 2 -800 -450 200 R 50 50 1 1 I
-X EN 3 -800 0 200 R 50 50 1 1 I
-X Set 4 0 750 200 D 50 50 1 1 I
-X Reset 5 0 -800 200 U 50 50 1 1 I
-X Out 6 800 400 200 L 50 50 1 1 O
-X Nout 7 800 -450 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# dac_bridge_1
-#
-DEF dac_bridge_1 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "dac_bridge_1" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -50 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X OUT1 2 550 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 P
-X B 2 -200 0 225 R 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# limit
-#
-DEF limit U 0 40 Y Y 1 F N
-F0 "U" 50 -50 60 H V C CNN
-F1 "limit" 50 50 60 H V C CNN
-F2 "" 0 50 60 H V C CNN
-F3 "" 0 50 60 H V C CNN
-DRAW
-C 300 0 0 0 1 0 N
-P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N
-X IN 1 -400 0 200 R 50 50 1 1 I
-X OUT 2 600 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib
deleted file mode 100644
index fffeca36..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib
+++ /dev/null
@@ -1,18 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# d_inverter-RESCUE-lm555n
-#
-DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N
-F0 "U" -150 100 40 H V C CNN
-F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N
-X in 1 -250 0 150 R 25 25 1 1 I
-X out 2 250 0 150 L 25 25 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir
deleted file mode 100644
index 682d4945..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir
+++ /dev/null
@@ -1,31 +0,0 @@
-* /home/ash98/Downloads/lm555n/lm555n.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-E2  Net-_E2-Pad1_ GND /c /d 10000		
-U1  Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT		
-R8  Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500		
-R7  Net-_E2-Pad1_ Net-_R7-Pad2_ 25		
-R6  Net-_E1-Pad1_ Net-_R6-Pad2_ 25		
-E1  Net-_E1-Pad1_ GND /b /a 10000		
-R4  /b /a 2E6		
-R5  /c /d 2E6		
-R3  /c Net-_Q1-Pad3_ 5000		
-R2  /a /c 5000		
-R1  Net-_R1-Pad1_ /a 5000		
-U8  Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch		
-U7  Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter		
-U5  Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1		
-U4  Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1		
-U6  Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1		
-U3  Net-_R7-Pad2_ Net-_U3-Pad2_ limit		
-U2  Net-_R6-Pad2_ Net-_U2-Pad2_ limit		
-U9  Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1		
-U10  Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1		
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-
-.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
deleted file mode 100644
index a81070a1..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out
+++ /dev/null
@@ -1,42 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
-.include npn_1.lib
-* Inverter d_inverter
-* SR Latch d_srlatch
-e2  18 0 23 14 10000
-* Limiter limit8
-* Digital to Analog converter dac8
-* Analog to Digital converter adc8
-u1  22 14 7 6 15 16 3 13 port
-r8  9 2 1500
-q1 3 2 22 npn_1
-r7  18 20 25
-r6  17 19 25
-e1  17 0 16 15 10000
-r4  16 15 2e6
-r5  23 14 2e6
-r3  23 22 5000
-r2  15 23 5000
-r1  13 15 5000
-a1 5 21 u5
-.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
-a2 1 4 5 21 21 8 10 u6
-.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
-+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
-+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
-a3 19 11 u4
-a4 20 12 u4
-.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0)
-a5 [8] [7] u3
-a6 [10] [9] u3
-.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
-a7 [11] [4] u2
-a8 [12] [1] u2
-a9 [6] [5] u2
-.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
-
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro
deleted file mode 100644
index 0a5408b6..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=Tue Apr  2 17:35:59 2019
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=/home/yogesh/FreeEDA/library
-[eeschema/libraries]
-LibName1=lm555n-rescue
-LibName2=power
-LibName3=device
-LibName4=transistors
-LibName5=conn
-LibName6=linear
-LibName7=regul
-LibName8=74xx
-LibName9=cmos4000
-LibName10=adc-dac
-LibName11=memory
-LibName12=xilinx
-LibName13=special
-LibName14=microcontrollers
-LibName15=dsp
-LibName16=microchip
-LibName17=analog_switches
-LibName18=motorola
-LibName19=texas
-LibName20=intel
-LibName21=audio
-LibName22=interface
-LibName23=digital-audio
-LibName24=philips
-LibName25=display
-LibName26=cypress
-LibName27=siliconi
-LibName28=opto
-LibName29=atmel
-LibName30=contrib
-LibName31=valves
-LibName32=analogSpice
-LibName33=analogXSpice
-LibName34=converterSpice
-LibName35=digitalSpice
-LibName36=linearSpice
-LibName37=measurementSpice
-LibName38=portSpice
-LibName39=sourcesSpice
-LibName40=digitalXSpice
-LibName41=eSim_User
-LibName42=eSim_Subckt
-LibName43=eSim_Sources
-LibName44=eSim_PSpice
-LibName45=eSim_Power
-LibName46=eSim_Plot
-LibName47=eSim_Miscellaneous
-LibName48=eSim_Hybrid
-LibName49=eSim_Digital
-LibName50=eSim_Devices
-LibName51=eSim_Analog
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch
deleted file mode 100644
index 28110b13..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.sch
+++ /dev/null
@@ -1,518 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:lm555n-rescue
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:eSim_Sources
-LIBS:eSim_PSpice
-LIBS:eSim_Power
-LIBS:eSim_Plot
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Hybrid
-LIBS:eSim_Digital
-LIBS:eSim_Devices
-LIBS:eSim_Analog
-LIBS:lm555n-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "17 dec 2012"
-Rev ""
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diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub
deleted file mode 100644
index b524f5c6..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n.sub
+++ /dev/null
@@ -1,39 +0,0 @@
-* Subcircuit lm555n
-.subckt lm555n 22 14 7 6 15 16 3 13
-.include npn_1.lib 
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
-* Inverter d_inverter
-* SR Latch d_srlatch
-e2  18 0 23 14 10000
-* Limiter limit8
-* Digital to Analog converter dac8
-* Analog to Digital converter adc8
-r8  9 2 1500
-q1 3 2 22 npn_1
-r7  18 20 25
-r6  17 19 25
-e1  17 0 16 15 10000
-r4  16 15 2e6
-r5  23 14 2e6
-r3  23 22 5000
-r2  15 23 5000
-r1  13 15 5000
-a1 5 21 u5
-.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
-a2 1 4 5 21 21 8 10 u6
-.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
-+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
-+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
-a3 19 11 u4
-a4 20 12 u4
-.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0)
-a5 [8] [7] u3
-a6 [10] [9] u3
-.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
-a7 [11] [4] u2
-a8 [12] [1] u2
-a9 [6] [5] u2
-.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
-*control statements
-
-.ends lm555n
diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
deleted file mode 100644
index 58d33ec5..00000000
--- a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/npn_1.lib b/src/SubcircuitLibrary/lm555n/npn_1.lib
deleted file mode 100644
index a1818ed8..00000000
--- a/src/SubcircuitLibrary/lm555n/npn_1.lib
+++ /dev/null
@@ -1,29 +0,0 @@
-.model npn_1 NPN(
-+ Vtf=1.7 
-+ Cjc=0.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.5p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=500
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=125
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/NPN.lib b/src/SubcircuitLibrary/lm7805/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/lm7805/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm7805/PNP.lib b/src/SubcircuitLibrary/lm7805/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/lm7805/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/lm7805/Q_PNP.lib b/src/SubcircuitLibrary/lm7805/Q_PNP.lib
deleted file mode 100644
index 154ed2d8..00000000
--- a/src/SubcircuitLibrary/lm7805/Q_PNP.lib
+++ /dev/null
@@ -1 +0,0 @@
-.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/analysis b/src/SubcircuitLibrary/lm7805/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/lm7805/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib
deleted file mode 100644
index aaf8454e..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib
+++ /dev/null
@@ -1,136 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-F2 "" -70 0 50 V V C CNN
-F3 "" 0 0 50 H V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S -40 -100 40 100 0 1 10 N
-X ~ 1 0 150 50 D 50 50 1 1 P
-X ~ 2 0 -150 50 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 P
-X B 2 -200 0 225 R 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 P
-X B 2 -200 0 225 R 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# zener
-#
-DEF zener U 0 40 Y Y 1 F N
-F0 "U" -50 -100 60 H V C CNN
-F1 "zener" 0 100 60 H V C CNN
-F2 "" 50 0 60 H V C CNN
-F3 "" 50 0 60 H V C CNN
-DRAW
-P 2 0 1 0 100 -50 50 -100 N
-P 2 0 1 0 100 50 100 -50 N
-P 2 0 1 0 100 50 150 100 N
-P 4 0 1 0 0 50 0 -50 100 0 0 50 N
-X ~ IN -200 0 200 R 50 43 1 1 I
-X ~ OUT 300 0 200 L 50 43 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir b/src/SubcircuitLibrary/lm7805/lm7805.cir
deleted file mode 100644
index 081b4920..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805.cir
+++ /dev/null
@@ -1,51 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1  Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k		
-R2  Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500		
-R3  Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k		
-R4  Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k		
-U1  Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener		
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-R5  Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500		
-Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q4  Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN		
-R6  Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k		
-Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
-R7  Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k		
-Q6  Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN		
-R10  Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k		
-Q7  Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN		
-Q8  Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN		
-Q12  Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN		
-R12  Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k		
-R9  Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k		
-Q5  Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP		
-Q9  Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP		
-R8  Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100		
-R11  Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
-Q11  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN		
-Q13  Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN		
-R13  Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
-R14  Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k		
-Q14  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP		
-Q15  Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN		
-R17  Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k		
-R16  Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k		
-R15  Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k		
-U2  Net-_Q15-Pad2_ Net-_R15-Pad2_ zener		
-Q16  Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN		
-Q17  Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN		
-R18  Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200		
-R20  Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3		
-R19  Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240		
-U3  Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir.out b/src/SubcircuitLibrary/lm7805/lm7805.cir.out
deleted file mode 100644
index f122fba6..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805.cir.out
+++ /dev/null
@@ -1,60 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir
-
-.include PNP.lib
-.include NPN.lib
-r1  net-_q16-pad1_ net-_q1-pad2_ 100k
-r2  net-_q16-pad1_ net-_q1-pad1_ 500
-r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
-r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
-* u1  net-_q10-pad3_ net-_q1-pad2_ zener
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-r5  net-_q10-pad2_ net-_q10-pad3_ 500
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
-r6  net-_q2-pad3_ net-_q3-pad1_ 1k
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
-r7  net-_q3-pad2_ net-_q10-pad3_ 6k
-q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
-r10  net-_q6-pad3_ net-_q10-pad3_ 1k
-q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
-q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
-q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
-r12  net-_q12-pad3_ net-_q2-pad3_ 6k
-r9  net-_q2-pad3_ net-_c1-pad2_ 20k
-q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
-q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
-r8  net-_q16-pad1_ net-_q5-pad3_ 100
-r11  net-_q16-pad1_ net-_q9-pad3_ 50
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
-q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
-r13  net-_q11-pad3_ net-_q10-pad3_ 6k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-r14  net-_q10-pad1_ net-_c1-pad1_ 6k
-q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
-q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
-r17  net-_q12-pad2_ net-_q10-pad3_ 5k
-r16  net-_q12-pad1_ net-_q12-pad2_ 1.385k
-r15  net-_q16-pad1_ net-_r15-pad2_ 10k
-* u2  net-_q15-pad2_ net-_r15-pad2_ zener
-q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
-q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
-r18  net-_q16-pad3_ net-_q12-pad1_ 200
-r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
-r19  net-_q17-pad3_ net-_q15-pad2_ 240
-* u3  net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port
-a1 net-_q10-pad3_ net-_q1-pad2_ u1
-a2 net-_q15-pad2_ net-_r15-pad2_ u2
-* Schematic Name: zener, NgSpice Name: zener
-.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
-* Schematic Name: zener, NgSpice Name: zener
-.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.pro b/src/SubcircuitLibrary/lm7805/lm7805.pro
deleted file mode 100644
index d410e2fa..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=Mon Aug 26 14:34:23 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
-
diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sch b/src/SubcircuitLibrary/lm7805/lm7805.sch
deleted file mode 100644
index 701d163d..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805.sch
+++ /dev/null
@@ -1,757 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:lm7805-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L R R1
-U 1 1 5CE41429
-P 1250 1600
-F 0 "R1" V 1330 1600 50  0000 C CNN
-F 1 "100k" V 1250 1600 50  0000 C CNN
-F 2 "" V 1180 1600 50  0001 C CNN
-F 3 "" H 1250 1600 50  0001 C CNN
-	1    1250 1600
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R2
-U 1 1 5CE4148B
-P 1950 1600
-F 0 "R2" V 2030 1600 50  0000 C CNN
-F 1 "500" V 1950 1600 50  0000 C CNN
-F 2 "" V 1880 1600 50  0001 C CNN
-F 3 "" H 1950 1600 50  0001 C CNN
-	1    1950 1600
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R3
-U 1 1 5CE414A5
-P 1950 3050
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-F 2 "" V 1880 3050 50  0001 C CNN
-F 3 "" H 1950 3050 50  0001 C CNN
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-F 2 "" V 1880 3750 50  0001 C CNN
-F 3 "" H 1950 3750 50  0001 C CNN
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-$Comp
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-F 2 "" H 1300 3350 60  0000 C CNN
-F 3 "" H 1300 3350 60  0000 C CNN
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-F 2 "" H 2050 2450 29  0000 C CNN
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-$EndComp
-$Comp
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-F 2 "" V 1880 4600 50  0001 C CNN
-F 3 "" H 1950 4600 50  0001 C CNN
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-$EndComp
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	1250 5200 3200 5200
-Wire Wire Line
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-Wire Wire Line
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-F 0 "Q2" H 2550 3400 50  0000 R CNN
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-F 2 "" H 2850 3450 29  0000 C CNN
-F 3 "" H 2650 3350 60  0000 C CNN
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-	1    0    0    -1  
-$EndComp
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-F 1 "eSim_NPN" H 3050 4250 50  0000 R CNN
-F 2 "" H 3300 4200 29  0000 C CNN
-F 3 "" H 3100 4100 60  0000 C CNN
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-$EndComp
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-F 1 "1k" V 2750 3850 50  0000 C CNN
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-F 3 "" H 2750 3850 50  0001 C CNN
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-$EndComp
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-F 0 "Q3" H 2750 4700 50  0000 R CNN
-F 1 "eSim_NPN" H 2800 4800 50  0000 R CNN
-F 2 "" H 3050 4750 29  0000 C CNN
-F 3 "" H 2850 4650 60  0000 C CNN
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-Wire Wire Line
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-Wire Wire Line
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-F 3 "" H 3200 4900 50  0001 C CNN
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-$EndComp
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-F 2 "" H 3850 4750 29  0000 C CNN
-F 3 "" H 3650 4650 60  0000 C CNN
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-F 2 "" V 3680 5100 50  0001 C CNN
-F 3 "" H 3750 5100 50  0001 C CNN
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-F 2 "" H 3900 2850 29  0000 C CNN
-F 3 "" H 3700 2750 60  0000 C CNN
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-$EndComp
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-F 2 "" H 3900 3500 29  0000 C CNN
-F 3 "" H 3700 3400 60  0000 C CNN
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-$EndComp
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-F 2 "" H 4550 3100 29  0000 C CNN
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-F 1 "eSim_PNP" H 3400 1850 50  0000 R CNN
-F 2 "" H 3650 1800 29  0000 C CNN
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-$EndComp
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-F 3 "" H 4200 1250 50  0001 C CNN
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-$EndComp
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-F 0 "Q10" H 4000 2250 50  0000 R CNN
-F 1 "eSim_NPN" H 4050 2350 50  0000 R CNN
-F 2 "" H 4300 2300 29  0000 C CNN
-F 3 "" H 4100 2200 60  0000 C CNN
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-$EndComp
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-Wire Wire Line
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-U 1 1 5CE4439E
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-F 1 "eSim_NPN" H 4250 4550 50  0000 R CNN
-F 2 "" H 4500 4500 29  0000 C CNN
-F 3 "" H 4300 4400 60  0000 C CNN
-	1    4300 4400
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-$EndComp
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-F 2 "" H 4800 4900 29  0000 C CNN
-F 3 "" H 4600 4800 60  0000 C CNN
-	1    4600 4800
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-$EndComp
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-U 1 1 5CE444B9
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-F 2 "" V 4330 5050 50  0001 C CNN
-F 3 "" H 4400 5050 50  0001 C CNN
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-	1    0    0    -1  
-$EndComp
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-F 0 "C1" H 4075 4250 50  0000 L CNN
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-F 2 "" H 4088 4000 30  0000 C CNN
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-	1    4050 4150
-	0    1    1    0   
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-Wire Wire Line
-	4400 4150 4400 4200
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-Wire Wire Line
-	4700 5300 4700 5000
-Connection ~ 4400 5300
-Wire Wire Line
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-U 1 1 5CE44FFF
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-F 2 "" V 4630 3650 50  0001 C CNN
-F 3 "" H 4700 3650 50  0001 C CNN
-	1    4700 3650
-	1    0    0    -1  
-$EndComp
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-F 2 "" H 5250 4050 29  0000 C CNN
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-	1    5050 3950
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-Wire Wire Line
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-	1    5400 2150
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-$EndComp
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-Wire Wire Line
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-Wire Wire Line
-	5300 2600 5300 2350
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-U 1 1 5CE46DDE
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-	1    6050 4250
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-$Comp
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-U 1 1 5CE47F7A
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-F 1 "10k" V 5850 1300 50  0000 C CNN
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-	1    5850 1300
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-	5850 1050 5850 1150
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-F 3 "" H 5900 1900 60  0000 C CNN
-	1    5850 1900
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-$EndComp
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-Wire Wire Line
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-Wire Wire Line
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-U 1 1 5CE4907A
-P 6550 1600
-F 0 "Q16" H 6450 1650 50  0000 R CNN
-F 1 "eSim_NPN" H 6500 1750 50  0000 R CNN
-F 2 "" H 6750 1700 29  0000 C CNN
-F 3 "" H 6550 1600 60  0000 C CNN
-	1    6550 1600
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-$EndComp
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-U 1 1 5CE4942E
-P 7300 1950
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-F 1 "eSim_NPN" H 7250 2100 50  0000 R CNN
-F 2 "" H 7500 2050 29  0000 C CNN
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-	1    7300 1950
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	6650 1400 6650 1050
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-U 1 1 5CE498BA
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-F 0 "R18" V 6730 2450 50  0000 C CNN
-F 1 "200" V 6650 2450 50  0000 C CNN
-F 2 "" V 6580 2450 50  0001 C CNN
-F 3 "" H 6650 2450 50  0001 C CNN
-	1    6650 2450
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-U 1 1 5CE4999A
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-F 2 "" V 7330 2450 50  0001 C CNN
-F 3 "" H 7400 2450 50  0001 C CNN
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-U 1 1 5CE49AF5
-P 7000 2250
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-F 2 "" V 6930 2250 50  0001 C CNN
-F 3 "" H 7000 2250 50  0001 C CNN
-	1    7000 2250
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-	5850 2250 6850 2250
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-Wire Wire Line
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-Wire Wire Line
-	7150 2250 7400 2250
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-Wire Wire Line
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-Wire Wire Line
-	6100 2650 7400 2650
-Wire Wire Line
-	7400 2650 7400 2600
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-Wire Wire Line
-	6650 2600 6650 2650
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-U 1 1 5CE4AAF6
-P 8050 1050
-F 0 "U3" H 8100 1150 30  0000 C CNN
-F 1 "PORT" H 8050 1050 30  0000 C CNN
-F 2 "" H 8050 1050 60  0000 C CNN
-F 3 "" H 8050 1050 60  0000 C CNN
-	1    8050 1050
-	-1   0    0    1   
-$EndComp
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-L PORT U3
-U 3 1 5CE4B13E
-P 7700 3000
-F 0 "U3" H 7750 3100 30  0000 C CNN
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-F 2 "" H 7700 3000 60  0000 C CNN
-F 3 "" H 7700 3000 60  0000 C CNN
-	3    7700 3000
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-$EndComp
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-U 2 1 5CE4B701
-P 6650 5300
-F 0 "U3" H 6700 5400 30  0000 C CNN
-F 1 "PORT" H 6650 5300 30  0000 C CNN
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-F 3 "" H 6650 5300 60  0000 C CNN
-	2    6650 5300
-	-1   0    0    1   
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-Wire Wire Line
-	5950 1600 5950 1550
-Wire Wire Line
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-Wire Wire Line
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-	7300 2650 7300 3000
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diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sub b/src/SubcircuitLibrary/lm7805/lm7805.sub
deleted file mode 100644
index 7ee1489c..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805.sub
+++ /dev/null
@@ -1,54 +0,0 @@
-* Subcircuit lm7805
-.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ 
-* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir
-.include PNP.lib
-.include NPN.lib
-r1  net-_q16-pad1_ net-_q1-pad2_ 100k
-r2  net-_q16-pad1_ net-_q1-pad1_ 500
-r3  net-_q1-pad3_ net-_q2-pad2_ 3.3k
-r4  net-_q2-pad2_ net-_q10-pad2_ 2.7k
-* u1  net-_q10-pad3_ net-_q1-pad2_ zener
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-r5  net-_q10-pad2_ net-_q10-pad3_ 500
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
-q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222
-r6  net-_q2-pad3_ net-_q3-pad1_ 1k
-q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222
-r7  net-_q3-pad2_ net-_q10-pad3_ 6k
-q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222
-r10  net-_q6-pad3_ net-_q10-pad3_ 1k
-q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222
-q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222
-q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222
-r12  net-_q12-pad3_ net-_q2-pad3_ 6k
-r9  net-_q2-pad3_ net-_c1-pad2_ 20k
-q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A
-q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A
-r8  net-_q16-pad1_ net-_q5-pad3_ 100
-r11  net-_q16-pad1_ net-_q9-pad3_ 50
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222
-q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222
-r13  net-_q11-pad3_ net-_q10-pad3_ 6k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-r14  net-_q10-pad1_ net-_c1-pad1_ 6k
-q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A
-q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222
-r17  net-_q12-pad2_ net-_q10-pad3_ 5k
-r16  net-_q12-pad1_ net-_q12-pad2_ 1.385k
-r15  net-_q16-pad1_ net-_r15-pad2_ 10k
-* u2  net-_q15-pad2_ net-_r15-pad2_ zener
-q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222
-q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222
-r18  net-_q16-pad3_ net-_q12-pad1_ 200
-r20  net-_q17-pad3_ net-_q12-pad1_ 0.3
-r19  net-_q17-pad3_ net-_q15-pad2_ 240
-a1 net-_q10-pad3_ net-_q1-pad2_ u1
-a2 net-_q15-pad2_ net-_r15-pad2_ u2
-* Schematic Name: zener, NgSpice Name: zener
-.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
-* Schematic Name: zener, NgSpice Name: zener
-.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 )
-* Control Statements
-
-.ends lm7805
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml
deleted file mode 100644
index 7395bd7c..00000000
--- a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/NPN.lib b/src/SubcircuitLibrary/lm_741/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/SubcircuitLibrary/lm_741/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/SubcircuitLibrary/lm_741/PNP.lib b/src/SubcircuitLibrary/lm_741/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/SubcircuitLibrary/lm_741/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/SubcircuitLibrary/lm_741/analysis b/src/SubcircuitLibrary/lm_741/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/lm_741/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib
deleted file mode 100644
index 04e3fecd..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib
+++ /dev/null
@@ -1,119 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20  -80 -30  80 -30 N
-P 2 0 1 20  -80 30  80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir b/src/SubcircuitLibrary/lm_741/lm_741.cir
deleted file mode 100644
index 4a5917ea..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741.cir
+++ /dev/null
@@ -1,43 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
-Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
-Q6  Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP		
-Q5  Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP		
-Q3  Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
-Q4  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q9  Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q8  Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN		
-Q7  Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
-R1  Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k		
-R2  Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k		
-R3  Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k		
-Q12  Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
-Q13  Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
-R4  Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k		
-R11  Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k		
-Q10  Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q11  Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
-Q14  Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
-R8  Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k		
-R7  Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
-Q16  Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN		
-Q15  Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN		
-R5  Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k		
-R6  Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50		
-Q17  Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN		
-Q18  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN		
-Q20  Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN		
-R9  Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25		
-R10  Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50		
-Q19  Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP		
-U1  Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir.out b/src/SubcircuitLibrary/lm_741/lm_741.cir.out
deleted file mode 100644
index a00bd86a..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741.cir.out
+++ /dev/null
@@ -1,46 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1  net-_q7-pad3_ net-_q12-pad3_ 1k
-r2  net-_q3-pad3_ net-_q12-pad3_ 50k
-r3  net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4  net-_q13-pad3_ net-_q12-pad3_ 5k
-r11  net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5  net-_q15-pad2_ net-_q12-pad3_ 50k
-r6  net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9  net-_q18-pad3_ net-_q20-pad3_ 25
-r10  net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* u1  net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.pro b/src/SubcircuitLibrary/lm_741/lm_741.pro
deleted file mode 100644
index cbe83f35..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=Fri Jun  7 21:53:51 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sch b/src/SubcircuitLibrary/lm_741/lm_741.sch
deleted file mode 100644
index b017fd2b..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741.sch
+++ /dev/null
@@ -1,697 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:lm_741-cache
-EELAYER 25 0
-EELAYER END
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-	7600 4950 7600 4500
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-Wire Wire Line
-	7600 2300 8600 2300
-Wire Wire Line
-	8300 2300 8300 2550
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-Connection ~ 7600 2300
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-F 0 "U1" H 1900 4950 30  0000 C CNN
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-F 2 "" H 1850 4850 60  0000 C CNN
-F 3 "" H 1850 4850 60  0000 C CNN
-	5    1850 4850
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-	1    1850 5100
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-Wire Wire Line
-	2550 4850 2550 4900
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-Connection ~ 4050 4900
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-F 3 "" H 9600 6050 60  0000 C CNN
-	8    9600 6050
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diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sub b/src/SubcircuitLibrary/lm_741/lm_741.sub
deleted file mode 100644
index fa8d27b1..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741.sub
+++ /dev/null
@@ -1,40 +0,0 @@
-* Subcircuit lm_741
-.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? 
-* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1  net-_q7-pad3_ net-_q12-pad3_ 1k
-r2  net-_q3-pad3_ net-_q12-pad3_ 50k
-r3  net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4  net-_q13-pad3_ net-_q12-pad3_ 5k
-r11  net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1  net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5  net-_q15-pad2_ net-_q12-pad3_ 50k
-r6  net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9  net-_q18-pad3_ net-_q20-pad3_ 25
-r10  net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* Control Statements
-
-.ends lm_741
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml
deleted file mode 100644
index b61322bb..00000000
--- a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/npn_1.lib b/src/SubcircuitLibrary/lm_741/npn_1.lib
deleted file mode 100644
index a1818ed8..00000000
--- a/src/SubcircuitLibrary/lm_741/npn_1.lib
+++ /dev/null
@@ -1,29 +0,0 @@
-.model npn_1 NPN(
-+ Vtf=1.7 
-+ Cjc=0.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.5p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=500
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=125
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm_741/pnp_1.lib b/src/SubcircuitLibrary/lm_741/pnp_1.lib
deleted file mode 100644
index a4ee06da..00000000
--- a/src/SubcircuitLibrary/lm_741/pnp_1.lib
+++ /dev/null
@@ -1,29 +0,0 @@
-.model pnp_1 PNP(
-+ Vtf=1.7 
-+ Cjc=1.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.3p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=250
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=25
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/analysis b/src/SubcircuitLibrary/opto_isolator_switch/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib
deleted file mode 100644
index 88d58478..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib
+++ /dev/null
@@ -1,99 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# CCCS
-#
-DEF CCCS F 0 40 Y Y 1 F N
-F0 "F" 0 150 50 H V C CNN
-F1 "CCCS" -200 -50 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir
deleted file mode 100644
index 5fc9dd50..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir
+++ /dev/null
@@ -1,15 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 20 15:52:58 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1  Net-_R1-Pad1_ Net-_F1-Pad3_ 1000		
-F1  Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_F1-Pad3_ Net-_F1-Pad4_ 3		
-R2  Net-_C1-Pad2_ Net-_F1-Pad4_ 1000		
-U1  Net-_R1-Pad1_ Net-_F1-Pad4_ Net-_C1-Pad1_ Net-_C1-Pad2_ PORT		
-C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 14n		
-
-.end
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out
deleted file mode 100644
index afeeaa02..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir
-
-r1  net-_r1-pad1_ net-_f1-pad3_ 1000
-* f1
-r2  net-_c1-pad2_ net-_f1-pad4_ 1000
-* u1  net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ port
-c1  net-_c1-pad1_ net-_c1-pad2_ 14n
-Vf1 net-_f1-pad3_ net-_f1-pad4_ 0
-f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro
deleted file mode 100644
index 47ae9917..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro
+++ /dev/null
@@ -1,83 +0,0 @@
-update=Thu Jun 20 15:32:48 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch
deleted file mode 100644
index 3f1c7298..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch
+++ /dev/null
@@ -1,178 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:opto_isolator_switch-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_R R1
-U 1 1 5D0B5974
-P 4350 3450
-F 0 "R1" H 4400 3580 50  0000 C CNN
-F 1 "1000" H 4400 3500 50  0000 C CNN
-F 2 "" H 4400 3430 30  0000 C CNN
-F 3 "" V 4400 3500 30  0000 C CNN
-	1    4350 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L CCCS F1
-U 1 1 5D0B59A2
-P 5200 3450
-F 0 "F1" H 5200 3600 50  0000 C CNN
-F 1 "3" H 5000 3400 50  0000 C CNN
-F 2 "" H 5200 3450 60  0000 C CNN
-F 3 "" H 5200 3450 60  0000 C CNN
-	1    5200 3450
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5D0B59D5
-P 5200 4050
-F 0 "R2" H 5250 4180 50  0000 C CNN
-F 1 "1000" H 5250 4100 50  0000 C CNN
-F 2 "" H 5250 4030 30  0000 C CNN
-F 3 "" V 5250 4100 30  0000 C CNN
-	1    5200 4050
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	4550 3400 5000 3400
-Wire Wire Line
-	5000 3500 4750 3500
-Wire Wire Line
-	4750 3500 4750 3700
-Wire Wire Line
-	5250 3950 5250 3750
-Wire Wire Line
-	5250 3150 5250 3000
-Wire Wire Line
-	5250 3000 5650 3000
-Wire Wire Line
-	5650 3000 5650 3350
-Wire Wire Line
-	5650 3350 5700 3350
-Wire Wire Line
-	5250 4250 5250 4350
-Wire Wire Line
-	4250 3400 4000 3400
-$Comp
-L PORT U1
-U 1 1 5D0B5AC7
-P 3750 3400
-F 0 "U1" H 3800 3500 30  0000 C CNN
-F 1 "PORT" H 3750 3400 30  0000 C CNN
-F 2 "" H 3750 3400 60  0000 C CNN
-F 3 "" H 3750 3400 60  0000 C CNN
-	1    3750 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5D0B5B16
-P 4750 3950
-F 0 "U1" H 4800 4050 30  0000 C CNN
-F 1 "PORT" H 4750 3950 30  0000 C CNN
-F 2 "" H 4750 3950 60  0000 C CNN
-F 3 "" H 4750 3950 60  0000 C CNN
-	2    4750 3950
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5D0B5B84
-P 6050 3800
-F 0 "U1" H 6100 3900 30  0000 C CNN
-F 1 "PORT" H 6050 3800 30  0000 C CNN
-F 2 "" H 6050 3800 60  0000 C CNN
-F 3 "" H 6050 3800 60  0000 C CNN
-	4    6050 3800
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5D0B5BF0
-P 5950 3350
-F 0 "U1" H 6000 3450 30  0000 C CNN
-F 1 "PORT" H 5950 3350 30  0000 C CNN
-F 2 "" H 5950 3350 60  0000 C CNN
-F 3 "" H 5950 3350 60  0000 C CNN
-	3    5950 3350
-	-1   0    0    1   
-$EndComp
-$Comp
-L eSim_C C1
-U 1 1 5D0B5EB6
-P 5500 3350
-F 0 "C1" H 5525 3450 50  0000 L CNN
-F 1 "14n" H 5525 3250 50  0000 L CNN
-F 2 "" H 5538 3200 30  0000 C CNN
-F 3 "" H 5500 3350 60  0000 C CNN
-	1    5500 3350
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5500 3200 5500 3000
-Connection ~ 5500 3000
-Wire Wire Line
-	5500 3500 5500 3800
-Wire Wire Line
-	5250 3800 5800 3800
-Connection ~ 5250 3800
-Connection ~ 5500 3800
-Wire Wire Line
-	5250 4350 4900 4350
-Wire Wire Line
-	4900 4350 4900 3500
-Connection ~ 4900 3500
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub
deleted file mode 100644
index 4f386a6f..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit opto_isolator_switch
-.subckt opto_isolator_switch net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir
-r1  net-_r1-pad1_ net-_f1-pad3_ 1000
-* f1
-r2  net-_c1-pad2_ net-_f1-pad4_ 1000
-c1  net-_c1-pad1_ net-_c1-pad2_ 14n
-Vf1 net-_f1-pad3_ net-_f1-pad4_ 0
-f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3
-* Control Statements
-
-.ends opto_isolator_switch
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml
deleted file mode 100644
index 2c2d65c1..00000000
--- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt
deleted file mode 100644
index e69de29b..00000000
diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt
deleted file mode 100644
index e69de29b..00000000
diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib
deleted file mode 100644
index ef18bb50..00000000
--- a/src/SubcircuitLibrary/scr/D.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL D1N750 D(
-+  Vj=.75
-+  Nbvl=14.976
-+  Cjo=175p
-+  Rs=.25
-+  Isr=1.859n
-+  Eg=1.11
-+  M=.5516
-+  Nbv=1.6989
-+  N=1
-+  Tbv1=-21.277u
-+  Bv=8.1
-+  Fc=.5
-+  Ikf=0
-+  Nr=2
-+  Ibv=20.245m
-+  Is=880.5E-18
-+  Xti=3
-+  Ibvl=1.9556m
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib
deleted file mode 100644
index a2f61dce..00000000
--- a/src/SubcircuitLibrary/scr/PowerDiode.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/analysis b/src/SubcircuitLibrary/scr/analysis
deleted file mode 100644
index 687c71ec..00000000
--- a/src/SubcircuitLibrary/scr/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-12 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib
deleted file mode 100644
index 0a685b80..00000000
--- a/src/SubcircuitLibrary/scr/scr-cache.lib
+++ /dev/null
@@ -1,150 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# C
-#
-DEF C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "C" 25 -100 50 H V L CNN
-F2 "" 38 -150 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 50 50 1 1 P
-X ~ 2 0 -150 110 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# CCCS
-#
-DEF CCCS F 0 40 Y Y 1 F N
-F0 "F" 0 150 50 H V C CNN
-F1 "CCCS" -200 -50 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-# DIODE
-#
-DEF DIODE D 0 40 N N 1 F N
-F0 "D" 0 100 40 H V C CNN
-F1 "DIODE" 0 -100 40 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- D?
- S*
-$ENDFPLIST
-DRAW
-P 2 0 1 6 50 50 50 -50 N
-P 3 0 1 0 -50 50 50 0 -50 -50 F
-X A 1 -200 0 150 R 40 40 1 1 P
-X K 2 200 0 150 L 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# R-RESCUE-scr
-#
-DEF R-RESCUE-scr R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "R-RESCUE-scr" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# aswitch
-#
-DEF aswitch U 0 40 Y Y 1 F N
-F0 "U" 450 300 60 H V C CNN
-F1 "aswitch" 450 200 60 H V C CNN
-F2 "" 450 100 60 H V C CNN
-F3 "" 450 100 60 H V C CNN
-DRAW
-S 200 250 650 100 0 1 0 N
-X ~ 2 0 150 200 R 50 50 1 1 O
-X ~ 3 850 150 200 L 50 50 1 1 O
-X ~ 1_IN 450 -100 200 U 50 20 1 1 I
-ENDDRAW
-ENDDEF
-#
-# dc-RESCUE-scr
-#
-DEF dc-RESCUE-scr v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/scr/scr-rescue.lib b/src/SubcircuitLibrary/scr/scr-rescue.lib
deleted file mode 100644
index 64237b7d..00000000
--- a/src/SubcircuitLibrary/scr/scr-rescue.lib
+++ /dev/null
@@ -1,39 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# R-RESCUE-scr
-#
-DEF R-RESCUE-scr R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "R-RESCUE-scr" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# dc-RESCUE-scr
-#
-DEF dc-RESCUE-scr v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/scr/scr.cir b/src/SubcircuitLibrary/scr/scr.cir
deleted file mode 100644
index 4b279764..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir
+++ /dev/null
@@ -1,20 +0,0 @@
-* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec  8 15:47:20 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  3 7 1 PORT		
-F2  3 9 2 3 100		
-D1  5 2 D		
-C1  3 9 10u		
-F1  3 9 4 3 10		
-v1  8 4 dc		
-v2  6 5 dc		
-U1  9 1 6 aswitch		
-R1  7 8 50		
-R2  3 9 1		
-
-.end
diff --git a/src/SubcircuitLibrary/scr/scr.cir.out b/src/SubcircuitLibrary/scr/scr.cir.out
deleted file mode 100644
index d600f25d..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir.out
+++ /dev/null
@@ -1,29 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-
-.include PowerDiode.lib
-* u2  3 7 1 port
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 (1 6)  u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) 
-.tran 0e-12 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro
deleted file mode 100644
index ca0df803..00000000
--- a/src/SubcircuitLibrary/scr/scr.pro
+++ /dev/null
@@ -1,45 +0,0 @@
-update=Wed Jul 31 19:51:09 2019
-last_client=kicad
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=scr-rescue
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Sources
-LibName8=eSim_Subckt
-LibName9=eSim_User
-LibName10=power
-LibName11=device
-LibName12=transistors
-LibName13=conn
-LibName14=linear
-LibName15=regul
-LibName16=74xx
-LibName17=cmos4000
-LibName18=adc-dac
-LibName19=memory
-LibName20=xilinx
-LibName21=special
-LibName22=microcontrollers
-LibName23=dsp
-LibName24=microchip
-LibName25=analog_switches
-LibName26=motorola
-LibName27=texas
-LibName28=intel
-LibName29=audio
-LibName30=interface
-LibName31=digital-audio
-LibName32=philips
-LibName33=display
-LibName34=cypress
-LibName35=siliconi
-LibName36=opto
-LibName37=atmel
-LibName38=contrib
-LibName39=valves
diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch
deleted file mode 100644
index 69244f56..00000000
--- a/src/SubcircuitLibrary/scr/scr.sch
+++ /dev/null
@@ -1,242 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:scr-rescue
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:scr-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "21 aug 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
-	3600 3250 3600 3150
-Connection ~ 5550 4950
-Wire Wire Line
-	5800 3900 5800 3850
-Wire Wire Line
-	5800 3850 6150 3850
-Wire Wire Line
-	6150 3850 6150 4950
-Wire Wire Line
-	6150 4950 3600 4950
-Connection ~ 4300 4950
-Wire Wire Line
-	4300 4950 4300 4050
-Wire Wire Line
-	4300 4050 3850 4050
-Wire Wire Line
-	4700 5400 4700 5950
-Wire Wire Line
-	4250 5950 4250 5500
-Connection ~ 4250 4950
-Wire Wire Line
-	4250 4950 4250 5200
-Wire Wire Line
-	5550 3600 5550 3450
-Wire Wire Line
-	5550 4950 5550 4250
-Wire Wire Line
-	3600 4950 3600 4400
-Wire Wire Line
-	3600 2300 3600 2850
-Wire Wire Line
-	3600 2300 3150 2300
-Wire Wire Line
-	3600 4150 3600 4300
-Wire Wire Line
-	5550 4150 5550 4000
-Wire Wire Line
-	5550 2550 5550 2250
-Wire Wire Line
-	4700 4950 4700 5100
-Connection ~ 4700 4950
-Wire Wire Line
-	6650 2000 6650 5950
-Connection ~ 4700 5950
-Wire Wire Line
-	3850 4650 3850 5950
-Wire Wire Line
-	3850 5950 6650 5950
-Connection ~ 4250 5950
-Wire Wire Line
-	5800 4500 5800 5950
-Connection ~ 5800 5950
-$Comp
-L PORT U2
-U 3 1 53F4C93D
-P 6650 2250
-F 0 "U2" H 6650 2200 30  0000 C CNN
-F 1 "PORT" H 6650 2250 30  0000 C CNN
-F 2 "" H 6650 2250 60  0001 C CNN
-F 3 "" H 6650 2250 60  0001 C CNN
-	3    6650 2250
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U2
-U 2 1 53F4C934
-P 2900 2300
-F 0 "U2" H 2900 2250 30  0000 C CNN
-F 1 "PORT" H 2900 2300 30  0000 C CNN
-F 2 "" H 2900 2300 60  0001 C CNN
-F 3 "" H 2900 2300 60  0001 C CNN
-	2    2900 2300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U2
-U 1 1 53F4C92A
-P 6400 4950
-F 0 "U2" H 6400 4900 30  0000 C CNN
-F 1 "PORT" H 6400 4950 30  0000 C CNN
-F 2 "" H 6400 4950 60  0001 C CNN
-F 3 "" H 6400 4950 60  0001 C CNN
-	1    6400 4950
-	-1   0    0    1   
-$EndComp
-$Comp
-L CCCS F2
-U 1 1 53F4C735
-P 5750 4200
-F 0 "F2" H 5550 4300 50  0000 C CNN
-F 1 "100" H 5550 4150 50  0000 C CNN
-F 2 "" H 5750 4200 60  0001 C CNN
-F 3 "" H 5750 4200 60  0001 C CNN
-	1    5750 4200
-	0    1    1    0   
-$EndComp
-$Comp
-L DIODE D1
-U 1 1 53F4C6D9
-P 5550 3800
-F 0 "D1" H 5550 3900 40  0000 C CNN
-F 1 "D" H 5550 3700 40  0000 C CNN
-F 2 "" H 5550 3800 60  0001 C CNN
-F 3 "" H 5550 3800 60  0001 C CNN
-	1    5550 3800
-	0    1    1    0   
-$EndComp
-$Comp
-L C C1
-U 1 1 53F4C6C2
-P 4700 5250
-F 0 "C1" H 4750 5350 50  0000 L CNN
-F 1 "10u" H 4750 5150 50  0000 L CNN
-F 2 "" H 4700 5250 60  0001 C CNN
-F 3 "" H 4700 5250 60  0001 C CNN
-	1    4700 5250
-	1    0    0    -1  
-$EndComp
-$Comp
-L CCCS F1
-U 1 1 53F4C67F
-P 3800 4350
-F 0 "F1" H 3600 4450 50  0000 C CNN
-F 1 "10" H 3600 4300 50  0000 C CNN
-F 2 "" H 3800 4350 60  0001 C CNN
-F 3 "" H 3800 4350 60  0001 C CNN
-	1    3800 4350
-	0    1    1    0   
-$EndComp
-$Comp
-L dc-RESCUE-scr v1
-U 1 1 565DBF58
-P 3600 3700
-F 0 "v1" H 3400 3800 60  0000 C CNN
-F 1 "dc" H 3400 3650 60  0000 C CNN
-F 2 "R1" H 3300 3700 60  0000 C CNN
-F 3 "" H 3600 3700 60  0000 C CNN
-	1    3600 3700
-	1    0    0    -1  
-$EndComp
-$Comp
-L dc-RESCUE-scr v2
-U 1 1 565DC066
-P 5550 3000
-F 0 "v2" H 5350 3100 60  0000 C CNN
-F 1 "dc" H 5350 2950 60  0000 C CNN
-F 2 "R1" H 5250 3000 60  0000 C CNN
-F 3 "" H 5550 3000 60  0000 C CNN
-	1    5550 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L aswitch U1
-U 1 1 565DC87E
-P 6400 2100
-F 0 "U1" H 6850 2400 60  0000 C CNN
-F 1 "aswitch" H 6850 2300 60  0000 C CNN
-F 2 "" H 6850 2200 60  0000 C CNN
-F 3 "" H 6850 2200 60  0000 C CNN
-	1    6400 2100
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5950 2000 6650 2000
-$Comp
-L R-RESCUE-scr R1
-U 1 1 5666B019
-P 3550 2950
-F 0 "R1" H 3600 3080 50  0000 C CNN
-F 1 "50" H 3600 3000 50  0000 C CNN
-F 2 "" H 3600 2930 30  0000 C CNN
-F 3 "" V 3600 3000 30  0000 C CNN
-	1    3550 2950
-	0    1    1    0   
-$EndComp
-$Comp
-L R-RESCUE-scr R2
-U 1 1 5666B17A
-P 4200 5300
-F 0 "R2" H 4250 5430 50  0000 C CNN
-F 1 "1" H 4250 5350 50  0000 C CNN
-F 2 "" H 4250 5280 30  0000 C CNN
-F 3 "" V 4250 5350 30  0000 C CNN
-	1    4200 5300
-	0    1    1    0   
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/scr/scr.sub b/src/SubcircuitLibrary/scr/scr.sub
deleted file mode 100644
index 398c8921..00000000
--- a/src/SubcircuitLibrary/scr/scr.sub
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1 
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 (1 6)  u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr
diff --git a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml
deleted file mode 100644
index 8ff6e8d3..00000000
--- a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/scr/userDiode.lib b/src/SubcircuitLibrary/scr/userDiode.lib
deleted file mode 100644
index 89b96f4a..00000000
--- a/src/SubcircuitLibrary/scr/userDiode.lib
+++ /dev/null
@@ -1 +0,0 @@
-.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
diff --git a/src/SubcircuitLibrary/triac/PowerDiode.lib b/src/SubcircuitLibrary/triac/PowerDiode.lib
deleted file mode 100644
index d6fb6469..00000000
--- a/src/SubcircuitLibrary/triac/PowerDiode.lib
+++ /dev/null
@@ -1 +0,0 @@
-.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/src/SubcircuitLibrary/triac/analysis b/src/SubcircuitLibrary/triac/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/triac/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/triac/triac-cache.lib b/src/SubcircuitLibrary/triac/triac-cache.lib
deleted file mode 100644
index 0466a3e6..00000000
--- a/src/SubcircuitLibrary/triac/triac-cache.lib
+++ /dev/null
@@ -1,139 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# C
-#
-DEF C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C?
- C_????_*
- C_????
- SMD*_c
- Capacitor*
-$ENDFPLIST
-DRAW
-P 2 0 1 20  -80 -30  80 -30 N
-P 2 0 1 20  -80 30  80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# CCCS
-#
-DEF CCCS F 0 40 Y Y 1 F N
-F0 "F" 0 150 50 H V C CNN
-F1 "CCCS" -200 -50 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-# D
-#
-DEF D D 0 40 N N 1 F N
-F0 "D" 0 100 50 H V C CNN
-F1 "D" 0 -100 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- Diode_*
- D-Pak_TO252AA
- *SingleDiode
- *_Diode_*
- *SingleDiode*
-$ENDFPLIST
-DRAW
-P 2 0 1 6  50 50  50 -50 N
-P 3 0 1 0  -50 50  50 0  -50 -50 F
-X A 1 -150 0 100 R 40 40 1 1 P
-X K 2 150 0 100 L 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# aswitch
-#
-DEF aswitch U 0 40 Y Y 1 F N
-F0 "U" 450 300 60 H V C CNN
-F1 "aswitch" 450 200 60 H V C CNN
-F2 "" 450 100 60 H V C CNN
-F3 "" 450 100 60 H V C CNN
-DRAW
-S 200 250 650 100 0 1 0 N
-X ~ 2 0 150 200 R 50 50 1 1 O
-X ~ 3 850 150 200 L 50 50 1 1 O
-X ~ 1_IN 450 -100 200 U 50 20 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/triac/triac.cir b/src/SubcircuitLibrary/triac/triac.cir
deleted file mode 100644
index c533d42f..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir
+++ /dev/null
@@ -1,23 +0,0 @@
-* /opt/eSim/src/SubcircuitLibrary/triac/triac.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec  8 15:32:06 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3  8 11 10 PORT		
-F3  8 9 1 8 10		
-v3  7 2 DC		
-F2  8 9 3 5 10		
-v2  6 3 DC		
-C1  8 9 10u		
-F1  8 9 4 8 100		
-v1  10 4 DC		
-U1  9 11 6 aswitch		
-U2  9 2 11 aswitch		
-R1  8 9 1		
-D1  5 8 D		
-D2  1 7 D		
-
-.end
diff --git a/src/SubcircuitLibrary/triac/triac.cir.out b/src/SubcircuitLibrary/triac/triac.cir.out
deleted file mode 100644
index d2eb7c77..00000000
--- a/src/SubcircuitLibrary/triac/triac.cir.out
+++ /dev/null
@@ -1,38 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-
-.include PowerDiode.lib
-* u3  8 11 10 port
-* f3
-v3 7 2  dc 0
-* f2
-v2 6 3  dc 0
-c1  8 9 10u
-* f1
-v1 10 4  dc 0
-* u1  9 11 6 aswitch
-* u2  9 2 11 aswitch
-r1  8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 (11 6)  u1
-a2 9 (2 11)  u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
-
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/triac/triac.pro b/src/SubcircuitLibrary/triac/triac.pro
deleted file mode 100644
index 5b1f5f89..00000000
--- a/src/SubcircuitLibrary/triac/triac.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Tue Dec  8 14:16:32 2015
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Sources
-LibName7=eSim_Subckt
-LibName8=eSim_User
-LibName9=power
-LibName10=device
-LibName11=transistors
-LibName12=conn
-LibName13=linear
-LibName14=regul
-LibName15=74xx
-LibName16=cmos4000
-LibName17=adc-dac
-LibName18=memory
-LibName19=xilinx
-LibName20=special
-LibName21=microcontrollers
-LibName22=dsp
-LibName23=microchip
-LibName24=analog_switches
-LibName25=motorola
-LibName26=texas
-LibName27=intel
-LibName28=audio
-LibName29=interface
-LibName30=digital-audio
-LibName31=philips
-LibName32=display
-LibName33=cypress
-LibName34=siliconi
-LibName35=opto
-LibName36=atmel
-LibName37=contrib
-LibName38=valves
diff --git a/src/SubcircuitLibrary/triac/triac.sch b/src/SubcircuitLibrary/triac/triac.sch
deleted file mode 100644
index f30533a0..00000000
--- a/src/SubcircuitLibrary/triac/triac.sch
+++ /dev/null
@@ -1,308 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:triac-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "22 sep 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L PORT U3
-U 3 1 541D1606
-P 1250 1750
-F 0 "U3" H 1250 1700 30  0000 C CNN
-F 1 "PORT" H 1250 1750 30  0000 C CNN
-F 2 "" H 1250 1750 60  0001 C CNN
-F 3 "" H 1250 1750 60  0001 C CNN
-	3    1250 1750
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U3
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-F 1 "PORT" H 1300 900 30  0000 C CNN
-F 2 "" H 1300 900 60  0001 C CNN
-F 3 "" H 1300 900 60  0001 C CNN
-	2    1300 900 
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U3
-U 1 1 541D15F6
-P 1150 4050
-F 0 "U3" H 1150 4000 30  0000 C CNN
-F 1 "PORT" H 1150 4050 30  0000 C CNN
-F 2 "" H 1150 4050 60  0001 C CNN
-F 3 "" H 1150 4050 60  0001 C CNN
-	1    1150 4050
-	1    0    0    -1  
-$EndComp
-$Comp
-L CCCS F3
-U 1 1 541D1417
-P 6250 3100
-F 0 "F3" H 6050 3200 50  0000 C CNN
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-F 2 "" H 6250 3100 60  0001 C CNN
-F 3 "" H 6250 3100 60  0001 C CNN
-	1    6250 3100
-	0    1    1    0   
-$EndComp
-$Comp
-L DC v3
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-F 2 "R1" H 5750 1950 60  0000 C CNN
-F 3 "" H 6050 1950 60  0001 C CNN
-	1    6050 1950
-	-1   0    0    1   
-$EndComp
-$Comp
-L CCCS F2
-U 1 1 541D13A3
-P 3900 2550
-F 0 "F2" H 3700 2650 50  0000 C CNN
-F 1 "10" H 3700 2500 50  0000 C CNN
-F 2 "" H 3900 2550 60  0001 C CNN
-F 3 "" H 3900 2550 60  0001 C CNN
-	1    3900 2550
-	0    1    1    0   
-$EndComp
-$Comp
-L DC v2
-U 1 1 541D1398
-P 3700 1850
-F 0 "v2" H 3500 1950 60  0000 C CNN
-F 1 "DC" H 3500 1800 60  0000 C CNN
-F 2 "R1" H 3400 1850 60  0000 C CNN
-F 3 "" H 3700 1850 60  0001 C CNN
-	1    3700 1850
-	1    0    0    -1  
-$EndComp
-$Comp
-L C C1
-U 1 1 541D137C
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-F 0 "C1" H 3350 4450 50  0000 L CNN
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-F 2 "" H 3300 4350 60  0001 C CNN
-F 3 "" H 3300 4350 60  0001 C CNN
-	1    3300 4350
-	1    0    0    -1  
-$EndComp
-$Comp
-L CCCS F1
-U 1 1 541D1363
-P 2100 3600
-F 0 "F1" H 1900 3700 50  0000 C CNN
-F 1 "100" H 1900 3550 50  0000 C CNN
-F 2 "" H 2100 3600 60  0001 C CNN
-F 3 "" H 2100 3600 60  0001 C CNN
-	1    2100 3600
-	0    1    1    0   
-$EndComp
-$Comp
-L DC v1
-U 1 1 541D1357
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-F 3 "" H 1900 2900 60  0001 C CNN
-	1    1900 2900
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-$EndComp
-$Comp
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-U 1 1 56669B8A
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-F 1 "aswitch" H 5050 1300 60  0000 C CNN
-F 2 "" H 5050 1200 60  0000 C CNN
-F 3 "" H 5050 1200 60  0000 C CNN
-	1    4600 1100
-	-1   0    0    1   
-$EndComp
-$Comp
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-$EndComp
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-Connection ~ 4450 4050
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	4150 700  4150 1000
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-Wire Wire Line
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-$Comp
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-U 1 1 5666A886
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-F 1 "1" H 2750 4300 50  0000 C CNN
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-$Comp
-L D D2
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-	1    6050 2650
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-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/triac/triac.sub b/src/SubcircuitLibrary/triac/triac.sub
deleted file mode 100644
index 760908b0..00000000
--- a/src/SubcircuitLibrary/triac/triac.sub
+++ /dev/null
@@ -1,32 +0,0 @@
-* Subcircuit triac
-.subckt triac 8 11 10 
-* /opt/esim/src/subcircuitlibrary/triac/triac.cir
-.include PowerDiode.lib
-* f3
-v3 7 2  dc 0
-* f2
-v2 6 3  dc 0
-c1  8 9 10u
-* f1
-v1 10 4  dc 0
-* u1  9 11 6 aswitch
-* u2  9 2 11 aswitch
-r1  8 9 1
-d1 5 8 PowerDiode
-d2 1 7 PowerDiode
-Vf3 1 8 0
-f3 8 9 Vf3 10
-Vf2 3 5 0
-f2 8 9 Vf2 10
-Vf1 4 8 0
-f1 8 9 Vf1 100
-a1 9 (11 6)  u1
-a2 9 (2 11)  u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
-
-* Control Statements
-
-.ends triac
diff --git a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml
deleted file mode 100644
index 80da52b3..00000000
--- a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">1</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-1</field10></u2></model><devicemodel><d2><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d2><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/analysis b/src/SubcircuitLibrary/ua741/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/ua741/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.lib b/src/SubcircuitLibrary/ua741/ua741-cache.lib
deleted file mode 100644
index 9114d342..00000000
--- a/src/SubcircuitLibrary/ua741/ua741-cache.lib
+++ /dev/null
@@ -1,100 +0,0 @@
-EESchema-LIBRARY Version 2.3  Date: Saturday 17 November 2012 08:10:48 AM IST
-#encoding utf-8
-#
-# C
-#
-DEF C C 0 10 N Y 1 F N
-F0 "C" 50 100 50 H V L CNN
-F1 "C" 50 -100 50 H V L CNN
-$FPLIST
- SM*
- C?
- C1-1
-$ENDFPLIST
-DRAW
-P 2 0 1 10  -100 -30  100 -30 N
-P 2 0 1 10  -100 30  100 30 N
-X ~ 1 0 200 170 D 40 40 1 1 P
-X ~ 2 0 -200 170 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GND
-#
-DEF ~GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND" 0 -70 30 H I C CNN
-DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 0 -50 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 270 30 H I C CNN
-F1 "PWR_FLAG" 0 230 30 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 3 0 1 0  0 0  0 100  0 100 N
-P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-$FPLIST
- R?
- SM0603
- SM0805
- R?-*
-$ENDFPLIST
-DRAW
-S -40 150 40 -150 0 1 12 N
-X ~ 1 0 250 100 D 60 60 1 1 P
-X ~ 2 0 -250 100 U 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# VCVS
-#
-DEF VCVS E 0 40 Y Y 1 F N
-F0 "E" -200 100 50 H V C CNN
-F1 "VCVS" -200 -50 50 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/ua741/ua741.cir b/src/SubcircuitLibrary/ua741/ua741.cir
deleted file mode 100644
index de797429..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.cir
+++ /dev/null
@@ -1,15 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U1  6 7 3 PORT		
-Rout1  3 2 75		
-Eout1  2 0 1 0 1		
-Cbw1  1 0 31.85e-9		
-Rbw1  1 4 0.5e6		
-Ein1  4 0 7 6 100e3		
-Rin1  7 6 2e6		
-
-.end
diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.out b/src/SubcircuitLibrary/ua741/ua741.cir.out
deleted file mode 100644
index 72e68514..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
-
-* u1  6 7 3 port
-rout1  3 2 75
-eout1  2 0 1 0 1
-cbw1  1 0 31.85e-9
-rbw1  1 4 0.5e6
-ein1  4 0 7 6 100e3
-rin1  7 6 2e6
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro
deleted file mode 100644
index 5dbb81a5..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.pro
+++ /dev/null
@@ -1,72 +0,0 @@
-update=Monday 17 December 2012 06:14:06 PM IST
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=/home/yogesh/FreeEDA/library
-NetFmt=1
-HPGLSpd=20
-HPGLDm=15
-HPGLNum=1
-offX_A4=0
-offY_A4=0
-offX_A3=0
-offY_A3=0
-offX_A2=0
-offY_A2=0
-offX_A1=0
-offY_A1=0
-offX_A0=0
-offY_A0=0
-offX_A=0
-offY_A=0
-offX_B=0
-offY_B=0
-offX_C=0
-offY_C=0
-offX_D=0
-offY_D=0
-offX_E=0
-offY_E=0
-RptD_X=0
-RptD_Y=100
-RptLab=1
-LabSize=60
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=analogSpice
-LibName32=converterSpice
-LibName33=digitalSpice
-LibName34=linearSpice
-LibName35=measurementSpice
-LibName36=portSpice
-LibName37=sourcesSpice
-LibName38=analogXSpice
diff --git a/src/SubcircuitLibrary/ua741/ua741.sch b/src/SubcircuitLibrary/ua741/ua741.sch
deleted file mode 100644
index 7dfc5e1a..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.sch
+++ /dev/null
@@ -1,219 +0,0 @@
-EESchema Schematic File Version 2  date Wednesday 19 December 2012 10:15:16 AM IST
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:analogXSpice
-LIBS:ua741-cache
-EELAYER 25  0
-EELAYER END
-$Descr A4 11700 8267
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "19 dec 2012"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Text Notes 3800 2400 0    60   ~ 0
-Op-Amp
-Text Notes 3750 2850 0    60   ~ 0
-VCCS
-Text Notes 5800 2500 0    60   ~ 0
-out
-Text Notes 2750 3100 0    60   ~ 0
--
-Text Notes 2700 2600 0    60   ~ 0
-+
-$Comp
-L PORT U1
-U 6 1 5082C027
-P 6250 2500
-F 0 "U1" H 6250 2450 30  0000 C CNN
-F 1 "PORT" H 6250 2500 30  0000 C CNN
-	6    6250 2500
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5082C011
-P 2300 3100
-F 0 "U1" H 2300 3050 30  0000 C CNN
-F 1 "PORT" H 2300 3100 30  0000 C CNN
-	2    2300 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5082C00B
-P 2250 2600
-F 0 "U1" H 2250 2550 30  0000 C CNN
-F 1 "PORT" H 2250 2600 30  0000 C CNN
-	3    2250 2600
-	1    0    0    -1  
-$EndComp
-Connection ~ 3700 3200
-Wire Wire Line
-	3450 3200 3700 3200
-Connection ~ 5000 3300
-Wire Wire Line
-	3700 3300 5250 3300
-Wire Wire Line
-	5250 3300 5250 3200
-Connection ~ 4550 3300
-Wire Wire Line
-	5000 3300 5000 2950
-Connection ~ 3700 3300
-Wire Wire Line
-	4550 3300 4550 3100
-Wire Wire Line
-	3900 2500 3700 2500
-Wire Wire Line
-	3700 2500 3700 2550
-Wire Wire Line
-	3450 2900 3300 2900
-Wire Wire Line
-	3300 2900 3300 3200
-Wire Wire Line
-	3300 3200 2950 3200
-Connection ~ 2950 3100
-Wire Wire Line
-	2950 3200 2950 3100
-Wire Wire Line
-	3000 2600 2500 2600
-Wire Wire Line
-	2550 3100 3000 3100
-Wire Wire Line
-	2950 2600 2950 2500
-Connection ~ 2950 2600
-Wire Wire Line
-	2950 2500 3300 2500
-Wire Wire Line
-	3300 2500 3300 2800
-Wire Wire Line
-	3300 2800 3450 2800
-Wire Wire Line
-	3700 3150 3700 3400
-Wire Wire Line
-	4550 2500 4550 2700
-Wire Wire Line
-	4400 2500 5000 2500
-Wire Wire Line
-	5000 2500 5000 2850
-Connection ~ 4550 2500
-Wire Wire Line
-	5250 2600 5250 2500
-Wire Wire Line
-	5250 2500 5350 2500
-Wire Wire Line
-	5850 2500 6000 2500
-$Comp
-L PWR_FLAG #FLG01
-U 1 1 508152A0
-P 3450 3200
-F 0 "#FLG01" H 3450 3470 30  0001 C CNN
-F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
-	1    3450 3200
-	1    0    0    -1  
-$EndComp
-$Comp
-L R Rout1
-U 1 1 50813F5B
-P 5600 2500
-F 0 "Rout1" V 5680 2500 50  0000 C CNN
-F 1 "75" V 5600 2500 50  0000 C CNN
-	1    5600 2500
-	0    1    1    0   
-$EndComp
-$Comp
-L VCVS Eout1
-U 1 1 50813F0F
-P 5200 2900
-F 0 "Eout1" H 5000 3000 50  0000 C CNN
-F 1 "1" H 5000 2850 50  0000 C CNN
-	1    5200 2900
-	0    1    1    0   
-$EndComp
-$Comp
-L C Cbw1
-U 1 1 50813EE0
-P 4550 2900
-F 0 "Cbw1" H 4600 3000 50  0000 L CNN
-F 1 "31.85e-9" H 4600 2800 50  0000 L CNN
-	1    4550 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L R Rbw1
-U 1 1 50813EAB
-P 4150 2500
-F 0 "Rbw1" V 4230 2500 50  0000 C CNN
-F 1 "0.5e6" V 4150 2500 50  0000 C CNN
-	1    4150 2500
-	0    1    1    0   
-$EndComp
-$Comp
-L GND #PWR02
-U 1 1 50813E0D
-P 3700 3400
-F 0 "#PWR02" H 3700 3400 30  0001 C CNN
-F 1 "GND" H 3700 3330 30  0001 C CNN
-	1    3700 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L VCVS Ein1
-U 1 1 50813D7C
-P 3650 2850
-F 0 "Ein1" H 3450 2950 50  0000 C CNN
-F 1 "100e3" H 3450 2800 50  0000 C CNN
-	1    3650 2850
-	0    1    1    0   
-$EndComp
-$Comp
-L R Rin1
-U 1 1 50813C57
-P 3000 2850
-F 0 "Rin1" V 3080 2850 50  0000 C CNN
-F 1 "2e6" V 3000 2850 50  0000 C CNN
-	1    3000 2850
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/ua741/ua741.sub b/src/SubcircuitLibrary/ua741/ua741.sub
deleted file mode 100644
index ad26c001..00000000
--- a/src/SubcircuitLibrary/ua741/ua741.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit ua741
-.subckt ua741 6 7 3 
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
-rout1  3 2 75
-eout1  2 0 1 0 1
-cbw1  1 0 31.85e-9
-rbw1  1 4 0.5e6
-ein1  4 0 7 6 100e3
-rin1  7 6 2e6
-* Control Statements
-
-.ends ua741
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml
deleted file mode 100644
index 9c7bb530..00000000
--- a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ujt/D.lib b/src/SubcircuitLibrary/ujt/D.lib
deleted file mode 100644
index 8a7fb4da..00000000
--- a/src/SubcircuitLibrary/ujt/D.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis
deleted file mode 100644
index ffc57a6b..00000000
--- a/src/SubcircuitLibrary/ujt/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 5e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib
deleted file mode 100644
index 3e78b1ee..00000000
--- a/src/SubcircuitLibrary/ujt/emitter.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.model emitter D(
-+ Vj=1
-+ Cjo=1.700E-12
-+ Rs=4.755E-01
-+ Is=21.3P
-+ M=1.959E-01
-+ N=1.8
-+ Bv=1.000E+02
-+ tt=3.030E-09
-+ Ibv=1.000E-04
-)
diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt
deleted file mode 100644
index e69de29b..00000000
diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt
deleted file mode 100644
index e69de29b..00000000
diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib
deleted file mode 100644
index ff75f664..00000000
--- a/src/SubcircuitLibrary/ujt/ujt-cache.lib
+++ /dev/null
@@ -1,137 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# CCVS
-#
-DEF CCVS H 0 40 Y Y 1 F N
-F0 "H" 0 150 50 H V C CNN
-F1 "CCVS" -200 -50 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-S -100 100 100 -100 0 1 0 N
-X + 1 -300 50 200 R 35 35 1 1 P
-X - 2 300 50 200 L 35 35 1 1 P
-X +c 3 -50 -200 100 U 35 35 1 1 P
-X -c 4 50 -200 100 U 35 35 1 1 P
-ENDDRAW
-ENDDEF
-#
-# NLDS
-#
-DEF NLDS BB 0 40 Y Y 1 F N
-F0 "BB" 0 0 60 H V C CNN
-F1 "NLDS" 0 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 0 141 0 1 0 N
-X 1 1 0 350 200 D 50 50 1 1 B
-X 2 2 0 -350 200 U 50 50 1 1 B
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_Diode
-#
-DEF eSim_Diode D 0 40 N N 1 F N
-F0 "D" 0 100 50 H V C CNN
-F1 "eSim_Diode" 0 -100 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- TO-???*
- *SingleDiode
- *_Diode_*
- *SingleDiode*
- D_*
-$ENDFPLIST
-DRAW
-T 0 -100 50 60 0 0 0 A Normal 0 C C
-T 0 100 50 60 0 0 0 K Normal 0 C C
-P 2 0 1 6 50 50 50 -50 N
-P 3 0 1 0 -50 50 50 0 -50 -50 F
-X A 1 -150 0 100 R 40 40 1 1 P
-X K 2 150 0 100 L 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir
deleted file mode 100644
index e0e911d7..00000000
--- a/src/SubcircuitLibrary/ujt/ujt.cir
+++ /dev/null
@@ -1,18 +0,0 @@
-* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R3  /0 /6 1000k		
-H1  /6 /0 /4 /5 1k		
-C1  /5 /7 35p		
-R1  /7 /2 38.15k		
-R2  /3 /5 2.518k		
-U1  /1 /2 /3 PORT		
-B1  /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)		
-D1  /1 /4 eSim_Diode		
-
-.end
diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out
deleted file mode 100644
index 2045c539..00000000
--- a/src/SubcircuitLibrary/ujt/ujt.cir.out
+++ /dev/null
@@ -1,22 +0,0 @@
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-
-.include emitter.lib
-r3  /0 /6 1000k
-* h1
-c1  /5 /7 35p
-r1  /7 /2 38.15k
-r2  /3 /5 2.518k
-* u1  /1 /2 /3 port
-b1  /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
-d1 /1 /4 emitter
-Vh1 /4 /5 0
-h1 /6 /0 Vh1 1k
-.tran 5e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/ujt/ujt.pro b/src/SubcircuitLibrary/ujt/ujt.pro
deleted file mode 100644
index 24c5e186..00000000
--- a/src/SubcircuitLibrary/ujt/ujt.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Tue Jun 11 16:36:40 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
-LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch
deleted file mode 100644
index a82bddf7..00000000
--- a/src/SubcircuitLibrary/ujt/ujt.sch
+++ /dev/null
@@ -1,199 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:eSim_Sources
-LIBS:eSim_Power
-LIBS:eSim_Plot
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Hybrid
-LIBS:eSim_Digital
-LIBS:eSim_Devices
-LIBS:eSim_Analog
-LIBS:ujt-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_R R3
-U 1 1 5CF5F733
-P 6650 3400
-F 0 "R3" H 6700 3530 50  0000 C CNN
-F 1 "1000k" H 6700 3450 50  0000 C CNN
-F 2 "" H 6700 3380 30  0000 C CNN
-F 3 "" V 6700 3450 30  0000 C CNN
-	1    6650 3400
-	0    1    -1   0   
-$EndComp
-$Comp
-L CCVS H1
-U 1 1 5CF5F77B
-P 6150 3350
-F 0 "H1" H 6150 3500 50  0000 C CNN
-F 1 "1k" H 5950 3300 50  0000 C CNN
-F 2 "" H 6150 3350 60  0000 C CNN
-F 3 "" H 6150 3350 60  0000 C CNN
-	1    6150 3350
-	0    1    1    0   
-$EndComp
-$Comp
-L eSim_C C1
-U 1 1 5CF61B3A
-P 5150 4700
-F 0 "C1" H 5175 4800 50  0000 L CNN
-F 1 "35p" H 5175 4600 50  0000 L CNN
-F 2 "" H 5188 4550 30  0000 C CNN
-F 3 "" H 5150 4700 60  0000 C CNN
-	1    5150 4700
-	1    0    0    -1  
-$EndComp
-$Comp
-L eSim_R R1
-U 1 1 5CF6211F
-P 4300 4850
-F 0 "R1" H 4350 4980 50  0000 C CNN
-F 1 "38.15k" H 4350 4900 50  0000 C CNN
-F 2 "" H 4350 4830 30  0000 C CNN
-F 3 "" V 4350 4900 30  0000 C CNN
-	1    4300 4850
-	0    -1   -1   0   
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5CF6218A
-P 4550 3650
-F 0 "R2" H 4600 3780 50  0000 C CNN
-F 1 "2.518k" H 4600 3700 50  0000 C CNN
-F 2 "" H 4600 3630 30  0000 C CNN
-F 3 "" V 4600 3700 30  0000 C CNN
-	1    4550 3650
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF6830A
-P 4250 4150
-F 0 "U1" H 4300 4250 30  0000 C CNN
-F 1 "PORT" H 4250 4150 30  0000 C CNN
-F 2 "" H 4250 4150 60  0000 C CNN
-F 3 "" H 4250 4150 60  0000 C CNN
-	2    4250 4150
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF689AD
-P 5950 2200
-F 0 "U1" H 6000 2300 30  0000 C CNN
-F 1 "PORT" H 5950 2200 30  0000 C CNN
-F 2 "" H 5950 2200 60  0000 C CNN
-F 3 "" H 5950 2200 60  0000 C CNN
-	1    5950 2200
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF69586
-P 4600 3000
-F 0 "U1" H 4650 3100 30  0000 C CNN
-F 1 "PORT" H 4600 3000 30  0000 C CNN
-F 2 "" H 4600 3000 60  0000 C CNN
-F 3 "" H 4600 3000 60  0000 C CNN
-	3    4600 3000
-	0    1    1    0   
-$EndComp
-Text Label 5600 4100 0    60   ~ 0
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-Text Label 5950 3150 0    60   ~ 0
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-Text Label 5950 2600 0    60   ~ 0
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-Text Label 6450 3050 0    60   ~ 0
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-Text Label 6450 3650 0    60   ~ 0
-0
-$Comp
-L NLDS B1
-U 1 1 5CFD2C88
-P 5950 4800
-F 0 "B1" H 5950 4800 60  0000 C CNN
-F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60  0000 C CNN
-F 2 "" H 5950 4800 60  0000 C CNN
-F 3 "" H 5950 4800 60  0000 C CNN
-	1    5950 4800
-	1    0    0    -1  
-$EndComp
-Text Label 5350 5250 0    60   ~ 0
-7
-Text Label 4600 3450 0    60   ~ 0
-3
-Text Label 4250 4500 0    60   ~ 0
-2
-$Comp
-L eSim_Diode D1
-U 1 1 5CFF8BB7
-P 5950 2850
-F 0 "D1" H 5950 2950 50  0000 C CNN
-F 1 "eSim_Diode" H 5950 2750 50  0000 C CNN
-F 2 "" H 5950 2850 60  0000 C CNN
-F 3 "" H 5950 2850 60  0000 C CNN
-	1    5950 2850
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	6200 3050 6700 3050
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-	6700 3050 6700 3200
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-	6300 3650 6700 3650
-Wire Wire Line
-	5950 2450 5950 2700
-Wire Wire Line
-	5950 3000 5950 3300
-Wire Wire Line
-	5950 3400 5950 3850
-Wire Wire Line
-	5950 3850 5950 4100
-Wire Wire Line
-	5950 4100 5950 4450
-Wire Wire Line
-	5150 4100 5150 4550
-Wire Wire Line
-	4600 4100 5150 4100
-Wire Wire Line
-	5150 4100 5950 4100
-Connection ~ 5950 4100
-Wire Wire Line
-	5150 4850 5150 5250
-Wire Wire Line
-	4250 5250 5150 5250
-Wire Wire Line
-	5150 5250 5950 5250
-Wire Wire Line
-	4250 5250 4250 4950
-Wire Wire Line
-	4600 4100 4600 3850
-Connection ~ 5150 4100
-Wire Wire Line
-	4250 4650 4250 4400
-Wire Wire Line
-	4600 3550 4600 3250
-Wire Wire Line
-	5950 5250 5950 5150
-Connection ~ 5150 5250
-Wire Wire Line
-	6700 3650 6700 3500
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub
deleted file mode 100644
index 2fb1db35..00000000
--- a/src/SubcircuitLibrary/ujt/ujt.sub
+++ /dev/null
@@ -1,16 +0,0 @@
-* Subcircuit ujt
-.subckt ujt /1 /2 /3 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir
-.include emitter.lib
-r3  /0 /6 1000k
-* h1
-c1  /5 /7 35p
-r1  /7 /2 38.15k
-r2  /3 /5 2.518k
-b1  /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6)
-d1 /1 /4 emitter
-Vh1 /4 /5 0
-h1 /6 /0 Vh1 1k
-* Control Statements
-
-.ends ujt
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml
deleted file mode 100644
index 4468b395..00000000
--- a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/browser/pages/User-Manual/eSim.html b/src/browser/pages/User-Manual/eSim.html
deleted file mode 100644
index 79afa31e..00000000
--- a/src/browser/pages/User-Manual/eSim.html
+++ /dev/null
@@ -1,3672 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
-  "http://www.w3.org/TR/html4/loose.dtd">
-<html >
-<head><title>eSim Manual</title> 
-<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
-<meta name="generator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)">
-<meta name="originator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)">
-<!-- html -->
-<meta name="src" content="esim.tex">
-<meta name="date" content="2015-09-15 14:59:00">
-<link rel="stylesheet" type="text/css" href="esim.css">
-</head><body
->
-
-<div class="center"
->
-<!--l. 1--><p class="noindent" >
-<!--l. 2--><p class="noindent" ><span
-class="cmbx-12x-x-207">eSim</span><br /><br />
-<span
-class="cmbx-12x-x-144">An open source EDA tool for circuit design,</span>
-<span
-class="cmbx-12x-x-144">simulation, analysis and PCB design</span><br />
-
-<img
-src="figures/logo-trimmed.png" alt="PIC"
->
-<span
-class="cmbx-12x-x-144">eSim User Manual</span><br />
-<span
-class="cmr-10">version 1.0.0</span><br />
-<span
-class="cmbx-10">Prepared By:</span><br />
-<span
-class="cmr-10">eSim Team</span><br />
-<span
-class="cmr-10">FOSSEE at IIT,Bombay</span>
-
-<!--l. 17--><p class="noindent" ><img
-src="figures/iitblogo.png" alt="PIC"
-><br />
-<span
-class="cmr-10">Indian Institute of Technology Bombay</span><br />
-<img
-src="esim0x.png" alt="&#x25CB;BY:"  class="oalign" >   <img
-src="esim1x.png" alt="&#x25CB;$\"  class="oalign" > <img
-src="esim2x.png" alt="&#x25CB;="  class="oalign" > <br />
-<span
-class="cmr-10">August 2015</span></div>
-
-
-   <h2 class="likechapterHead"><a
- id="x1-1000"></a>Contents</h2> <div class="tableofcontents">
-   <span class="chapterToc" >1 <a
-href="#x1-20001" id="QQ2-1-2">Introduction</a></span>
-<br />   <span class="chapterToc" >2 <a
-href="#x1-30002" id="QQ2-1-3">Installing eSim</a></span>
-<br />   <span class="chapterToc" >3 <a
-href="#x1-40003" id="QQ2-1-4">Architecture of eSim</a></span>
-<br />   &#x00A0;<span class="sectionToc" >3.1 <a
-href="#x1-50003.1" id="QQ2-1-5">Modules used in eSim</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.1 <a
-href="#x1-60003.1.1" id="QQ2-1-6">Eeschema</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.2 <a
-href="#x1-70003.1.2" id="QQ2-1-7">CvPcb</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.3 <a
-href="#x1-80003.1.3" id="QQ2-1-8">Pcbnew</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.4 <a
-href="#x1-90003.1.4" id="QQ2-1-9">KiCad to Ngspice converter</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.5 <a
-href="#x1-100003.1.5" id="QQ2-1-10">Model Builder</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.6 <a
-href="#x1-110003.1.6" id="QQ2-1-11">Subcircuit Builder</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >3.1.7 <a
-href="#x1-120003.1.7" id="QQ2-1-12">Ngspice</a></span>
-<br />   &#x00A0;<span class="sectionToc" >3.2 <a
-href="#x1-130003.2" id="QQ2-1-13">Work flow of eSim</a></span>
-<br />   <span class="chapterToc" >4 <a
-href="#x1-140004" id="QQ2-1-15">Getting Started</a></span>
-<br />   &#x00A0;<span class="sectionToc" >4.1 <a
-href="#x1-150004.1" id="QQ2-1-16">eSim Main Window</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >4.1.1 <a
-href="#x1-160004.1.1" id="QQ2-1-17">How to launch eSim in Ubuntu?</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >4.1.2 <a
-href="#x1-170004.1.2" id="QQ2-1-19">Main-GUI</a></span>
-<br />   <span class="chapterToc" >5 <a
-href="#x1-280005" id="QQ2-1-33">Schematic Creation</a></span>
-<br />   &#x00A0;<span class="sectionToc" >5.1 <a
-href="#x1-290005.1" id="QQ2-1-34">Familiarizing the Schematic Editor interface</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.1.1 <a
-href="#x1-300005.1.1" id="QQ2-1-36">Top menu bar</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.1.2 <a
-href="#x1-310005.1.2" id="QQ2-1-38">Top toolbar</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.1.3 <a
-href="#x1-320005.1.3" id="QQ2-1-40">Toolbar on the right</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.1.4 <a
-href="#x1-330005.1.4" id="QQ2-1-42">Toolbar on the left</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.1.5 <a
-href="#x1-340005.1.5" id="QQ2-1-44">Hotkeys</a></span>
-<br />   &#x00A0;<span class="sectionToc" >5.2 <a
-href="#x1-350005.2" id="QQ2-1-45">Schematic creation for simulation</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.2.1 <a
-href="#x1-360005.2.1" id="QQ2-1-47">Selection and placement of components</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.2.2 <a
-href="#x1-370005.2.2" id="QQ2-1-51">Wiring the circuit</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.2.3 <a
-href="#x1-380005.2.3" id="QQ2-1-53">Assigning values to components</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.2.4 <a
-href="#x1-390005.2.4" id="QQ2-1-55">Annotation and ERC</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >5.2.5 <a
-href="#x1-400005.2.5" id="QQ2-1-59">Netlist generation</a></span>
-<br />   <span class="chapterToc" >6 <a
-href="#x1-410006" id="QQ2-1-61">PCB Design</a></span>
-<br />   &#x00A0;<span class="sectionToc" >6.1 <a
-href="#x1-420006.1" id="QQ2-1-62">Schematic creation for PCB design</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.1.1 <a
-href="#x1-430006.1.1" id="QQ2-1-64">Netlist generation for PCB</a></span>
-
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.1.2 <a
-href="#x1-440006.1.2" id="QQ2-1-66">Mapping of components using Footprint Editor</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.1.3 <a
-href="#x1-450006.1.3" id="QQ2-1-67">Familiarising the Footprint Editor tool</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.1.4 <a
-href="#x1-470006.1.4" id="QQ2-1-71">Viewing footprints in 2D and 3D</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.1.5 <a
-href="#x1-480006.1.5" id="QQ2-1-75">Mapping of components in the RC circuit</a></span>
-<br />   &#x00A0;<span class="sectionToc" >6.2 <a
-href="#x1-490006.2" id="QQ2-1-77">Creation of PCB layout</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.2.1 <a
-href="#x1-500006.2.1" id="QQ2-1-78">Familiarizing the Layout Editor tool</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.2.2 <a
-href="#x1-520006.2.2" id="QQ2-1-82">Hotkeys</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >6.2.3 <a
-href="#x1-530006.2.3" id="QQ2-1-83">PCB design example using RC circuit</a></span>
-<br />   <span class="chapterToc" >7 <a
-href="#x1-540007" id="QQ2-1-98">Model Editor</a></span>
-<br />   &#x00A0;<span class="sectionToc" >7.1 <a
-href="#x1-550007.1" id="QQ2-1-100">Creating New Model Library </a></span>
-<br />   &#x00A0;<span class="sectionToc" >7.2 <a
-href="#x1-560007.2" id="QQ2-1-105">Editing Current Model Library</a></span>
-<br />   &#x00A0;<span class="sectionToc" >7.3 <a
-href="#x1-570007.3" id="QQ2-1-107">Uploading external .lib file to eSim repository</a></span>
-<br />   <span class="chapterToc" >8 <a
-href="#x1-580008" id="QQ2-1-108">SubCircuit Builder</a></span>
-<br />   &#x00A0;<span class="sectionToc" >8.1 <a
-href="#x1-590008.1" id="QQ2-1-110">Creating a SubCircuit</a></span>
-<br />   &#x00A0;<span class="sectionToc" >8.2 <a
-href="#x1-600008.2" id="QQ2-1-118">Edit a Subcircuit</a></span>
-<br />   <span class="chapterToc" >9 <a
-href="#x1-610009" id="QQ2-1-119">Solved Examples</a></span>
-<br />   &#x00A0;<span class="sectionToc" >9.1 <a
-href="#x1-620009.1" id="QQ2-1-120">Solved Examples</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >9.1.1 <a
-href="#x1-630009.1.1" id="QQ2-1-121">Basic RC Circuit</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >9.1.2 <a
-href="#x1-660009.1.2" id="QQ2-1-136">Half Wave Rectifier</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >9.1.3 <a
-href="#x1-690009.1.3" id="QQ2-1-143">Precision Rectifier</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >9.1.4 <a
-href="#x1-720009.1.4" id="QQ2-1-150">Inverting Amplifier</a></span>
-<br />   &#x00A0;&#x00A0;<span class="subsectionToc" >9.1.5 <a
-href="#x1-750009.1.5" id="QQ2-1-157">Half Adder Example</a></span>
-<br />   <span class="chapterToc" > <a
-href="#Q1-1-166">References                                                    </a></span>
-   </div>
-
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;1</span><br /><a
- id="x1-20001"></a>Introduction</h2>  Electronic systems are an integral part of human life. They have
-simplified our lives to a great extent. Starting from small systems made of a few
-discrete components to the present day integrated circuits (ICs) with millions of
-logic gates, electronic systems have undergone a sea change. As a result, design of
-electronic systems too have become extremely difficult and time consuming. Thanks to
-a host of computer aided design tools, we have been able to come up with quick
-and efficient designs. These are called <span
-class="cmtt-10x-x-109">Electronic Design Automation </span>or <span
-class="cmtt-10x-x-109">EDA</span>
-<a
- id="dx1-2001"></a>tools.
-<!--l. 20--><p class="noindent" >Let us see the steps involved in EDA.<a
- id="dx1-2002"></a> In the first stage, the specifications of the system are
-laid out. These specifications are then converted to a design. The design could be in
-the form of a circuit schematic, logical description using an HDL language, etc.
-The design is then simulated and re-designed, if needed, to achieve the desired
-results. Once simulation achieves the specifications, the design is either converted to
-a PCB, a chip layout, or ported to an FPGA. The final product is again tested
-for specifications. The whole cycle is repeated until desired results are obtained
-<span class="cite">&#x00A0;[<a
-href="#Xeda">9</a>]</span>.
-<!--l. 31--><p class="indent" >   A person who builds an electronic system has to first design the circuit, produce a virtual
-representation of it through a schematic for easy comprehension, simulate it and finally
-convert it into a Printed Circuit Board (PCB). <a
- id="dx1-2003"></a>There are various tools available that will help
-us do this. Some of the popular EDA tools are those of <span
-class="cmtt-10x-x-109">Cadence</span>, <span
-class="cmtt-10x-x-109">Synopys</span>, <span
-class="cmtt-10x-x-109">Mentor Graphics</span>
-and <span
-class="cmtt-10x-x-109">Xilinx</span>. Although these are fairly comprehensive and high end, their licenses are
-expensive, being proprietary.
-<!--l. 40--><p class="indent" >   There are some free and open source EDA tools like <span
-class="cmtt-10x-x-109">gEDA</span>, <span
-class="cmtt-10x-x-109">KiCad </span>and <span
-class="cmtt-10x-x-109">Ngspice</span>. The main
-drawback of these open source tools is that they are not comprehensive. Some of them are
-capable of PCB design (e.g. <span
-class="cmtt-10x-x-109">KiCad</span>) while some of them are capable of performing simulations
-(e.g. <span
-class="cmtt-10x-x-109">gEDA</span>). To the best of our knowledge, there is no open source software that can perform
-circuit design, simulation and layout design together. eSim is capable of doing all of the
-above.
-<!--l. 49--><p class="indent" >   eSim is a free and open source EDA tool. It is an acronym for <span
-class="cmbx-10x-x-109">E</span>lectronics <span
-class="cmbx-10x-x-109">Sim</span>ulation.
-eSim is created using open source software packages, such as KiCad, Ngspice and Python. <a
- id="dx1-2004"></a><a
- id="dx1-2005"></a>
-<a
- id="dx1-2006"></a>Using eSim, one can create circuit schematics, perform simulations and design PCB
-layouts. It can create or edit new device models, and create or edit subcircuits for
-simulation.
-<!--l. 57--><p class="indent" >   Because of these reasons, eSim is expected to be useful for students, teachers and other
-professionals who would want to study and/or design electronic systems. eSim is also useful
-for entrepreneurs and small scale enterprises who do not have the capability to invest in
-heavily priced proprietary tools.
-<!--l. 63--><p class="indent" >   This book introduces eSim to the reader and illustrates all the features of eSim with
-examples. Chapter&#x00A0;<a
-href="#x1-30002">2<!--tex4ht:ref: chap2 --></a> gives step by step instructions to install eSim on a typical computer
-system and to validate the installation. The software architecture of eSim is presented in
-Chapter&#x00A0;<a
-href="#x1-40003">3<!--tex4ht:ref: chap3 --></a>. Chapter&#x00A0;<a
-href="#x1-140004">4<!--tex4ht:ref: chap4 --></a> gets the user started with eSim. It takes them through a tour
-
-of eSim with the help of a simple RC circuit example. Chapter 5 illustrates how
-to simulate circuits. Chapter 6 explains PCB design using eSim, in detail. The
-advanced features of eSim such as Model Builder covered in Chapter 7 and Sub
-circuiting is covered in Chapter 8. Chapter&#x00A0;<a
-href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> illustrates how to use eSim for solving
-problems.
-<!--l. 73--><p class="indent" >   The following convention has been adopted throughout this manual.All the
-menu names, options under each menu item, tool names, certain points to be noted,
-etc., are given in <span
-class="cmti-10x-x-109">italics</span>. Some keywords, names of certain windows/dialog boxes,
-names of some files/projects/folders, messages displayed during an activity, names
-of websites, component references, etc., are given in <span
-class="cmtt-10x-x-109">typewriter </span>font. Some key
-presses, e.g. <span
-class="cmtt-10x-x-109">Enter </span>key, <span
-class="cmtt-10x-x-109">F1 </span>key, <span
-class="cmtt-10x-x-109">y </span>for yes, etc., are also mentioned in <span
-class="cmtt-10x-x-109">typewriter</span>
-font.
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;2</span><br /><a
- id="x1-30002"></a>Installing eSim</h2>
-     <dl class="enumerate"><dt class="enumerate">
-   1. </dt><dd
-class="enumerate"><span
-class="cmbx-10x-x-109">eSim installation in Ubuntu:</span><br
-class="newline" />After downloading the zip file from https://github.com/FOSSEE/eSim to a local
-     directory unpack it using:<br
-class="newline" />&#x00A0;&#x00A0;&#x00A0;&#x00A0;&#x00A0;                                           <span
-class="cmbx-10x-x-109">$ unzip eSim.zip </span><br
-class="newline" />Now change directories in to the top-level source directory (where this INSTALL
-     file can be found).
-     <!--l. 13--><p class="noindent" >To install eSim and other dependecies run the following command. <br
-class="newline" />&#x00A0;&#x00A0;&#x00A0;&#x00A0;&#x00A0;                                           <span
-class="cmbx-10x-x-109">$ ../install-linux.sh &#8211;install </span><br
-class="newline" />Above script will install eSim along with dependencies.
-     <!--l. 19--><p class="noindent" >eSim will be installed to /opt/eSim
-     <!--l. 21--><p class="noindent" >To run eSim you can directly run it from terminal as <br
-class="newline" />&#x00A0;&#x00A0;&#x00A0;&#x00A0;&#x00A0;                                           <span
-class="cmbx-10x-x-109">$ esim </span><br
-class="newline" />or you can double click on eSim icon created on desktop after installation.</dd></dl>
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;3</span><br /><a
- id="x1-40003"></a>Architecture of eSim</h2>
-<!--l. 6--><p class="noindent" >eSim is a CAD <a
- id="dx1-4001"></a>tool that helps electronic system designers to design, test and analyse their
-circuits. But the important feature of this tool is that it is open source and hence the user can
-modify the source as per his/her need. The software provides a generic, modular and
-extensible platform for experiment with electronic circuits. This software runs on all
-Ubuntu Linux distributions and some flavours of Windows. It uses <span
-class="cmtt-10x-x-109">Python</span>, <span
-class="cmtt-10x-x-109">KiCad </span>and
-<span
-class="cmtt-10x-x-109">Ngspice</span>.
-<!--l. 13--><p class="indent" >   The objective behind the development of eSim is to provide an open source EDA solution
-for electronics and electrical engineers. The software should be capable of performing
-schematic creation, PCB design and circuit simulation (analog, digital and mixed signal). It
-should provide facilities to create new models and components. The architecture of eSim has
-been designed by keeping these objectives in mind.
-   <h3 class="sectionHead"><span class="titlemark">3.1   </span> <a
- id="x1-50003.1"></a>Modules used in eSim</h3>
-<!--l. 21--><p class="noindent" >Various open-source tools have been used for the underlying build-up of eSim. In this section
-we will give a brief idea about all the modules used in eSim.
-<!--l. 23--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">3.1.1   </span> <a
- id="x1-60003.1.1"></a>Eeschema</h4>
-<a
- id="dx1-6001"></a>
-<a
- id="dx1-6002"></a>
-<!--l. 24--><p class="noindent" >Eeschema is an integrated software where all functions of circuit drawing, control, layout,
-library management and access to the PCB design software are carried out. It is the
-schematic editor tool used in KiCad <span class="cite">&#x00A0;[<a
-href="#Xeeschema">11</a>]</span>. Eeschema is intended to work with PCB layout
-software such as Pcbnew. It provides netlist that describes the electrical connections of the
-PCB. Eeschema also integrates a component editor which allows the creation, editing and
-visualization of components. It also allows the user to effectively handle the symbol
-libraries i.e; import, export, addition and deletion of library components. Eeschema
-also integrates the following additional but essential functions needed for a modern
-schematic capture software: <a
- id="x1-6003r1"></a>1.&#x00A0;Design rules check <a
- id="dx1-6004"></a>(<span
-class="cmtt-10x-x-109">DRC</span>) for the automatic control of
-incorrect connections and inputs of components left unconnected. <a
- id="x1-6005r2"></a>2.&#x00A0;Generation of
-layout files in <span
-class="cmtt-10x-x-109">POSTSCRIPT</span> <a
- id="dx1-6006"></a>or <span
-class="cmtt-10x-x-109">HPGL</span> <a
- id="dx1-6007"></a>format. <a
- id="x1-6008r3"></a>3.&#x00A0;Generation of layout files printable via
-printer. <a
- id="x1-6009r4"></a>4.&#x00A0;Bill of material generation. <a
- id="x1-6010r5"></a>5.&#x00A0;Netlist generation for PCB layout or for
-simulation.
-This module is indicated by the label 1 in Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 45--><p class="indent" >   As Eeschema is originally intended for PCB Design, there are no fictitious
-
-components<span class="footnote-mark"><a
-href="esim2.html#fn1x3"><sup class="textsuperscript">1</sup></a></span><a
- id="x1-6011f1"></a>
-such as voltage or current sources. Thus, we have added a new library for different types of
-voltage and current sources such as sine, pulse and square wave. We have also built a library
-which gives printing and plotting solutions. This extension, developed by us for eSim, is
-indicated by the label 2 in Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-   <h4 class="subsectionHead"><span class="titlemark">3.1.2   </span> <a
- id="x1-70003.1.2"></a>CvPcb</h4>
-<a
- id="dx1-7001"></a>
-<!--l. 58--><p class="noindent" >CvPcb is a tool that allows the user to associate components in the schematic to component
-footprints when designing the printed circuit board. CvPcb is the footprint editor tool in
-KiCad <span class="cite">&#x00A0;[<a
-href="#Xeeschema">11</a>]</span>. Typically the netlist file generated by Eeschema does not specify which printed
-circuit board footprint is associated with each component in the schematic. However, this is
-not always the case as component footprints can be associated during schematic capture by
-setting the component&#8217;s footprint field. CvPcb provides a convenient method of associating
-footprints to components. It provides footprint list filtering, footprint viewing, and 3D
-component model viewing to help ensure that the correct footprint is associated with each
-component. Components can be assigned to their corresponding footprints manually or
-automatically by creating equivalence files. Equivalence files are look up tables
-associating each component with its footprint. This interactive approach is simpler
-and less error prone than directly associating footprints in the schematic editor.
-This is because CvPcb not only allows automatic association, but also allows to
-see the list of available footprints and displays them on the screen to ensure the
-correct footprint is being associated. This module is indicated by the label 3 in
-Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 80--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">3.1.3   </span> <a
- id="x1-80003.1.3"></a>Pcbnew</h4>
-<a
- id="dx1-8001"></a>
-<!--l. 81--><p class="noindent" >Pcbnew is a powerful printed circuit board software tool. It is the layout editor tool
-used in KiCad <span class="cite">&#x00A0;[<a
-href="#Xeeschema">11</a>]</span>. It is used in association with the schematic capture software
-Eeschema, which provides the netlist. Netlist describes the electrical connections of
-the circuit. CvPcb is used to assign each component, in the netlist produced by
-Eeschema, to a module that is used by Pcbnew. The features of Pcbnew are given
-below:
-
-     <ul class="itemize1">
-     <li class="itemize">It  manages  libraries  of  modules.  Each  module  is  a  drawing  of  the  physical
-     component including its footprint<a
- id="dx1-8002"></a> - the layout of pads providing connections to the
-     component. The required modules are automatically loaded during the reading of
-     the netlist produced by CvPcb.
-     </li>
-     <li class="itemize">Pcbnew  integrates  automatically  and  immediately  any  circuit  modification  by
-     removal of any erroneous tracks, addition of new components, or by modifying
-     any value (and under certain conditions any reference) of old or new modules,
-     according to the electrical connections appearing in the schematic.
-     </li>
-     <li class="itemize">This tool provides a rats nest display, a hairline connecting the pads of modules
-     connected on the schematic. These connections move dynamically as track and
-     module movements are made.
-     </li>
-     <li class="itemize">It has an active Design Rules Check (<span
-class="cmtt-10x-x-109">DRC</span>) which automatically indicates any error
-     of track layout in real time.
-     </li>
-     <li class="itemize">It automatically generates a copper plane, with or without thermal breaks on the
-     pads.
-     </li>
-     <li class="itemize">It  has  a  simple  but  effective  auto  router  to  assist  in  the  production  of  the
-     circuit. An export/import in <span
-class="cmtt-10x-x-109">SPECCTRA </span>dsn format allows to use more advanced
-     auto-routers.
-     </li>
-     <li class="itemize">It provides options specifically for the production of ultra high frequency circuits
-     (such as pads of trapezoidal and complex form, automatic layout of coils on the
-     printed circuit).
-     </li>
-     <li class="itemize">Pcbnew displays the elements (tracks, pads, texts, drawings and more) as actual size
-     and according to personal preferences such as:
-          <ul class="itemize2">
-          <li class="itemize">display in full or outline.
-          </li>
-          <li class="itemize">display the track/pad clearance.</li></ul>
-
-     </li></ul>
-<!--l. 121--><p class="noindent" >This module is indicated by the label 4 in Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-   <h4 class="subsectionHead"><span class="titlemark">3.1.4   </span> <a
- id="x1-90003.1.4"></a>KiCad to Ngspice converter</h4>
-<!--l. 124--><p class="noindent" >We can provide analysis parameters, and the source details through this module. It also
-allows us to add and edit the device models and subcircuits, included in the circuit
-schematic. Finally, this module facilitates the conversion of KiCad netlist to Ngspice
-compatible ones. It is developed by us for eSim and it is indicated by the label 7 in
-Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 149--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">3.1.5   </span> <a
- id="x1-100003.1.5"></a>Model Builder</h4>
-<a
- id="dx1-10001"></a>
-<!--l. 150--><p class="noindent" >This tool provides the facility to define a new model for devices such as, <a
- id="x1-10002r1"></a>1.&#x00A0;Diode <a
- id="x1-10003r2"></a>2.&#x00A0;Bipolar
-Junction Transistor (BJT) <a
- id="x1-10004r3"></a>3.&#x00A0;Metal Oxide Semiconductor Field Effect Transistor
-(MOSFET) <a
- id="x1-10005r4"></a>4.&#x00A0;Junction Field Effect Transistor (JFET) <a
- id="x1-10006r5"></a>5.&#x00A0;IGBT and <a
- id="x1-10007r6"></a>6.&#x00A0;Magnetic
-core.
-This module also helps edit existing models. It is developed by us for eSim and it is indicated
-by the label 5 in Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 164--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">3.1.6   </span> <a
- id="x1-110003.1.6"></a>Subcircuit Builder</h4>
-<a
- id="dx1-11001"></a>
-<!--l. 164--><p class="noindent" >This module allows the user to create a subcircuit for a component. Once the subcircuit for a
-component is created, the user can use it in other circuits. It has the facility to define new
-components such as, Op-amps and IC-555. This component also helps edit existing
-subcircuits. This module is developed by us for eSim and it is indicated by the label 6 in
-Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 172--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">3.1.7   </span> <a
- id="x1-120003.1.7"></a>Ngspice</h4>
-<a
- id="dx1-12001"></a>
-<!--l. 173--><p class="noindent" >Ngspice is a general purpose circuit simulation program for nonlinear dc, nonlinear transient,
-and linear ac analysis <span class="cite">&#x00A0;[<a
-href="#Xngspice-web">12</a>]</span>. Circuits may contain resistors, capacitors, inductors, mutual
-inductors, independent voltage and current sources, four types of dependent sources, lossless
-and lossy transmission lines (two separate implementations), switches, uniform
-
-distributed RC lines, and the five most common semiconductor devices: diodes,
-<a
- id="dx1-12002"></a>BJTs, <a
- id="dx1-12003"></a>JFETs, MESFETs, and MOSFET. <a
- id="dx1-12004"></a>This module is indicated by the label 9 in
-Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>.
-<!--l. 184--><p class="noindent" >
-   <h3 class="sectionHead"><span class="titlemark">3.2   </span> <a
- id="x1-130003.2"></a>Work flow of eSim</h3>
-<!--l. 185--><p class="noindent" >Fig.&#x00A0;<a
-href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a> shows the work flow in eSim. The block diagram consists of mainly three
-parts:
-     <ul class="itemize1">
-     <li class="itemize">Schematic Editor
-     </li>
-     <li class="itemize">PCB Layout Editor
-     </li>
-     <li class="itemize">Circuit Simulators</li></ul>
-<!--l. 193--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-130011"></a>
-
-
-<!--l. 196--><p class="noindent" ><img
-src="figures/blockdiagram.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;3.1: </span><span
-class="content">Work flow in eSim. (Boxes with dotted lines denote the modules developed
-in this work).</span></div><!--tex4ht:label?: x1-130011 -->
-
-<!--l. 201--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 203--><p class="indent" >   Here we explain the role of each block in designing electronic systems. Circuit design is the
-first step in the design of an electronic circuit. Generally a circuit diagram is drawn on a
-paper, and then entered into a computer using a schematic editor. Eeschema is the schematic
-editor for eSim. Thus all the functionalities of Eeschema are naturally available in eSim.
-<a
- id="dx1-13002"></a>
-<!--l. 210--><p class="indent" >   Libraries for components, explicitly or implicitly supported by Ngspice, have been created
-using the features of Eeschema. As Eeschema is originally intended for PCB design, there are
-no fictitious components such as voltage or current sources. Thus, a new library for different
-types of voltage and current sources such as sine, pulse and square wave, has been added in
-eSim. A library which gives the functionality of printing and plotting has also been
-created.
-<!--l. 219--><p class="indent" >   The schematic editor provides a netlist file, which describes the electrical connections of
-the design. In order to create a PCB layout, physical components are required to be mapped
-into their footprints. To perform component to footprint mapping, CvPcb is used. Footprints
-have been created for the components in the newly created libraries. Pcbnew is used to draw
-a PCB layout.
-<!--l. 227--><p class="indent" >   After designing a circuit, it is essential to check the integrity of the circuit design. In the
-case of large electronic circuits, breadboard testing is impractical. In such cases, electronic
-system designers rely heavily on simulation. The accuracy of the simulation results can be
-increased by accurate modeling of the circuit elements. Model Builder provides the facility to
-define a new model for devices and edit existing models. Complex circuit elements can be
-created by hierarchical modeling. Subcircuit Builder provides an easy way to create a
-subcircuit.
-<!--l. 238--><p class="indent" >   The netlist generated by Schematic Editor cannot be directly used for simulation due to
-compatibility issues. Netlist Converter converts it into Ngspice compatible format. The
-type of simulation to be performed and the corresponding options are provided
-through a graphical user interface (GUI). This is called KiCad to Ngspice Converter in
-eSim.
-<!--l. 245--><p class="indent" >   eSim uses Ngspice for analog, digital, mixed-level/mixed-signal circuit simulation. Ngspice
-is based on three open source software packages<span class="cite">&#x00A0;[<a
-href="#Xspice">14</a>]</span>:
-     <ul class="itemize1">
-     <li class="itemize">Spice3f5 (analog circuit simulator)
-     </li>
-     <li class="itemize">Cider1b1 (couples Spice3f5 circuit simulator to DSIM device simulator)
-     </li>
-     <li class="itemize">Xspice (code modeling support and simulation of digital components through an
-     event driven algorithm)</li></ul>
-<!--l. 253--><p class="noindent" >It is a part of gEDA <a
- id="dx1-13003"></a>project. Ngspice is capable of simulating devices with BSIM, <a
- id="dx1-13004"></a>EKV, HICUM, <a
- id="dx1-13005"></a><a
- id="dx1-13006"></a>
-
-HiSim, <a
- id="dx1-13007"></a>PSP, <a
- id="dx1-13008"></a>and PTM <a
- id="dx1-13009"></a>models. It is widely used due to its accuracy even for the latest
-technology devices.
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;4</span><br /><a
- id="x1-140004"></a>Getting Started</h2>
-<!--l. 5--><p class="noindent" >In this chapter we will get started with eSim. We will run through the various options
-available with an example circuit. Referring to this chapter will make one familiar with
-eSim and will help plan the project before actually designing a circuit. Lets get
-started.
-   <h3 class="sectionHead"><span class="titlemark">4.1   </span> <a
- id="x1-150004.1"></a>eSim Main Window</h3>
-<!--l. 12--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">4.1.1   </span> <a
- id="x1-160004.1.1"></a>How to launch eSim in Ubuntu?</h4>
-<!--l. 13--><p class="noindent" >After installation is completed, to launch eSim 1. Go to terminal.<br
-class="newline" />2. Type <span
-class="cmbx-10x-x-109">esim </span>and hit enter.<br
-class="newline" />The first window that appears is workspace dialog as shown in Fig.&#x00A0;<a
-href="#x1-160011">4.1<!--tex4ht:ref: workspace --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-160011"></a>
-
-
-<!--l. 19--><p class="noindent" ><img
-src="figures/workspace.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;4.1: </span><span
-class="content">eSim-Workspace</span></div><!--tex4ht:label?: x1-160011 -->
-
-<!--l. 22--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 24--><p class="indent" >   The default workspace is eSim-Workspace under home directory. To create new workspace
-use <span
-class="cmti-10x-x-109">browse </span>option.
-   <h4 class="subsectionHead"><span class="titlemark">4.1.2   </span> <a
- id="x1-170004.1.2"></a>Main-GUI</h4>
-<!--l. 27--><p class="noindent" >The main GUI window of eSim is as shown in Fig.&#x00A0;<a
-href="#x1-170012">4.2<!--tex4ht:ref: maingui --></a> <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-170012"></a>
-
-
-<!--l. 30--><p class="noindent" ><img
-src="figures/maingui.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;4.2: </span><span
-class="content">eSim Main GUI</span></div><!--tex4ht:label?: x1-170012 -->
-
-<!--l. 33--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 34--><p class="indent" >   The eSim main window consists of the following symbols.
-     <dl class="enumerate"><dt class="enumerate">
-   1. </dt><dd
-class="enumerate">Toolbar
-     </dd><dt class="enumerate">
-   2. </dt><dd
-class="enumerate">Menubar
-     </dd><dt class="enumerate">
-   3. </dt><dd
-class="enumerate">Project explorer
-     </dd><dt class="enumerate">
-   4. </dt><dd
-class="enumerate">Dockarea
-     </dd><dt class="enumerate">
-   5. </dt><dd
-class="enumerate">Console area</dd></dl>
-   <h5 class="subsubsectionHead"><a
- id="x1-180004.1.2"></a>Toolbar</h5>
-<!--l. 44--><p class="noindent" ><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-180013"></a>
-
-
-<!--l. 46--><p class="noindent" ><img
-src="figures/guitoolbar.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;4.3: </span><span
-class="content">Toolbar</span></div><!--tex4ht:label?: x1-180013 -->
-
-<!--l. 49--><p class="noindent" ></div><hr class="endfigure">
-     <ul class="itemize1">
-     <li class="itemize">Open Schematic: The first tool on the toolbar i.e. <span
-class="cmti-10x-x-109">Schematic Editor</span><a
- id="dx1-18002"></a>. Clicking on
-     this button will open Eeschema, the KiCad schematic editor.
-     </li>
-     <li class="itemize">Convert  KiCad  to  Ngspice:  This  converter  converts  KiCad  spice  netlist  into
-     Ngspice compatible netlist. The KiCad to Ngspice window consists of total five
-     tabs as namely <span
-class="cmti-10x-x-109">Analysis, Device Model, Source Details, Model Library, Subcircuits</span>.
-     Once  the  values  have  been  entered,  press  the  <span
-class="cmtt-10x-x-109">Convert </span>key.  It  will  generate
-     <span
-class="cmtt-10x-x-109">.cir.out </span>file in the same project directory.<br
-class="newline" />Note that <span
-class="cmti-10x-x-109">KiCad to Ngspice Converter </span>can only be used if current project has
-     created the KiCad spice netlist file <span
-class="cmtt-10x-x-109">.cir</span>.<br
-class="newline" />
-     <!--l. 62--><p class="noindent" >The details of tabs under KiCad to Ngspice converter are as follows:<br
-class="newline" />
-     <h5 class="subsubsectionHead"><a
- id="x1-190004.1.2"></a>Analysis</h5>
-     <!--l. 65--><p class="noindent" >This feature helps the user to perform different types of analysis such as Operating
-     point analysis, <a
- id="dx1-19001"></a>DC analysis, <a
- id="dx1-19002"></a>AC analysis, <a
- id="dx1-19003"></a>transient analysis. <a
- id="dx1-19004"></a>It has the facility
-     to
-          <ul class="itemize2">
-          <li class="itemize">Insert type of analysis such as AC or DC or Transient
-          </li>
-          <li class="itemize">Insert values for analysis</li></ul>
-     <!--l. 73--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-200004.1.2"></a>Source Details</h5>
-     <!--l. 74--><p class="noindent" >eSim sources are added from <span
-class="cmtt-10x-x-109">eSim</span><span
-class="cmtt-10x-x-109">_Sources </span>library. Source such as <span
-class="cmti-10x-x-109">SINE, AC, DC,</span>
-     <span
-class="cmti-10x-x-109">PULSE </span>are in this library. The parameter values to all the sources added in the
-     shcematic can be given through &#8217;Source Details&#8217;.
-
-     <!--l. 76--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-210004.1.2"></a>Ngspice Model</h5>
-     <!--l. 77--><p class="noindent" >Ngspice has in built model such as <span
-class="cmti-10x-x-109">flipflop(D,SR,JK,T),gain,summer </span>etc. which can be
-     utilised while building a circuit. eSim allows to add and modify Ngspice model
-     parameter through Ngspice Model tab.
-     <!--l. 80--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-220004.1.2"></a>Device Modeling</h5>
-     <!--l. 81--><p class="noindent" >Devices like <span
-class="cmti-10x-x-109">Diode, JFET, MOSFET, IGBT, MOS </span>etc used in the circuit can be
-     modeled using device model libraries. eSim also provides editing and adding new model
-     libraries. While converting KiCad to Ngspice, these library files are added to the
-     corresponding devices used in the circuit.
-     <!--l. 83--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-230004.1.2"></a>Subcircuits</h5>
-     <!--l. 84--><p class="noindent" >Subcircuits are circuits within circuit. Subcircuiting helps to reuse the parts of the
-     circuits. The subcircuits in the main circuits are added using this facility. Also, eSim
-     provides us with the facility to edit already existing subcircuits.
-     </li>
-     <li class="itemize">Simulation: The netlist generated using the <span
-class="cmti-10x-x-109">KiCad to Ngspice </span>converter is
-     simulated using simulation button. Clicking on the <span
-class="cmti-10x-x-109">Simulation </span>button will run
-     the Ngspice simulation for current project. Python plotting window will open, as
-     shown in Fig.&#x00A0;<a
-href="#x1-230014">4.4<!--tex4ht:ref: simulation-op --></a>. It shows the output waveform of current project. In the
-     Ngspice tab we can view the output plotted by Ngspice. <hr class="figure"><div class="figure"
-><a
- id="x1-230014"></a> <img
-src="figures/simulation-op.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;4.4: </span><span
-class="content">Simulation Output in Python Plotting Window</span></div><!--tex4ht:label?: x1-230014 -->
-     <!--l. 94--><p class="noindent" ></div><hr class="endfigure">
-     </li>
-     <li class="itemize">Foot Print Editor: Clicking on the <span
-class="cmti-10x-x-109">Footprint Editor </span>tool will open the <span
-class="cmtt-10x-x-109">CvPcb</span>
-     <a
- id="dx1-23002"></a>window. This window will ideally open the .net file for the current project. So,
-     before using this tool, one should have the netlist for PCB design (a .net
-     file).
-     </li>
-     <li class="itemize">PCB Layout: Clicking on the <span
-class="cmti-10x-x-109">Layout Editor </span>tool will open <span
-class="cmtt-10x-x-109">Pcbnew</span><a
- id="dx1-23003"></a>, the layout editor
-
-     used in eSim. In this window, one will create the PCB. It involves laying
-     tracks and vias, performing optimum routing of tracks, creating one or more
-     copper layers for PCB, etc. It will be saved as a <span
-class="cmtt-10x-x-109">.brd </span>file in the current project
-     directory.
-     </li>
-     <li class="itemize">Model Editor: eSim also gives an option to re-configure the model library of a device. It
-     facilitates the user to change model library of devices such as diode, transistor,
-     MOSFET, etc.
-     </li>
-     <li class="itemize">Subcircuit: eSim has an option to build subcircuits. The subcircuits can again have
-     components having subcircuits and so on. This enables users to build commonly used
-     circuits as subcircuits and then use it across circuits. For example, one can build a 12
-     Volt power supply as a subcircuit and then use it as just a single component across
-     circuits without having to recreate it. Clicking on <span
-class="cmti-10x-x-109">Subcircuit Builder </span>tool will allow one
-     to edit or create a subcircuit.
-     <!--l. 126--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-240004.1.2"></a>Menubar</h5>
-          <ul class="itemize2">
-          <li class="itemize">New Project: New projects are created in the eSim-workspace. When this
-          menu is selected, a new window opens up with <span
-class="cmtt-10x-x-109">Enter Project name </span>field.
-          Type the name of the new project and click on OK. A project directory will
-          be created in eSim-Workspace. The name of this folder will be the same as
-          that of the project created. Make sure project name does not have any spaces.
-          </li>
-          <li class="itemize">Open Project: This opens the file dialog of defalut workspace where the
-          projects are stored. The project can be selected which is then added in the
-          project explorer.
-          </li>
-          <li class="itemize">Exit: This button closes the project window and exits.
-          </li>
-          <li class="itemize">Help: It opens user manual in the dockarea.</li></ul>
-
-     <!--l. 141--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-250004.1.2"></a>Project Explorer</h5>
-     <!--l. 142--><p class="noindent" >Project explorer has tree of all the project previously added in it. On right clicking the
-     project we can simply remove or refresh the project in the explorer. Also on
-     double/right clicking, the project file can be opened in the text editor which can then be
-     edited.
-     <!--l. 145--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-260004.1.2"></a>Dockarea</h5>
-     <!--l. 146--><p class="noindent" >This area is used to open the following windows.
-          <dl class="enumerate"><dt class="enumerate">
-       1. </dt><dd
-class="enumerate">KiCad to Ngspice converter
-          </dd><dt class="enumerate">
-       2. </dt><dd
-class="enumerate">Ngspice plotting
-          </dd><dt class="enumerate">
-       3. </dt><dd
-class="enumerate">Python plotting
-          </dd><dt class="enumerate">
-       4. </dt><dd
-class="enumerate">Model builder
-          </dd><dt class="enumerate">
-       5. </dt><dd
-class="enumerate">Subcircuit builder</dd></dl>
-     <!--l. 155--><p class="noindent" >
-     <h5 class="subsubsectionHead"><a
- id="x1-270004.1.2"></a>Console Area</h5>
-     <!--l. 156--><p class="noindent" >Console area provides information about the activity done in current project.
-     </li></ul>
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;5</span><br /><a
- id="x1-280005"></a>Schematic Creation</h2>  The first step in the design of an electronic system is the
-design of its circuit. This circuit is usually created using a <span
-class="cmtt-10x-x-109">Schematic Editor</span><a
- id="dx1-28001"></a> and is called a
-<span
-class="cmtt-10x-x-109">Schematic</span>. <a
- id="dx1-28002"></a>eSim uses <span
-class="cmtt-10x-x-109">Eeschema</span> <a
- id="dx1-28003"></a>as its schematic editor. Eeschema is the schematic editor of
-KiCad. <a
- id="dx1-28004"></a>It is a powerful schematic editor software. It allows the creation and modification of
-components and symbol libraries and supports multiple hierarchical layers of printed circuit
-design.
-   <h3 class="sectionHead"><span class="titlemark">5.1   </span> <a
- id="x1-290005.1"></a>Familiarizing the Schematic Editor interface</h3>
-<!--l. 22--><p class="noindent" >Fig.&#x00A0;<a
-href="#x1-290011">5.1<!--tex4ht:ref: eesch1 --></a> shows the schematic editor and the various menu and toolbars. We will explain them
-briefly in this section. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-290011"></a>
-
-<div class="center"
->
-<!--l. 25--><p class="noindent" >
-
-<!--l. 26--><p class="noindent" ><img
-src="figures/schematic1.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.1: </span><span
-class="content">Schematic editor with the menu bar and toolbars marked</span></div><!--tex4ht:label?: x1-290011 -->
-</div>
-
-<!--l. 30--><p class="indent" >   </div><hr class="endfigure">
-   <h4 class="subsectionHead"><span class="titlemark">5.1.1   </span> <a
- id="x1-300005.1.1"></a>Top menu bar</h4>
-<!--l. 35--><p class="noindent" >The top menu bar will be available at the top left corner. Some of the important menu
-options in the top menu bar are:
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">File - The file menu items are given below:
-          <dl class="compactenum"><dt class="compactenum">
-      (a) </dt><dd
-class="compactenum">New - Clear current schematic and start a new one
-          </dd><dt class="compactenum">
-      (b) </dt><dd
-class="compactenum">Open - Open a schematic
-          </dd><dt class="compactenum">
-      (c) </dt><dd
-class="compactenum">Open Recent - A list of recently opened files for loading
-          </dd><dt class="compactenum">
-      (d) </dt><dd
-class="compactenum">Save Whole Schematic project - Save current sheet and all its hierarchy.
-          </dd><dt class="compactenum">
-      (e) </dt><dd
-class="compactenum">Save Current Sheet Only - Save current sheet, but not others in a hierarchy.
-          </dd><dt class="compactenum">
-      (f) </dt><dd
-class="compactenum">Save Current sheet as - Save current sheet with a new name.
-          </dd><dt class="compactenum">
-      (g) </dt><dd
-class="compactenum">Print - Access to print menu (See Fig.&#x00A0;<a
-href="#x1-300112">5.2<!--tex4ht:ref: print --></a>).
-          </dd><dt class="compactenum">
-      (h) </dt><dd
-class="compactenum">Plot - Plot the schematic in Postscript, HPGL, SVF or DXF format
-          </dd><dt class="compactenum">
-       (i) </dt><dd
-class="compactenum">Quit - Quit the schematic editor.</dd></dl>
-     <!--l. 53--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-300112"></a>
-<div class="center"
->
-<!--l. 54--><p class="noindent" >
-
-<!--l. 55--><p class="noindent" ><img
-src="figures/print.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.2: </span><span
-class="content">Print options</span></div><!--tex4ht:label?: x1-300112 -->
-</div>
-     <!--l. 59--><p class="noindent" ></div><hr class="endfigure">
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">Place - The place menu has shortcuts for placing various items like components, wire
-     and junction, on to the schematic editor window. See Sec.&#x00A0;<a
-href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> to know more about
-     various shortcut keys (hotkeys).
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Preferences - The preferences menu has the following options:
-          <dl class="compactenum"><dt class="compactenum">
-
-      (a) </dt><dd
-class="compactenum">Library - Select libraries and library paths
-          </dd><dt class="compactenum">
-      (b) </dt><dd
-class="compactenum">Colors - Select colors for various items.
-          </dd><dt class="compactenum">
-      (c) </dt><dd
-class="compactenum">Options - Display schematic editor options (Units, Grid size).
-          </dd><dt class="compactenum">
-      (d) </dt><dd
-class="compactenum">Language - Shows the current list of translations. Use default.
-          </dd><dt class="compactenum">
-      (e) </dt><dd
-class="compactenum">Hotkeys - Access to the hot keys menu. See Sec.&#x00A0;<a
-href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> about hotkeys.
-          </dd><dt class="compactenum">
-      (f) </dt><dd
-class="compactenum">Read preferences - Read configuration file.
-          </dd><dt class="compactenum">
-      (g) </dt><dd
-class="compactenum">Save preferences - Save configuration file.</dd></dl>
-     </dd></dl>
-<!--l. 79--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">5.1.2   </span> <a
- id="x1-310005.1.2"></a>Top toolbar</h4>
-<a
- id="dx1-31001"></a>
-<a
- id="dx1-31002"></a>
-<!--l. 80--><p class="noindent" >Some of the important tools in the top toolbar are discussed below. They are marked in
-Fig.&#x00A0;<a
-href="#x1-310033">5.3<!--tex4ht:ref: eeschem2 --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-310033"></a>
-
-
-<!--l. 84--><p class="noindent" ><img
-src="figures/toptoolbar.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.3: </span><span
-class="content">Toolbar on top with important tools marked</span></div><!--tex4ht:label?: x1-310033 -->
-
-<!--l. 87--><p class="indent" >   </div><hr class="endfigure">
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">Save - Save the current schematic
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">Library Editor - Create or edit components.
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Library Browser - Browse through the various component libraries available
-     </dd><dt class="compactenum">
-   4. </dt><dd
-class="compactenum">Navigate schematic hierarchy - Navigate among the root and sub-sheets in the
-     hierarchy
-     </dd><dt class="compactenum">
-   5. </dt><dd
-class="compactenum">Print - Print the schematic
-     </dd><dt class="compactenum">
-   6. </dt><dd
-class="compactenum">Generate netlist - Generate a netlist for PCB design or for simulation.
-     </dd><dt class="compactenum">
-   7. </dt><dd
-class="compactenum">Annotate - Annotate the schematic
-     </dd><dt class="compactenum">
-   8. </dt><dd
-class="compactenum">Check ERC - Do Electric Rules Check for the schematic
-     </dd><dt class="compactenum">
-   9. </dt><dd
-class="compactenum">Create BOM - Create a Bill of Materials of the schematic</dd></dl>
-   <h4 class="subsectionHead"><span class="titlemark">5.1.3   </span> <a
- id="x1-320005.1.3"></a>Toolbar on the right</h4>
-<a
- id="dx1-32001"></a>
-<a
- id="dx1-32002"></a>
-<!--l. 104--><p class="noindent" >The toolbar on the right side of the schematic editor window has many important tools. Some
-of them are marked in Fig.&#x00A0;<a
-href="#x1-320034">5.4<!--tex4ht:ref: eeschem3 --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-320034"></a>
-
-
-<!--l. 108--><p class="noindent" ><img
-src="figures/rightoolbar.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.4: </span><span
-class="content">Toolbar on right with important tools marked</span></div><!--tex4ht:label?: x1-320034 -->
-
-<!--l. 111--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 112--><p class="indent" >   Let us now look at each of these tools and their uses.
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">Place a component - Load a component to the schematic. See Sec.&#x00A0;<a
-href="#x1-360005.2.1">5.2.1<!--tex4ht:ref: selplace --></a> for more
-     details.
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">Place a power port - Load a power port (Vcc, ground) to the schematic
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Place wire - Draw wires to connect components in schematic
-     </dd><dt class="compactenum">
-   4. </dt><dd
-class="compactenum">Place bus - Place a bus on the schematic
-     </dd><dt class="compactenum">
-   5. </dt><dd
-class="compactenum">Place a no connect - Place a no connect flag, particularly useful in ICs
-     </dd><dt class="compactenum">
-   6. </dt><dd
-class="compactenum">Place a local label - Place a label or node name which is local to the schematic
-     </dd><dt class="compactenum">
-   7. </dt><dd
-class="compactenum">Place a global label - Place a global label (these are connected across all schematic
-     diagrams in the hierarchy)
-     </dd><dt class="compactenum">
-   8. </dt><dd
-class="compactenum">Place a text or comment - Place a text or comment in the schematic</dd></dl>
-   <h4 class="subsectionHead"><span class="titlemark">5.1.4   </span> <a
- id="x1-330005.1.4"></a>Toolbar on the left</h4>
-<a
- id="dx1-33001"></a>
-<a
- id="dx1-33002"></a>
-<!--l. 126--><p class="noindent" >Some of the important tools in the toolbar on the left are discussed below. They are marked
-in Fig.&#x00A0;<a
-href="#x1-330035">5.5<!--tex4ht:ref: eeschem4 --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-330035"></a>
-
-
-<!--l. 130--><p class="noindent" ><img
-src="figures/lefttoolbar.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.5: </span><span
-class="content">Toolbar on left with important tools marked</span></div><!--tex4ht:label?: x1-330035 -->
-
-<!--l. 133--><p class="indent" >   </div><hr class="endfigure">
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">Show/Hide grid - Show or Hide the grid in the schematic editor. Pressing the tool
-     again hides (shows) the grid if it was shown (hidden) earlier.
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">Show hidden pins - Show hidden pins of certain components, for example, power
-     pins of certain ICs.</dd></dl>
-   <h4 class="subsectionHead"><span class="titlemark">5.1.5   </span> <a
- id="x1-340005.1.5"></a>Hotkeys</h4>
-<!--l. 142--><p class="noindent" >A set of keyboard keys are associated with various operations in the schematic editor. These
-keys save time and make it easy to switch from one operation to another. The list of hotkeys
-can be viewed by going to Preferences in the top menu bar. Choose <span
-class="cmti-10x-x-109">Hotkeys </span>and
-select <span
-class="cmti-10x-x-109">List current keys</span>. The hotkeys can also be edited by selecting the option
-<span
-class="cmti-10x-x-109">Edit Hotkeys</span>. Some frequently used hotkeys, along with their functions, are given
-below:
-     <ul>
-     <li class="compactitem">F1 - Zoom in
-     </li>
-     <li class="compactitem">F2 - Zoom out
-     </li>
-     <li class="compactitem">Ctrl + Z - Undo
-     </li>
-     <li class="compactitem">Delete - Delete item
-     </li>
-     <li class="compactitem">M - Move item
-     </li>
-     <li class="compactitem">C - Copy item
-     </li>
-     <li class="compactitem">A - Add/place component
-     </li>
-     <li class="compactitem">P - Place power component
-     </li>
-     <li class="compactitem">R - Rotate item
-     </li>
-     <li class="compactitem">X - Mirror component about X axis
-     </li>
-     <li class="compactitem">Y - Mirror component about Y axis
-     </li>
-     <li class="compactitem">E - Edit schematic component
-     </li>
-
-     <li class="compactitem">W - Place wire
-     </li>
-     <li class="compactitem">T - Add text
-     </li>
-     <li class="compactitem">S - Add sheet</li></ul>
-<!--l. 166--><p class="noindent" ><span
-class="cmti-10x-x-109">Note: Both lower and upper-case keys will work as hotkeys</span>.
-<!--l. 168--><p class="noindent" >
-   <h3 class="sectionHead"><span class="titlemark">5.2   </span> <a
- id="x1-350005.2"></a>Schematic creation for simulation</h3>
-<a
- id="dx1-35001"></a>
-<!--l. 170--><p class="noindent" >There are certain differences between the schematic created for simulation and that created
-for PCB design. We need certain components like plots and current sources. For simulation
-whereas these are not needed for PCB design. For PCB design, we would require connectors
-(e.g. DB15 and 2 pin connector) for taking signals in and out of the PCB whereas
-these have no meaning in simulation. This section covers schematic creation for
-simulation.
-<!--l. 177--><p class="indent" >   The first step in the creation of circuit schematic is the selection and placement of
-required components. The components are grouped under eSim-libraries as shown in Fig.&#x00A0;<a
-href="#x1-350026">5.6<!--tex4ht:ref: libraries --></a>.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-350026"></a>
-
-
-<!--l. 181--><p class="noindent" ><img
-src="figures/libraries.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.6: </span><span
-class="content">eSim-Components Libraries</span></div><!--tex4ht:label?: x1-350026 -->
-
-<!--l. 184--><p class="indent" >   </div><hr class="endfigure">
-   <h4 class="subsectionHead"><span class="titlemark">5.2.1   </span> <a
- id="x1-360005.2.1"></a>Selection and placement of components</h4>
-<a
- id="dx1-36001"></a>
-<!--l. 189--><p class="noindent" >We would need a resistor, a capacitor, a voltage source, ground terminal. To place a resistor
-on the schematic editor window, select the <span
-class="cmti-10x-x-109">Place a component </span>tool from the toolbar
-on the right side and click anywhere on the schematic editor. This opens up the
-component selection window. Resistor component can be found under <span
-class="cmti-10x-x-109">eSim</span><span
-class="cmti-10x-x-109">_Devices</span>
-library. Fig.&#x00A0;<a
-href="#x1-360027">5.7<!--tex4ht:ref: resistor --></a> shows the selection of resistor component. Click on OK. A resistor
-will be tied to the cursor. Place the resistor on the schematic editor by a single
-click.
-<!--l. 196--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-360027"></a>
-
-
-<!--l. 198--><p class="noindent" ><img
-src="figures/resistor.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.7: </span><span
-class="content">Placing a resistor using the Place a Component tool</span></div><!--tex4ht:label?: x1-360027 -->
-
-<!--l. 201--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 202--><p class="indent" >   To place the next component, i.e., capacitor, click again on the schematic editor.Similarly,
-Capacitor component is found under <span
-class="cmti-10x-x-109">eSim</span><span
-class="cmti-10x-x-109">_Devices </span>library. Click on OK. Place the capacitor
-on the schematic editor by a single click. Let us now place a sinusoidal voltage source. This is
-required for performing transient analysis. To place it, click again on the schematic editor. On
-the component selection window, choose the library <span
-class="cmti-10x-x-109">eSim</span><span
-class="cmti-10x-x-109">_source </span>by double clicking on it.
-Select the component <span
-class="cmtt-10x-x-109">SINE </span>and click on OK. Place the sine source on the schematic editor by
-a single click.
-<!--l. 211--><p class="indent" >   Place the component by clicking on the schematic editor. Similarly place <span
-class="cmtt-10x-x-109">gnd</span>, a ground
-terminal and <span
-class="cmtt-10x-x-109">power</span><span
-class="cmtt-10x-x-109">_flag </span>under <span
-class="cmtt-10x-x-109">power </span>library. Once all the components are placed, the
-schematic editor would look like the Fig.&#x00A0;<a
-href="#x1-360038">5.8<!--tex4ht:ref: afterplace --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-360038"></a>
-
-
-<!--l. 216--><p class="noindent" ><img
-src="figures/afterplace.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.8: </span><span
-class="content">All RC circuit components placed</span></div><!--tex4ht:label?: x1-360038 -->
-
-<!--l. 219--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 220--><p class="indent" >   Let us rotate the resistor to complete the circuit. To rotate the resistor, place the cursor
-on the resistor and press the key <span
-class="cmtt-10x-x-109">R</span>. Note that if the cursor is placed above the letter <span
-class="cmtt-10x-x-109">R </span>(not
-<span
-class="cmtt-10x-x-109">R?</span>) on the resistor, it asks to clarify selection. Choose the option <span
-class="cmti-10x-x-109">Component R</span>. This can be
-avoided by placing the cursor slightly away from the letter R as shown in Fig.&#x00A0;<a
-href="#x1-360059">5.9<!--tex4ht:ref: rotate --></a>. This
-applies to all components.<a
- id="dx1-36004"></a> <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-360059"></a>
-
-
-<!--l. 228--><p class="noindent" ><img
-src="figures/rotate.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.9: </span><span
-class="content">Placing the cursor (cross mark) slightly away from the letter R</span></div><!--tex4ht:label?: x1-360059 -->
-
-<!--l. 231--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 232--><p class="indent" >   If one wants to move a component, place the cursor on top of the component and press the
-key <span
-class="cmtt-10x-x-109">M</span>. The component will be tied to the cursor and can be moved in any direction.
-<a
- id="dx1-36006"></a>
-   <h4 class="subsectionHead"><span class="titlemark">5.2.2   </span> <a
- id="x1-370005.2.2"></a>Wiring the circuit</h4>
-<a
- id="dx1-37001"></a>
-<!--l. 238--><p class="noindent" >The next step is to wire the connections. Let us connect the resistor to the capacitor.
-To do so, point the cursor to the terminal of resistor to be connected and press
-the key <span
-class="cmtt-10x-x-109">W</span>. It has now changed to the wiring mode. Move the cursor towards the
-terminal of the capacitor and click on it. A wire is formed as shown in Fig.&#x00A0;<a
-href="#x1-37002r1">5.10a<!--tex4ht:ref: wire1 --></a>.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-3700510"></a>
-
-<a
- id="x1-37002r1"></a>
-<!--l. 248--><p class="noindent" > <img
-src="figures/wire1.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Initial</span>
-<span
-class="cmr-9">stages</span>                                <a
- id="x1-37003r2"></a> <img
-src="figures/wirefin.png" alt="PIC"
->
-                                     <span
-class="cmr-9">(b)</span>
-                                     <span
-class="cmr-9">Wiring</span>
-                                     <span
-class="cmr-9">done</span>                                 <a
- id="x1-37004r3"></a> <img
-src="figures/schemfin.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(c)</span>
-                                                                          <span
-class="cmr-9">Final</span>
-                                                                          <span
-class="cmr-9">schematic</span>
-                                                                          <span
-class="cmr-9">with</span>
-                                                                          <span
-class="cmr-9">PWR</span><span
-class="cmr-9">_FLAG</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.10: </span><span
-class="content">Various stages of wiring</span></div><!--tex4ht:label?: x1-3700510 -->
-
-<!--l. 256--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 257--><p class="indent" >   Similarly connect the wires between all terminals and the final schematic would look like
-Fig.&#x00A0;<a
-href="#x1-37003r2">5.10b<!--tex4ht:ref: wirefin --></a>.
-   <h4 class="subsectionHead"><span class="titlemark">5.2.3   </span> <a
- id="x1-380005.2.3"></a>Assigning values to components</h4>
-<a
- id="dx1-38001"></a>
-<!--l. 261--><p class="noindent" >We need to assign values to the components in our circuit i.e., resistor and capacitor. Note
-that the sine voltage source has been placed for simulation. The specifications of sine source
-will be given during simulation. To assign value to the resistor, place the cursor above the
-letter <span
-class="cmtt-10x-x-109">R </span>(not <span
-class="cmtt-10x-x-109">R?</span>) and press the key <span
-class="cmtt-10x-x-109">E</span>. Choose <span
-class="cmti-10x-x-109">Field value</span>. Type <span
-class="cmtt-10x-x-109">1k </span>in the <span
-class="cmti-10x-x-109">Edit value field </span>box
-as shown in Fig.&#x00A0;<a
-href="#x1-3800211">5.11<!--tex4ht:ref: field --></a>. 1k means 1<span
-class="cmmi-10x-x-109">k</span>&Omega;. Similarly give the value <span
-class="cmtt-10x-x-109">1u </span>for the capacitor. 1u means
-1<span
-class="cmmi-10x-x-109">&mu;F</span>.
-<!--l. 271--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-3800211"></a>
-
-
-<!--l. 273--><p class="noindent" ><img
-src="figures/field.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.11: </span><span
-class="content">Editing value of resistor</span></div><!--tex4ht:label?: x1-3800211 -->
-
-<!--l. 276--><p class="indent" >   </div><hr class="endfigure">
-   <h4 class="subsectionHead"><span class="titlemark">5.2.4   </span> <a
- id="x1-390005.2.4"></a>Annotation and ERC</h4>
-<a
- id="dx1-39001"></a>
-<a
- id="dx1-39002"></a>
-<a
- id="dx1-39003"></a>
-<a
- id="dx1-39004"></a>
-<!--l. 280--><p class="noindent" >The next step is to annotate the schematic. Annotation gives unique references to the
-components. To annotate the schematic, click on <span
-class="cmti-10x-x-109">Annotate schematic </span>tool from the
-top toolbar. Click on <span
-class="cmtt-10x-x-109">annotation</span>, then click on <span
-class="cmtt-10x-x-109">OK </span>and finally click on close as
-shown in Fig.&#x00A0;<a
-href="#x1-3900813">5.13<!--tex4ht:ref: anno --></a>. The schematic is now annotated. The question marks next to
-component references have been replaced by unique numbers. If there are more than
-one instance of a component (say resistor), the annotation will be done as R1, R2,
-etc.
-<!--l. 289--><p class="indent" >   Let us now do <span
-class="cmtt-10x-x-109">ERC </span>or <span
-class="cmtt-10x-x-109">Electric Rules Check</span>. To do so, click on <span
-class="cmti-10x-x-109">Perform electric rules</span>
-<span
-class="cmti-10x-x-109">check </span>tool from the top toolbar. Click on <span
-class="cmti-10x-x-109">Test Erc </span>button. The error as shown in Fig.&#x00A0;<a
-href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a>
-may be displayed. Click on close in the test erc<a
- id="dx1-39005"></a> window. <a
- id="dx1-39006"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-3900712"></a>
-
-
-<!--l. 296--><p class="noindent" ><img
-src="figures/erc2.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.12: </span><span
-class="content">ERC error</span></div><!--tex4ht:label?: x1-3900712 -->
-
-<!--l. 299--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 300--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-3900813"></a>
-
-
-<!--l. 302--><p class="noindent" ><img
-src="figures/anno.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.13: </span><span
-class="content">Steps in annotating a schematic: 1. First click on Annotation then 2. Click
-on Ok then 3. Click on close</span></div><!--tex4ht:label?: x1-3900813 -->
-
-<!--l. 305--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 306--><p class="indent" >   There will be a green arrow pointing to the source of error in the schematic. Here it points
-to the ground terminal. This is shown in Fig.&#x00A0;<a
-href="#x1-3900914">5.14<!--tex4ht:ref: ercgnd --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-3900914"></a>
-
-
-<!--l. 311--><p class="noindent" ><img
-src="figures/ercgnd.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.14: </span><span
-class="content">Green arrow pointing to Ground terminal indicating an ERC error</span></div><!--tex4ht:label?: x1-3900914 -->
-
-<!--l. 314--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 315--><p class="indent" >   To correct this error, place a <span
-class="cmtt-10x-x-109">PWR</span><span
-class="cmtt-10x-x-109">_FLAG </span>from the Eeschema library <span
-class="cmti-10x-x-109">power</span>. <a
- id="dx1-39010"></a>Connect the
-power flag to the ground terminal as shown in Fig.&#x00A0;<a
-href="#x1-37004r3">5.10c<!--tex4ht:ref: schemfin --></a>. One needs to place <span
-class="cmtt-10x-x-109">PWR</span><span
-class="cmtt-10x-x-109">_FLAG</span>
-wherever the error shown in Fig.&#x00A0;<a
-href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a> is obtained. Repeat the ERC. Now there are no errors.
-With this we have created the schematic for simulation.
-   <h4 class="subsectionHead"><span class="titlemark">5.2.5   </span> <a
- id="x1-400005.2.5"></a>Netlist generation</h4>
-<a
- id="dx1-40001"></a>
-<!--l. 326--><p class="noindent" >To simulate the circuit that has been created in the previous section, we need to generate its
-netlist. <span
-class="cmtt-10x-x-109">Netlist </span>is a list of components in the schematic along with their connection
-information. <a
- id="dx1-40002"></a>To do so, click on the <span
-class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar. Click on spice
-from the window that opens up. Check the option <span
-class="cmtt-10x-x-109">Default Format</span>. Then click on <span
-class="cmti-10x-x-109">Generate</span>.
-This is shown in Fig.&#x00A0;<a
-href="#x1-4000315">5.15<!--tex4ht:ref: chap5net --></a>. Save the netlist. This will be a <span
-class="cmtt-10x-x-109">.cir </span>file. Do not change the
-directory while saving. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-4000315"></a>
-
-
-<!--l. 337--><p class="noindent" ><img
-src="figures/netlist.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;5.15: </span><span
-class="content">Steps in generating a Netlist for simulation: 1. Click on Spice then 2.
-Check the option <span
-class="cmtt-10x-x-109">Default Format </span>then 3. Click on Generate </span></div><!--tex4ht:label?: x1-4000315 -->
-
-<!--l. 340--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 341--><p class="indent" >   Now the netlist is ready to be simulated. Refer to <span class="cite">&#x00A0;[<a
-href="#Xkicad">15</a>]</span> or <span class="cite">&#x00A0;[<a
-href="#Xkicad2">16</a>]</span> to know more about
-Eeschema.
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;6</span><br /><a
- id="x1-410006"></a>PCB Design</h2>  Printed Circuit Board (PCB) <a
- id="dx1-41001"></a>design is an important step in
-electronic system design. Every component of the circuit needs to be placed and connections
-routed to minimise delay and area. Each component has an associated footprint. Footprint
-refers to the physical layout of a component that is required to mount it on the PCB.<a
- id="dx1-41002"></a> <a
- id="dx1-41003"></a>PCB
-design involves associating footprints to all components, placing them appropriately to
-minimise wire length and area, connecting the footprints using tracks/vias and finally
-extracting the required files needed for printing the PCB. Let us see the steps to design PCB
-using eSim.
-   <h3 class="sectionHead"><span class="titlemark">6.1   </span> <a
- id="x1-420006.1"></a>Schematic creation for PCB design</h3>
-<!--l. 16--><p class="noindent" >In Chapter&#x00A0;<a
-href="#x1-610009">9<!--tex4ht:ref: chap5 --></a>, we will see the differences between schematic for simulation and schematic for
-PCB design. Let us design the PCB for a RC circuit. A resistor, capacitor, ground, power flag
-and a connector are required. Connectors are used to take signals in and out of the
-PCB.
-<!--l. 22--><p class="indent" >   Create the circuit schematic as shown in Fig.&#x00A0;<a
-href="#x1-420011">6.1<!--tex4ht:ref: pcbschfin --></a>. The two pin connector (<span
-class="cmti-10x-x-109">CONN</span><span
-class="cmti-10x-x-109">_2</span>) can
-be placed from the Eeschema library <span
-class="cmti-10x-x-109">conn</span>. Do the annotation and test for ERC. Refer to
-Chapter&#x00A0;<a
-href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> to know more about basic steps in schematic creation.
-<!--l. 28--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-420011"></a>
-
-
-<!--l. 30--><p class="noindent" ><img
-src="figures/pcbschfin.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.1: </span><span
-class="content">Final circuit schematic for RC low pass circuit</span></div><!--tex4ht:label?: x1-420011 -->
-
-<!--l. 33--><p class="indent" >   </div><hr class="endfigure">
-   <h4 class="subsectionHead"><span class="titlemark">6.1.1   </span> <a
- id="x1-430006.1.1"></a>Netlist generation for PCB</h4>
-<a
- id="dx1-43001"></a>
-<a
- id="dx1-43002"></a>
-<!--l. 38--><p class="noindent" >The netlist for PCB is different from that for simulation. To generate netlist for PCB, click on
-the <span
-class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar in Schematic editor. In the Netlist window,
-under the tab <span
-class="cmti-10x-x-109">Pcbnew</span>, <a
- id="dx1-43003"></a>click on the button <span
-class="cmti-10x-x-109">Netlist</span>. This is shown in Fig.&#x00A0;<a
-href="#x1-430042">6.2<!--tex4ht:ref: netlistpcb --></a>. Click on
-<span
-class="cmti-10x-x-109">Save </span>in the Save netlist file dialog box that opens up. Do not change the directory
-or the name of the netlist file. Save the schematic and close the schematic editor.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-430042"></a>
-
-
-<!--l. 48--><p class="noindent" ><img
-src="figures/netlistpcb.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.2: </span><span
-class="content">Netlist generation for PCB</span></div><!--tex4ht:label?: x1-430042 -->
-
-<!--l. 51--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 52--><p class="indent" >   <span
-class="cmti-10x-x-109">Note that the netlist for PCB has an extension </span><span
-class="cmtt-10x-x-109">.net</span><span
-class="cmti-10x-x-109">. The netlist created for simulation</span>
-<span
-class="cmti-10x-x-109">has an extension </span><span
-class="cmtt-10x-x-109">.cir</span>.
-   <h4 class="subsectionHead"><span class="titlemark">6.1.2   </span> <a
- id="x1-440006.1.2"></a>Mapping of components using Footprint Editor</h4>
-<a
- id="dx1-44001"></a>
-<a
- id="dx1-44002"></a>
-<a
- id="dx1-44003"></a>
-<!--l. 59--><p class="noindent" >Once the netlist for PCB is created, one needs to map each component in the netlist to a
-footprint. The tool <span
-class="cmti-10x-x-109">Footprint Editor </span>is used for this. eSim uses <span
-class="cmtt-10x-x-109">CvPcb </span>as its footprint editor.
-<span
-class="cmtt-10x-x-109">CvPcb </span>is the footprint editor tool in KiCad. <a
- id="dx1-44004"></a>
-<!--l. 64--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">6.1.3   </span> <a
- id="x1-450006.1.3"></a>Familiarising the Footprint Editor tool</h4>
-<a
- id="dx1-45001"></a>
-<!--l. 67--><p class="noindent" >If one opens the <span
-class="cmti-10x-x-109">Footprint Editor </span>after creating the <span
-class="cmtt-10x-x-109">.net </span>netlist file, the Footprint editor as
-shown in Fig.&#x00A0;<a
-href="#x1-450023">6.3<!--tex4ht:ref: fe --></a> will be obtained. The menu bar and toolbars and the panes are marked in
-this figure. The menu bar will be available in the top left corner. The left pane has a list of
-components in the netlist file and the right pane has a list of available footprints for each
-component. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-450023"></a>
-
-
-<!--l. 75--><p class="noindent" ><img
-src="figures/fe.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.3: </span><span
-class="content">Footprint editor with the menu bar, toolbar, left pane and right pane
-marked</span></div><!--tex4ht:label?: x1-450023 -->
-
-<!--l. 78--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 79--><p class="indent" >   <span
-class="cmti-10x-x-109">Note that if the Footprint Editor is opened before creating a &#8216;.net&#8217; file, then the left and</span>
-<span
-class="cmti-10x-x-109">right panes will be empty</span>.
-   <h5 class="subsubsectionHead"><a
- id="x1-460006.1.3"></a>Toolbar</h5>
-<!--l. 82--><p class="noindent" >Some of the important tools in the toolbar are shown in Fig.&#x00A0;<a
-href="#x1-460014">6.4<!--tex4ht:ref: tb_fe --></a>. They are explained below:
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-460014"></a>
-
-
-<!--l. 86--><p class="noindent" ><img
-src="figures/tb_fe.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.4: </span><span
-class="content">Some important tools in the toolbar</span></div><!--tex4ht:label?: x1-460014 -->
-
-<!--l. 89--><p class="indent" >   </div><hr class="endfigure">
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">Save  netlist  and  footprint  files  -  Save  the  netlist  and  the  footprints  that  are
-     associated with it.
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">View selected footprint - View the selected footprint in 2D. See Sec.&#x00A0;<a
-href="#x1-470006.1.4">6.1.4<!--tex4ht:ref: viewfp --></a> for more
-     details.
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Automatic  footprint  association  -  Perform  footprint  association  for  each
-     component automatically. Footprints will be selected from the list of footprints
-     available.
-     </dd><dt class="compactenum">
-   4. </dt><dd
-class="compactenum">Delete all associations - Delete all the footprint associations made
-     </dd><dt class="compactenum">
-   5. </dt><dd
-class="compactenum">Display filtered footprint list - Display a filtered list of footprints suitable to the
-     selected component
-     </dd><dt class="compactenum">
-   6. </dt><dd
-class="compactenum">Display full footprint list - Display the list of all footprints available (without
-     filtering)</dd></dl>
-   <h4 class="subsectionHead"><span class="titlemark">6.1.4   </span> <a
- id="x1-470006.1.4"></a>Viewing footprints in 2D and 3D</h4>
-<a
- id="dx1-47001"></a>
-<a
- id="dx1-47002"></a>
-<!--l. 110--><p class="noindent" >To view a footprint in 2D, select it from the right pane and click on <span
-class="cmti-10x-x-109">View selected footprint</span>
-from the menu bar. Let us view the footprint for <span
-class="cmtt-10x-x-109">SM1210</span>. Choose SM1210 from
-the right pane as shown in Fig.&#x00A0;<a
-href="#x1-470035">6.5<!--tex4ht:ref: sm --></a>. On clicking the <span
-class="cmti-10x-x-109">View selected footprint </span>tool,
-the <span
-class="cmtt-10x-x-109">Footprint </span>window with the view in 2D will be displayed. Click on the <span
-class="cmti-10x-x-109">3D</span>
-tool in the <span
-class="cmtt-10x-x-109">Footprint </span>window, as shown in Fig.&#x00A0;<a
-href="#x1-470046">6.6<!--tex4ht:ref: 3d --></a>. A top view of the selected
-footprint in 3D is obtained. Click on the footprint and rotate it using mouse to get 3D
-views from various angles. One such side view of the footprint in 3D is shown in
-Fig.&#x00A0;<a
-href="#x1-470057">6.7<!--tex4ht:ref: 3dv --></a>.
-<!--l. 121--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-470035"></a>
-
-
-<!--l. 123--><p class="noindent" ><img
-src="figures/sm.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.5: </span><span
-class="content">Viewing footprint for SM1210: 1. Choose the footprint SM1210 from the
-right pane, 2. Click on <span
-class="cmti-10x-x-109">View selected footprint</span></span></div><!--tex4ht:label?: x1-470035 -->
-
-<!--l. 127--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 128--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-470046"></a>
-
-
-<!--l. 130--><p class="noindent" ><img
-src="figures/3d.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.6: </span><span
-class="content">Footprint view in 2D. Click on <span
-class="cmti-10x-x-109">3D </span>to get 3D view</span></div><!--tex4ht:label?: x1-470046 -->
-
-<!--l. 133--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 134--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-470057"></a>
-
-
-<!--l. 136--><p class="noindent" ><img
-src="figures/3dv.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.7: </span><span
-class="content">Side view of the footprint in 3D</span></div><!--tex4ht:label?: x1-470057 -->
-
-<!--l. 139--><p class="indent" >   </div><hr class="endfigure">
-   <h4 class="subsectionHead"><span class="titlemark">6.1.5   </span> <a
- id="x1-480006.1.5"></a>Mapping of components in the RC circuit</h4>
-<!--l. 142--><p class="noindent" >Click on <span
-class="cmtt-10x-x-109">C1 </span>from the left pane. Choose the footprint <span
-class="cmti-10x-x-109">C1 </span>from the right pane by double
-clicking on it. Click on connector <span
-class="cmtt-10x-x-109">P1 </span>from the left pane. Choose the footprint <span
-class="cmti-10x-x-109">SIL-2 </span>from the
-right pane by double clicking on it. Similarly choose the footprint <span
-class="cmti-10x-x-109">R3 </span>for the resistor <span
-class="cmtt-10x-x-109">R1</span>. The
-footprint mapping is shown in Fig.&#x00A0;<a
-href="#x1-480018">6.8<!--tex4ht:ref: map --></a>. Save the footprint association by clicking on the <span
-class="cmti-10x-x-109">Save</span>
-<span
-class="cmti-10x-x-109">netlist and footprint files </span>tool from the <span
-class="cmtt-10x-x-109">CvPcb </span>toolbar. The <span
-class="cmtt-10x-x-109">Save Net and component List</span>
-window appears. Browse to the directory where the schematic file for this project is saved and
-click on <span
-class="cmti-10x-x-109">Save</span>. The netlist gets saved and the <span
-class="cmti-10x-x-109">Footprint Editor </span>window closes automatically.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-480018"></a>
-
-
-<!--l. 155--><p class="noindent" ><img
-src="figures/map.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.8: </span><span
-class="content">Footprint mapping done</span></div><!--tex4ht:label?: x1-480018 -->
-
-<!--l. 158--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 159--><p class="indent" >   <span
-class="cmti-10x-x-109">Note that one needs to browse to the directory where the schematic file is saved and save</span>
-<span
-class="cmti-10x-x-109">the &#8216;.net&#8217; file in the same directory</span>.
-   <h3 class="sectionHead"><span class="titlemark">6.2   </span> <a
- id="x1-490006.2"></a>Creation of PCB layout</h3>
-<a
- id="dx1-49001"></a>
-<a
- id="dx1-49002"></a>
-<!--l. 164--><p class="noindent" >The next step is to place the footprints and lay tracks between them to get the layout. This is
-done using the <span
-class="cmti-10x-x-109">Layout Editor </span>tool. eSim uses <span
-class="cmtt-10x-x-109">Pcbnew</span>, the layout creation tool in KiCad, as its
-layout editor.
-<!--l. 169--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">6.2.1   </span> <a
- id="x1-500006.2.1"></a>Familiarizing the Layout Editor tool</h4>
-<a
- id="dx1-50001"></a>
-<!--l. 172--><p class="noindent" >The layout editor with the various menu bar and toolbars is shown in Fig.&#x00A0;<a
-href="#x1-500029">6.9<!--tex4ht:ref: pcbnew --></a>.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-500029"></a>
-
-
-<!--l. 176--><p class="noindent" ><img
-src="figures/pcbnew.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.9: </span><span
-class="content">Layout editor with menu bar, toolbars and layer options marked</span></div><!--tex4ht:label?: x1-500029 -->
-
-<!--l. 179--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 180--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5000310"></a>
-
-
-<!--l. 182--><p class="noindent" ><img
-src="figures/toptble.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.10: </span><span
-class="content">Top toolbar with important tools marked</span></div><!--tex4ht:label?: x1-5000310 -->
-
-<!--l. 185--><p class="indent" >   </div><hr class="endfigure">
-   <h5 class="subsubsectionHead"><a
- id="x1-510006.2.1"></a>Top toolbar</h5>
-<!--l. 188--><p class="noindent" >Some of the important menu options in the top menu bar are shown in Fig.&#x00A0;<a
-href="#x1-5000310">6.10<!--tex4ht:ref: toptble --></a>. They are
-explained below:
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">Save board - Save the printed circuit board
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">Module editor - Open module editor to edit footprint modules or libraries
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Read netlist - Import the netlist whose layout needs to be created.
-     </dd><dt class="compactenum">
-   4. </dt><dd
-class="compactenum">Perform design rules check - Check for design rules, unconnected nets, etc., in the
-     layout.
-     </dd><dt class="compactenum">
-   5. </dt><dd
-class="compactenum">Select working layer - Selection of working layer
-     </dd><dt class="compactenum">
-   6. </dt><dd
-class="compactenum">Show active layer selections and select layer pair for route and place - Select layer
-     in top and bottom layers. It also shows the currently active layer selections.
-     </dd><dt class="compactenum">
-   7. </dt><dd
-class="compactenum">Mode footprint: Manual/automatic move and place - Move and place modules</dd></dl>
-<!--l. 206--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">6.2.2   </span> <a
- id="x1-520006.2.2"></a>Hotkeys</h4>
-<a
- id="dx1-52001"></a>
-<!--l. 208--><p class="noindent" >A list of hotkeys are given below:
-     <dl class="compactenum"><dt class="compactenum">
-   1. </dt><dd
-class="compactenum">F1 - Zoom in
-     </dd><dt class="compactenum">
-   2. </dt><dd
-class="compactenum">F2 - Zoom out
-     </dd><dt class="compactenum">
-   3. </dt><dd
-class="compactenum">Delete - Delete Track or Footprint
-     </dd><dt class="compactenum">
-   4. </dt><dd
-class="compactenum">X - Add new track
-     </dd><dt class="compactenum">
-   5. </dt><dd
-class="compactenum">V - Add Via
-     </dd><dt class="compactenum">
-   6. </dt><dd
-class="compactenum">M - Move Item
-
-     </dd><dt class="compactenum">
-   7. </dt><dd
-class="compactenum">F - Flip Footprint
-     </dd><dt class="compactenum">
-   8. </dt><dd
-class="compactenum">R - Rotate Item
-     </dd><dt class="compactenum">
-   9. </dt><dd
-class="compactenum">G - Drag Footprint
-     </dd><dt class="compactenum">
-  10. </dt><dd
-class="compactenum">Ctrl+Z - Undo
-     </dd><dt class="compactenum">
-  11. </dt><dd
-class="compactenum">E - Edit Item</dd></dl>
-<!--l. 222--><p class="noindent" >The list can be viewed by selecting <span
-class="cmti-10x-x-109">Preferences </span>from the top menu bar and choosing <span
-class="cmti-10x-x-109">List Current</span>
-<span
-class="cmti-10x-x-109">Keys </span>from the option <span
-class="cmti-10x-x-109">Hotkeys</span>.
-<!--l. 226--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">6.2.3   </span> <a
- id="x1-530006.2.3"></a>PCB design example using RC circuit</h4>
-<a
- id="dx1-53001"></a>
-<!--l. 227--><p class="noindent" >Click on <span
-class="cmti-10x-x-109">Layout Editor </span>from the eSim toolbar. Click on <span
-class="cmti-10x-x-109">Read Netlist </span>tool from the top
-toolbar. Click on <span
-class="cmti-10x-x-109">Browse Netlist files </span>on the Netlist window that opens up. Select the <span
-class="cmtt-10x-x-109">.net </span>file
-that was modified after assigning footprints. Click on <span
-class="cmti-10x-x-109">Open</span>. Now Click on <span
-class="cmti-10x-x-109">Read Current</span>
-<span
-class="cmti-10x-x-109">Netlist </span>on the Netlist window. The message area in the Netlist window says that
-the RC_pcb.net has been read. The sequence of operations is shown in Fig.&#x00A0;<a
-href="#x1-5300411">6.11<!--tex4ht:ref: brnet --></a>.
-<a
- id="dx1-53002"></a><a
- id="dx1-53003"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5300411"></a>
-
-
-<!--l. 238--><p class="noindent" ><img
-src="figures/rcpcb.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.11: </span><span
-class="content">Importing netlist file to layout editor: 1. Browse netlist Files, 2. Choose
-the RC_pcb.net file, 3. Read Netlist file, 4. Close</span></div><!--tex4ht:label?: x1-5300411 -->
-
-<!--l. 242--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 243--><p class="indent" >   The footprint modules will now be imported to the top left hand corner of the layout
-editor window. This is shown in Fig.&#x00A0;<a
-href="#x1-5300512">6.12<!--tex4ht:ref: netlisttop --></a>. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5300512"></a>
-
-
-<!--l. 247--><p class="noindent" ><img
-src="figures/netlisttop.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.12: </span><span
-class="content">Footprint modules imported to top left corner of layout editor window</span></div><!--tex4ht:label?: x1-5300512 -->
-
-<!--l. 250--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 251--><p class="indent" >   Zoom in to the top left corner by pressing the key <span
-class="cmtt-10x-x-109">F1 </span>or using the scroll button of the
-mouse. The zoomed in version of the imported netlist is shown in Fig.&#x00A0;<a
-href="#x1-5300613">6.13<!--tex4ht:ref: zoom --></a>.
-<!--l. 255--><p class="indent" >   Let us now place this in the center of the layout editor window. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5300613"></a>
-
-
-<!--l. 259--><p class="noindent" ><img
-src="figures/zoom.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.13: </span><span
-class="content">Zoomed in version of the imported netlist</span></div><!--tex4ht:label?: x1-5300613 -->
-
-<!--l. 262--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 263--><p class="indent" >   Click on <span
-class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place </span>tool from the top toolbar.
-Place the cursor near the center of the layout editor window. Right click and choose <span
-class="cmti-10x-x-109">Glob</span>
-<span
-class="cmti-10x-x-109">move and place</span>. Choose <span
-class="cmti-10x-x-109">move all modules</span>. The sequence of operations is shown in Fig.&#x00A0;<a
-href="#x1-5300714">6.14<!--tex4ht:ref: movep --></a>.
-Click on <span
-class="cmti-10x-x-109">Yes </span>on the confirmation window to move the modules. Zoom in using the F1 key.
-The current placement of components after zooming in is shown in Fig.&#x00A0;<a
-href="#x1-53008r1">6.15a<!--tex4ht:ref: curplace --></a>.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5300714"></a>
-
-
-<!--l. 272--><p class="noindent" ><img
-src="figures/movep.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.14: </span><span
-class="content">Moving and placing modules to the center of layout editor. 1. Click on
-<span
-class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place</span>, 2. Place cursor at center of layout
-editor and right click on it 3. Choose <span
-class="cmti-10x-x-109">Glob Move and Place </span>and then choose <span
-class="cmti-10x-x-109">Move All</span>
-<span
-class="cmti-10x-x-109">Modules.</span></span></div><!--tex4ht:label?: x1-5300714 -->
-
-<!--l. 279--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 286--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5301015"></a>
-
-<a
- id="x1-53008r1"></a>
-<!--l. 290--><p class="noindent" > <img
-src="figures/curplace.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Zoomed</span>
-<span
-class="cmr-9">in</span>
-<span
-class="cmr-9">version</span>
-<span
-class="cmr-9">of  the</span>
-<span
-class="cmr-9">current</span>
-<span
-class="cmr-9">placement</span>
-<span
-class="cmr-9">after</span>
-<span
-class="cmr-9">moving</span>
-<span
-class="cmr-9">modules</span>
-<span
-class="cmr-9">to  the</span>
-<span
-class="cmr-9">center</span>
-<span
-class="cmr-9">of  the</span>
-<span
-class="cmr-9">layout</span>
-<span
-class="cmr-9">editor</span>                                                                      <a
- id="x1-53009r2"></a> <img
-src="figures/fplace.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(b)</span>
-                                                                          <span
-class="cmr-9">Final</span>
-                                                                          <span
-class="cmr-9">placement</span>
-                                                                          <span
-class="cmr-9">of</span>
-                                                                          <span
-class="cmr-9">footprints</span>
-                                                                          <span
-class="cmr-9">after</span>
-                                                                          <span
-class="cmr-9">rotating</span>
-                                                                          <span
-class="cmr-9">and</span>
-                                                                          <span
-class="cmr-9">moving</span>
-                                                                          <span
-class="cmr-9">P1</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.15: </span><span
-class="content">Different stages of placement of modules on PCB</span></div><!--tex4ht:label?: x1-5301015 -->
-
-<!--l. 295--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 296--><p class="indent" >   We need to arrange the modules properly to lay tracks. Rotate the connector P1 by
-placing the cursor on top of P1 and pressing R. Move it by placing the cursor on top of it and
-pressing M. The final placement is shown in Fig.&#x00A0;<a
-href="#x1-53009r2">6.15b<!--tex4ht:ref: fplace --></a>. <a
- id="dx1-53011"></a>
-<!--l. 302--><p class="indent" >   Let us now lay the tracks. Let us first change the track width. Click on <span
-class="cmti-10x-x-109">Design rules </span>from
-the top menu bar. Click on <span
-class="cmti-10x-x-109">Design rules</span>. This is shown in Fig.&#x00A0;<a
-href="#x1-5301416">6.16<!--tex4ht:ref: drules --></a>. The <span
-class="cmti-10x-x-109">Design Rules Editor</span>
-window opens up. Here one can edit the various design rules. Double click on the track width
-field to edit it. Type 0.8 and press <span
-class="cmtt-10x-x-109">Enter</span>. Click on OK. Fig.&#x00A0;<a
-href="#x1-5301517">6.17<!--tex4ht:ref: druleedit --></a> shows the sequence of
-operations. <a
- id="dx1-53012"></a><a
- id="dx1-53013"></a> <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5301416"></a>
-
-
-<!--l. 312--><p class="noindent" ><img
-src="figures/drules.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.16: </span><span
-class="content">Choose <span
-class="cmti-10x-x-109">Design Rules </span>from the top menu bar and <span
-class="cmti-10x-x-109">Design Rules </span>again</span></div><!--tex4ht:label?: x1-5301416 -->
-
-<!--l. 316--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 317--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5301517"></a>
-
-
-<!--l. 319--><p class="noindent" ><img
-src="figures/druleedit.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.17: </span><span
-class="content">Changing the track width: 1. Double click on <span
-class="cmti-10x-x-109">Track Width </span>field and type
-0.8, 2. Click on <span
-class="cmti-10x-x-109">OK</span></span></div><!--tex4ht:label?: x1-5301517 -->
-
-<!--l. 323--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 325--><p class="indent" >   Click on <span
-class="cmti-10x-x-109">Back </span>from the <span
-class="cmti-10x-x-109">Layer </span>options as shown in Fig.&#x00A0;<a
-href="#x1-5301718">6.18<!--tex4ht:ref: layer --></a>. <a
- id="dx1-53016"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5301718"></a>
-
-
-<!--l. 329--><p class="noindent" ><img
-src="figures/layer.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.18: </span><span
-class="content">Choosing the copper layer <span
-class="cmti-10x-x-109">Back</span></span></div><!--tex4ht:label?: x1-5301718 -->
-
-<!--l. 332--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 333--><p class="indent" >   Let us now start laying the tracks. Place the cursor above the left terminal of R1
-in the layout editor window. Press the key <span
-class="cmtt-10x-x-109">x</span>. Move the cursor down and double
-click on the left terminal of C1. A track is formed. This is shown in Fig.&#x00A0;<a
-href="#x1-53018r1">6.19a<!--tex4ht:ref: track1 --></a>.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302119"></a>
-
-<a
- id="x1-53018r1"></a>
-<!--l. 341--><p class="noindent" > <img
-src="figures/track1.png" alt="PIC"
->
-<span
-class="cmr-9">(a)   A</span>
-<span
-class="cmr-9">track</span>
-<span
-class="cmr-9">formed</span>
-<span
-class="cmr-9">between</span>
-<span
-class="cmr-9">resistor</span>
-<span
-class="cmr-9">and</span>
-<span
-class="cmr-9">capacitor</span>                              <a
- id="x1-53019r2"></a> <img
-src="figures/track2.png" alt="PIC"
->
-                                     <span
-class="cmr-9">(b)  A</span>
-                                     <span
-class="cmr-9">track</span>
-                                     <span
-class="cmr-9">formed</span>
-                                     <span
-class="cmr-9">between</span>
-                                     <span
-class="cmr-9">capacitor</span>
-                                     <span
-class="cmr-9">and</span>
-                                     <span
-class="cmr-9">connector</span>                              <a
- id="x1-53020r3"></a> <img
-src="figures/track3.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(c)   A</span>
-                                                                          <span
-class="cmr-9">track</span>
-                                                                          <span
-class="cmr-9">formed</span>
-                                                                          <span
-class="cmr-9">between</span>
-                                                                          <span
-class="cmr-9">connector</span>
-                                                                          <span
-class="cmr-9">and</span>
-                                                                          <span
-class="cmr-9">resistor</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.19: </span><span
-class="content">Different stages of laying tracks during PCB design</span></div><!--tex4ht:label?: x1-5302119 -->
-
-<!--l. 349--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 350--><p class="indent" >   Similarly lay the track between capacitor C1 and connector P1 as shown in
-Fig.&#x00A0;<a
-href="#x1-53019r2">6.19b<!--tex4ht:ref: track2 --></a>. The last track needs to be laid at an angle. To do so, place the cursor
-above the second terminal of R1. Press the key x and move the cursor diagonally
-down. Double click on the other terminal of the connector. The track will be laid
-as shown in Fig.&#x00A0;<a
-href="#x1-53020r3">6.19c<!--tex4ht:ref: track3 --></a>. All tracks are now laid. The next step is to create PCB
-edges.
-<!--l. 358--><p class="indent" >   Choose <span
-class="cmti-10x-x-109">PCB</span><span
-class="cmti-10x-x-109">_edges </span>from the <span
-class="cmti-10x-x-109">Layer </span>options to add edges. Click on <span
-class="cmti-10x-x-109">Add graphic line or</span>
-<span
-class="cmti-10x-x-109">polygon </span>from the toolbar on the left. Fig.&#x00A0;<a
-href="#x1-5302320">6.20<!--tex4ht:ref: pcbedges --></a> shows the sequence of operations. Let us now
-start drawing edges for PCB. <a
- id="dx1-53022"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302320"></a>
-
-
-<!--l. 365--><p class="noindent" ><img
-src="figures/pcbedges.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.20: </span><span
-class="content">Creating PCB edges: 1. Choose <span
-class="cmti-10x-x-109">PCB</span><span
-class="cmti-10x-x-109">_Edges </span>from <span
-class="cmti-10x-x-109">Layer </span>options 2. Choose
-<span
-class="cmti-10x-x-109">Add graphic line or polygon </span>from left toolbar</span></div><!--tex4ht:label?: x1-5302320 -->
-
-<!--l. 370--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 371--><p class="indent" >   Click to the left of the layout. Move cursor horizontally to the right. Click once to change
-orientation. Move cursor vertically down. Draw the edges as shown in Fig.&#x00A0;<a
-href="#x1-5302421">6.21<!--tex4ht:ref: pcbed --></a>. Double click
-to finish drawing the edges. <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302421"></a>
-
-
-<!--l. 377--><p class="noindent" ><img
-src="figures/pcbed.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.21: </span><span
-class="content">PCB edges drawn</span></div><!--tex4ht:label?: x1-5302421 -->
-
-<!--l. 380--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 382--><p class="indent" >   Click on <span
-class="cmti-10x-x-109">Perform design rules check </span>from the top toolbar to check for design rules. The
-<span
-class="cmti-10x-x-109">DRC Control </span>window opens up. Click on <span
-class="cmti-10x-x-109">Start DRC</span>. There are no errors under the <span
-class="cmtt-10x-x-109">Error</span>
-<span
-class="cmtt-10x-x-109">messages </span>tab. Click on <span
-class="cmti-10x-x-109">OK </span>to close DRC control window. Fig.&#x00A0;<a
-href="#x1-5302622">6.22<!--tex4ht:ref: drc --></a> shows the sequence of
-operations. <a
- id="dx1-53025"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302622"></a>
-
-
-<!--l. 390--><p class="noindent" ><img
-src="figures/drc.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.22: </span><span
-class="content">Performing design rules check: 1. Click on <span
-class="cmti-10x-x-109">Start DRC</span>, 2. Click on <span
-class="cmti-10x-x-109">Ok</span></span></div><!--tex4ht:label?: x1-5302622 -->
-
-<!--l. 394--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 395--><p class="indent" >   Click on <span
-class="cmti-10x-x-109">Save board </span>on the top toolbar.
-<!--l. 397--><p class="indent" >   To generate Gerber files, click on <span
-class="cmti-10x-x-109">File </span>from the top menu bar. Click on <span
-class="cmti-10x-x-109">Plot</span>. This is shown
-in Fig.&#x00A0;<a
-href="#x1-5302823">6.23<!--tex4ht:ref: plot --></a>. The plot window opens up. One can choose which layers to plot by
-selecting/deselecting them from the <span
-class="cmtt-10x-x-109">Layers </span>pane on the left side. One can also choose the
-format used to plot them. Choose <span
-class="cmti-10x-x-109">Gerber</span>. The output directory of the plots created
-can also be chosen. By default, it is the project directory. Some more options can
-be chosen in this window. Click on <span
-class="cmti-10x-x-109">Plot</span>. The message window shows the location
-in which the Gerber files are created. Click on <span
-class="cmti-10x-x-109">Close</span>. This is shown in Fig.&#x00A0;<a
-href="#x1-5302924">6.24<!--tex4ht:ref: plot2 --></a>.
-<a
- id="dx1-53027"></a><hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302823"></a>
-
-
-<!--l. 410--><p class="noindent" ><img
-src="figures/plot.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.23: </span><span
-class="content">Choosing <span
-class="cmti-10x-x-109">Plot </span>from the <span
-class="cmti-10x-x-109">File </span>menu</span></div><!--tex4ht:label?: x1-5302823 -->
-
-<!--l. 413--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 414--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-5302924"></a>
-
-
-<!--l. 416--><p class="noindent" ><img
-src="figures/plot2.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;6.24: </span><span
-class="content">Creating Gerber files: 1. Choose <span
-class="cmti-10x-x-109">Gerber </span>as the plot format, 2. Click on
-<span
-class="cmti-10x-x-109">Plot</span>. Message window shows location in which Gerber files are created, 3. Click on <span
-class="cmti-10x-x-109">Close</span></span></div><!--tex4ht:label?: x1-5302924 -->
-
-<!--l. 421--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 422--><p class="indent" >   The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to
-<span class="cite">&#x00A0;[<a
-href="#Xkicad">15</a>]</span> or <span class="cite">&#x00A0;[<a
-href="#Xkicad2">16</a>]</span>.
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;7</span><br /><a
- id="x1-540007"></a>Model Editor</h2>
-<!--l. 4--><p class="noindent" >Spice based simulators include a feature which allows accurate modeling of semiconductor
-devices such as diodes, transistors etc. eSim Model Editor provides a facility to define a new
-model for devices such as <span
-class="cmti-10x-x-109">diodes, MOSFET, BJT, JFET, IGBT, Magnetic core </span>etc. Model
-Editor in eSim lets the user enter the values of parameters depending on the type of
-device for which a model is required. The parameter values can be obtained from the
-data-sheet of the device. A newly created model can be exported to the model library
-and one can import it for different projects, whenever required. Model Editor also
-provides a facility to edit existing models. The GUI of the model editor is as shown in
-Fig.&#x00A0;<a
-href="#x1-540011">7.1<!--tex4ht:ref: modeleditor --></a>
-<!--l. 15--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-540011"></a>
-
-
-<!--l. 17--><p class="noindent" ><img
-src="figures/modeleditor_new.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.1: </span><span
-class="content">Model Editor</span></div><!--tex4ht:label?: x1-540011 -->
-
-<!--l. 20--><p class="indent" >   </div><hr class="endfigure">
-   <h3 class="sectionHead"><span class="titlemark">7.1   </span> <a
- id="x1-550007.1"></a>Creating New Model Library </h3>
-<!--l. 24--><p class="noindent" >eSim lets us create new model libraries based on the template model libraries. On selecting
-<span
-class="cmtt-10x-x-109">New </span>button the window is popped as shown in Fig.&#x00A0;<a
-href="#x1-550012">7.2<!--tex4ht:ref: modeleditor_new --></a>. The name has to be unique otherwise
-the error message appears on the window.
-<!--l. 27--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-550012"></a>
-
-
-<!--l. 29--><p class="noindent" ><img
-src="figures/modeleditor.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.2: </span><span
-class="content">Creating New Model Library</span></div><!--tex4ht:label?: x1-550012 -->
-
-<!--l. 32--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 33--><p class="indent" >   After the OK button is pressed the type of model library to be created is chosen by
-selecting one of the types on the left hand side i.e. <span
-class="cmtt-10x-x-109">Diode, BJT, MOS, JFET, IGBT,</span>
-<span
-class="cmtt-10x-x-109">Magnetic Core</span>. The template model library opens up in a tabular form as shown in Fig.&#x00A0;<a
-href="#x1-550023">7.3<!--tex4ht:ref: modelnew --></a>
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-550023"></a>
-
-
-<!--l. 36--><p class="noindent" ><img
-src="figures/modelnew.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.3: </span><span
-class="content">Choosing the Template Model Library </span></div><!--tex4ht:label?: x1-550023 -->
-
-<!--l. 39--><p class="indent" >   </div><hr class="endfigure">
-
-<!--l. 43--><p class="indent" >   New parameters can be added or current parameters can be removed using <span
-class="cmtt-10x-x-109">ADD</span>
-and <span
-class="cmtt-10x-x-109">REMOVE </span>buttons. Also the values of parameters can be changed in the table.
-Adding and removing the parameters in library files is shown in the Fig.&#x00A0;<a
-href="#x1-550034">7.4<!--tex4ht:ref: modeladd --></a> and
-Fig.&#x00A0;<a
-href="#x1-550045">7.5<!--tex4ht:ref: modelremove --></a>
-<!--l. 45--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-550034"></a>
-
-
-<!--l. 47--><p class="noindent" ><img
-src="figures/modeladd.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.4: </span><span
-class="content">Adding the Parameter in a Library</span></div><!--tex4ht:label?: x1-550034 -->
-
-<!--l. 50--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 52--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-550045"></a>
-
-
-<!--l. 54--><p class="noindent" ><img
-src="figures/modelremove.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.5: </span><span
-class="content">Removing a Parameter from a Library </span></div><!--tex4ht:label?: x1-550045 -->
-
-<!--l. 57--><p class="indent" >   </div><hr class="endfigure">
-<!--l. 59--><p class="indent" >   After the editing of the model library is done, the file can be saved by selecting the <span
-class="cmtt-10x-x-109">SAVE</span>
-button. These libraries are saved in the <span
-class="cmti-10x-x-109">User Libraries </span>folder under <span
-class="cmti-10x-x-109">deviceModelLibrary</span>
-repository.
-   <h3 class="sectionHead"><span class="titlemark">7.2   </span> <a
- id="x1-560007.2"></a>Editing Current Model Library</h3>
-<!--l. 62--><p class="noindent" >The existing model library can be modified using <span
-class="cmtt-10x-x-109">EDIT </span>option. On clicking the <span
-class="cmtt-10x-x-109">EDIT </span>button
-the file dialog opens where all the library files are saved as shown in Fig.&#x00A0;<a
-href="#x1-560016">7.6<!--tex4ht:ref: modeledit --></a>. You can select
-the library you want to edit. Once you are done with the editing, click on <span
-class="cmtt-10x-x-109">SAVE</span>
-button.
-<!--l. 65--><p class="indent" >   <hr class="figure"><div class="figure"
->
-
-<a
- id="x1-560016"></a>
-
-
-<!--l. 67--><p class="noindent" ><img
-src="figures/modeledit.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;7.6: </span><span
-class="content">Editing Existing Model Library</span></div><!--tex4ht:label?: x1-560016 -->
-
-<!--l. 70--><p class="indent" >   </div><hr class="endfigure">
-   <h3 class="sectionHead"><span class="titlemark">7.3   </span> <a
- id="x1-570007.3"></a>Uploading external .lib file to eSim repository</h3>
-<!--l. 73--><p class="noindent" >eSim directly cannot use the external .lib file. It has to be uploaded to eSim repository before
-using it in a circuit. eSim provides the facility to upload library files. They are then converted
-into xml format, which can be easily modified from the eSim interface. On clicking <span
-class="cmtt-10x-x-109">UPLOAD</span>
-button the library can be uploaded from any location. The model library will be
-saved with the name you have provided, in the <span
-class="cmti-10x-x-109">User Libraries </span>folder of repository
-<span
-class="cmti-10x-x-109">deviceModelLibrary</span>.
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;8</span><br /><a
- id="x1-580008"></a>SubCircuit Builder</h2> Subcircuit is a way to implement hierarchical modeling.
-Once a subcircuit for a compo- nent is created, it can be used in other circuits.
-eSim provides an easy way to create a subcircuit. The following Fig.&#x00A0;<a
-href="#x1-580011">8.1<!--tex4ht:ref: subcircuit_mainwin --></a> shows
-the window that is opened when the SubCircuit tool is chosen from the toolbar.
-<hr class="figure"><div class="figure"
->
-
-<a
- id="x1-580011"></a>
-
-
-<!--l. 8--><p class="noindent" ><img
-src="figures/subcirciut_window.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.1: </span><span
-class="content">Subcircuit Window</span></div><!--tex4ht:label?: x1-580011 -->
-
-<!--l. 11--><p class="noindent" ></div><hr class="endfigure">
-
-   <h3 class="sectionHead"><span class="titlemark">8.1   </span> <a
- id="x1-590008.1"></a>Creating a SubCircuit</h3>
-<!--l. 32--><p class="noindent" >The steps to create subcircuit are as follows.
-     <ul class="itemize1">
-     <li class="itemize">After opening the Subcircuit tool, click on <span
-class="cmtt-10x-x-109">New Subcircuit Schematic </span>button.
-     It will ask the name of the subcircuit. Enter the name of subcircuit (without any
-     spaces) and click <span
-class="cmtt-10x-x-109">OK </span>as shown in Fig.&#x00A0;<a
-href="#x1-590012">8.2<!--tex4ht:ref: newsubcktschematic --></a>.
-     <!--l. 39--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-590012"></a> <img
-src="figures/newsubcktschematic.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.2: </span><span
-class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590012 -->
-     <!--l. 44--><p class="noindent" ></div><hr class="endfigure">
-     </li>
-     <li class="itemize">After clicking <span
-class="cmtt-10x-x-109">OK </span>button it will open KiCad schematic. Draw your circuit
-     which will be later used as a subcircuit. e.g the Fig.&#x00A0;<a
-href="#x1-590023">8.3<!--tex4ht:ref: createsubcktsch --></a> shows the half adder
-     circuit.
-     <!--l. 49--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-590023"></a> <img
-src="figures/createsubcktsch.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.3: </span><span
-class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590023 -->
-     <!--l. 54--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Once you complete the circuit, assign port to the node of your circuit which will be
-     used to connect with the main circuit. The circuit will look like Fig.&#x00A0;<a
-href="#x1-590034">8.4<!--tex4ht:ref: halfadder --></a> after
-     adding PORT to it. The PORT symbol can be found in Eeschema as shown in
-     Fig.&#x00A0;<a
-href="#x1-590045">8.5<!--tex4ht:ref: port --></a>.
-     <!--l. 61--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-590034"></a> <img
-src="figures/ha_sub.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.4: </span><span
-class="content">Half-Adder Subcircuit </span></div><!--tex4ht:label?: x1-590034 -->
-     <!--l. 66--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 69--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-590045"></a> <img
-src="figures/port_lib.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.5: </span><span
-class="content">Selection of PORT component</span></div><!--tex4ht:label?: x1-590045 -->
-     <!--l. 74--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Next step is to save the schematic and generate KiCad netlist as explained in Chapter
-     5.
-     </li>
-     <li class="itemize">To use this as a subcircuit, create a block in KiCad Eeschema by following steps given
-     below:
-          <dl class="enumerate"><dt class="enumerate">
-       1. </dt><dd
-class="enumerate">Go to library browser of Eeschema.
-          </dd><dt class="enumerate">
-       2. </dt><dd
-class="enumerate">Select the working library as eSim_Subckt as shown in Fig.&#x00A0;<a
-href="#x1-590076">8.6<!--tex4ht:ref: esimsubckt --></a> <hr class="figure"><div class="figure"
-><a
- id="x1-590076"></a> <img
-src="figures/esim-subckt.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.6: </span><span
-class="content">Selecting Working Library</span></div><!--tex4ht:label?: x1-590076 -->
-          <!--l. 90--><p class="noindent" ></div><hr class="endfigure">
-
-          </dd><dt class="enumerate">
-       3. </dt><dd
-class="enumerate">Click on create a new component with reference X as shown in Fig.&#x00A0;<a
-href="#x1-590097">8.7<!--tex4ht:ref: subcktnewcomp --></a> <hr class="figure"><div class="figure"
-><a
- id="x1-590097"></a>
-          <img
-src="figures/subcktnewcomp.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.7: </span><span
-class="content">Creating New Component</span></div><!--tex4ht:label?: x1-590097 -->
-          <!--l. 99--><p class="noindent" ></div><hr class="endfigure">
-          </dd><dt class="enumerate">
-       4. </dt><dd
-class="enumerate">Start drawing the subcircuit block. Update and save it as shown in Fig.&#x00A0;<a
-href="#x1-590118">8.8<!--tex4ht:ref: block --></a>.
-          <!--l. 104--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-590118"></a> <img
-src="figures/halfadderblock.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;8.8: </span><span
-class="content">Half-Adder Subcircuit Block</span></div><!--tex4ht:label?: x1-590118 -->
-          <!--l. 109--><p class="noindent" ></div><hr class="endfigure">
-          </dd></dl>
-
-     </li>
-     <li class="itemize">Close the Eeschema window and click on Convert KiCad to Ngspice button in subcircuit
-     builder tool. This will convert the KiCad spice netlist to Ngspice netlist. And it will
-     save your subcircuit into eSim repository, which you can add in your main
-     circuit.
-     </li></ul>
-<!--l. 120--><p class="noindent" >
-   <h3 class="sectionHead"><span class="titlemark">8.2   </span> <a
- id="x1-600008.2"></a>Edit a Subcircuit</h3>
-<!--l. 121--><p class="noindent" >The steps to edit a subcircuit are as follows.
-     <ul class="itemize1">
-     <li class="itemize">After opening the Subcircuit tool, click on <span
-class="cmtt-10x-x-109">Edit Subcircuit Schematic </span>button.
-     It will open a dialog box where you can select any subcircuit for editing.
-     </li>
-     <li class="itemize">After selecting the subcircuit it will open it in KiCad Eeschema, where you can
-     edit the subcircuit.
-     </li>
-     <li class="itemize">Next step is to save the schematic and generate KiCad netlist.
-     </li>
-     <li class="itemize">If you have edited the number of ports then you have to change the block in KiCad
-     Eeschema accordingly.
-     </li>
-     <li class="itemize">Close the Eeschema window and click on <span
-class="cmtt-10x-x-109">Convert KiCad to Ngspice </span>button in
-     subcircuit builder tool to convert the edited subcircuit KiCad netlist into Ngspice
-     netlist.
-     </li></ul>
-
-   <h2 class="chapterHead"><span class="titlemark">Chapter&#x00A0;9</span><br /><a
- id="x1-610009"></a>Solved Examples</h2>
-   <h3 class="sectionHead"><span class="titlemark">9.1   </span> <a
- id="x1-620009.1"></a>Solved Examples</h3>
-<!--l. 8--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">9.1.1   </span> <a
- id="x1-630009.1.1"></a>Basic RC Circuit</h4>
-<!--l. 9--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-640009.1.1"></a>Problem Statement:</h5>
-<!--l. 9--><p class="noindent" >Plot the Input and Output Waveform of an RC circuit whose input voltage (Vs) is 50Hz,
-3V peak to peak. The values of Resistor (R) and Capacitor(C) are 1<span
-class="cmmi-10x-x-109">k </span>and 1<span
-class="cmmi-10x-x-109">uf</span>
-respectively.
-   <h5 class="subsubsectionHead"><a
- id="x1-650009.1.1"></a>Solution:</h5>
-     <ul class="itemize1">
-     <li class="itemize">Creating a Project: The new project is created by clicking the <span
-class="cmtt-10x-x-109">New </span>icon on the
-     menubar. The name of the project is given in the pop up window as shown in
-     Fig.&#x00A0;<a
-href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. <hr class="figure"><div class="figure"
-><a
- id="x1-650011"></a> <img
-src="figures/rc1.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.1: </span><span
-class="content">Creating New Project</span></div><!--tex4ht:label?: x1-650011 -->
-     <!--l. 20--><p class="noindent" ></div><hr class="endfigure">
-     </li>
-     <li class="itemize">Creating the Schematic: To create the schematic, click the very first icon of the left
-     toolbar as shown in the Fig.&#x00A0;<a
-href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.
-     <!--l. 25--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650022"></a> <img
-src="figures/rc2.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.2: </span><span
-class="content">Open Schematic Editor</span></div><!--tex4ht:label?: x1-650022 -->
-     <!--l. 31--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 33--><p class="noindent" >To create a schematic in KiCad, we need to place the required components. Fig.&#x00A0;<a
-href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a>
-     shows the icon on the right toolbar which opens the component library.
-     <!--l. 35--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650033"></a> <img
-src="figures/rc_component.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.3: </span><span
-class="content">Place Component Icon</span></div><!--tex4ht:label?: x1-650033 -->
-     <!--l. 41--><p class="noindent" ></div><hr class="endfigure">
-
-     <!--l. 45--><p class="noindent" >After all the required components of the simple RC circuit are placed, wiring is done
-     using the <span
-class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig.&#x00A0;<a
-href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>
-     <!--l. 47--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650044"></a> <img
-src="figures/rc_wire.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.4: </span><span
-class="content">Place Wire Icon</span></div><!--tex4ht:label?: x1-650044 -->
-     <!--l. 53--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 55--><p class="noindent" >Next step is <span
-class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig.&#x00A0;<a
-href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span
-class="cmtt-10x-x-109">ERC</span>.
-     <!--l. 57--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650055"></a> <img
-src="figures/erc1.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.5: </span><span
-class="content">Electric Rules Check Icon</span></div><!--tex4ht:label?: x1-650055 -->
-     <!--l. 63--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 65--><p class="noindent" >Fig.&#x00A0;<a
-href="#x1-650066">9.6<!--tex4ht:ref: rc_complete1 --></a> shows the RC circuit after connecting the components by wire.
-     <!--l. 67--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650066"></a> <img
-src="figures/rc_complete1.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.6: </span><span
-class="content">RC circuit</span></div><!--tex4ht:label?: x1-650066 -->
-     <!--l. 72--><p class="noindent" ></div><hr class="endfigure">
-
-     <!--l. 76--><p class="noindent" >After clicking the <span
-class="cmtt-10x-x-109">ERC </span>icon a window opens up. Click the <span
-class="cmtt-10x-x-109">Run </span>button to run rules check.
-     The errors are listed in as shown in Fig.&#x00A0;<a
-href="#x1-65007r1">9.7a<!--tex4ht:ref: erc2 --></a>. This error is handled by adding <span
-class="cmtt-10x-x-109">Power</span>
-     <span
-class="cmtt-10x-x-109">Flag </span>as shown in Fig.&#x00A0;<a
-href="#x1-65008r2">9.7b<!--tex4ht:ref: rc_pwr --></a>.
-     <!--l. 78--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650097"></a> <a
- id="x1-65007r1"></a> <img
-src="figures/erc2.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">ERC</span>
- <span
-class="cmr-9">Run</span>                                                                                                               <a
- id="x1-65008r2"></a> <img
-src="figures/rc_pwr.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">Power</span>
-                                                                                                                     <span
-class="cmr-9">Flag</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.7: </span><span
-class="content">ERC check and POWER FLAG</span></div><!--tex4ht:label?: x1-650097 -->
-     <!--l. 87--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 89--><p class="noindent" >After adding the <span
-class="cmtt-10x-x-109">Power Flag </span>the completed RC circuit is shown in Fig.&#x00A0;<a
-href="#x1-65010r1">9.8a<!--tex4ht:ref: rc_schematic --></a> and the
-     netlist is generated as shown in Fig.&#x00A0;<a
-href="#x1-65011r2">9.8b<!--tex4ht:ref: rc_netlist --></a>.
-     <!--l. 92--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650128"></a> <a
- id="x1-65010r1"></a> <img
-src="figures/rc_schematic.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">Schematic</span>
- <span
-class="cmr-9">of  RC</span>
- <span
-class="cmr-9">circuit</span>                                                                                                            <a
- id="x1-65011r2"></a> <img
-src="figures/rc_netlistgeneration.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">Generating</span>
-                                                                                                                     <span
-class="cmr-9">KiCad</span>
-                                                                                                                     <span
-class="cmr-9">Netlist</span>
-                                                                                                                     <span
-class="cmr-9">of  RC</span>
-                                                                                                                     <span
-class="cmr-9">circuit</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.8: </span><span
-class="content">RC Schematic and Netlist Generation</span></div><!--tex4ht:label?: x1-650128 -->
-     <!--l. 101--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Convert KiCad to Ngspice: To convert KiCad netlist of RC circuit to NgSpice
-     compatible netlist click on KiCad to Ngspice icon as shown in Fig.&#x00A0;<a
-href="#x1-650139">9.9<!--tex4ht:ref: rcki2ng --></a>.
-     <!--l. 107--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-650139"></a> <img
-src="figures/rc_ki2ng.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.9: </span><span
-class="content">Convert KiCad to Ngspice Icon</span></div><!--tex4ht:label?: x1-650139 -->
-     <!--l. 112--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 114--><p class="noindent" >Now you can enter the type of analysis and source details as shown in Fig.&#x00A0;<a
-href="#x1-65014r1">9.10a<!--tex4ht:ref: rc_analysistab --></a> and
-     Fig.&#x00A0;<a
-href="#x1-65015r2">9.10b<!--tex4ht:ref: rc_sourcedetailstab --></a> respectively.
-     <!--l. 116--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-6501610"></a> <a
- id="x1-65014r1"></a> <img
-src="figures/rc_analysistab.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">RC</span>
- <span
-class="cmr-9">Analysis</span>                                                                                                         <a
- id="x1-65015r2"></a> <img
-src="figures/rc_sourcedetailstab.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">RC</span>
-                                                                                                                     <span
-class="cmr-9">Source</span>
-                                                                                                                     <span
-class="cmr-9">Details</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.10: </span><span
-class="content">RC Analysis and Source Detail</span></div><!--tex4ht:label?: x1-6501610 -->
-     <!--l. 125--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 126--><p class="noindent" >The other tab will be empty as RC circuit do not use any Ngspice model, device library
-     and subcircuit.
-     <!--l. 128--><p class="noindent" >After entering the value, press the convert button. It will convert the netlist into
-     Ngspice compatible netlist.
-
-     </li>
-     <li class="itemize">Simulation: To run Ngspice simulation click the simulation icon in the tool bar
-     as shown in the Fig.&#x00A0;<a
-href="#x1-6501711">9.11<!--tex4ht:ref: rcplot --></a>. <hr class="figure"><div class="figure"
-><a
- id="x1-6501711"></a> <img
-src="figures/rc_plot.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.11: </span><span
-class="content">Simulation Icon</span></div><!--tex4ht:label?: x1-6501711 -->
-     <!--l. 139--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 141--><p class="noindent" >In eSim, there are two types of plot. First is normal Ngspice plot and second is
-     interactive python plot as shown in Fig.&#x00A0;<a
-href="#x1-65018r1">9.12a<!--tex4ht:ref: rc_ngspiceplot --></a> and Fig.&#x00A0;<a
-href="#x1-65019r2">9.12b<!--tex4ht:ref: rc_pythonplot --></a> respectively.
-     <!--l. 143--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-6502012"></a> <a
- id="x1-65018r1"></a> <img
-src="figures/rc_ngspiceplot.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">Ngspice</span>
- <span
-class="cmr-9">Plot</span>
- <span
-class="cmr-9">of RC</span>                                                                                                            <a
- id="x1-65019r2"></a> <img
-src="figures/rc_pythonplot.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">Python</span>
-                                                                                                                     <span
-class="cmr-9">Plot</span>
-                                                                                                                     <span
-class="cmr-9">of RC</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.12: </span><span
-class="content">Ngspice and Interactive Python Plotting</span></div><!--tex4ht:label?: x1-6502012 -->
-     <!--l. 152--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 154--><p class="noindent" >In the interactive python plot you can select any node or branch to plot voltage or
-     current across it. Also it has the facility to plot basic functions across the node like
-     addition, substraction, multiplication, division and v/s.
-     </li></ul>
-
-<!--l. 160--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">9.1.2   </span> <a
- id="x1-660009.1.2"></a>Half Wave Rectifier</h4>
-<!--l. 162--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-670009.1.2"></a>Problem Statement:</h5>
-<!--l. 162--><p class="noindent" >Plot the Input and Output Waveform of Half Wave Rectifier circuit where the input voltage
-(Vs) is 50Hz, 2V peak to peak. The value for Resistor (R) is 1k.
-<!--l. 164--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-680009.1.2"></a>Solution:</h5>
-<!--l. 165--><p class="noindent" >The new project is created by clicking the <span
-class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project
-is given in the window shown in Fig.&#x00A0;<a
-href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>.
-     <ul class="itemize1">
-     <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left
-     toolbar as shown in the Fig.&#x00A0;<a
-href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br
-class="newline" />
-     <!--l. 171--><p class="noindent" >After the KiCad window is opened, to create a schematic we need to place the
-     required components. Fig.&#x00A0;<a
-href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens
-     the component library.<br
-class="newline" />
-     <!--l. 174--><p class="noindent" >After all the required components of the simple Half Wave rectifier circuits are
-     placed, wiring is done using the <span
-class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig.&#x00A0;<a
-href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a><br
-class="newline" />
-     <!--l. 176--><p class="noindent" >Next step is <span
-class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig.&#x00A0;<a
-href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span
-class="cmtt-10x-x-109">ERC</span>. After
-     completing all the above steps the final Half Wave Rectifier schematic will look
-     like Fig.&#x00A0;<a
-href="#x1-6800113">9.13<!--tex4ht:ref: hwr_schematic --></a>.<br
-class="newline" />
-     <!--l. 178--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-6800113"></a> <img
-src="figures/hwr_schematic.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.13: </span><span
-class="content">Schematic of Half Wave Rectifier circuit</span></div><!--tex4ht:label?: x1-6800113 -->
-     <!--l. 183--><p class="noindent" ></div><hr class="endfigure">
-
-     <!--l. 187--><p class="noindent" >KiCad netlist is generated as shown in the Fig.&#x00A0;<a
-href="#x1-6800214">9.14<!--tex4ht:ref: hwr_netlistgeneration --></a> <br
-class="newline" />
-     <!--l. 189--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-6800214"></a> <img
-src="figures/hwr_netlistgeneration.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.14: </span><span
-class="content">Half Wave Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-6800214 -->
-     <!--l. 194--><p class="noindent" ></div><hr class="endfigure">
-     </li>
-     <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on the <span
-class="cmtt-10x-x-109">KiCad-Ngspice</span>
-     <span
-class="cmtt-10x-x-109">converter </span>button. This will open converter window where you can enter details of
-     Analysis, Source values and Device library.
-     <!--l. 198--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-6800615"></a> <a
- id="x1-68003r1"></a> <img
-src="figures/hwr_analysistab.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">Half</span>
- <span
-class="cmr-9">Wave</span>
- <span
-class="cmr-9">Rectifier</span>
- <span
-class="cmr-9">Analysis</span>                                               <a
- id="x1-68004r2"></a> <img
-src="figures/hwr_sourcedetailstab.png" alt="PIC"
->
-                                                  <span
-class="cmr-9">(b)</span>
-                                                           <span
-class="cmr-9">Half</span>
-                                                           <span
-class="cmr-9">Wave</span>
-                                                           <span
-class="cmr-9">Rectifier</span>
-                                                           <span
-class="cmr-9">Source</span>
-                                                           <span
-class="cmr-9">Details</span>                                                 <a
- id="x1-68005r3"></a> <img
-src="figures/hwr_devicemodelingtab.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(c)</span>
-                                                                                                                     <span
-class="cmr-9">Half</span>
-                                                                                                                     <span
-class="cmr-9">Wave</span>
-                                                                                                                     <span
-class="cmr-9">Rectifier</span>
-                                                                                                                     <span
-class="cmr-9">Device</span>
-                                                                                                                     <span
-class="cmr-9">Modeling</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.15: </span><span
-class="content">Analysis, Source and Device Tab</span></div><!--tex4ht:label?: x1-6800615 -->
-     <!--l. 210--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 212--><p class="noindent" >Under device library you can add the library for diode used in the circuit. If you do not
-     add any library it will take default Ngspice model.
-     </li>
-     <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run
-     simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure"
-><a
- id="x1-6800916"></a> <a
- id="x1-68007r1"></a> <img
-src="figures/hwr_ngspiceplot.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Ngspice</span>
-<span
-class="cmr-9">Plot</span>
-<span
-class="cmr-9">of</span>
-<span
-class="cmr-9">Half</span>
-<span
-class="cmr-9">Wave</span>
-<span
-class="cmr-9">Rectifier</span>           <a
- id="x1-68008r2"></a> <img
-src="figures/hwr_pythonplot.png" alt="PIC"
->
-                    <span
-class="cmr-9">(b)</span>
-                        <span
-class="cmr-9">Python</span>
-                        <span
-class="cmr-9">Plot</span>
-                        <span
-class="cmr-9">of</span>
-                        <span
-class="cmr-9">Half</span>
-                        <span
-class="cmr-9">Wave</span>
-                        <span
-class="cmr-9">Rectifier</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.16: </span><span
-class="content">Half Wave Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-6800916 -->
-     <!--l. 225--><p class="noindent" ></div><hr class="endfigure">
-     </li></ul>
-
-<!--l. 232--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">9.1.3   </span> <a
- id="x1-690009.1.3"></a>Precision Rectifier</h4>
-<!--l. 233--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-700009.1.3"></a>Problem Statement:</h5>
-<!--l. 233--><p class="noindent" >Plot the input and output waveform of the Precision Rectifier circuit where input voltage
-(Vs) is 50<span
-class="cmmi-10x-x-109">Hz </span>, 3<span
-class="cmmi-10x-x-109">V </span>peak to peak.
-<!--l. 235--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-710009.1.3"></a>Solution:</h5>
-<!--l. 236--><p class="noindent" >The new project is created by clicking the <span
-class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project
-is given as shown in the Fig.&#x00A0;<a
-href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>.
-     <ul class="itemize1">
-     <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left
-     toolbar as shown in the Fig.&#x00A0;<a
-href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br
-class="newline" />After the KiCad window is opened, to create a schematic we need to place the
-     required components. Fig.&#x00A0;<a
-href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens
-     the component library.<br
-class="newline" />After all the required components of the precision rectifier circuit are placed,
-     wiring is done using the <span
-class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig.&#x00A0;<a
-href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br
-class="newline" />Next step is <span
-class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig.&#x00A0;<a
-href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span
-class="cmtt-10x-x-109">ERC</span>. The
-     Fig.&#x00A0;<a
-href="#x1-7100117">9.17<!--tex4ht:ref: pr_schematic --></a> shows the complete Precision Rectifier schematic after removing the
-     errors.
-     <!--l. 246--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-7100117"></a> <img
-src="figures/pr_schematic.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.17: </span><span
-class="content">Schematic of Precision Rectifier circuit</span></div><!--tex4ht:label?: x1-7100117 -->
-     <!--l. 251--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 253--><p class="noindent" >The KiCad netlist is generated as shown in Fig.&#x00A0;<a
-href="#x1-7100218">9.18<!--tex4ht:ref: pr_netlistgeneration --></a>.<br
-class="newline" />
-     <!--l. 255--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-7100218"></a> <img
-src="figures/pr_netlistgeneration.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.18: </span><span
-class="content">Precision Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7100218 -->
-     <!--l. 260--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice
-     converter button.<br
-class="newline" />
-     <!--l. 266--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values,
-     Device library and Subcircuit.
-     <!--l. 268--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-7100719"></a> <a
- id="x1-71003r1"></a> <img
-src="figures/pr_analysistab.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">Precision</span>
- <span
-class="cmr-9">Rectifier</span>
- <span
-class="cmr-9">Analysis</span>                                                                                                         <a
- id="x1-71004r2"></a> <img
-src="figures/pr_sourcedetailstab.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">Precision</span>
-                                                                                                                     <span
-class="cmr-9">Rectifier</span>
-                                                                                                                     <span
-class="cmr-9">Source</span>
-                                                                                                                     <span
-class="cmr-9">Details</span>
-<a
- id="x1-71005r3"></a>
-<!--l. 278--><p class="noindent" > <img
-src="figures/pr_devicemodelingtab.png" alt="PIC"
->
-<span
-class="cmr-9">(c)</span>
-<span
-class="cmr-9">Precision</span>
-<span
-class="cmr-9">Rectifier</span>
-<span
-class="cmr-9">Device</span>
-<span
-class="cmr-9">Modeling</span>                                                                   <a
- id="x1-71006r4"></a> <img
-src="figures/pr_subcircuitstab.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(d)</span>
-                                                                          <span
-class="cmr-9">Precision</span>
-                                                                          <span
-class="cmr-9">Rectifier</span>
-                                                                          <span
-class="cmr-9">Subcircuit</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.19: </span><span
-class="content">Analysis, Source, Device library and Subcircuit tab</span></div><!--tex4ht:label?: x1-7100719 -->
-     <!--l. 283--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 285--><p class="noindent" >Under device library you can add the library for the diode used in the circuit. If you do
-     not add any library it will take default Ngspice model for diode.<br
-class="newline" />
-     <!--l. 288--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to
-     add subcircuit it will throw an error.
-
-     </li>
-     <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run the
-     simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure"
-><a
- id="x1-7101020"></a> <a
- id="x1-71008r1"></a> <img
-src="figures/pr_ngspiceplot.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Ngspice</span>
-<span
-class="cmr-9">Plot</span>
-<span
-class="cmr-9">of</span>
-<span
-class="cmr-9">Precision</span>
-<span
-class="cmr-9">Rectifier</span>           <a
- id="x1-71009r2"></a> <img
-src="figures/pr_pythonplot.png" alt="PIC"
->
-                    <span
-class="cmr-9">(b)</span>
-                        <span
-class="cmr-9">Python</span>
-                        <span
-class="cmr-9">Plot</span>
-                        <span
-class="cmr-9">of</span>
-                        <span
-class="cmr-9">Precision</span>
-                        <span
-class="cmr-9">Rectifier</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.20: </span><span
-class="content">Precision Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-7101020 -->
-     <!--l. 302--><p class="noindent" ></div><hr class="endfigure">
-     </li></ul>
-
-<!--l. 309--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">9.1.4   </span> <a
- id="x1-720009.1.4"></a>Inverting Amplifier</h4>
-<!--l. 310--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-730009.1.4"></a>Problem Statement:</h5>
-<!--l. 311--><p class="noindent" >Plot the Input and Output Waveform of Inverting Amplifier circuit where the input voltage
-(Vs) is 50<span
-class="cmmi-10x-x-109">Hz</span>, 2<span
-class="cmmi-10x-x-109">V </span>peak to peak and gain is 2.
-   <h5 class="subsubsectionHead"><a
- id="x1-740009.1.4"></a>Solution:</h5>
-     <ul class="itemize1">
-     <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left
-     toolbar as shown in the Fig.&#x00A0;<a
-href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br
-class="newline" />After the KiCad window is opened, to create a schematic we need to place the
-     required components. Fig.&#x00A0;<a
-href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens
-     the component library.<br
-class="newline" />After all the required components of the inverting amplifier circuit are placed,
-     wiring is done using the <span
-class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig.&#x00A0;<a
-href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br
-class="newline" />Next step is <span
-class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig.&#x00A0;<a
-href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span
-class="cmtt-10x-x-109">ERC</span>.
-     <!--l. 321--><p class="noindent" >The Fig.&#x00A0;<a
-href="#x1-7400121">9.21<!--tex4ht:ref: ia_schematic --></a> shows the complete Precision Rectifier schematic after removing
-     the errors.
-     <!--l. 323--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-7400121"></a> <img
-src="figures/ia_schematic.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.21: </span><span
-class="content">Schematic of Inverting Amplifier circuit</span></div><!--tex4ht:label?: x1-7400121 -->
-     <!--l. 328--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 330--><p class="noindent" >The KiCad netlist is generated as shown in Fig.&#x00A0;<a
-href="#x1-7400222">9.22<!--tex4ht:ref: ia_netlistgeneration --></a>.<br
-class="newline" /><hr class="figure"><div class="figure"
-><a
- id="x1-7400222"></a> <img
-src="figures/ia_netlistgeneration.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.22: </span><span
-class="content">Inverting Amplifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7400222 -->
-     <!--l. 336--><p class="noindent" ></div><hr class="endfigure">
-     </li>
-     <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice
-     converter button.<br
-class="newline" />
-     <!--l. 342--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values,
-     Device library and Subcircuit.
-
-     <!--l. 344--><p class="noindent" >Subcircuit of Op-Amp is shown in Fig.&#x00A0;<a
-href="#x1-74006r4">9.23d<!--tex4ht:ref: ia_sub --></a> <hr class="figure"><div class="figure"
-><a
- id="x1-7400723"></a> <a
- id="x1-74003r1"></a> <img
-src="figures/ia_analysistab.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Inverting</span>
-<span
-class="cmr-9">Amplifier</span>
-<span
-class="cmr-9">Analysis</span>                                 <a
- id="x1-74004r2"></a> <img
-src="figures/ia_sourcedetailstab.png" alt="PIC"
->
-                                      <span
-class="cmr-9">(b)</span>
-                                              <span
-class="cmr-9">Inverting</span>
-                                              <span
-class="cmr-9">Amplifier</span>
-                                              <span
-class="cmr-9">Source</span>
-                                              <span
-class="cmr-9">Details</span>
-<a
- id="x1-74005r3"></a>
-<!--l. 355--><p class="noindent" > <img
-src="figures/ia_subcircuitstab.png" alt="PIC"
->
-<span
-class="cmr-9">(c)</span>
-<span
-class="cmr-9">Inverting</span>
-<span
-class="cmr-9">Amplifier</span>
-<span
-class="cmr-9">Subcircuit</span>                                                                  <a
- id="x1-74006r4"></a> <img
-src="figures/ia_sub.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(d)</span>
-                                                                          <span
-class="cmr-9">Sub-Circuit</span>
-                                                                          <span
-class="cmr-9">of</span>
-                                                                          <span
-class="cmr-9">Op-Amp</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.23: </span><span
-class="content">Analysis, Source, and Subcircuit tab</span></div><!--tex4ht:label?: x1-7400723 -->
-     <!--l. 360--><p class="noindent" ></div><hr class="endfigure">
-
-     <!--l. 363--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to
-     add subcircuit, it will throw an error.<br
-class="newline" />
-     </li>
-     <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run
-     simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure"
-><a
- id="x1-7401024"></a> <a
- id="x1-74008r1"></a> <img
-src="figures/ia_ngspiceplot.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Inverting</span>
-<span
-class="cmr-9">Amplifier</span>
-<span
-class="cmr-9">Ngspice</span>
-<span
-class="cmr-9">Plot</span>
-<a
- id="x1-74009r2"></a>
-<!--l. 374--><p class="noindent" > <img
-src="figures/ia_pythonplot.png" alt="PIC"
->
-<span
-class="cmr-9">(b)</span>
-<span
-class="cmr-9">Inverting</span>
-<span
-class="cmr-9">Amplifier</span>
-<span
-class="cmr-9">Python</span>
-<span
-class="cmr-9">Plot</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.24: </span><span
-class="content">Inverting Amplifier Simulation Output</span></div><!--tex4ht:label?: x1-7401024 -->
-     <!--l. 376--><p class="noindent" ></div><hr class="endfigure">
-     </li></ul>
-
-<!--l. 386--><p class="noindent" >
-   <h4 class="subsectionHead"><span class="titlemark">9.1.5   </span> <a
- id="x1-750009.1.5"></a>Half Adder Example</h4>
-<!--l. 388--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-760009.1.5"></a>Problem Statement:</h5>
-<!--l. 388--><p class="noindent" >Plot the Input and Output Waveform of Half Adder circuit.
-<!--l. 390--><p class="noindent" >
-   <h5 class="subsubsectionHead"><a
- id="x1-770009.1.5"></a>Solution:</h5>
-     <ul class="itemize1">
-     <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left
-     toolbar as shown in the Fig.&#x00A0;<a
-href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br
-class="newline" />After the KiCad window is opened, to create a schematic we need to place the
-     required components. Fig.&#x00A0;<a
-href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens
-     the component library.<br
-class="newline" />After all the required components of the Half Adder circuit are placed, wiring is
-     done using the <span
-class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig.&#x00A0;<a
-href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br
-class="newline" />Next step is <span
-class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig.&#x00A0;<a
-href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span
-class="cmtt-10x-x-109">ERC</span>.
-     <!--l. 399--><p class="noindent" >The Fig.&#x00A0;<a
-href="#x1-7700125">9.25<!--tex4ht:ref: ha_schematic --></a> shows the complete Half Adder schematic after removing the
-     errors. <hr class="figure"><div class="figure"
-><a
- id="x1-7700125"></a> <img
-src="figures/ha_schematic.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.25: </span><span
-class="content">Schematic of Half Adder circuit</span></div><!--tex4ht:label?: x1-7700125 -->
-     <!--l. 405--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 407--><p class="noindent" >The KiCad netlist is generated as shown in Fig.&#x00A0;<a
-href="#x1-7700226">9.26<!--tex4ht:ref: ha_netlistgeneration --></a>.<br
-class="newline" /><hr class="figure"><div class="figure"
-><a
- id="x1-7700226"></a> <img
-src="figures/ha_netlistgeneration.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.26: </span><span
-class="content">Half Adder circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7700226 -->
-     <!--l. 413--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist click on KiCad-Ngspice
-     converter button.<br
-class="newline" />
-     <!--l. 420--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values,
-     Ngspice model and Subcircuit.
-     <!--l. 422--><p class="noindent" ><hr class="figure"><div class="figure"
-><a
- id="x1-7700727"></a> <a
- id="x1-77003r1"></a> <img
-src="figures/ha_analysistab.png" alt="PIC"
->
- <span
-class="cmr-9">(a)</span>
- <span
-class="cmr-9">Half</span>
- <span
-class="cmr-9">Adder</span>
- <span
-class="cmr-9">Analysis</span>                                                                                                         <a
- id="x1-77004r2"></a> <img
-src="figures/ha_sourcedetailstab.png" alt="PIC"
->
-                                                                                                   <span
-class="cmr-9">(b)</span>
-                                                                                                                     <span
-class="cmr-9">Half</span>
-                                                                                                                     <span
-class="cmr-9">Adder</span>
-                                                                                                                     <span
-class="cmr-9">Source</span>
-                                                                                                                     <span
-class="cmr-9">Details</span>
-<a
- id="x1-77005r3"></a>
-<!--l. 432--><p class="noindent" > <img
-src="figures/ha_ngspicemodeltab.png" alt="PIC"
->
-<span
-class="cmr-9">(c)</span>
-<span
-class="cmr-9">Half</span>
-<span
-class="cmr-9">Adder</span>
-<span
-class="cmr-9">Ngspice</span>
-<span
-class="cmr-9">Model</span>                                                                     <a
- id="x1-77006r4"></a> <img
-src="figures/ha_subcircuitstab.png" alt="PIC"
->
-                                                                          <span
-class="cmr-9">(d)</span>
-                                                                          <span
-class="cmr-9">Half</span>
-                                                                          <span
-class="cmr-9">Adder</span>
-                                                                          <span
-class="cmr-9">Subcircuit</span>
-                                                                          <span
-class="cmr-9">Model</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.27: </span><span
-class="content">Analysis, Source, Ngspice Model and Subcircuit tab</span></div><!--tex4ht:label?: x1-7700727 -->
-     <!--l. 437--><p class="noindent" ></div><hr class="endfigure">
-     <!--l. 439--><p class="noindent" >Subcircuit of Half Adder in Fig.&#x00A0;<a
-href="#x1-7700828">9.28<!--tex4ht:ref: ha_sub --></a> <hr class="figure"><div class="figure"
-><a
- id="x1-7700828"></a> <img
-src="figures/ha_sub.png" alt="PIC"
->
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.28: </span><span
-class="content">Half Adder Subcircuit</span></div><!--tex4ht:label?: x1-7700828 -->
-     <!--l. 445--><p class="noindent" ></div><hr class="endfigure">
-
-     </li>
-     <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run
-     simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure"
-><a
- id="x1-7701129"></a> <a
- id="x1-77009r1"></a> <img
-src="figures/ha_ngspiceplot.png" alt="PIC"
->
-<span
-class="cmr-9">(a)</span>
-<span
-class="cmr-9">Half</span>
-<span
-class="cmr-9">Adder</span>
-<span
-class="cmr-9">Ngspice</span>
-<span
-class="cmr-9">Plot</span>                 <a
- id="x1-77010r2"></a> <img
-src="figures/ha_pythonplot.png" alt="PIC"
->
-                    <span
-class="cmr-9">(b)</span>
-                        <span
-class="cmr-9">Half</span>
-                        <span
-class="cmr-9">Adder</span>
-                        <span
-class="cmr-9">Python</span>
-                        <span
-class="cmr-9">Plot</span>
-<br /> <div class="caption"
-><span class="id">Figure&#x00A0;9.29: </span><span
-class="content">Half Adder Simulation Output</span></div><!--tex4ht:label?: x1-7701129 -->
-     <!--l. 459--><p class="noindent" ></div><hr class="endfigure">
-     </li></ul>
-
-   <h2 class="likechapterHead"><a
- id="x1-780009.1.5"></a>References</h2><a
- id="Q1-1-166"></a>
-    <div class="thebibliography">
-    <p class="bibitem" ><span class="biblabel">
-  [1]<span class="bibsp">&#x00A0;&#x00A0;&#x00A0;</span></span><a
- id="Xsedra"></a>A.&#x00A0;S.  Sedra  and  K.&#x00A0;C.  Smith,  <span
-class="cmti-10x-x-109">Microelectronic  Circuits  -  Theory  and</span>
-    <span
-class="cmti-10x-x-109">Applications</span>.   Oxford University Press, 2009.
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xkmm11-csi"></a>K.&#x00A0;M. Moudgalya, &#8220;Spoken Tutorial: A Collaborative and Scalable Education
-    Technology,&#8221; <span
-class="cmti-10x-x-109">CSI Communications</span>, vol.&#x00A0;35, no.&#x00A0;6, pp. 10&#8211;12, September 2011,
-    available at <a
-href="http://spoken-tutorial.org/CSI.pdf" class="url" >http://spoken-tutorial.org/CSI.pdf</a>.
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xscilab"></a>(2013, May). [Online]. Available: <a
-href="http://www.scilab.org/" class="url" >http://www.scilab.org/</a>
-    </p>
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- id="XGARUDA"></a>(2013,                     May).                     [Online].                     Available:
-    <a
-href="http://scilab-test.garudaindia.in/scilab_in/,
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-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="XT10KT"></a>D.&#x00A0;B.  Phatak.  (2013,  May)  Teach  10,000  teacher  programme.  [Online].
-    Available: <a
-href="http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do" class="url" >http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
-  [6]<span class="bibsp">&#x00A0;&#x00A0;&#x00A0;</span></span><a
- id="XT10KT-kal"></a>K.&#x00A0;Kannan and K.&#x00A0;Narayanan, &#8220;Ict-enabled scalable workshops for engineering
-    college teachers in india,&#8221; in <span
-class="cmti-10x-x-109">Post-Secondary Education and Technology: A Global</span>
-    <span
-class="cmti-10x-x-109">Perspective on Opportunities and Obstacles to Development (International and</span>
-    <span
-class="cmti-10x-x-109">Development  Education)</span>,  R.&#x00A0;Clohey,  S.&#x00A0;Austin-Li,  and  J.&#x00A0;C.  Weldman,  Eds.
-    Palgrave Macmillan, 2012.
-
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="XT10KT-kgp"></a>(2013, May) Teach 10,000 teacher programme on analog electronics. [Online].
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-href="http://www.nmeict.iitkgp.ernet.in/Analogmain.htm" class="url" >http://www.nmeict.iitkgp.ernet.in/Analogmain.htm</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xaakash"></a>(2013, May). [Online]. Available: <a
-href="http://www.aakashlabs.org/" class="url" >http://www.aakashlabs.org/</a>
-    </p>
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- id="Xeda"></a>(2013,                     May).                     [Online].                     Available:
-    <a
-href="http://en.wikipedia.org/wiki/Electronic_design_automation" class="url" >http://en.wikipedia.org/wiki/Electronic_design_automation</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xsynaptic"></a>(2013, May) Synaptic Package Manager Spoken Tutorial. [Online]. Available:
-    <a
-href="http://www.spoken-tutorial.org/list_videos?view=1&foss=Linux&language=English" class="url" >http://www.spoken-tutorial.org/list_videos?view=1&amp;foss=Linux&amp;language=English</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xeeschema"></a>(2013,                     May).                     [Online].                     Available:
-    <a
-href="http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xngspice-web"></a>(2013, May). [Online]. Available: <a
-href="http://ngspice.sourceforge.net/" class="url" >http://ngspice.sourceforge.net/</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xscilab-in"></a>(2013, May). [Online]. Available: <a
-href="http://scilab.in/" class="url" >http://scilab.in/</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xspice"></a>S.&#x00A0;M.  Sandler  and  C.&#x00A0;Hymowitz,  <span
-class="cmti-10x-x-109">SPICE  Circuit  Handbook</span>.     New  York:
-    McGraw-Hill Professional, 2006.
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xkicad"></a>J.-P.    Charras    and    F.&#x00A0;Tappero.    (2013,    May).    [Online].    Available:
-    <a
-href="http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation</a>
-
-    </p>
-    <p class="bibitem" ><span class="biblabel">
- [16]<span class="bibsp">&#x00A0;&#x00A0;&#x00A0;</span></span><a
- id="Xkicad2"></a>D.&#x00A0;Jahshan    and    P.&#x00A0;Hutchinson.    (2013,    May).    [Online].    Available:
-    <a
-href="http://bazaar.launchpad.net/~kicad-developers/kicad/doc/files/head:/doc/tutorials/" class="url" >http://bazaar.launchpad.net/<span
-class="cmsy-8">&sim;</span>kicad-developers/kicad/doc/files/head:/doc/tutorials/</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
- [17]<span class="bibsp">&#x00A0;&#x00A0;&#x00A0;</span></span><a
- id="Xngspice"></a>P.&#x00A0;Nenzi and H.&#x00A0;Vogt. (2013) Ngspice users manual version 25plus. [Online].
-    Available: <a
-href="http://ngspice.sourceforge.net/docs/ngspice-manual.pdf" class="url" >http://ngspice.sourceforge.net/docs/ngspice-manual.pdf</a>
-    </p>
-    <p class="bibitem" ><span class="biblabel">
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- id="Xkmm11-TUGboat"></a>K.&#x00A0;M. Moudgalya, &#8220;<span class="LATEX">L<span class="A">A</span><span class="TEX">T<span
-class="E">E</span>X</span></span>&#x00A0;Training through Spoken Tutorials,&#8221; <span
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-</p>
-    </div>
-
-</body></html>
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diff --git a/src/browser/pages/welcome.html b/src/browser/pages/welcome.html
deleted file mode 100644
index 6c4a6d11..00000000
--- a/src/browser/pages/welcome.html
+++ /dev/null
@@ -1,55 +0,0 @@
-<html>
-
-<head>
-<style>
-body {
-	font-family: sans-serif;
-	margin: 0px;
-	padding: 0px;
-	background-color: #efefef;
-}
-
-h1{
-	font-weight: bold;
-	font-size: 22pt;
-	color: #eeeeee;
-	padding: 10px;
-	background-color: #165982;
-	border: 4px outset  #0E324B;
-}
-
-p{
-	margin: 0px 10px 0px 10px;
-}
-
-pre{
-	margin: 0px 10px 0px 10px;
-	font-family: monospaced;
-	font-size: 10pt;
-}
-#license{
-	font-size:8pt;
-}
-
-</style>
-<head>
-
-<body>
-<h1>About eSim</h1>
-<center><img src="../../../images/logo.png" alt="eSim logo" height="100" width="100"></center>
-<br/> 
-<p>
-<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>), Ngspice (<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>) and GHDL (<a href=http://ghdl.free.fr/>http://ghdl.free.fr/</a>). eSim source is released under <b>GNU General Public License.</b> 
-</p>
-<br/>
-<p>
-This tool is developed by the <b>FOSSEE team at IIT Bombay</b>. To know more about eSim, please visit: <a href=http://esim.fossee.in>http://esim.fossee.in</a>.
- </p>
-<br/>
-<p>
-To discuss more about eSim please visits at <a href=http://forums.fossee.in>http://forums.fossee.in</a>
-</p>
-<br />
-</body>
-
-</html>
diff --git a/src/deviceModelLibrary/Diode/D.lib b/src/deviceModelLibrary/Diode/D.lib
deleted file mode 100644
index 8a7fb4da..00000000
--- a/src/deviceModelLibrary/Diode/D.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
diff --git a/src/deviceModelLibrary/Diode/D.xml b/src/deviceModelLibrary/Diode/D.xml
deleted file mode 100644
index 8b6b14c8..00000000
--- a/src/deviceModelLibrary/Diode/D.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<library>
-<model_name>D</model_name>
-<ref_model>1N4148</ref_model>
-<param>
-	<Is>2.495E-09</Is>
-	<Rs>4.755E-01</Rs>
-	<N>1.679E+00</N>
-    <tt>3.030E-09</tt>
-	<Cjo>1.700E-12</Cjo>
-	<M>1.959E-01</M>
-	<Vj>1</Vj>
-	<Bv>1.000E+02</Bv>
-	<Ibv>1.000E-04</Ibv>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Diode/LED.lib b/src/deviceModelLibrary/Diode/LED.lib
deleted file mode 100644
index 000831b2..00000000
--- a/src/deviceModelLibrary/Diode/LED.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model LED D(is=4.36625E-25 rs=3.00014 n=1.38167 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
diff --git a/src/deviceModelLibrary/Diode/LED.xml b/src/deviceModelLibrary/Diode/LED.xml
deleted file mode 100644
index 91eb9169..00000000
--- a/src/deviceModelLibrary/Diode/LED.xml
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>D</model_name><ref_model>LED</ref_model><param><cjo>1.700E-12</cjo><rs>4.755E-01</rs><is>2.495E-09</is><m>1.959E-01</m><n>1.679E00</n><bv>1.000E02</bv><ibv>1.000E-04</ibv><tt>3.030E-09</tt><vj>1</vj></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Diode/PowerDiode.lib b/src/deviceModelLibrary/Diode/PowerDiode.lib
deleted file mode 100644
index a2f61dce..00000000
--- a/src/deviceModelLibrary/Diode/PowerDiode.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Diode/PowerDiode.xml b/src/deviceModelLibrary/Diode/PowerDiode.xml
deleted file mode 100644
index 06dceda1..00000000
--- a/src/deviceModelLibrary/Diode/PowerDiode.xml
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>D</model_name><ref_model>PowerDiode</ref_model><param><Vj>.75</Vj><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><bv>1800</bv><Fc>.5</Fc><Ikf>0</Ikf><Nr>2</Nr><Ibv>20.245m</Ibv><Is>2.2E-15</Is><Xti>3</Xti><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.lib b/src/deviceModelLibrary/Diode/ZenerD1N750.lib
deleted file mode 100644
index 890c37fe..00000000
--- a/src/deviceModelLibrary/Diode/ZenerD1N750.lib
+++ /dev/null
@@ -1,3 +0,0 @@
-.model D1N750	D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 
-+ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m 
-+ Nbvl=14.976 Tbv1=-21.277u) 
diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.xml b/src/deviceModelLibrary/Diode/ZenerD1N750.xml
deleted file mode 100644
index 546d1156..00000000
--- a/src/deviceModelLibrary/Diode/ZenerD1N750.xml
+++ /dev/null
@@ -1,24 +0,0 @@
-<library>
-<model_name>D</model_name>
-<ref_model>D1N750</ref_model>
-<param>
-	<Is>880.5E-18</Is>
-	<Rs>.25</Rs>
-	<Ikf>0</Ikf>
-	<N>1</N>
-	<Xti>3</Xti>
-	<Eg>1.11</Eg>
-	<Cjo>175p</Cjo>
-	<M>.5516</M>
-	<Vj>.75</Vj>
-	<Fc>.5</Fc>
-	<Isr>1.859n</Isr>
-	<Nr>2</Nr>
-	<Bv>8.1</Bv>
-	<Ibv>20.245m</Ibv>
-	<Nbv>1.6989</Nbv>
-	<Ibvl>1.9556m</Ibvl>
-	<Nbvl>14.976</Nbvl>
-	<Tbv1>-21.277u</Tbv1>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/IGBT/NIGBT.lib b/src/deviceModelLibrary/IGBT/NIGBT.lib
deleted file mode 100644
index 86cd1b4e..00000000
--- a/src/deviceModelLibrary/IGBT/NIGBT.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.MODEL IXGH40N60 NIGBT(
-+  TAU=287.56E-9
-+  KF=.36047
-+  AREA=37.500E-6
-+  AGD=18.750E-6
-+  KP=50.034
-+  VT=4.1822
-+  CGS=31.942E-9
-+  COXD=53.188E-9
-+  VTD=2.6570
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/IGBT/NIGBT.xml b/src/deviceModelLibrary/IGBT/NIGBT.xml
deleted file mode 100644
index 38d9d094..00000000
--- a/src/deviceModelLibrary/IGBT/NIGBT.xml
+++ /dev/null
@@ -1,4 +0,0 @@
-<library>
-<model_name>NIGBT</model_name>
-<ref_model>IXGH40N60</ref_model>
-<param><TAU>287.56E-9</TAU><KF>.36047</KF><AREA>37.500E-6</AREA><AGD>18.750E-6</AGD><KP>50.034</KP><VT>4.1822</VT><CGS>31.942E-9</CGS><COXD>53.188E-9</COXD><VTD>2.6570</VTD></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/IGBT/PIGBT.lib b/src/deviceModelLibrary/IGBT/PIGBT.lib
deleted file mode 100644
index d4f9e814..00000000
--- a/src/deviceModelLibrary/IGBT/PIGBT.lib
+++ /dev/null
@@ -1,10 +0,0 @@
-.MODEL IXGH40N60 PIGBT (
-+ TAU=287.56E-9
-+ KP=50.034
-+ AREA=37.500E-6
-+ AGD=18.750E-6
-+ VT=4.1822
-+ KF=.36047
-+ CGS=31.942E-9
-+ COXD=53.188E-9
-+ VTD=2.6570)
diff --git a/src/deviceModelLibrary/IGBT/PIGBT.xml b/src/deviceModelLibrary/IGBT/PIGBT.xml
deleted file mode 100644
index 1e57f2e3..00000000
--- a/src/deviceModelLibrary/IGBT/PIGBT.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<library>
-<model_name>PIGBT</model_name>
-<ref_model>IXGH40N60</ref_model>
-<param>
-<TAU>287.56E-9</TAU>
-<KP>50.034</KP>
-<AREA>37.500E-6</AREA>
-<AGD>18.750E-6</AGD>
-<VT>4.1822</VT>
-<KF>.36047</KF>
-<CGS>31.942E-9</CGS>
-<COXD>53.188E-9</COXD>
-<VTD>2.6570 </VTD>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/JFET/NJF.lib b/src/deviceModelLibrary/JFET/NJF.lib
deleted file mode 100644
index dbb2cbae..00000000
--- a/src/deviceModelLibrary/JFET/NJF.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model J2N3819	NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+		Af=1)
diff --git a/src/deviceModelLibrary/JFET/NJF.xml b/src/deviceModelLibrary/JFET/NJF.xml
deleted file mode 100644
index 94753691..00000000
--- a/src/deviceModelLibrary/JFET/NJF.xml
+++ /dev/null
@@ -1,29 +0,0 @@
-<library>
-<model_name>NJF</model_name>
-<ref_model>J2N3819</ref_model>
-<param>
-<Beta>1.304m</Beta>
-<Betatce>-.5</Betatce>
-<Rd>1 </Rd>
-<Rs>1 </Rs>
-<Lambda>2.25m</Lambda> 
-<Vto>-3</Vto>
-<Vtotc>-2.5m</Vtotc>
-<Is>33.57f </Is>
-<Isr>322.4f </Isr>
-<N>1</N>
-<Nr>2</Nr>
-<Xti>3</Xti>
-<Alpha>311.7u</Alpha>
-<Vk>243.6 </Vk>
-<Cgd>1.6p </Cgd>
-<M>.3622 </M>
-<Pb>1</Pb>
-<Fc>.5</Fc>
-<Cgs>2.414p</Cgs>
-<Kf>9.882E-18</Kf>
-<Af>1</Af>
-
-
-</param>
-</library>
diff --git a/src/deviceModelLibrary/JFET/PJF.lib b/src/deviceModelLibrary/JFET/PJF.lib
deleted file mode 100644
index 5589571d..00000000
--- a/src/deviceModelLibrary/JFET/PJF.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-.model J2N3820	PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+		Af=1)
-
diff --git a/src/deviceModelLibrary/JFET/PJF.xml b/src/deviceModelLibrary/JFET/PJF.xml
deleted file mode 100644
index f682f8cb..00000000
--- a/src/deviceModelLibrary/JFET/PJF.xml
+++ /dev/null
@@ -1,27 +0,0 @@
-<library>
-<model_name>PJF</model_name>
-<ref_model>J2N3820</ref_model>
-<param>
-<Beta>1.304m </Beta>
-<Betatce>-.5</Betatce> 
-<Rd>1 </Rd>
-<Rs>1 </Rs>
-<Lambda>2.25m</Lambda> 
-<Vto>-3</Vto>
-<Vtotc>-2.5m </Vtotc>
-<Is>33.57f </Is>
-<Isr>322.4f</Isr> 
-<N>1 </N>
-<Nr>2 </Nr>
-<Xti>3 </Xti>
-<Alpha>311.7u</Alpha>
-<Vk>243.6 </Vk>
-<Cgd>1.6p </Cgd>
-<M>.3622 </M>
-<Pb>1 </Pb>
-<Fc>.5 </Fc>
-<Cgs>2.414p </Cgs>
-<Kf>9.882E-18</Kf>
-<Af>1</Af>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib
deleted file mode 100644
index 2e6f4635..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib
+++ /dev/null
@@ -1,6 +0,0 @@
-.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
-+ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
-+ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
-+ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
-+ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
-+ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.xml b/src/deviceModelLibrary/MOS/NMOS-0.5um.xml
deleted file mode 100644
index 08fdf0e3..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-0.5um.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>mos_n</ref_model>
-<param>
-<TPG>1</TPG>
-<TOX>9.5n </TOX>
-<CJ>550u </CJ>
-<ETA>0.02125 </ETA>
-<VMAX>1.8E05</VMAX>
-<GAMMA>0.62</GAMMA>
-<CGSO>0.3n </CGSO>
-<LD>50n </LD>
-<MJSW>0.35 </MJSW>
-<PB>1.1</PB>
-<CGBO>0.45n </CGBO>
-<XJ>0.2U </XJ>
-<CGDO>0.3n </CGDO>
-<KAPPA>0.1 </KAPPA>
-<LEVEL>3 </LEVEL>
-<VTO>0.6 </VTO>
-<NFS>7.20E11 </NFS>
-<THETA>0.23 </THETA>
-<CJSW>0.3n </CJSW>
-<PHI>0.7 </PHI>
-<RSH>2.0 </RSH>
-<MJ>0.6 </MJ>
-<UO>420</UO>
-<KP>156u </KP>
-<DELTA>0.88</DELTA>
-<NSUB>1.40E17</NSUB>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.lib b/src/deviceModelLibrary/MOS/NMOS-180nm.lib
deleted file mode 100644
index 51e9b119..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-180nm.lib
+++ /dev/null
@@ -1,13 +0,0 @@
-.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
-+            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
-+            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
-+            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
-+            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
-+            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
-+            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
-+            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
-+            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
-+            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
-+            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
-+            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
-+            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.xml b/src/deviceModelLibrary/MOS/NMOS-180nm.xml
deleted file mode 100644
index d0249bb6..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-180nm.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>CMOSN</ref_model>
-<param>
-<LEVEL>8 </LEVEL>
-<VERSION>3.2 </VERSION>
-<TNOM>27 </TNOM>
-<TOX>4.1E-9 </TOX>
-<XJ>1E-7 </XJ>
-<NCH>2.3549E17 </NCH>
-<VTH0>0.3823463 </VTH0>
-<K1>0.5810697 </K1>
-<K2>4.774618E-3 </K2>
-<K3>0.0431669 </K3>
-<K3B>1.1498346</K3B> 
-<W0>1E-7 </W0>
-<NLX>1.910552E-7 </NLX>
-<DVT0W>0 </DVT0W>
-<DVT1W>0 </DVT1W>
-<DVT2W>0 </DVT2W>
-<DVT0>1.2894824 </DVT0>
-<DVT1>0.3622063 </DVT1>
-<DVT2>0.0713729 </DVT2>
-<U0>280.633249 </U0>
-<UA>-1.208537E-9 </UA>
-<UB>2.158625E-18</UB>
-<UC>5.342807E-11 </UC>
-<VSAT>9.366802E4</VSAT>
-<A0>1.7593146 </A0>
-<AGS>0.3939741 </AGS>
-<B0>-6.413949E-9 </B0>
-<B1>-1E-7 </B1>
-<KETA>-5.180424E-4</KETA>
-<A1>0 </A1>
-<A2>1 </A2>
-<RDSW>105.5517558</RDSW> 
-<PRWG>0.5 </PRWG>
-<PRWB>-0.1998871 </PRWB>
-<WR>1 </WR>
-<WINT>7.904732E-10 </WINT>
-<LINT>1.571424E-8 </LINT>
-<XL>0</XL>
-<XW>-1E-8 </XW>
-<DWG>1.297221E-9 </DWG>
-<DWB>1.479041E-9</DWB>
-<VOFF>-0.0955434 </VOFF>
-<NFACTOR>2.4358891 </NFACTOR>
-<CIT>0 </CIT>
-<CDSC>2.4E-4 </CDSC>
-<CDSCD>0</CDSCD>
-<CDSCB>0 </CDSCB>
-<ETA0>=3.104851E-3 </ETA0>
-<ETAB>-2.512384E-5 </ETAB>
-<DSUB>0.0167075 </DSUB>
-<PCLM>0.8073191 </PCLM>
-<PDIBLC1>0.1666161 </PDIBLC1>
-<PDIBLC2>3.112892E-3 </PDIBLC2>
-<PDIBLCB>-0.1 </PDIBLCB>
-<DROUT>0.7875618 </DROUT>
-<PSCBE1>8E10 </PSCBE1>
-<PSCBE2>9.213635E-10 </PSCBE2>
-<PVAG>3.85243E-3 </PVAG>
-<DELTA>0.01 </DELTA>
-<RSH>6.7 </RSH>
-<MOBMOD>1</MOBMOD>
-<PRT>0 </PRT>
-<UTE>-1.5 </UTE>
-<KT1>-0.11 </KT1>
-<KT1L>0 </KT1L>
-<KT2>0.022 </KT2>
-<UA1>4.31E-9 </UA1>
-<UB1>-7.61E-18 </UB1>
-<UC1>-5.6E-11 </UC1>
-<AT>3.3E4 </AT>
-<WL>0 </WL>
-<WLN>1</WLN>
-<WW>0 </WW>
-<WWN>1 </WWN>
-<WWL>0 </WWL>
-<LL>0 </LL>
-<LLN>1 </LLN>
-<LW>0 </LW>
-<LWN>1 </LWN>
-<LWL>0 </LWL>
-<CAPMOD>2 </CAPMOD>
-<XPART>0.5 </XPART>
-<CGDO>7.08E-10 </CGDO>
-<CGSO>7.08E-10 </CGSO>/
-<CGBO>1E-12</CGBO>
-<CJ>9.68858E-4 </CJ>
-<PB>0.8 </PB>
-<MJ>0.3864502 </MJ>
-<CJSW>2.512138E-10 </CJSW>
-<PBSW>0.809286 </PBSW>
-<MJSW>0.1060414 </MJSW>
-<CJSWG>3.3E-10 </CJSWG>
-<PBSWG>0.809286 </PBSWG>
-<MJSWG>0.1060414 </MJSWG>
-<CF>0 </CF>
-<PVTH0>-1.192722E-3 </PVTH0>
-<PRDSW>-5 </PRDSW>
-<PK2>6.450505E-5 </PK2>
-<WKETA>-4.27294E-4 </WKETA>
-<LKETA>-0.0104078 </LKETA>
-<PU0>6.3268729 </PU0>
-<PUA>2.226552E-11 </PUA>
-<PUB>0 </PUB>
-<PVSAT>969.1480157</PVSAT>
-<PETA0>1E-4 </PETA0>
-<PKETA>-1.049509E-3</PKETA>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.lib b/src/deviceModelLibrary/MOS/NMOS-5um.lib
deleted file mode 100644
index a237e1fe..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-5um.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-* 5um technology
-
-.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
-+ Level=1
-+ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.xml b/src/deviceModelLibrary/MOS/NMOS-5um.xml
deleted file mode 100644
index 358fbdbe..00000000
--- a/src/deviceModelLibrary/MOS/NMOS-5um.xml
+++ /dev/null
@@ -1,24 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>mos_n</ref_model>
-<param>
-<Cgso>0.4n</Cgso>
-<Tox>85n</Tox> 
-<Vto>1</Vto>
-<phi>0.7</phi> 
-<Level>1</Level>
-<Mj>.5</Mj>
-<UO>750</UO>
-<Cgdo>0.4n</Cgdo>
-<Gamma>1.4</Gamma>
-<LAMBDA>0.01 </LAMBDA>
-<LD>0.7u </LD>
-<JS>1u </JS>
-<CJ>0.4m</CJ>
-<CJSW>0.8n</CJSW>
-<MJSW>0.5 </MJSW>
-<PB>0.7</PB>
-<CGBO>0.2n</CGBO>
-
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib
deleted file mode 100644
index 848e8b05..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib
+++ /dev/null
@@ -1,6 +0,0 @@
-.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
-+ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
-+ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
-+ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
-+ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
-+ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.xml b/src/deviceModelLibrary/MOS/PMOS-0.5um.xml
deleted file mode 100644
index 013d461c..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-0.5um.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>mos_p</ref_model>
-<param>
-<TPG>-1 </TPG>
-<TOX>9.5n </TOX>
-<CJ>950u </CJ>
-<ETA>0.025 </ETA>
-<VMAX>0.3u </VMAX>
-<GAMMA>0.52 </GAMMA>
-<CGSO>0.35n </CGSO>
-<LD>70n </LD>
-<MJSW>0.25 </MJSW>
-<PB>1 </PB>
-<CGBO>0.45n </CGBO>
-<XJ>0.2U </XJ>
-<CGDO>0.35n </CGDO>
-<KAPPA>8.0 </KAPPA>
-<LEVEL>3 </LEVEL>
-<VTO>-0.6 </VTO>
-<NFS>6.50E11 </NFS>
-<THETA>0.2 </THETA>
-<CJSW>0.2n </CJSW>
-<PHI>0.7 </PHI>
-<RSH>2.5 </RSH>
-<MJ>0.5</MJ>
-<UO>130 </UO>
-<KP>48u </KP>
-<DELTA>0.25 </DELTA>
-<NSUB>1.0E17</NSUB>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.lib b/src/deviceModelLibrary/MOS/PMOS-180nm.lib
deleted file mode 100644
index 032b5b95..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-180nm.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
-+            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
-+            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
-+            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
-+            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
-+            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
-+            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
-+            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
-+            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
-+            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
-+            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.xml b/src/deviceModelLibrary/MOS/PMOS-180nm.xml
deleted file mode 100644
index 6696752d..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-180nm.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>CMOSP</ref_model>
-<param>
-<LEVEL>8 </LEVEL>
-<VERSION>3.2 </VERSION>
-<TNOM>27 </TNOM>
-<TOX>4.1E-9 </TOX>
-<XJ>1E-7 </XJ>
-<NCH>4.1589E17 </NCH>
-<VTH0>-0.3938813 </VTH0>
-<K1>0.5479015</K1>
-<K2>0.0360586 </K2>
-<K3>0.0993095 </K3>
-<K3B>5.7086622</K3B> 
-<W0>1E-6 </W0>
-<NLX>1.313191E-7 </NLX>
-<DVT0W>0 </DVT0W>
-<DVT1W>0 </DVT1W>
-<DVT2W>0 </DVT2W>
-<DVT0>0.4911363</DVT0>
-<DVT1>0.2227356</DVT1>
-<DVT2>0.1 </DVT2>
-<U0>115.6852975 </U0>
-<UA>1.505832E-9</UA> 
-<UB>1E-21 </UB>
-<UC>-1E-10 </UC>
-<VSAT>1.329694E5 </VSAT>
-<A0>1.7590478 </A0>
-<AGS>0.3641621 </AGS>
-<B0>3.427126E-7 </B0>
-<B1>1.062928E-6 </B1>
-<KETA>0.0134667 </KETA>
-<A1>0.6859506 </A1>
-<A2>0.3506788 </A2>
-<RDSW>168.5705677</RDSW>
-<PRWG>0.5 </PRWG>
-<PRWB>-0.4987371 </PRWB>
-<WR>1 </WR>
-<WINT>0 </WINT>
-<LINT>3.028832E-8 </LINT>
-<XL>0 </XL>
-<XW>-1E-8 </XW>
-<DWG>-2.349633E-8 </DWG>
-<DWB>-7.152486E-9 </DWB>
-<VOFF>-0.0994037 </VOFF>
-<NFACTOR>1.9424315 </NFACTOR>
-<CIT>0 </CIT>
-<CDSC>2.4E-4 </CDSC>
-<CDSCD>0 </CDSCD>
-<CDSCB>0 </CDSCB>
-<ETA0>0.0608072 </ETA0>
-<ETAB>-0.0426148</ETAB>
-<DSUB>0.7343015 </DSUB>
-<PCLM>3.2579974 </PCLM>
-<PDIBLC1>7.229527E-6 </PDIBLC1>
-<PDIBLC2>0.025389 </PDIBLC2>
-<PDIBLCB>-1E-3 </PDIBLCB>
-<DROUT>0 </DROUT>
-<PSCBE1>1.454878E10</PSCBE1>
-<PSCBE2>4.202027E-9 </PSCBE2>
-<PVAG>15 </PVAG>
-<DELTA>0.01 </DELTA>
-<RSH>7.8 </RSH>
-<MOBMOD>1 </MOBMOD>
-<PRT>0 </PRT>
-<UTE>-1.5 </UTE>
-<KT1>-0.11 </KT1>
-<KT1L>0 </KT1L>
-<KT2>0.022 </KT2>
-<UA1>4.31E-9</UA1>
-<UB1>-7.61E-18 </UB1>
-<UC1>-5.6E-11 </UC1>
-<AT>3.3E4 </AT>
-<WL>0 </WL>
-<WLN>1 </WLN>
-<WW>0 </WW>
-<WWN>1 </WWN>
-<WWL>0 </WWL>
-<LL>0 </LL>
-<LLN>1 </LLN>
-<LW>0 </LW>
-<LWN>1 </LWN>
-<LWL>0 </LWL>
-<CAPMOD>2 </CAPMOD>
-<XPART>0.5</XPART>
-<CGDO>6.32E-10 </CGDO>
-<CGSO>6.32E-10 </CGSO>
-<CGBO>1E-12 </CGBO>
-<CJ>1.172138E-3 </CJ>
-<PB>0.8421173 </PB>
-<MJ>0.4109788 </MJ>
-<CJSW>2.242609E-10 </CJSW>
-<PBSW>0.8</PBSW>
-<MJSW>0.3752089 </MJSW>
-<CJSWG>4.22E-10 </CJSWG>
-<PBSWG>0.8 </PBSWG>
-<MJSWG>0.3752089 </MJSWG>
-<CF>0 </CF>
-<PVTH0>1.888482E-3 </PVTH0>
-<PRDSW>11.5315407 </PRDSW>
-<PK2>1.559399E-3 </PK2>
-<WKETA>0.0319301 </WKETA>
-<LKETA>2.955547E-3 </LKETA>
-<PU0>-1.1105313 </PU0>
-<PUA>-4.62102E-11</PUA> 
-<PUB>1E-21 </PUB>
-<PVSAT>50 </PVSAT>
-<PETA0>1E-4 </PETA0>
-<PKETA>-4.346368E-3 </PKETA>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.lib b/src/deviceModelLibrary/MOS/PMOS-5um.lib
deleted file mode 100644
index 9c3ed976..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-5um.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-*5um technology
-
-.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
-+ Level=1
-+ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.xml b/src/deviceModelLibrary/MOS/PMOS-5um.xml
deleted file mode 100644
index f68bada2..00000000
--- a/src/deviceModelLibrary/MOS/PMOS-5um.xml
+++ /dev/null
@@ -1,23 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>mos_p</ref_model>
-<param>
-<Cgso>0.4n </Cgso>
-<Tox>85n </Tox>
-<Vto>-1 </Vto>
-<phi>0.65</phi>
-<Level>1</Level>
-<Mj>.5 </Mj>
-<UO>250 </UO>
-<Cgdo>0.4n </Cgdo>
-<Gamma>0.65 </Gamma>
-<LAMBDA>0.03 </LAMBDA>
-<LD>0.6u </LD>
-<JS>1u </JS>
-<CJ>0.18m </CJ>
-<CJSW>0.6n </CJSW>
-<MJSW>0.5 </MJSW>
-<PB>0.7 </PB>
-<CGBO>0.2n</CGBO>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Misc/CORE.lib b/src/deviceModelLibrary/Misc/CORE.lib
deleted file mode 100644
index a7581029..00000000
--- a/src/deviceModelLibrary/Misc/CORE.lib
+++ /dev/null
@@ -1,9 +0,0 @@
-.MODEL K3019PL_3C8 Core(
-+  A=44.82 
-+  C=.4112
-+  abc=123
-+  Area=1.38
-+  K=25.74
-+  MS=415.2K
-+  Path=4.52
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Misc/CORE.xml b/src/deviceModelLibrary/Misc/CORE.xml
deleted file mode 100644
index c95d9db0..00000000
--- a/src/deviceModelLibrary/Misc/CORE.xml
+++ /dev/null
@@ -1,4 +0,0 @@
-<library>
-<model_name>Core</model_name>
-<ref_model>K3019PL_3C8</ref_model>
-<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library>
diff --git a/src/deviceModelLibrary/Templates/CORE.lib b/src/deviceModelLibrary/Templates/CORE.lib
deleted file mode 100644
index a7581029..00000000
--- a/src/deviceModelLibrary/Templates/CORE.lib
+++ /dev/null
@@ -1,9 +0,0 @@
-.MODEL K3019PL_3C8 Core(
-+  A=44.82 
-+  C=.4112
-+  abc=123
-+  Area=1.38
-+  K=25.74
-+  MS=415.2K
-+  Path=4.52
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/CORE.xml b/src/deviceModelLibrary/Templates/CORE.xml
deleted file mode 100644
index c95d9db0..00000000
--- a/src/deviceModelLibrary/Templates/CORE.xml
+++ /dev/null
@@ -1,4 +0,0 @@
-<library>
-<model_name>Core</model_name>
-<ref_model>K3019PL_3C8</ref_model>
-<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library>
diff --git a/src/deviceModelLibrary/Templates/D.lib b/src/deviceModelLibrary/Templates/D.lib
deleted file mode 100644
index 8a7fb4da..00000000
--- a/src/deviceModelLibrary/Templates/D.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
diff --git a/src/deviceModelLibrary/Templates/D.xml b/src/deviceModelLibrary/Templates/D.xml
deleted file mode 100644
index 8b6b14c8..00000000
--- a/src/deviceModelLibrary/Templates/D.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<library>
-<model_name>D</model_name>
-<ref_model>1N4148</ref_model>
-<param>
-	<Is>2.495E-09</Is>
-	<Rs>4.755E-01</Rs>
-	<N>1.679E+00</N>
-    <tt>3.030E-09</tt>
-	<Cjo>1.700E-12</Cjo>
-	<M>1.959E-01</M>
-	<Vj>1</Vj>
-	<Bv>1.000E+02</Bv>
-	<Ibv>1.000E-04</Ibv>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NIGBT.lib b/src/deviceModelLibrary/Templates/NIGBT.lib
deleted file mode 100644
index 8c09dcbc..00000000
--- a/src/deviceModelLibrary/Templates/NIGBT.lib
+++ /dev/null
@@ -1,10 +0,0 @@
-.MODEL IXGH40N60 NIGBT (
-+ TAU=287.56E-9
-+ KP=50.034
-+ AREA=37.500E-6
-+ AGD=18.750E-6
-+ VT=4.1822
-+ KF=.36047
-+ CGS=31.942E-9
-+ COXD=53.188E-9
-+ VTD=2.6570)
diff --git a/src/deviceModelLibrary/Templates/NIGBT.xml b/src/deviceModelLibrary/Templates/NIGBT.xml
deleted file mode 100644
index 97f33196..00000000
--- a/src/deviceModelLibrary/Templates/NIGBT.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<library>
-<model_name>NIGBT</model_name>
-<ref_model>IXGH40N60</ref_model>
-<param>
-<TAU>287.56E-9</TAU>
-<KP>50.034</KP>
-<AREA>37.500E-6</AREA>
-<AGD>18.750E-6</AGD>
-<VT>4.1822</VT>
-<KF>.36047</KF>
-<CGS>31.942E-9</CGS>
-<COXD>53.188E-9</COXD>
-<VTD>2.6570</VTD>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NJF.lib b/src/deviceModelLibrary/Templates/NJF.lib
deleted file mode 100644
index dbb2cbae..00000000
--- a/src/deviceModelLibrary/Templates/NJF.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model J2N3819	NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+		Af=1)
diff --git a/src/deviceModelLibrary/Templates/NJF.xml b/src/deviceModelLibrary/Templates/NJF.xml
deleted file mode 100644
index 94753691..00000000
--- a/src/deviceModelLibrary/Templates/NJF.xml
+++ /dev/null
@@ -1,29 +0,0 @@
-<library>
-<model_name>NJF</model_name>
-<ref_model>J2N3819</ref_model>
-<param>
-<Beta>1.304m</Beta>
-<Betatce>-.5</Betatce>
-<Rd>1 </Rd>
-<Rs>1 </Rs>
-<Lambda>2.25m</Lambda> 
-<Vto>-3</Vto>
-<Vtotc>-2.5m</Vtotc>
-<Is>33.57f </Is>
-<Isr>322.4f </Isr>
-<N>1</N>
-<Nr>2</Nr>
-<Xti>3</Xti>
-<Alpha>311.7u</Alpha>
-<Vk>243.6 </Vk>
-<Cgd>1.6p </Cgd>
-<M>.3622 </M>
-<Pb>1</Pb>
-<Fc>.5</Fc>
-<Cgs>2.414p</Cgs>
-<Kf>9.882E-18</Kf>
-<Af>1</Af>
-
-
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib
deleted file mode 100644
index 2e6f4635..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib
+++ /dev/null
@@ -1,6 +0,0 @@
-.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
-+ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
-+ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
-+ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
-+ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
-+ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.xml b/src/deviceModelLibrary/Templates/NMOS-0.5um.xml
deleted file mode 100644
index 08fdf0e3..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-0.5um.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>mos_n</ref_model>
-<param>
-<TPG>1</TPG>
-<TOX>9.5n </TOX>
-<CJ>550u </CJ>
-<ETA>0.02125 </ETA>
-<VMAX>1.8E05</VMAX>
-<GAMMA>0.62</GAMMA>
-<CGSO>0.3n </CGSO>
-<LD>50n </LD>
-<MJSW>0.35 </MJSW>
-<PB>1.1</PB>
-<CGBO>0.45n </CGBO>
-<XJ>0.2U </XJ>
-<CGDO>0.3n </CGDO>
-<KAPPA>0.1 </KAPPA>
-<LEVEL>3 </LEVEL>
-<VTO>0.6 </VTO>
-<NFS>7.20E11 </NFS>
-<THETA>0.23 </THETA>
-<CJSW>0.3n </CJSW>
-<PHI>0.7 </PHI>
-<RSH>2.0 </RSH>
-<MJ>0.6 </MJ>
-<UO>420</UO>
-<KP>156u </KP>
-<DELTA>0.88</DELTA>
-<NSUB>1.40E17</NSUB>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.lib b/src/deviceModelLibrary/Templates/NMOS-180nm.lib
deleted file mode 100644
index 51e9b119..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-180nm.lib
+++ /dev/null
@@ -1,13 +0,0 @@
-.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
-+            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
-+            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
-+            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
-+            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
-+            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
-+            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
-+            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
-+            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
-+            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
-+            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
-+            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
-+            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.xml b/src/deviceModelLibrary/Templates/NMOS-180nm.xml
deleted file mode 100644
index d0249bb6..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-180nm.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>CMOSN</ref_model>
-<param>
-<LEVEL>8 </LEVEL>
-<VERSION>3.2 </VERSION>
-<TNOM>27 </TNOM>
-<TOX>4.1E-9 </TOX>
-<XJ>1E-7 </XJ>
-<NCH>2.3549E17 </NCH>
-<VTH0>0.3823463 </VTH0>
-<K1>0.5810697 </K1>
-<K2>4.774618E-3 </K2>
-<K3>0.0431669 </K3>
-<K3B>1.1498346</K3B> 
-<W0>1E-7 </W0>
-<NLX>1.910552E-7 </NLX>
-<DVT0W>0 </DVT0W>
-<DVT1W>0 </DVT1W>
-<DVT2W>0 </DVT2W>
-<DVT0>1.2894824 </DVT0>
-<DVT1>0.3622063 </DVT1>
-<DVT2>0.0713729 </DVT2>
-<U0>280.633249 </U0>
-<UA>-1.208537E-9 </UA>
-<UB>2.158625E-18</UB>
-<UC>5.342807E-11 </UC>
-<VSAT>9.366802E4</VSAT>
-<A0>1.7593146 </A0>
-<AGS>0.3939741 </AGS>
-<B0>-6.413949E-9 </B0>
-<B1>-1E-7 </B1>
-<KETA>-5.180424E-4</KETA>
-<A1>0 </A1>
-<A2>1 </A2>
-<RDSW>105.5517558</RDSW> 
-<PRWG>0.5 </PRWG>
-<PRWB>-0.1998871 </PRWB>
-<WR>1 </WR>
-<WINT>7.904732E-10 </WINT>
-<LINT>1.571424E-8 </LINT>
-<XL>0</XL>
-<XW>-1E-8 </XW>
-<DWG>1.297221E-9 </DWG>
-<DWB>1.479041E-9</DWB>
-<VOFF>-0.0955434 </VOFF>
-<NFACTOR>2.4358891 </NFACTOR>
-<CIT>0 </CIT>
-<CDSC>2.4E-4 </CDSC>
-<CDSCD>0</CDSCD>
-<CDSCB>0 </CDSCB>
-<ETA0>=3.104851E-3 </ETA0>
-<ETAB>-2.512384E-5 </ETAB>
-<DSUB>0.0167075 </DSUB>
-<PCLM>0.8073191 </PCLM>
-<PDIBLC1>0.1666161 </PDIBLC1>
-<PDIBLC2>3.112892E-3 </PDIBLC2>
-<PDIBLCB>-0.1 </PDIBLCB>
-<DROUT>0.7875618 </DROUT>
-<PSCBE1>8E10 </PSCBE1>
-<PSCBE2>9.213635E-10 </PSCBE2>
-<PVAG>3.85243E-3 </PVAG>
-<DELTA>0.01 </DELTA>
-<RSH>6.7 </RSH>
-<MOBMOD>1</MOBMOD>
-<PRT>0 </PRT>
-<UTE>-1.5 </UTE>
-<KT1>-0.11 </KT1>
-<KT1L>0 </KT1L>
-<KT2>0.022 </KT2>
-<UA1>4.31E-9 </UA1>
-<UB1>-7.61E-18 </UB1>
-<UC1>-5.6E-11 </UC1>
-<AT>3.3E4 </AT>
-<WL>0 </WL>
-<WLN>1</WLN>
-<WW>0 </WW>
-<WWN>1 </WWN>
-<WWL>0 </WWL>
-<LL>0 </LL>
-<LLN>1 </LLN>
-<LW>0 </LW>
-<LWN>1 </LWN>
-<LWL>0 </LWL>
-<CAPMOD>2 </CAPMOD>
-<XPART>0.5 </XPART>
-<CGDO>7.08E-10 </CGDO>
-<CGSO>7.08E-10 </CGSO>/
-<CGBO>1E-12</CGBO>
-<CJ>9.68858E-4 </CJ>
-<PB>0.8 </PB>
-<MJ>0.3864502 </MJ>
-<CJSW>2.512138E-10 </CJSW>
-<PBSW>0.809286 </PBSW>
-<MJSW>0.1060414 </MJSW>
-<CJSWG>3.3E-10 </CJSWG>
-<PBSWG>0.809286 </PBSWG>
-<MJSWG>0.1060414 </MJSWG>
-<CF>0 </CF>
-<PVTH0>-1.192722E-3 </PVTH0>
-<PRDSW>-5 </PRDSW>
-<PK2>6.450505E-5 </PK2>
-<WKETA>-4.27294E-4 </WKETA>
-<LKETA>-0.0104078 </LKETA>
-<PU0>6.3268729 </PU0>
-<PUA>2.226552E-11 </PUA>
-<PUB>0 </PUB>
-<PVSAT>969.1480157</PVSAT>
-<PETA0>1E-4 </PETA0>
-<PKETA>-1.049509E-3</PKETA>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.lib b/src/deviceModelLibrary/Templates/NMOS-5um.lib
deleted file mode 100644
index a237e1fe..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-5um.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-* 5um technology
-
-.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
-+ Level=1
-+ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.xml b/src/deviceModelLibrary/Templates/NMOS-5um.xml
deleted file mode 100644
index 358fbdbe..00000000
--- a/src/deviceModelLibrary/Templates/NMOS-5um.xml
+++ /dev/null
@@ -1,24 +0,0 @@
-<library>
-<model_name>NMOS</model_name>
-<ref_model>mos_n</ref_model>
-<param>
-<Cgso>0.4n</Cgso>
-<Tox>85n</Tox> 
-<Vto>1</Vto>
-<phi>0.7</phi> 
-<Level>1</Level>
-<Mj>.5</Mj>
-<UO>750</UO>
-<Cgdo>0.4n</Cgdo>
-<Gamma>1.4</Gamma>
-<LAMBDA>0.01 </LAMBDA>
-<LD>0.7u </LD>
-<JS>1u </JS>
-<CJ>0.4m</CJ>
-<CJSW>0.8n</CJSW>
-<MJSW>0.5 </MJSW>
-<PB>0.7</PB>
-<CGBO>0.2n</CGBO>
-
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/NPN.lib b/src/deviceModelLibrary/Templates/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/deviceModelLibrary/Templates/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/deviceModelLibrary/Templates/NPN.xml b/src/deviceModelLibrary/Templates/NPN.xml
deleted file mode 100644
index b2698bb1..00000000
--- a/src/deviceModelLibrary/Templates/NPN.xml
+++ /dev/null
@@ -1,33 +0,0 @@
-<library>
-<model_name>NPN</model_name>
-<ref_model>Q2N2222</ref_model>
-<param>
-<Is>14.34f </Is>
-<Xti>3 </Xti>
-<Eg>1.11 </Eg>
-<Vaf>74.03 </Vaf>
-<Bf>400 </Bf>
-<Ne>1.307 </Ne>
-<Ise>14.34f </Ise>
-<Ikf>.2847 </Ikf>
-<Xtb>1.5 </Xtb>
-<Br>6.092 </Br>
-<Nc>2 </Nc>
-<Isc>0 </Isc>
-<Ikr>0 </Ikr>
-<Rc>1 </Rc>
-<Cjc>7.306p </Cjc>
-<Mjc>.3416 </Mjc>
-<Vjc>.75 </Vjc>
-<Fc>.5 </Fc>
-<Cje>22.01p </Cje>
-<Mje>.377 </Mje>
-<Vje>.75 </Vje>
-<Tr>46.91n </Tr>
-<Tf>411.1p </Tf>
-<Itf>.6 </Itf>
-<Vtf>1.7 </Vtf>
-<Xtf>3 </Xtf>
-<Rb>10 </Rb>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PIGBT.lib b/src/deviceModelLibrary/Templates/PIGBT.lib
deleted file mode 100644
index d4f9e814..00000000
--- a/src/deviceModelLibrary/Templates/PIGBT.lib
+++ /dev/null
@@ -1,10 +0,0 @@
-.MODEL IXGH40N60 PIGBT (
-+ TAU=287.56E-9
-+ KP=50.034
-+ AREA=37.500E-6
-+ AGD=18.750E-6
-+ VT=4.1822
-+ KF=.36047
-+ CGS=31.942E-9
-+ COXD=53.188E-9
-+ VTD=2.6570)
diff --git a/src/deviceModelLibrary/Templates/PIGBT.xml b/src/deviceModelLibrary/Templates/PIGBT.xml
deleted file mode 100644
index 1e57f2e3..00000000
--- a/src/deviceModelLibrary/Templates/PIGBT.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<library>
-<model_name>PIGBT</model_name>
-<ref_model>IXGH40N60</ref_model>
-<param>
-<TAU>287.56E-9</TAU>
-<KP>50.034</KP>
-<AREA>37.500E-6</AREA>
-<AGD>18.750E-6</AGD>
-<VT>4.1822</VT>
-<KF>.36047</KF>
-<CGS>31.942E-9</CGS>
-<COXD>53.188E-9</COXD>
-<VTD>2.6570 </VTD>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PJF.lib b/src/deviceModelLibrary/Templates/PJF.lib
deleted file mode 100644
index 5589571d..00000000
--- a/src/deviceModelLibrary/Templates/PJF.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-.model J2N3820	PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+		Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+		Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+		Af=1)
-
diff --git a/src/deviceModelLibrary/Templates/PJF.xml b/src/deviceModelLibrary/Templates/PJF.xml
deleted file mode 100644
index f682f8cb..00000000
--- a/src/deviceModelLibrary/Templates/PJF.xml
+++ /dev/null
@@ -1,27 +0,0 @@
-<library>
-<model_name>PJF</model_name>
-<ref_model>J2N3820</ref_model>
-<param>
-<Beta>1.304m </Beta>
-<Betatce>-.5</Betatce> 
-<Rd>1 </Rd>
-<Rs>1 </Rs>
-<Lambda>2.25m</Lambda> 
-<Vto>-3</Vto>
-<Vtotc>-2.5m </Vtotc>
-<Is>33.57f </Is>
-<Isr>322.4f</Isr> 
-<N>1 </N>
-<Nr>2 </Nr>
-<Xti>3 </Xti>
-<Alpha>311.7u</Alpha>
-<Vk>243.6 </Vk>
-<Cgd>1.6p </Cgd>
-<M>.3622 </M>
-<Pb>1 </Pb>
-<Fc>.5 </Fc>
-<Cgs>2.414p </Cgs>
-<Kf>9.882E-18</Kf>
-<Af>1</Af>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib
deleted file mode 100644
index 848e8b05..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib
+++ /dev/null
@@ -1,6 +0,0 @@
-.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
-+ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
-+ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
-+ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
-+ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
-+ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.xml b/src/deviceModelLibrary/Templates/PMOS-0.5um.xml
deleted file mode 100644
index 013d461c..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-0.5um.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>mos_p</ref_model>
-<param>
-<TPG>-1 </TPG>
-<TOX>9.5n </TOX>
-<CJ>950u </CJ>
-<ETA>0.025 </ETA>
-<VMAX>0.3u </VMAX>
-<GAMMA>0.52 </GAMMA>
-<CGSO>0.35n </CGSO>
-<LD>70n </LD>
-<MJSW>0.25 </MJSW>
-<PB>1 </PB>
-<CGBO>0.45n </CGBO>
-<XJ>0.2U </XJ>
-<CGDO>0.35n </CGDO>
-<KAPPA>8.0 </KAPPA>
-<LEVEL>3 </LEVEL>
-<VTO>-0.6 </VTO>
-<NFS>6.50E11 </NFS>
-<THETA>0.2 </THETA>
-<CJSW>0.2n </CJSW>
-<PHI>0.7 </PHI>
-<RSH>2.5 </RSH>
-<MJ>0.5</MJ>
-<UO>130 </UO>
-<KP>48u </KP>
-<DELTA>0.25 </DELTA>
-<NSUB>1.0E17</NSUB>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.lib b/src/deviceModelLibrary/Templates/PMOS-180nm.lib
deleted file mode 100644
index 032b5b95..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-180nm.lib
+++ /dev/null
@@ -1,11 +0,0 @@
-.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
-+            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
-+            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
-+            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
-+            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
-+            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
-+            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
-+            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
-+            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
-+            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
-+            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.xml b/src/deviceModelLibrary/Templates/PMOS-180nm.xml
deleted file mode 100644
index 6696752d..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-180nm.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>CMOSP</ref_model>
-<param>
-<LEVEL>8 </LEVEL>
-<VERSION>3.2 </VERSION>
-<TNOM>27 </TNOM>
-<TOX>4.1E-9 </TOX>
-<XJ>1E-7 </XJ>
-<NCH>4.1589E17 </NCH>
-<VTH0>-0.3938813 </VTH0>
-<K1>0.5479015</K1>
-<K2>0.0360586 </K2>
-<K3>0.0993095 </K3>
-<K3B>5.7086622</K3B> 
-<W0>1E-6 </W0>
-<NLX>1.313191E-7 </NLX>
-<DVT0W>0 </DVT0W>
-<DVT1W>0 </DVT1W>
-<DVT2W>0 </DVT2W>
-<DVT0>0.4911363</DVT0>
-<DVT1>0.2227356</DVT1>
-<DVT2>0.1 </DVT2>
-<U0>115.6852975 </U0>
-<UA>1.505832E-9</UA> 
-<UB>1E-21 </UB>
-<UC>-1E-10 </UC>
-<VSAT>1.329694E5 </VSAT>
-<A0>1.7590478 </A0>
-<AGS>0.3641621 </AGS>
-<B0>3.427126E-7 </B0>
-<B1>1.062928E-6 </B1>
-<KETA>0.0134667 </KETA>
-<A1>0.6859506 </A1>
-<A2>0.3506788 </A2>
-<RDSW>168.5705677</RDSW>
-<PRWG>0.5 </PRWG>
-<PRWB>-0.4987371 </PRWB>
-<WR>1 </WR>
-<WINT>0 </WINT>
-<LINT>3.028832E-8 </LINT>
-<XL>0 </XL>
-<XW>-1E-8 </XW>
-<DWG>-2.349633E-8 </DWG>
-<DWB>-7.152486E-9 </DWB>
-<VOFF>-0.0994037 </VOFF>
-<NFACTOR>1.9424315 </NFACTOR>
-<CIT>0 </CIT>
-<CDSC>2.4E-4 </CDSC>
-<CDSCD>0 </CDSCD>
-<CDSCB>0 </CDSCB>
-<ETA0>0.0608072 </ETA0>
-<ETAB>-0.0426148</ETAB>
-<DSUB>0.7343015 </DSUB>
-<PCLM>3.2579974 </PCLM>
-<PDIBLC1>7.229527E-6 </PDIBLC1>
-<PDIBLC2>0.025389 </PDIBLC2>
-<PDIBLCB>-1E-3 </PDIBLCB>
-<DROUT>0 </DROUT>
-<PSCBE1>1.454878E10</PSCBE1>
-<PSCBE2>4.202027E-9 </PSCBE2>
-<PVAG>15 </PVAG>
-<DELTA>0.01 </DELTA>
-<RSH>7.8 </RSH>
-<MOBMOD>1 </MOBMOD>
-<PRT>0 </PRT>
-<UTE>-1.5 </UTE>
-<KT1>-0.11 </KT1>
-<KT1L>0 </KT1L>
-<KT2>0.022 </KT2>
-<UA1>4.31E-9</UA1>
-<UB1>-7.61E-18 </UB1>
-<UC1>-5.6E-11 </UC1>
-<AT>3.3E4 </AT>
-<WL>0 </WL>
-<WLN>1 </WLN>
-<WW>0 </WW>
-<WWN>1 </WWN>
-<WWL>0 </WWL>
-<LL>0 </LL>
-<LLN>1 </LLN>
-<LW>0 </LW>
-<LWN>1 </LWN>
-<LWL>0 </LWL>
-<CAPMOD>2 </CAPMOD>
-<XPART>0.5</XPART>
-<CGDO>6.32E-10 </CGDO>
-<CGSO>6.32E-10 </CGSO>
-<CGBO>1E-12 </CGBO>
-<CJ>1.172138E-3 </CJ>
-<PB>0.8421173 </PB>
-<MJ>0.4109788 </MJ>
-<CJSW>2.242609E-10 </CJSW>
-<PBSW>0.8</PBSW>
-<MJSW>0.3752089 </MJSW>
-<CJSWG>4.22E-10 </CJSWG>
-<PBSWG>0.8 </PBSWG>
-<MJSWG>0.3752089 </MJSWG>
-<CF>0 </CF>
-<PVTH0>1.888482E-3 </PVTH0>
-<PRDSW>11.5315407 </PRDSW>
-<PK2>1.559399E-3 </PK2>
-<WKETA>0.0319301 </WKETA>
-<LKETA>2.955547E-3 </LKETA>
-<PU0>-1.1105313 </PU0>
-<PUA>-4.62102E-11</PUA> 
-<PUB>1E-21 </PUB>
-<PVSAT>50 </PVSAT>
-<PETA0>1E-4 </PETA0>
-<PKETA>-4.346368E-3 </PKETA>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.lib b/src/deviceModelLibrary/Templates/PMOS-5um.lib
deleted file mode 100644
index 9c3ed976..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-5um.lib
+++ /dev/null
@@ -1,5 +0,0 @@
-*5um technology
-
-.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
-+ Level=1
-+ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.xml b/src/deviceModelLibrary/Templates/PMOS-5um.xml
deleted file mode 100644
index f68bada2..00000000
--- a/src/deviceModelLibrary/Templates/PMOS-5um.xml
+++ /dev/null
@@ -1,23 +0,0 @@
-<library>
-<model_name>PMOS</model_name>
-<ref_model>mos_p</ref_model>
-<param>
-<Cgso>0.4n </Cgso>
-<Tox>85n </Tox>
-<Vto>-1 </Vto>
-<phi>0.65</phi>
-<Level>1</Level>
-<Mj>.5 </Mj>
-<UO>250 </UO>
-<Cgdo>0.4n </Cgdo>
-<Gamma>0.65 </Gamma>
-<LAMBDA>0.03 </LAMBDA>
-<LD>0.6u </LD>
-<JS>1u </JS>
-<CJ>0.18m </CJ>
-<CJSW>0.6n </CJSW>
-<MJSW>0.5 </MJSW>
-<PB>0.7 </PB>
-<CGBO>0.2n</CGBO>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Templates/PNP.lib b/src/deviceModelLibrary/Templates/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/deviceModelLibrary/Templates/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/deviceModelLibrary/Templates/PNP.xml b/src/deviceModelLibrary/Templates/PNP.xml
deleted file mode 100644
index 681b3fd9..00000000
--- a/src/deviceModelLibrary/Templates/PNP.xml
+++ /dev/null
@@ -1,33 +0,0 @@
-<library>
-<model_name>PNP</model_name>
-<ref_model>Q2N2907A</ref_model>
-<param>
-<Is>650.6E-18</Is> 
-<Xti>3 </Xti>
-<Eg>1.11 </Eg>
-<Vaf>115.7 </Vaf>
-<Bf>231.7 </Bf>
-<Ne>1.829</Ne>
-<Ise>54.81f </Ise>
-<Ikf>1.079 </Ikf>
-<Xtb>1.5 </Xtb>
-<Br>3.563 </Br>
-<Nc>2 </Nc>
-<Isc>0 </Isc>
-<Ikr>0</Ikr> 
-<Rc>.715</Rc>
-<Cjc>14.76p </Cjc>
-<Mjc>.5383 </Mjc>
-<Vjc>.75 </Vjc>
-<Fc>.5 </Fc>
-<Cje>19.82p </Cje>
-<Mje>.3357 </Mje>
-<Vje>.75</Vje>
-<Tr>111.3n </Tr>
-<Tf>603.7p </Tf>
-<Itf>.65 </Itf>
-<Vtf>5 </Vtf>
-<Xtf>1.7 </Xtf>
-<Rb>10</Rb>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/Transistor/BC547B.lib b/src/deviceModelLibrary/Transistor/BC547B.lib
deleted file mode 100644
index 723537a7..00000000
--- a/src/deviceModelLibrary/Transistor/BC547B.lib
+++ /dev/null
@@ -1 +0,0 @@
-.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14  NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56  RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8)
diff --git a/src/deviceModelLibrary/Transistor/BC547B.xml b/src/deviceModelLibrary/Transistor/BC547B.xml
deleted file mode 100644
index da06e5c4..00000000
--- a/src/deviceModelLibrary/Transistor/BC547B.xml
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>NPN</model_name><ref_model>BC547B</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Isc>0 </Isc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ise>14.34f </Ise><Br>6.092 </Br><Ikf>.2847 </Ikf><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Vjc>.75 </Vjc><Vje>.75 </Vje><Xtf>3 </Xtf><Itf>.6 </Itf><Is>14.34f </Is><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Transistor/NPN.lib b/src/deviceModelLibrary/Transistor/NPN.lib
deleted file mode 100644
index 6509fe7a..00000000
--- a/src/deviceModelLibrary/Transistor/NPN.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/src/deviceModelLibrary/Transistor/NPN.xml b/src/deviceModelLibrary/Transistor/NPN.xml
deleted file mode 100644
index ee2abcbc..00000000
--- a/src/deviceModelLibrary/Transistor/NPN.xml
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>NPN</model_name><ref_model>Q2N2222</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400</Bf><Fc>.5 </Fc><Ikf>.2847 </Ikf><Br>6.092 </Br><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Isc>0 </Isc><Ise>14.34f </Ise><Xtf>3 </Xtf><Vje>.75 </Vje><Is>14.34f </Is><Itf>.6 </Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/Transistor/PNP.lib b/src/deviceModelLibrary/Transistor/PNP.lib
deleted file mode 100644
index 7edda0ea..00000000
--- a/src/deviceModelLibrary/Transistor/PNP.lib
+++ /dev/null
@@ -1,4 +0,0 @@
-.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
-+		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
-+		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
-+		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/src/deviceModelLibrary/Transistor/PNP.xml b/src/deviceModelLibrary/Transistor/PNP.xml
deleted file mode 100644
index 681b3fd9..00000000
--- a/src/deviceModelLibrary/Transistor/PNP.xml
+++ /dev/null
@@ -1,33 +0,0 @@
-<library>
-<model_name>PNP</model_name>
-<ref_model>Q2N2907A</ref_model>
-<param>
-<Is>650.6E-18</Is> 
-<Xti>3 </Xti>
-<Eg>1.11 </Eg>
-<Vaf>115.7 </Vaf>
-<Bf>231.7 </Bf>
-<Ne>1.829</Ne>
-<Ise>54.81f </Ise>
-<Ikf>1.079 </Ikf>
-<Xtb>1.5 </Xtb>
-<Br>3.563 </Br>
-<Nc>2 </Nc>
-<Isc>0 </Isc>
-<Ikr>0</Ikr> 
-<Rc>.715</Rc>
-<Cjc>14.76p </Cjc>
-<Mjc>.5383 </Mjc>
-<Vjc>.75 </Vjc>
-<Fc>.5 </Fc>
-<Cje>19.82p </Cje>
-<Mje>.3357 </Mje>
-<Vje>.75</Vje>
-<Tr>111.3n </Tr>
-<Tf>603.7p </Tf>
-<Itf>.65 </Itf>
-<Vtf>5 </Vtf>
-<Xtf>1.7 </Xtf>
-<Rb>10</Rb>
-</param>
-</library>
diff --git a/src/deviceModelLibrary/User Libraries/IN4002.lib b/src/deviceModelLibrary/User Libraries/IN4002.lib
deleted file mode 100644
index 35beac9e..00000000
--- a/src/deviceModelLibrary/User Libraries/IN4002.lib	
+++ /dev/null
@@ -1,5 +0,0 @@
-***************************************************************************************************************************************
-*SRC=1N4001G;DI_1N4001G;Diodes;Si;  50.0V  1.00A  2.00us   Diodes Inc. Glass Passivated Rectifier
-.MODEL DI_1N4001G D  ( IS=65.4p RS=42.2m BV=50.0 IBV=5.00u
-+ CJO=14.8p  M=0.333 N=1.36 TT=2.88u )
-***************************************************************************************************************************************
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/IN4002.xml b/src/deviceModelLibrary/User Libraries/IN4002.xml
deleted file mode 100644
index e72d83d7..00000000
--- a/src/deviceModelLibrary/User Libraries/IN4002.xml	
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>D</model_name><ref_model>DI_1N4001G</ref_model><param><CJO>14.8p</CJO><RS>42.2m</RS><IS>65.4p</IS><M>0.333</M><N>1.36</N><BV>50.0</BV><TT>2.88u</TT><IBV>5.00u
</IBV></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/ddnpn.lib b/src/deviceModelLibrary/User Libraries/ddnpn.lib
deleted file mode 100644
index 2e46a2f5..00000000
--- a/src/deviceModelLibrary/User Libraries/ddnpn.lib	
+++ /dev/null
@@ -1,29 +0,0 @@
-.MODEL ddnpn NPN(
-+  Vtf=10
-+  Cjc=2p
-+  Nc=2 
-+  Tr=10n
-+  Ne=1.5
-+  Cje=5p
-+  Vjc=.75 
-+  Xtb=1.5 
-+  Rc=0
-+  Tf=1n
-+  Xti=3 
-+  Ikr=0 
-+  Bf=400 
-+  Fc=.5 
-+  Ikf=0
-+  Br=1
-+  Mje=.3333
-+  Mjc=.3333
-+  Vaf=100
-+  Var=100
-+  Isc=0 
-+  Ise=0
-+  Xtf=0
-+  Vje=.75 
-+  Is=10f
-+  Itf=1
-+  Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/ddnpn.xml b/src/deviceModelLibrary/User Libraries/ddnpn.xml
deleted file mode 100644
index 767c1e41..00000000
--- a/src/deviceModelLibrary/User Libraries/ddnpn.xml	
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>NPN</model_name><ref_model>ddnpn</ref_model><param><Vtf>10</Vtf><Cjc>2p</Cjc><Nc>2 </Nc><Tr>10n</Tr><Ne>1.5</Ne><Cje>5p</Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rc>0</Rc><Tf>1n</Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ikf>0</Ikf><Br>1</Br><Mje>.3333</Mje><Mjc>.3333</Mjc><Vaf>100</Vaf><Var>100</Var><Isc>0 </Isc><Ise>0</Ise><Xtf>0</Xtf><Vje>.75 </Vje><Is>10f</Is><Itf>1</Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/ddpnp.lib b/src/deviceModelLibrary/User Libraries/ddpnp.lib
deleted file mode 100644
index b2ab39b1..00000000
--- a/src/deviceModelLibrary/User Libraries/ddpnp.lib	
+++ /dev/null
@@ -1,29 +0,0 @@
-.MODEL ddpnp PNP(
-+  Vtf=10
-+  Cjc=2p
-+  Nc=2 
-+  Tr=10n
-+  Ne=1.5
-+  Cje=5p
-+  Vjc=.75 
-+  Xtb=1.5 
-+  Rc=0
-+  Tf=1n
-+  Xti=3 
-+  Ikr=0
-+  Bf=200
-+  Fc=.5 
-+  Ikf=0
-+  Br=1
-+  Mje=.3333
-+  Mjc=.3333
-+  Vaf=100
-+  Var=100
-+  Isc=0 
-+  Ise=0
-+  Xtf=0
-+  Vje=.75
-+  Is=10f
-+  Itf=1
-+  Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/ddpnp.xml b/src/deviceModelLibrary/User Libraries/ddpnp.xml
deleted file mode 100644
index da0a1608..00000000
--- a/src/deviceModelLibrary/User Libraries/ddpnp.xml	
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>PNP</model_name><ref_model>ddpnp</ref_model><param><Vtf>10</Vtf><Cjc>2p</Cjc><Nc>2 </Nc><Tr>10n</Tr><Ne>1.5</Ne><Cje>5p</Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rc>0</Rc><Tf>1n</Tf><Xti>3 </Xti><Ikr>0</Ikr><Bf>200</Bf><Fc>.5 </Fc><Ikf>0</Ikf><Br>1</Br><Mje>.3333</Mje><Mjc>.3333</Mjc><Vaf>100</Vaf><Var>100</Var><Isc>0 </Isc><Ise>0</Ise><Xtf>0</Xtf><Vje>.75</Vje><Is>10f</Is><Itf>1</Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/emitter.lib b/src/deviceModelLibrary/User Libraries/emitter.lib
deleted file mode 100644
index 3af759f4..00000000
--- a/src/deviceModelLibrary/User Libraries/emitter.lib	
+++ /dev/null
@@ -1,4 +0,0 @@
-.MODEL emitter D(
-+  Is=21.3P
-+  N=1.8
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/emitter.xml b/src/deviceModelLibrary/User Libraries/emitter.xml
deleted file mode 100644
index 4774fb7f..00000000
--- a/src/deviceModelLibrary/User Libraries/emitter.xml	
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>D</model_name><ref_model>emitter</ref_model><param><Is>21.3P</Is><N>1.8</N></param></library>
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/npn_1.lib b/src/deviceModelLibrary/User Libraries/npn_1.lib
deleted file mode 100644
index 4a863e3e..00000000
--- a/src/deviceModelLibrary/User Libraries/npn_1.lib	
+++ /dev/null
@@ -1,29 +0,0 @@
-.model npn_1 NPN(
-+ Vtf=1.7 
-+ Cjc=0.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.5p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=500
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=125
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/pnp_1.lib b/src/deviceModelLibrary/User Libraries/pnp_1.lib
deleted file mode 100644
index c486429f..00000000
--- a/src/deviceModelLibrary/User Libraries/pnp_1.lib	
+++ /dev/null
@@ -1,29 +0,0 @@
-.model pnp_1 PNP(
-+ Vtf=1.7 
-+ Cjc=1.5p
-+ Nc=2 
-+ Tr=46.91n 
-+ Ne=1.307 
-+ Cje=0.3p
-+ Isc=0 
-+ Xtb=1.5 
-+ Rb=250
-+ Rc=1 
-+ Tf=411.1p 
-+ Xti=3 
-+ Ikr=0 
-+ Bf=25
-+ Fc=.5 
-+ Ise=14.34f 
-+ Br=6.092 
-+ Ikf=.2847 
-+ Mje=.377 
-+ Mjc=.3416 
-+ Vaf=74.03 
-+ Vjc=.75 
-+ Vje=.75 
-+ Xtf=3 
-+ Itf=.6 
-+ Is=14.34f 
-+ Eg=1.11 
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/userDiode.lib b/src/deviceModelLibrary/User Libraries/userDiode.lib
deleted file mode 100644
index ef18bb50..00000000
--- a/src/deviceModelLibrary/User Libraries/userDiode.lib	
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL D1N750 D(
-+  Vj=.75
-+  Nbvl=14.976
-+  Cjo=175p
-+  Rs=.25
-+  Isr=1.859n
-+  Eg=1.11
-+  M=.5516
-+  Nbv=1.6989
-+  N=1
-+  Tbv1=-21.277u
-+  Bv=8.1
-+  Fc=.5
-+  Ikf=0
-+  Nr=2
-+  Ibv=20.245m
-+  Is=880.5E-18
-+  Xti=3
-+  Ibvl=1.9556m
-)
\ No newline at end of file
diff --git a/src/deviceModelLibrary/User Libraries/userDiode.xml b/src/deviceModelLibrary/User Libraries/userDiode.xml
deleted file mode 100644
index d8584e1d..00000000
--- a/src/deviceModelLibrary/User Libraries/userDiode.xml	
+++ /dev/null
@@ -1 +0,0 @@
-<library><model_name>D</model_name><ref_model>D1N750</ref_model><param><Is>880.5E-18</Is><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><Bv>8.1</Bv><Fc>.5</Fc><Ikf>0</Ikf><Xti>3</Xti><Nr>2</Nr><Vj>.75</Vj><Ibv>20.245m</Ibv><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file
diff --git a/src/modelParamXML/Analog/aswitch.xml b/src/modelParamXML/Analog/aswitch.xml
deleted file mode 100644
index fe50ecd3..00000000
--- a/src/modelParamXML/Analog/aswitch.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<model>
-<name>aswitch</name>
-<type>Analog</type>
-<node_number>3</node_number>
-<title>Add Parameters for Analog Switch</title>
-<split>1-NV:2-V</split>
-<param>
-	<cntl_off default="0.0">Enter Control OFF value (default=0.0)</cntl_off>
-	<cntl_on default="1.0">Enter Control ON value(default=1.0)</cntl_on>
-	<r_off default="1.0e12">Enter OFF Resistance (default=1.0e12)</r_off>
-	<r_on default="1.0">Enter ON Resistance (default=1.0)</r_on>
-	<log default="TRUE">Enter Log (default=TRUE)</log>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/climit.xml b/src/modelParamXML/Analog/climit.xml
deleted file mode 100644
index 0d1f9c7e..00000000
--- a/src/modelParamXML/Analog/climit.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>climit</name>
-<type>Analog</type>
-<node_number>4</node_number>
-<title>Add Parameters for Controlled Limiter</title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset>
-	<gain default="1.0">Enter value for Gain (default=1.0)</gain>
-	<upper_delta default="0.0">Enter Output Upper Delta (default=0.0)</upper_delta>
-	<lower_delta default="0.0">Enter Output Lower Delta (default=0.0)</lower_delta>
-	<limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range>
-	<fraction default="false">Enter Fraction (default=false)</fraction>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Analog/d_dt.xml b/src/modelParamXML/Analog/d_dt.xml
deleted file mode 100644
index 65494392..00000000
--- a/src/modelParamXML/Analog/d_dt.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<model>
-<name>d_dt</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for Differentiator</title>
-<split>None</split>
-<param>
-	<gain default="1.0">Enter value for Gain (default=1.0)</gain>
-	<out_offset default="0.0">Enter offset for Output (default=0.0)</out_offset>
-	<out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit>
-	<out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit>
-	<limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/divide.xml b/src/modelParamXML/Analog/divide.xml
deleted file mode 100644
index d501ae4e..00000000
--- a/src/modelParamXML/Analog/divide.xml
+++ /dev/null
@@ -1,18 +0,0 @@
-<model>
-<name>divide</name>
-<type>Analog</type>
-<node_number>3</node_number>
-<title>Add Parameters for Multiplier</title>
-<split>None</split>
-<param>
-	<num_offset default="0.0">Enter offset for Numerator (default=0.0)</num_offset>
-	<num_gain default="1.0">Enter gain for Numerator (default=1.0)</num_gain>
-	<den_offset default="0.0">Enter offset for Denominator (default=0.0)</den_offset>
-	<den_gain default="1.0">Enter gain for Denominator (default=1.0)</den_gain>
-	<den_lower_limit default="1.0e-10">Enter Denominator Lower Limit (default=1.0e-10)</den_lower_limit>
-	<den_domain default="1.0e-10">Enter Denominator Domain (default=1.0e-10)</den_domain>
-	<fraction default="false">Enter Fraction (default=false)</fraction>
-	<out_gain default="1.0">Enter gain for output (default=1.0)</out_gain>
-	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/gain.xml b/src/modelParamXML/Analog/gain.xml
deleted file mode 100644
index a8656072..00000000
--- a/src/modelParamXML/Analog/gain.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>gain</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for model Gain</title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for input (default=0.0)</in_offset>
-	<gain vector="1" default="1.0">Enter gain (default=1.0)</gain>
-	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Analog/hyst.xml b/src/modelParamXML/Analog/hyst.xml
deleted file mode 100644
index 56a60c0f..00000000
--- a/src/modelParamXML/Analog/hyst.xml
+++ /dev/null
@@ -1,16 +0,0 @@
-<model>
-<name>hyst</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for Hysteresis</title>
-<split>None</split>
-<param>
-	<in_low default="0.0">Enter Input Low Value (default=0.0)</in_low>
-	<in_high default="1.0">Enter Input High Value (default=1.0)</in_high>
-	<hyst default="0.1">Enter Hysteresis (default=0.1)</hyst>
-	<out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit>
-	<out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit>
-	<input_domain default="0.01">Enter Input Domain Value (default=0.01)</input_domain>
-	<fraction default="TRUE">Enter Fraction (default=TRUE)</fraction>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/ilimit.xml b/src/modelParamXML/Analog/ilimit.xml
deleted file mode 100644
index 32b2149f..00000000
--- a/src/modelParamXML/Analog/ilimit.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<model>
-<name>ilimit</name>
-<type>Analog</type>
-<node_number>4</node_number>
-<title>Add Parameters for Current Limiter </title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset>
-	<gain default="1.0">Enter value for Gain (default=1.0)</gain>
-	<r_out_source default="1.0">Enter value for Sourcing Resistance (default=1.0)</r_out_source>
-	<r_out_sink default="1.0">Enter value for Sinking Resistance (default=1.0)</r_out_sink>
-	<i_limit_source default="1.0e-12">Enter Current Sourcing Limit (default=1.0e-12)</i_limit_source>
-	<i_limit_sink default="1.0e-12">Enter Current Sinking Limit (default=1.0e-12)</i_limit_sink>
-	<v_pwr_range default="1.0e-6">Enter Power Supply Range (default=1.0e-6)</v_pwr_range>
-	<i_source_range default="1.0e-9">Enter Current Sourcing Range (default=1.0e-9)</i_source_range>
-	<i_sink_range default="1.0e-9">Enter Current Sinking Range (default=1.0e-9)</i_sink_range>
-	<r_out_domain default="1.0e-9">Enter Voltage Delta Range (default=1.0e-9)</r_out_domain>	
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/int.xml b/src/modelParamXML/Analog/int.xml
deleted file mode 100644
index 6ccec625..00000000
--- a/src/modelParamXML/Analog/int.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>int</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for int</title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset>
-	<gain default="1.0">Enter value for Gain (default=1.0)</gain>
-	<out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit>
-	<out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit>
-	<limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range>
-	<out_ic default="0.0">Enter Output Initial Condition (default=0.0)</out_ic>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/limit.xml b/src/modelParamXML/Analog/limit.xml
deleted file mode 100644
index c2a1f382..00000000
--- a/src/modelParamXML/Analog/limit.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>limit</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for Limiter</title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset>
-	<gain default="1.0">Enter value for Gain (default=1.0)</gain>
-	<out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit>
-	<out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit>
-	<limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range>
-	<fraction default="false">Enter Fraction (default=false)</fraction>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/mult.xml b/src/modelParamXML/Analog/mult.xml
deleted file mode 100644
index e41463ff..00000000
--- a/src/modelParamXML/Analog/mult.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>mult</name>
-<type>Analog</type>
-<node_number>3</node_number>
-<title>Add Parameters for Multiplier</title>
-<split>2-V:1-NV</split>
-<param>
-	<in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset>
-	<in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain>
-	<out_gain default="1.0">Enter gain for output (default=1.0)</out_gain>
-	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/slew.xml b/src/modelParamXML/Analog/slew.xml
deleted file mode 100644
index 2eafde2d..00000000
--- a/src/modelParamXML/Analog/slew.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>slew</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for slew</title>
-<split>None</split>
-<param>
-	<rise_slope default="1.0e9">Enter Rising Slope Value (default=1.0e9)</rise_slope>
-	<fall_slop default="1.0e9">Enter Falling Slope Value (default=1.0e9)</fall_slop>
-	<range default="0.1">Enter Range (default=0.1)</range>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/summer.xml b/src/modelParamXML/Analog/summer.xml
deleted file mode 100644
index d9856b62..00000000
--- a/src/modelParamXML/Analog/summer.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>summer</name>
-<type>Analog</type>
-<node_number>3</node_number>
-<title>Add Parameters for Summer</title>
-<split>2-V:1-NV</split>
-<param>
-	<in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset>
-	<in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain>
-	<out_gain default="1.0">Enter gain for output (default=1.0)</out_gain>
-	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
-</param>
-</model>
diff --git a/src/modelParamXML/Analog/temp.xml b/src/modelParamXML/Analog/temp.xml
deleted file mode 100644
index 20f00004..00000000
--- a/src/modelParamXML/Analog/temp.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>gain</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameter for model gain</title>
-<split>None</split>
-<param>
-	<in_offset default="0.0">Enter offset for input (default=0.0)</in_offset>
-	<gain vector="2" default="1.0">Enter gain (default=1.0)</gain>
-	<out_offset default="0.0">Enter offset for output (default=0.0)</out_offset>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Analog/zener.xml b/src/modelParamXML/Analog/zener.xml
deleted file mode 100644
index c6e32c36..00000000
--- a/src/modelParamXML/Analog/zener.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<model>
-<name>zener</name>
-<type>Analog</type>
-<node_number>2</node_number>
-<title>Add Parameters for Zener Diode</title>
-<split>None</split>
-<param>
-	<v_breakdown default="5.6">Enter Breakdown Voltage (default=5.6)</v_breakdown>
-	<i_breakdown default="2.0e-2">Enter Breakdown Current (default=2.0e-2)</i_breakdown>
-	<i_sat default="1.0e-12">Enter Saturation Current (default=1.0e-12)</i_sat>
-	<n_forward default="1.0">Enter Forward Emission Coefficient (default=1.0)</n_forward>
-	<limit_switch default="FALSE">Enter Switch for Limiting (default=FALSE)</limit_switch>
-</param>
-</model>
diff --git a/src/modelParamXML/Digital/d_and.xml b/src/modelParamXML/Digital/d_and.xml
deleted file mode 100644
index cd4a1c76..00000000
--- a/src/modelParamXML/Digital/d_and.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_and</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for And Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_buffer.xml b/src/modelParamXML/Digital/d_buffer.xml
deleted file mode 100644
index e0661910..00000000
--- a/src/modelParamXML/Digital/d_buffer.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_buffer</name>
-<type>Digital</type>
-<node_number>2</node_number>
-<title>Add Parameters for Buffer</title>
-<split>None</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_dff.xml b/src/modelParamXML/Digital/d_dff.xml
deleted file mode 100644
index d5010e02..00000000
--- a/src/modelParamXML/Digital/d_dff.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<model>
-<name>d_dff</name>
-<type>Digital</type>
-<node_number>6</node_number>
-<title>Add Parameters for D Flipflop</title>
-<split>None</split>
-<param>
-	<clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load>
-	<clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_dlatch.xml b/src/modelParamXML/Digital/d_dlatch.xml
deleted file mode 100644
index 34e26418..00000000
--- a/src/modelParamXML/Digital/d_dlatch.xml
+++ /dev/null
@@ -1,20 +0,0 @@
-<model>
-<name>d_dlatch</name>
-<type>Digital</type>
-<node_number>6</node_number>
-<title>Add Parameters for D Latch</title>
-<split>None</split>
-<param>
-	<data_delay default ="1.0e-9">Enter Data Delay (default=1.0e-9)</data_delay>
-	<enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load>
-	<enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_fdiv.xml b/src/modelParamXML/Digital/d_fdiv.xml
deleted file mode 100644
index bab4f0d6..00000000
--- a/src/modelParamXML/Digital/d_fdiv.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>d_fdiv</name>
-<type>Digital</type>
-<node_number>2</node_number>
-<title>Add Parameters for Frequency Divider</title>
-<split>None</split>
-<param>
-	<div_factor default ="2">Enter Divide Factor (default=2)</div_factor>
-	<high_cycles default ="1">Enter value for High Cycles (default=1)</high_cycles>
-	<i_count default = "0">Enter Initial Count (default=0)</i_count>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<freq_in_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</freq_in_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_inverter.xml b/src/modelParamXML/Digital/d_inverter.xml
deleted file mode 100644
index e104712a..00000000
--- a/src/modelParamXML/Digital/d_inverter.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_inverter</name>
-<type>Digital</type>
-<node_number>2</node_number>
-<title>Add Parameters for Inverter</title>
-<split>None</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_jkff.xml b/src/modelParamXML/Digital/d_jkff.xml
deleted file mode 100644
index 78ce59cd..00000000
--- a/src/modelParamXML/Digital/d_jkff.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<model>
-<name>d_jkff</name>
-<type>Digital</type>
-<node_number>7</node_number>
-<title>Add Parameters for JK Flipflop</title>
-<split>None</split>
-<param>
-	<clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<jk_load default ="1.0e-12">Enter value for JK Load (default=1.0e-12)</jk_load>
-	<clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_nand.xml b/src/modelParamXML/Digital/d_nand.xml
deleted file mode 100644
index 0041419a..00000000
--- a/src/modelParamXML/Digital/d_nand.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_nand</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Nand Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_nor.xml b/src/modelParamXML/Digital/d_nor.xml
deleted file mode 100644
index 17a60fd5..00000000
--- a/src/modelParamXML/Digital/d_nor.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_nor</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Nor Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_or.xml b/src/modelParamXML/Digital/d_or.xml
deleted file mode 100644
index 8362e1b3..00000000
--- a/src/modelParamXML/Digital/d_or.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_or</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Or Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_pulldown.xml b/src/modelParamXML/Digital/d_pulldown.xml
deleted file mode 100644
index affd1745..00000000
--- a/src/modelParamXML/Digital/d_pulldown.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<model>
-<name>d_pulldown</name>
-<type>Digital</type>
-<node_number>1</node_number>
-<title>Add Parameters for Pulldown</title>
-<split>None</split>
-<param>
-	<load default="1.0e-12">Enter value of Load</load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_pullup.xml b/src/modelParamXML/Digital/d_pullup.xml
deleted file mode 100644
index 1ce491ff..00000000
--- a/src/modelParamXML/Digital/d_pullup.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<model>
-<name>d_pullup</name>
-<type>Digital</type>
-<node_number>1</node_number>
-<title>Add Parameters for Pullup</title>
-<split>None</split>
-<param>
-	<load default="1.0e-12">Enter value of Load</load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_ram.xml b/src/modelParamXML/Digital/d_ram.xml
deleted file mode 100644
index 73074201..00000000
--- a/src/modelParamXML/Digital/d_ram.xml
+++ /dev/null
@@ -1,16 +0,0 @@
-<model>
-<name>d_ram</name>
-<type>Digital</type>
-<node_number>5</node_number>
-<title>Add Parameters for RAM</title>
-<split>4-V:4-V:8-V:1-NV:3-V</split>
-<param>
-	<select_value default ="1">Enter Select Value (default=1)</select_value>
-	<ic default ="2">Enter IC (default=2)</ic>
-	<read_delay default ="100.0e-9">Enter Read Delay (default=100.0e-9)</read_delay>
-	<data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load>
-	<address_load default ="1.0e-12">Enter value for Address Load (default=1.0e-12)</address_load>
-	<select_load default ="1.0e-12">Enter value for Select Load (default=1.0e-12)</select_load>
-	<enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_source.xml b/src/modelParamXML/Digital/d_source.xml
deleted file mode 100644
index 9bd4347c..00000000
--- a/src/modelParamXML/Digital/d_source.xml
+++ /dev/null
@@ -1,11 +0,0 @@
-<model>
-<name>d_source</name>
-<type>Digital</type>
-<node_number>1</node_number>
-<title>Add Parameters for Digital Source</title>
-<split>4-V</split>
-<param>
-	<input_file default ="source.txt">Enter Input File (default=source.txt)</input_file>
-	<input_load default ="1.0e-12">Enter Input Load</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_srff.xml b/src/modelParamXML/Digital/d_srff.xml
deleted file mode 100644
index 9eb65175..00000000
--- a/src/modelParamXML/Digital/d_srff.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<model>
-<name>d_srff</name>
-<type>Digital</type>
-<node_number>7</node_number>
-<title>Add Parameters for SR Flipflop</title>
-<split>None</split>
-<param>
-	<clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load>
-	<clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_srlatch.xml b/src/modelParamXML/Digital/d_srlatch.xml
deleted file mode 100644
index 35dbc061..00000000
--- a/src/modelParamXML/Digital/d_srlatch.xml
+++ /dev/null
@@ -1,20 +0,0 @@
-<model>
-<name>d_srlatch</name>
-<type>Digital</type>
-<node_number>7</node_number>
-<title>Add Parameters for SR Latch</title>
-<split>None</split>
-<param>
-	<sr_delay default ="1.0e-9">Enter SR Delay (default=1.0e-9)</sr_delay>
-	<enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load>
-	<enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_state.xml b/src/modelParamXML/Digital/d_state.xml
deleted file mode 100644
index 2290a117..00000000
--- a/src/modelParamXML/Digital/d_state.xml
+++ /dev/null
@@ -1,16 +0,0 @@
-<model>
-<name>d_state</name>
-<type>Digital</type>
-<node_number>4</node_number>
-<title>Add Parameters for State Machine</title>
-<split>4-V:2-NV:8-V</split>
-<param>
-	<clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay>
-	<reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0e-9)</reset_delay>
-	<state_file default ="state.txt">Enter State File (default=state.txt)</state_file>
-	<reset_state default ="0">Enter Reset Value (default=0)</reset_state>
-	<input_load default ="1.0e-12">Enter value for Input Load (default=1.0e-12)</input_load>
-	<clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_tff.xml b/src/modelParamXML/Digital/d_tff.xml
deleted file mode 100644
index ed519d2c..00000000
--- a/src/modelParamXML/Digital/d_tff.xml
+++ /dev/null
@@ -1,19 +0,0 @@
-<model>
-<name>d_tff</name>
-<type>Digital</type>
-<node_number>6</node_number>
-<title>Add Parameters for T Flipflop</title>
-<split>None</split>
-<param>
-	<clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay>
-	<set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay>
-	<reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay>
-	<ic default ="0">Enter IC (default=0)</ic>
-	<t_load default ="1.0e-12">Enter value for T Load (default=1.0e-12)</t_load>
-	<clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load>
-	<set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load>
-	<reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_tristate.xml b/src/modelParamXML/Digital/d_tristate.xml
deleted file mode 100644
index 2835da30..00000000
--- a/src/modelParamXML/Digital/d_tristate.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_tristate</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Tristate Buffer</title>
-<split>None</split>
-<param>
-	<delay default ="1.0e-9">Enter Delay (default=1.0e-9)</delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-	<enable_load default ="1.0e-12">Enter Enable Load (default=1.0e-12)</enable_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_xnor.xml b/src/modelParamXML/Digital/d_xnor.xml
deleted file mode 100644
index 4b27bc4c..00000000
--- a/src/modelParamXML/Digital/d_xnor.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_xnor</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Xnor Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Digital/d_xor.xml b/src/modelParamXML/Digital/d_xor.xml
deleted file mode 100644
index ab238c6d..00000000
--- a/src/modelParamXML/Digital/d_xor.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<model>
-<name>d_xor</name>
-<type>Digital</type>
-<node_number>3</node_number>
-<title>Add Parameters for Xor Gate</title>
-<split>2-V:1-NV</split>
-<param>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-	<input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_1.xml b/src/modelParamXML/Hybrid/adc_bridge_1.xml
deleted file mode 100644
index 8d84cd01..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_1.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>1-V:1-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
diff --git a/src/modelParamXML/Hybrid/adc_bridge_2.xml b/src/modelParamXML/Hybrid/adc_bridge_2.xml
deleted file mode 100644
index 1e0ced95..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_2.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>2-V:2-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_3.xml b/src/modelParamXML/Hybrid/adc_bridge_3.xml
deleted file mode 100644
index 09d41850..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_3.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>3-V:3-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_4.xml b/src/modelParamXML/Hybrid/adc_bridge_4.xml
deleted file mode 100644
index b29201f5..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_4.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>4-V:4-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_5.xml b/src/modelParamXML/Hybrid/adc_bridge_5.xml
deleted file mode 100644
index bdacf1db..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_5.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>5-V:5-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_6.xml b/src/modelParamXML/Hybrid/adc_bridge_6.xml
deleted file mode 100644
index ee60247f..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_6.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>6-V:6-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_7.xml b/src/modelParamXML/Hybrid/adc_bridge_7.xml
deleted file mode 100644
index df96b366..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_7.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>7-V:7-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/adc_bridge_8.xml b/src/modelParamXML/Hybrid/adc_bridge_8.xml
deleted file mode 100644
index cdd7afaa..00000000
--- a/src/modelParamXML/Hybrid/adc_bridge_8.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<model>
-<name>adc_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for ADC</title>
-<split>8-V:8-V</split>
-<param>
-	<in_low default ="1.0">Enter value for in_low (default=1.0)</in_low>
-	<in_high default ="2.0">Enter value for in_high (default=2.0)</in_high>
-	<rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay>
-	<fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_1.xml b/src/modelParamXML/Hybrid/dac_bridge_1.xml
deleted file mode 100644
index c9e4eed1..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_1.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>1-V:1-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
diff --git a/src/modelParamXML/Hybrid/dac_bridge_2.xml b/src/modelParamXML/Hybrid/dac_bridge_2.xml
deleted file mode 100644
index c67b22bf..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_2.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>2-V:2-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_3.xml b/src/modelParamXML/Hybrid/dac_bridge_3.xml
deleted file mode 100644
index d080f94d..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_3.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>3-V:3-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_4.xml b/src/modelParamXML/Hybrid/dac_bridge_4.xml
deleted file mode 100644
index 988b575a..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_4.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>4-V:4-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_5.xml b/src/modelParamXML/Hybrid/dac_bridge_5.xml
deleted file mode 100644
index 39d8f2d2..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_5.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>5-V:5-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_6.xml b/src/modelParamXML/Hybrid/dac_bridge_6.xml
deleted file mode 100644
index 2016f971..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_6.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>6-V:6-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_7.xml b/src/modelParamXML/Hybrid/dac_bridge_7.xml
deleted file mode 100644
index 37fb936b..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_7.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>7-V:7-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Hybrid/dac_bridge_8.xml b/src/modelParamXML/Hybrid/dac_bridge_8.xml
deleted file mode 100644
index 72644ad9..00000000
--- a/src/modelParamXML/Hybrid/dac_bridge_8.xml
+++ /dev/null
@@ -1,15 +0,0 @@
-<model>
-<name>dac_bridge</name>
-<type>Hybrid</type>
-<node_number>2</node_number>
-<title>Add Parameters for DAC</title>
-<split>8-V:8-V</split>
-<param>
-	<out_low default ="0.0">Enter value for out_low (default=0.0)</out_low>
-	<out_high default ="5.0">Enter value for out_high (default=5.0)</out_high>
-	<out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef>
-	<input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load>
-	<t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise>
-	<t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall>
-</param>
-</model>
\ No newline at end of file
diff --git a/src/modelParamXML/Nghdl/.gitignore b/src/modelParamXML/Nghdl/.gitignore
deleted file mode 100644
index 86d0cb27..00000000
--- a/src/modelParamXML/Nghdl/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-# Ignore everything in this directory
-*
-# Except this file
-!.gitignore
\ No newline at end of file
diff --git a/src/ngspicetoModelica/Mapping.json b/src/ngspicetoModelica/Mapping.json
deleted file mode 100644
index e254d66a..00000000
--- a/src/ngspicetoModelica/Mapping.json
+++ /dev/null
@@ -1,281 +0,0 @@
-{
-	"Components":{
-				"R" : "Analog.Basic.Resistor",
-				"C" : "Analog.Basic.Capacitor",
-				"L" : "Analog.Basic.Inductor",
-				"e" : "Analog.Basic.VCV",
-				"g" : "Analog.Basic.VCC",
-				"f" : "Analog.Basic.CCC",
-				"h" : "Analog.Basic.CCV",
-				"0" : "Analog.Basic.Ground",
-				"gnd" : "Analog.Basic.Ground"
-
-		},
-	"Sources":{
-		"v":{
-			"pulse":"Analog.Sources.TrapezoidVoltage",
-			"sine":"Analog.Sources.SineVoltage",
-			"pwl" : "Analog.Sources.TableVoltage",
-			"dc" : "Analog.Sources.ConstantVoltage"
-		},
-
-		"i":{
-			"dc":"Analog.Sources.ConstantCurrent"
-		}
-		
-		},
-	"Devices":{
-		"d":{
-			"import":"Analog.Semiconductors.Diode",
-			"mapping":{
-
-				"is":"Ids"
-			},
-			"default":{
-				"Ids":"880.5e-18",
-				"Vt":"0.025",
-				"R":"1e12"
-			}
-
-		},
-
-		"m":{
-			"import":"BondLib.Electrical.Analog.Spice",
-			"mapping":{
-				"tnom":"Tnom",
-				"vto":"VT0",
-				"gamma":"GAMMA",
-				"phi":"PHI",
-				"ld":"LD",
-				"uo":"U0",
-				"lambda":"LAMBDA",
-				"tox":"TOX",
-				"pb":"PB",
-				"cj":"CJ",
-				"cjsw":"CJSW",
-				"mj":"MJ",
-				"mjsw":"MJSW",
-				"cgdo":"CGD0",
-				"js":"JS",
-				"cgbo":"CGB0",
-				"cgso":"CGS0"
-				
-			
-			},
-			"default":{
-				"Tnom":"300",
-				"VT0":"0",
-				"GAMMA":"0",
-				"PHI":"0",
-				"LD":"0",
-				"U0":"0",
-				"LAMBDA":"0",
-				"TOX":"3e-9",
-				"PB":"0.8",
-				"CJ":"0",
-				"CJSW":"1e-9",
-				"MJ":"0.33",
-				"MJSW":"0.33",
-				"CGD0":"0",
-				"JS":"0",
-				"CGB0":"0",
-				"CGS0":"0"
-
-
-			}
-
-		},	
-		"q":{
-			"import":"Analog.Semiconductors",
-			"mapping":{
-				"bf":"Bf",
-				"br":"Br",
-				"is":"Is",
-				"vak":"Vak",
-				"tf":"Tauf",
-				"tr":"Taur",
-				"cjs":"Ccs",
-				"cje":"Cje",
-				"cjc":"Cjc",
-				"vje":"Phie",
-				"mje":"Me",
-				"vjc":"Phic",
-				"mjc":"Mc"
-			},
-			"default":{
-				"Bf":"50",
-				"Br":"0.1",
-				"Is":"1e-16",
-				"Tauf":"1.2e-10",
-				"Taur":"5e-9",
-				"Vak":"0.02",
-				"Ccs":"1e-12",
-				"Cje":"4e-12",
-				"Cjc":"5e-13",
-				"Phie":"0.8",
-				"Me":"0.4",
-				"Phic":"0.8",
-				"Mc":"0.333"
-
-			}
-
-		},
-
-		 "j":{
-			"import":"Spice3.Internal.JFET",
-			"mapping":{
-				"kf":"KF",
-				"rs":"RS",
-				"is":"IS",
-				"cgd":"CGD",
-				"vto":"VTO",
-				"rd":"RD",
-				"pb":"PB",
-				"beta":"BETA",
-				"fc":"FC",
-				"af":"AF",
-				"cgs":"CGS",
-				"lambda":"LAMBDA",
-			    "b" : "B"
-					
-			},
-
-			"default":{
-				"KF":"0",
-				"RS":"0",
-				"IS":"1e-14",
-				"CGD":"0",
-				"VTO":"-2",
-				"RD":"0",
-				"PB":"1",
-				"BETA":"1e-4",
-				"FC":"0.5",
-				"AF":"1",
-				"CGS":"0",
-				"LAMBDA":"0",
-				"B":"1"
-
-
-			}
-		}
-
-		},
-	
-
-	"Models":{
-		"zener":{
-			"import":"Analog.Semiconductors.ZDiode",
-			"mapping":{
-				"v_breakdown":"Bv",
-				"i_breakdown":"Ibv",
-				"i_sat":"Ids",
-				"n_forward":"Nbv"
-
-			},
-			"default":{
-				"Ids":"880.5e-18",
-				"Vt":"0.025",
-				"R":"1e12",
-				"Bv":"8.1",
-				"Ibv":"0.020245",
-				"Nbv":"1.6989"
-
-			}
-
-		}
-	},
-	
-	"Units":{
-		"k":"e3",
-		"u":"e-6",
-		"p":"e-12",
-		"t":"e12",
-        "f":"e-15",
-		"g":"e9",
-		"m":"e-3",
-		"meg":"e6",
-		"n":"e-9",
-		
-        "v":"",
-        "a":"",
-        "s":"",
-        "hz":"",
-        "ohm":"",
-        "mho":"",
-        "h":"",
-
-
-        "kv":"e3",
-        "ka":"e3",
-        "ks":"e3",
-        "khz":"e3",
-        "kohm":"e3",
-        "kmho":"e3",
-        "kh":"e3",
-       
-        
-         "uv":"e-06",
-        "ua":"e-06",
-        "us":"e-06",
-        "uhz":"e-06",
-        "uohm":"e-06",
-        "umho":"e-06",
-        "uh":"e-06",
-       
-        "pv":"e-12",
-        "pa":"e-12",
-        "ps":"e-12",
-        "phz":"e-12",
-        "pohm":"e-12",
-        "pmho":"e-12",
-        "ph":"e-12",
-       
-        
-        "tv":"e12",
-        "ta":"e12",
-        "ts":"e12",
-        "thz":"e12",
-        "tohm":"e12",
-        "tmho":"e12",
-        "th":"e12",
-        
-        
-        "gv":"e9",
-        "ga":"e9",
-        "gs":"e9",
-        "ghz":"e9",
-        "gohm":"e9",
-        "gmho":"e9",
-        "gh":"e9",
-      
-        
-        "mv":"e-03",
-        "ma":"e-03",
-        "ms":"e-03",
-        "mhz":"e-03",
-        "mohm":"e-03",
-        "mmho":"e-03",
-        "mh":"e-03",
-     
-
-        "megv":"e06",
-        "mega":"e06",
-        "megs":"e06",
-        "meghz":"e06",
-        "megohm":"e06",
-        "megmho":"e06",
-        "megh":"e06",
-        
- 
-          
-        "nv":"e-09",
-        "na":"e-09",
-        "ns":"e-09",
-        "nhz":"e-09",
-        "nohm":"e-09",
-        "nmho":"e-09",
-        "nh":"e-09"
-        
-	}
-	
-}
diff --git a/src/supportFiles/fp-lib-table b/src/supportFiles/fp-lib-table
deleted file mode 100644
index ff605eaf..00000000
--- a/src/supportFiles/fp-lib-table
+++ /dev/null
@@ -1,92 +0,0 @@
-(fp_lib_table
-  (lib (name Battery_Holders)(type KiCad)(uri ${KISYSMOD}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders"))
-  (lib (name Buttons_Switches_SMD)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount"))
-  (lib (name Buttons_Switches_THT)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole"))
-  (lib (name Buzzers_Beepers)(type KiCad)(uri ${KISYSMOD}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices"))
-  (lib (name Capacitors_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount"))
-  (lib (name Capacitors_Tantalum_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount"))
-  (lib (name Capacitors_THT)(type KiCad)(uri ${KISYSMOD}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole"))
-  (lib (name Connectors_Card)(type KiCad)(uri ${KISYSMOD}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders"))
-  (lib (name Connectors_Harwin)(type KiCad)(uri ${KISYSMOD}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com"))
-  (lib (name Connectors_HDMI)(type KiCad)(uri ${KISYSMOD}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints"))
-  (lib (name Connectors_Hirose)(type KiCad)(uri ${KISYSMOD}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com"))
-  (lib (name Connectors_IEC_DIN)(type KiCad)(uri ${KISYSMOD}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints"))
-  (lib (name Connectors_JAE)(type KiCad)(uri ${KISYSMOD}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors"))
-  (lib (name Connectors_JST)(type KiCad)(uri ${KISYSMOD}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com"))
-  (lib (name Connectors_Mini-Universal)(type KiCad)(uri ${KISYSMOD}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok))
-  (lib (name Connectors_Molex)(type KiCad)(uri ${KISYSMOD}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com"))
-  (lib (name Connectors_Multicomp)(type KiCad)(uri ${KISYSMOD}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints"))
-  (lib (name Connectors_Phoenix)(type KiCad)(uri ${KISYSMOD}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints"))
-  (lib (name Connectors_Samtec)(type KiCad)(uri ${KISYSMOD}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints"))
-  (lib (name Connectors_TE-Connectivity)(type KiCad)(uri ${KISYSMOD}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com"))
-  (lib (name Connectors_Terminal_Blocks)(type KiCad)(uri ${KISYSMOD}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors"))
-  (lib (name Connectors_WAGO)(type KiCad)(uri ${KISYSMOD}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com"))
-  (lib (name Connectors_USB)(type KiCad)(uri ${KISYSMOD}/Connectors_USB.pretty)(options "")(descr "USB connector footprints"))
-  (lib (name Connectors)(type KiCad)(uri ${KISYSMOD}/Connectors.pretty)(options "")(descr "Assorted connector footprints"))
-  (lib (name Converters_DCDC_ACDC)(type KiCad)(uri ${KISYSMOD}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules"))
-  (lib (name Crystals)(type KiCad)(uri ${KISYSMOD}/Crystals.pretty)(options "")(descr "Crystals and oscillators"))
-  (lib (name Diodes_SMD)(type KiCad)(uri ${KISYSMOD}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount"))
-  (lib (name Diodes_THT)(type KiCad)(uri ${KISYSMOD}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole"))
-  (lib (name Displays_7-Segment)(type KiCad)(uri ${KISYSMOD}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays"))
-  (lib (name Displays)(type KiCad)(uri ${KISYSMOD}/Displays.pretty)(options "")(descr "Display modules"))
-  (lib (name Enclosures)(type KiCad)(uri ${KISYSMOD}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings"))
-  (lib (name EuroBoard_Outline)(type KiCad)(uri ${KISYSMOD}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed"))
-  (lib (name Fiducials)(type KiCad)(uri ${KISYSMOD}/Fiducials.pretty)(options "")(descr "Fiducial markings"))
-  (lib (name Fuse_Holders_and_Fuses)(type KiCad)(uri ${KISYSMOD}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders"))
-  (lib (name Hall-Effect_Transducers_LEM)(type KiCad)(uri ${KISYSMOD}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers"))
-  (lib (name Heatsinks)(type KiCad)(uri ${KISYSMOD}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products"))
-  (lib (name Housings_BGA)(type KiCad)(uri ${KISYSMOD}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)"))
-  (lib (name Housings_CSP)(type KiCad)(uri ${KISYSMOD}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)"))
-  (lib (name Housings_DFN_QFN)(type KiCad)(uri ${KISYSMOD}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN"))
-  (lib (name Housings_DIP)(type KiCad)(uri ${KISYSMOD}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP"))
-  (lib (name Housings_LCC)(type KiCad)(uri ${KISYSMOD}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)"))
-  (lib (name Housings_LGA)(type KiCad)(uri ${KISYSMOD}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)"))
-  (lib (name Housings_PGA)(type KiCad)(uri ${KISYSMOD}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)"))
-  (lib (name Housings_QFP)(type KiCad)(uri ${KISYSMOD}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)"))
-  (lib (name Housings_SIP)(type KiCad)(uri ${KISYSMOD}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)"))
-  (lib (name Housings_SOIC)(type KiCad)(uri ${KISYSMOD}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)"))
-  (lib (name Housings_SON)(type KiCad)(uri ${KISYSMOD}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)"))
-  (lib (name Housings_SSOP)(type KiCad)(uri ${KISYSMOD}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages"))
-  (lib (name Inductors_SMD)(type KiCad)(uri ${KISYSMOD}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount"))
-  (lib (name Inductors_THT)(type KiCad)(uri ${KISYSMOD}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole"))
-  (lib (name IR-DirectFETs)(type KiCad)(uri ${KISYSMOD}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier"))
-  (lib (name LEDs)(type KiCad)(uri ${KISYSMOD}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)"))
-  (lib (name Measurement_Points)(type KiCad)(uri ${KISYSMOD}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment"))
-  (lib (name Measurement_Scales)(type KiCad)(uri ${KISYSMOD}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges"))
-  (lib (name Microwave)(type KiCad)(uri ${KISYSMOD}/Microwave.pretty)(options "")(descr Microwave))
-  (lib (name Modules)(type KiCad)(uri ${KISYSMOD}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module"))
-  (lib (name Mounting_Holes)(type KiCad)(uri ${KISYSMOD}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners"))
-  (lib (name Opto-Devices)(type KiCad)(uri ${KISYSMOD}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices"))
-  (lib (name Oscillators)(type KiCad)(uri ${KISYSMOD}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules"))
-  (lib (name PFF_PSF_PSS_Leadforms)(type KiCad)(uri ${KISYSMOD}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages"))
-  (lib (name Pin_Headers)(type KiCad)(uri ${KISYSMOD}/Pin_Headers.pretty)(options "")(descr "Male pin headers"))
-  (lib (name Potentiometers)(type KiCad)(uri ${KISYSMOD}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors"))
-  (lib (name Power_Integrations)(type KiCad)(uri ${KISYSMOD}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints"))
-  (lib (name Relays_SMD)(type KiCad)(uri ${KISYSMOD}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages"))
-  (lib (name Relays_THT)(type KiCad)(uri ${KISYSMOD}/Relays_THT.pretty)(options "")(descr "Through hole relay packages"))
-  (lib (name Resistors_SMD)(type KiCad)(uri ${KISYSMOD}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount"))
-  (lib (name Resistors_THT)(type KiCad)(uri ${KISYSMOD}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole"))
-  (lib (name Resistors_Universal)(type KiCad)(uri ${KISYSMOD}/Resistors_Universal.pretty)(options "")(descr Experimental))
-  (lib (name RF_Antennas)(type KiCad)(uri ${KISYSMOD}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints"))
-  (lib (name RF_Modules)(type KiCad)(uri ${KISYSMOD}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules"))
-  (lib (name Shielding_Cabinets)(type KiCad)(uri ${KISYSMOD}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields"))
-  (lib (name SMD_Packages)(type KiCad)(uri ${KISYSMOD}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries"))
-  (lib (name Socket_Strips)(type KiCad)(uri ${KISYSMOD}/Socket_Strips.pretty)(options "")(descr "Female socket strips"))
-  (lib (name Sockets)(type KiCad)(uri ${KISYSMOD}/Sockets.pretty)(options "")(descr "IC sockets"))
-  (lib (name Symbols)(type KiCad)(uri ${KISYSMOD}/Symbols.pretty)(options "")(descr "PCB symbols"))
-  (lib (name TerminalBlocks_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks"))
-  (lib (name TerminalBlocks_WAGO)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks"))
-  (lib (name TO_SOT_Packages_SMD)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages"))
-  (lib (name TO_SOT_Packages_THT)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages"))
-  (lib (name Transformers_SMD)(type KiCad)(uri ${KISYSMOD}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers"))
-  (lib (name Transformers_THT)(type KiCad)(uri ${KISYSMOD}/Transformers_THT.pretty)(options "")(descr "Through hole transformers"))
-  (lib (name Transistors_OldSowjetAera)(type KiCad)(uri ${KISYSMOD}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors"))
-  (lib (name Valves)(type KiCad)(uri ${KISYSMOD}/Valves.pretty)(options "")(descr Valves))
-  (lib (name Varistors)(type KiCad)(uri ${KISYSMOD}/Varistors.pretty)(options "")(descr Varistors))
-  (lib (name Wire_Connections_Bridges)(type KiCad)(uri ${KISYSMOD}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points"))
-  (lib (name Wire_Pads)(type KiCad)(uri ${KISYSMOD}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points"))
-  (lib (name Choke_Common-Mode_Wurth)(type KiCad)(uri "$(KISYSMOD)Choke_Common-Mode_Wurth.pretty")(options "")(descr ""))
-  (lib (name Choke_Radial_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Radial_ThroughHole.pretty")(options "")(descr ""))
-  (lib (name Choke_SMD)(type KiCad)(uri "$(KISYSMOD)Choke_SMD.pretty")(options "")(descr ""))
-  (lib (name Choke_Toroid_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Toroid_ThroughHole.pretty")(options "")(descr ""))
-)
diff --git a/src/supportFiles/fp-lib-table-online b/src/supportFiles/fp-lib-table-online
deleted file mode 100644
index 5b4081ff..00000000
--- a/src/supportFiles/fp-lib-table-online
+++ /dev/null
@@ -1,88 +0,0 @@
-(fp_lib_table
-  (lib (name Battery_Holders)(type Github)(uri ${KIGITHUB}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders"))
-  (lib (name Buttons_Switches_SMD)(type Github)(uri ${KIGITHUB}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount"))
-  (lib (name Buttons_Switches_THT)(type Github)(uri ${KIGITHUB}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole"))
-  (lib (name Buzzers_Beepers)(type Github)(uri ${KIGITHUB}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices"))
-  (lib (name Capacitors_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount"))
-  (lib (name Capacitors_Tantalum_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount"))
-  (lib (name Capacitors_THT)(type Github)(uri ${KIGITHUB}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole"))
-  (lib (name Connectors_Card)(type Github)(uri ${KIGITHUB}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders"))
-  (lib (name Connectors_Harwin)(type Github)(uri ${KIGITHUB}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com"))
-  (lib (name Connectors_HDMI)(type Github)(uri ${KIGITHUB}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints"))
-  (lib (name Connectors_Hirose)(type Github)(uri ${KIGITHUB}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com"))
-  (lib (name Connectors_IEC_DIN)(type Github)(uri ${KIGITHUB}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints"))
-  (lib (name Connectors_JAE)(type Github)(uri ${KIGITHUB}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors"))
-  (lib (name Connectors_JST)(type Github)(uri ${KIGITHUB}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com"))
-  (lib (name Connectors_Mini-Universal)(type Github)(uri ${KIGITHUB}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok))
-  (lib (name Connectors_Molex)(type Github)(uri ${KIGITHUB}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com"))
-  (lib (name Connectors_Multicomp)(type Github)(uri ${KIGITHUB}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints"))
-  (lib (name Connectors_Phoenix)(type Github)(uri ${KIGITHUB}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints"))
-  (lib (name Connectors_Samtec)(type Github)(uri ${KIGITHUB}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints"))
-  (lib (name Connectors_TE-Connectivity)(type Github)(uri ${KIGITHUB}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com"))
-  (lib (name Connectors_Terminal_Blocks)(type Github)(uri ${KIGITHUB}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors"))
-  (lib (name Connectors_WAGO)(type Github)(uri ${KIGITHUB}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com"))
-  (lib (name Connectors_USB)(type Github)(uri ${KIGITHUB}/Connectors_USB.pretty)(options "")(descr "USB connector footprints"))
-  (lib (name Connectors)(type Github)(uri ${KIGITHUB}/Connectors.pretty)(options "")(descr "Assorted connector footprints"))
-  (lib (name Converters_DCDC_ACDC)(type Github)(uri ${KIGITHUB}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules"))
-  (lib (name Crystals)(type Github)(uri ${KIGITHUB}/Crystals.pretty)(options "")(descr "Crystals and oscillators"))
-  (lib (name Diodes_SMD)(type Github)(uri ${KIGITHUB}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount"))
-  (lib (name Diodes_THT)(type Github)(uri ${KIGITHUB}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole"))
-  (lib (name Displays_7-Segment)(type Github)(uri ${KIGITHUB}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays"))
-  (lib (name Displays)(type Github)(uri ${KIGITHUB}/Displays.pretty)(options "")(descr "Display modules"))
-  (lib (name Enclosures)(type Github)(uri ${KIGITHUB}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings"))
-  (lib (name EuroBoard_Outline)(type Github)(uri ${KIGITHUB}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed"))
-  (lib (name Fiducials)(type Github)(uri ${KIGITHUB}/Fiducials.pretty)(options "")(descr "Fiducial markings"))
-  (lib (name Fuse_Holders_and_Fuses)(type Github)(uri ${KIGITHUB}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders"))
-  (lib (name Hall-Effect_Transducers_LEM)(type Github)(uri ${KIGITHUB}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers"))
-  (lib (name Heatsinks)(type Github)(uri ${KIGITHUB}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products"))
-  (lib (name Housings_BGA)(type Github)(uri ${KIGITHUB}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)"))
-  (lib (name Housings_CSP)(type Github)(uri ${KIGITHUB}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)"))
-  (lib (name Housings_DFN_QFN)(type Github)(uri ${KIGITHUB}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN"))
-  (lib (name Housings_DIP)(type Github)(uri ${KIGITHUB}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP"))
-  (lib (name Housings_LCC)(type Github)(uri ${KIGITHUB}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)"))
-  (lib (name Housings_LGA)(type Github)(uri ${KIGITHUB}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)"))
-  (lib (name Housings_PGA)(type Github)(uri ${KIGITHUB}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)"))
-  (lib (name Housings_QFP)(type Github)(uri ${KIGITHUB}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)"))
-  (lib (name Housings_SIP)(type Github)(uri ${KIGITHUB}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)"))
-  (lib (name Housings_SOIC)(type Github)(uri ${KIGITHUB}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)"))
-  (lib (name Housings_SON)(type Github)(uri ${KIGITHUB}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)"))
-  (lib (name Housings_SSOP)(type Github)(uri ${KIGITHUB}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages"))
-  (lib (name Inductors_SMD)(type Github)(uri ${KIGITHUB}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount"))
-  (lib (name Inductors_THT)(type Github)(uri ${KIGITHUB}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole"))
-  (lib (name IR-DirectFETs)(type Github)(uri ${KIGITHUB}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier"))
-  (lib (name LEDs)(type Github)(uri ${KIGITHUB}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)"))
-  (lib (name Measurement_Points)(type Github)(uri ${KIGITHUB}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment"))
-  (lib (name Measurement_Scales)(type Github)(uri ${KIGITHUB}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges"))
-  (lib (name Microwave)(type Github)(uri ${KIGITHUB}/Microwave.pretty)(options "")(descr "Microwave"))
-  (lib (name Modules)(type Github)(uri ${KIGITHUB}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module"))
-  (lib (name Mounting_Holes)(type Github)(uri ${KIGITHUB}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners"))
-  (lib (name Opto-Devices)(type Github)(uri ${KIGITHUB}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices"))
-  (lib (name Oscillators)(type Github)(uri ${KIGITHUB}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules"))
-  (lib (name PFF_PSF_PSS_Leadforms)(type Github)(uri ${KIGITHUB}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages"))
-  (lib (name Pin_Headers)(type Github)(uri ${KIGITHUB}/Pin_Headers.pretty)(options "")(descr "Male pin headers"))
-  (lib (name Potentiometers)(type Github)(uri ${KIGITHUB}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors"))
-  (lib (name Power_Integrations)(type Github)(uri ${KIGITHUB}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints"))
-  (lib (name Relays_SMD)(type Github)(uri ${KIGITHUB}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages"))
-  (lib (name Relays_THT)(type Github)(uri ${KIGITHUB}/Relays_THT.pretty)(options "")(descr "Through hole relay packages"))
-  (lib (name Resistors_SMD)(type Github)(uri ${KIGITHUB}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount"))
-  (lib (name Resistors_THT)(type Github)(uri ${KIGITHUB}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole"))
-  (lib (name Resistors_Universal)(type Github)(uri ${KIGITHUB}/Resistors_Universal.pretty)(options "")(descr Experimental))
-  (lib (name RF_Antennas)(type Github)(uri ${KIGITHUB}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints"))
-  (lib (name RF_Modules)(type Github)(uri ${KIGITHUB}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules"))
-  (lib (name Shielding_Cabinets)(type Github)(uri ${KIGITHUB}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields"))
-  (lib (name SMD_Packages)(type Github)(uri ${KIGITHUB}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries"))
-  (lib (name Socket_Strips)(type Github)(uri ${KIGITHUB}/Socket_Strips.pretty)(options "")(descr "Female socket strips"))
-  (lib (name Sockets)(type Github)(uri ${KIGITHUB}/Sockets.pretty)(options "")(descr "IC sockets"))
-  (lib (name Symbols)(type Github)(uri ${KIGITHUB}/Symbols.pretty)(options "")(descr "PCB symbols"))
-  (lib (name TerminalBlocks_Phoenix)(type Github)(uri ${KIGITHUB}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks"))
-  (lib (name TerminalBlocks_WAGO)(type Github)(uri ${KIGITHUB}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks"))
-  (lib (name TO_SOT_Packages_SMD)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages"))
-  (lib (name TO_SOT_Packages_THT)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages"))
-  (lib (name Transformers_SMD)(type Github)(uri ${KIGITHUB}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers"))
-  (lib (name Transformers_THT)(type Github)(uri ${KIGITHUB}/Transformers_THT.pretty)(options "")(descr "Through hole transformers"))
-  (lib (name Transistors_OldSowjetAera)(type Github)(uri ${KIGITHUB}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors"))
-  (lib (name Valves)(type Github)(uri ${KIGITHUB}/Valves.pretty)(options "")(descr "Valves"))
-  (lib (name Varistors)(type Github)(uri ${KIGITHUB}/Varistors.pretty)(options "")(descr "Varistors"))
-  (lib (name Wire_Connections_Bridges)(type Github)(uri ${KIGITHUB}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points"))
-  (lib (name Wire_Pads)(type Github)(uri ${KIGITHUB}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points"))
-)
-- 
cgit 


From 567e3b725fcc9d22e27cfd854a573d3e64deaff1 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:39:52 +0530
Subject: restructured code - pyinstaller

---
 src/browser/UserManual.py                  |   4 +-
 src/browser/Welcome.py                     |   4 +-
 src/configuration/Appconfig.py             |   8 +-
 src/frontEnd/Application.py                |  73 ++++++-----
 src/frontEnd/ProjectExplorer.py            |  10 +-
 src/frontEnd/Workspace.py                  |  11 +-
 src/kicadtoNgspice/DeviceModel.py          |   5 +-
 src/kicadtoNgspice/KicadtoNgspice.py       |   4 +-
 src/kicadtoNgspice/Processing.py           |   2 +-
 src/kicadtoNgspice/SubcircuitTab.py        |   6 +-
 src/modelEditor/ModelEditor.py             |  12 +-
 src/ngspicetoModelica/ModelicaUI.py        | 201 +++++++++++++++++++++++------
 src/ngspicetoModelica/NgspicetoModelica.py | 189 ++-------------------------
 src/subcircuit/newSub.py                   |   2 +-
 src/subcircuit/openSub.py                  |   2 +-
 src/subcircuit/uploadSub.py                |  10 +-
 16 files changed, 252 insertions(+), 291 deletions(-)

(limited to 'src')

diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py
index 6f09190b..f733bb93 100644
--- a/src/browser/UserManual.py
+++ b/src/browser/UserManual.py
@@ -13,9 +13,9 @@ class UserManual(QtGui.QWidget):
 
         self.vlayout = QtGui.QVBoxLayout()
 
-        self.url = "../browser/pages/User-Manual/eSim.html"
+        self.url = "library/browser/User-Manual/eSim.html"
         self.test = webbrowser.open(
-            "../browser/pages/User-Manual/eSim.html", new=2)
+            "library/browser/User-Manual/eSim.html", new=2)
 
         self.setLayout(self.vlayout)
         self.show()
diff --git a/src/browser/Welcome.py b/src/browser/Welcome.py
index 2d91bcc9..69584f10 100644
--- a/src/browser/Welcome.py
+++ b/src/browser/Welcome.py
@@ -12,7 +12,9 @@ class Welcome(QtGui.QWidget):
         self.vlayout = QtGui.QVBoxLayout()
 
         self.browser = QtGui.QTextBrowser()
-        self.browser.setSource(QtCore.QUrl("../browser/pages/welcome.html"))
+        self.browser.setSource(QtCore.QUrl(
+            "library/browser/welcome.html")
+        )
         self.browser.setOpenExternalLinks(True)
         self.browser.setVerticalScrollBarPolicy(QtCore.Qt.ScrollBarAlwaysOff)
 
diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py
index dfe4363f..6a10f3d7 100644
--- a/src/configuration/Appconfig.py
+++ b/src/configuration/Appconfig.py
@@ -36,7 +36,7 @@ class Appconfig(QtGui.QWidget):
     # Home directory
     try:
         file = open(os.path.join(
-        	os.path.expanduser("~"), ".esim/workspace.txt"), 'r'
+            os.path.expanduser("~"), ".esim/workspace.txt"), 'r'
         )
         workspace_check, home = file.readline().split(' ', 1)
         file.close()
@@ -53,7 +53,7 @@ class Appconfig(QtGui.QWidget):
     workspace_text = "eSim stores your project in a folder called "
     workspace_text += "eSim-Workspace. You can choose a different "
     workspace_text += "workspace folder to use for this session."
-    
+
     procThread_list = []
     proc_dict = {}  # hold pids of all external windows of the current project
     dock_dict = {}  # holds all dockwidgets
@@ -61,7 +61,7 @@ class Appconfig(QtGui.QWidget):
         default_workspace["workspace"], ".projectExplorer.txt")
     }
 
-    noteArea = {"Note" : []}
+    noteArea = {"Note": []}
 
     parser_esim = SafeConfigParser()
     parser_esim.read(
@@ -80,7 +80,7 @@ class Appconfig(QtGui.QWidget):
 
     # Open file and read KiCad config path
     try:
-        file = open('../supportFiles/kicad_config_path.txt', 'r')
+        file = open('library/supportFiles/kicad_config_path.txt', 'r')
         kicad_path = file.read().rstrip()
         file.close()
     except BaseException as e:
diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 1b8a18c5..3ecf9941 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -16,7 +16,7 @@
 #      REVISION: Friday 14 February 2020
 # =========================================================================
 
-import pathmagic  # noqa
+from frontEnd import pathmagic  # noqa
 from PyQt4 import QtGui, QtCore
 from configuration.Appconfig import Appconfig
 from projManagement.openProject import OpenProjectInfo
@@ -64,10 +64,10 @@ class Application(QtGui.QMainWindow):
                          self.obj_appconfig._app_heigth)
         self.setWindowTitle(self.obj_appconfig._APPLICATION)
         self.showMaximized()
-        self.setWindowIcon(QtGui.QIcon('../../images/logo.png'))
+        self.setWindowIcon(QtGui.QIcon('images/logo.png'))
 
         self.systemTrayIcon = QtGui.QSystemTrayIcon(self)
-        self.systemTrayIcon.setIcon(QtGui.QIcon('../../images/logo.png'))
+        self.systemTrayIcon.setIcon(QtGui.QIcon('images/logo.png'))
         self.systemTrayIcon.setVisible(True)
 
     def initToolBar(self):
@@ -83,28 +83,28 @@ class Application(QtGui.QMainWindow):
         """
         # Top Tool bar
         self.newproj = QtGui.QAction(
-            QtGui.QIcon('../../images/newProject.png'),
+            QtGui.QIcon('images/newProject.png'),
             '<b>New Project</b>', self
         )
         self.newproj.setShortcut('Ctrl+N')
         self.newproj.triggered.connect(self.new_project)
 
         self.openproj = QtGui.QAction(
-            QtGui.QIcon('../../images/openProject.png'),
+            QtGui.QIcon('images/openProject.png'),
             '<b>Open Project</b>', self
         )
         self.openproj.setShortcut('Ctrl+O')
         self.openproj.triggered.connect(self.open_project)
 
         self.closeproj = QtGui.QAction(
-            QtGui.QIcon('../../images/closeProject.png'),
+            QtGui.QIcon('images/closeProject.png'),
             '<b>Close Project</b>', self
         )
         self.closeproj.setShortcut('Ctrl+X')
         self.closeproj.triggered.connect(self.close_project)
 
         self.wrkspce = QtGui.QAction(
-            QtGui.QIcon('../../images/workspace.ico'),
+            QtGui.QIcon('images/workspace.ico'),
             '<b>Change Workspace</b>', self
         )
         self.wrkspce.setShortcut('Ctrl+W')
@@ -112,19 +112,19 @@ class Application(QtGui.QMainWindow):
 
         self.switchmode = None
         self.validate_mode()
-        if self.online_flag == True:
+        if self.online_flag is True:
             self.switchmode = QtGui.QAction(QtGui.QIcon(
-                '../../images/online.png'),
+                'images/online.png'),
                 '<b>Go Offline</b>', self
             )
-        elif self.online_flag == False:
+        elif self.online_flag is False:
             self.switchmode = QtGui.QAction(QtGui.QIcon(
-                '../../images/offline.png'),
+                'images/offline.png'),
                 '<b>Go Online</b>', self
             )
         elif self.online_flag is None:
             self.switchmode = QtGui.QAction(QtGui.QIcon(
-                '../../images/disable.png'),
+                'images/disable.png'),
                 '<b>Mode switching has been disabled. ' +
                 'Default mode set to offline</b>', self
             )
@@ -133,7 +133,7 @@ class Application(QtGui.QMainWindow):
         self.switchmode.triggered.connect(self.change_mode)
 
         self.helpfile = QtGui.QAction(
-            QtGui.QIcon('../../images/helpProject.png'), '<b>Help</b>', self
+            QtGui.QIcon('images/helpProject.png'), '<b>Help</b>', self
         )
         self.helpfile.setShortcut('Ctrl+H')
         self.helpfile.triggered.connect(self.help_project)
@@ -156,7 +156,7 @@ class Application(QtGui.QMainWindow):
         self.logo = QtGui.QLabel()
         self.logopic = QtGui.QPixmap(
             os.path.join(
-                os.path.abspath('../..'), 'images', 'fosseeLogo.png'
+                os.path.abspath(''), 'images', 'fosseeLogo.png'
             ))
         self.logopic = self.logopic.scaled(
             QSize(150, 150), QtCore.Qt.KeepAspectRatio)
@@ -166,48 +166,45 @@ class Application(QtGui.QMainWindow):
 
         # Left Tool bar Action Widget
         self.kicad = QtGui.QAction(
-            QtGui.QIcon('../../images/kicad.png'),
+            QtGui.QIcon('images/kicad.png'),
             '<b>Open Schematic</b>', self
         )
         self.kicad.triggered.connect(self.obj_kicad.openSchematic)
 
         self.conversion = QtGui.QAction(
-            QtGui.QIcon('../../images/ki-ng.png'),
+            QtGui.QIcon('images/ki-ng.png'),
             '<b>Convert Kicad to Ngspice</b>', self
         )
         self.conversion.triggered.connect(self.obj_kicad.openKicadToNgspice)
 
         self.ngspice = QtGui.QAction(
-            QtGui.QIcon('../../images/ngspice.png'), '<b>Simulation</b>', self
+            QtGui.QIcon('images/ngspice.png'), '<b>Simulation</b>', self
         )
         self.ngspice.triggered.connect(self.open_ngspice)
 
         self.model = QtGui.QAction(
-            QtGui.QIcon('../../images/model.png'),
-            '<b>Model Editor</b>', self
+            QtGui.QIcon('images/model.png'), '<b>Model Editor</b>', self
         )
         self.model.triggered.connect(self.open_modelEditor)
 
         self.subcircuit = QtGui.QAction(
-            QtGui.QIcon('../../images/subckt.png'),
-            '<b>Subcircuit</b>', self
+            QtGui.QIcon('images/subckt.png'),'<b>Subcircuit</b>', self
         )
         self.subcircuit.triggered.connect(self.open_subcircuit)
 
         self.nghdl = QtGui.QAction(
-            QtGui.QIcon('../../images/nghdl.png'), '<b>Nghdl</b>', self
+            QtGui.QIcon('images/nghdl.png'), '<b>Nghdl</b>', self
         )
         self.nghdl.triggered.connect(self.open_nghdl)
 
         self.omedit = QtGui.QAction(
-            QtGui.QIcon('../../images/omedit.png'),
+            QtGui.QIcon('images/omedit.png'),
             '<b>Modelica Converter</b>', self
         )
         self.omedit.triggered.connect(self.open_OMedit)
 
         self.omoptim = QtGui.QAction(
-            QtGui.QIcon('../../images/omoptim.png'),
-            '<b>OM Optimisation</b>', self
+            QtGui.QIcon('images/omoptim.png'), '<b>OM Optimisation</b>', self
         )
         self.omoptim.triggered.connect(self.open_OMoptim)
 
@@ -353,7 +350,7 @@ class Application(QtGui.QMainWindow):
         """
         This functions checks whether proper fp-lib-table* files are \
         available or not. If not, then move appropriate files from \
-        supportFiles folder and set `self.online_flag` accordingly.
+        library/supportFiles folder and set `self.online_flag` accordingly.
 
         @params
 
@@ -385,7 +382,7 @@ class Application(QtGui.QMainWindow):
                               "/fp-lib-table")
                 else:
                     self.online_flag = False
-                        
+
             if remove:
                 # Remove invalid files
                 if os.path.exists(
@@ -401,9 +398,9 @@ class Application(QtGui.QMainWindow):
                               "/fp-lib-table-online")
 
                 # Restore original files
-                shutil.copy('../supportFiles/fp-lib-table-online',
+                shutil.copy('library/supportFiles/fp-lib-table-online',
                             self.obj_appconfig.kicad_path + "/")
-                shutil.copy('../supportFiles/fp-lib-table',
+                shutil.copy('library/supportFiles/fp-lib-table',
                             self.obj_appconfig.kicad_path + "/")
 
                 self.online_flag = False
@@ -445,7 +442,7 @@ class Application(QtGui.QMainWindow):
                     self.obj_appconfig.kicad_path + "/fp-lib-table"
                 )
                 self.switchmode.setIcon(
-                    QtGui.QIcon('../../images/offline.png')
+                    QtGui.QIcon('images/offline.png')
                 )
                 self.switchmode.setText('<b>Go Online</b>')
                 self.switchmode.setEnabled(True)
@@ -463,7 +460,7 @@ class Application(QtGui.QMainWindow):
                     self.obj_appconfig.kicad_path + "/fp-lib-table"
                 )
                 self.switchmode.setIcon(
-                    QtGui.QIcon('../../images/online.png')
+                    QtGui.QIcon('images/online.png')
                 )
                 self.switchmode.setText('<b>Go Offline</b>')
                 self.switchmode.setEnabled(True)
@@ -471,10 +468,12 @@ class Application(QtGui.QMainWindow):
 
             elif self.online_flag is None:
                 self.switchmode.setIcon(
-                    QtGui.QIcon('../../images/disable.png')
+                    QtGui.QIcon('images/disable.png')
+                )
+                self.switchmode.setText(
+                    '<b>Mode switching has been ' +
+                    'disabled. Default mode set to offline</b>.'
                 )
-                self.switchmode.setText('<b>Mode switching has been ' +
-                    'disabled. Default mode set to offline</b>.')
                 self.switchmode.setEnabled(False)
         else:
             self.msg = QtGui.QErrorMessage()
@@ -799,7 +798,7 @@ def main(args):
     print("Starting eSim......")
     app = QtGui.QApplication(args)
 
-    splash_pix = QtGui.QPixmap('../../images/splash_screen_esim.png')
+    splash_pix = QtGui.QPixmap('images/splash_screen_esim.png')
     splash = QtGui.QSplashScreen(splash_pix, QtCore.Qt.WindowStaysOnTopHint)
     splash.setMask(splash_pix.mask())
     splash.show()
@@ -809,13 +808,13 @@ def main(args):
 
     try:
         file = open(os.path.join(
-            os.path.expanduser("~"),".esim/workspace.txt"), 'r'
+            os.path.expanduser("~"), ".esim/workspace.txt"), 'r'
         )
         work = int(file.read(1))
         file.close()
     except IOError:
         work = 0
-    if work is not 0:
+    if work != 0:
         appView.obj_workspace.defaultWorkspace()
     else:
         appView.hide()
diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py
index 4462c584..c733c9b1 100644
--- a/src/frontEnd/ProjectExplorer.py
+++ b/src/frontEnd/ProjectExplorer.py
@@ -38,19 +38,19 @@ class ProjectExplorer(QtGui.QWidget):
             QTreeView { border-radius: 15px; border: 1px \
             solid gray; padding: 5px; width: 200px; height: 150px;  }\
             QTreeView::branch:has-siblings:!adjoins-item { \
-            border-image: url(../../images/vline.png) 0;} \
+            border-image: url(images/vline.png) 0;} \
             QTreeView::branch:has-siblings:adjoins-item { \
-            border-image: url(../../images/branch-more.png) 0; } \
+            border-image: url(images/branch-more.png) 0; } \
             QTreeView::branch:!has-children:!has-siblings:adjoins-item { \
-            border-image: url(../../images/branch-end.png) 0; } \
+            border-image: url(images/branch-end.png) 0; } \
             QTreeView::branch:has-children:!has-siblings:closed, \
             QTreeView::branch:closed:has-children:has-siblings { \
             border-image: none; \
-            image: url(../../images/branch-closed.png); } \
+            image: url(images/branch-closed.png); } \
             QTreeView::branch:open:has-children:!has-siblings, \
             QTreeView::branch:open:has-children:has-siblings  { \
             border-image: none; \
-            image: url(../../images/branch-open.png); } \
+            image: url(images/branch-open.png); } \
         ")
 
         for parents, children in list(
diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py
index 09092a69..6940da59 100644
--- a/src/frontEnd/Workspace.py
+++ b/src/frontEnd/Workspace.py
@@ -64,7 +64,7 @@ class Workspace(QtGui.QWidget):
         self.cancelbtn = QtGui.QPushButton('Cancel')
         self.cancelbtn.clicked.connect(self.defaultWorkspace)
 
-        #Checkbox
+        # Checkbox
         self.chkbox = QtGui.QCheckBox('Set Default', self)
         self.chkbox.setCheckState(int(self.obj_appconfig.workspace_check))
 
@@ -82,7 +82,7 @@ class Workspace(QtGui.QWidget):
         self.setWindowTitle("eSim")
         self.setWindowFlags(QtCore.Qt.WindowStaysOnTopHint)
         self.note.setReadOnly(True)
-        self.setWindowIcon(QtGui.QIcon('../../images/logo.png'))
+        self.setWindowIcon(QtGui.QIcon('images/logo.png'))
         self.setLayout(self.grid)
 
     def defaultWorkspace(self):
@@ -121,7 +121,8 @@ class Workspace(QtGui.QWidget):
         file = open(os.path.join(
             os.path.expanduser("~"), ".esim/workspace.txt"), 'w'
         )
-        file.writelines(str(self.obj_appconfig.workspace_check) +
+        file.writelines(
+            str(self.obj_appconfig.workspace_check) +
             " " + self.workspace_loc.text()
         )
         file.close()
@@ -148,10 +149,10 @@ class Workspace(QtGui.QWidget):
             self.obj_appconfig.project_explorer = json.load(
                 open(self.obj_appconfig.dictPath["path"])
             )
-        except:
+        except BaseException:
             self.obj_appconfig.project_explorer = {}
 
-        Appconfig.project_explorer = self.obj_appconfig.project_explorer        
+        Appconfig.project_explorer = self.obj_appconfig.project_explorer
 
         var_appView.obj_Mainview.obj_projectExplorer.treewidget.clear()
         for parent, children in self.obj_appconfig.project_explorer.items():
diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py
index 41faa6f0..65e09753 100644
--- a/src/kicadtoNgspice/DeviceModel.py
+++ b/src/kicadtoNgspice/DeviceModel.py
@@ -363,9 +363,8 @@ class DeviceModel(QtGui.QWidget):
 
         self.libfile = str(
             QtGui.QFileDialog.getOpenFileName(
-                self,
-                "Open Library Directory",
-                "../deviceModelLibrary",
+                self, "Open Library Directory",
+                "library/deviceModelLibrary",
                 "*.lib"))
 
         # Setting Library to Text Edit Line
diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index cfc4f671..18701c43 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -114,7 +114,7 @@ class MainWindow(QtGui.QWidget):
 
         """
         - Checking if any unknown model is used in schematic which is not
-          recognized by NgSpice.
+          recognized by Ngspice.
         - Also if the two model of same name is present under
           modelParamXML directory
         """
@@ -233,7 +233,7 @@ class MainWindow(QtGui.QWidget):
         - This function called when convert button clicked
         - Extracting data from the objs created above
         - Pushing this data to json, and dumping it finally
-        - Written to a ..._Previous_Valuse.json file in the projDirectory
+        - Written to a ..._Previous_Values.json file in the projDirectory
         - Finally, call createNetListFile, with the converted schematic
         """
         global schematicInfo
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index 427f0823..67ffd3f5 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -8,7 +8,7 @@ class PrcocessNetlist:
     - This class include all the function required for pre-proccessing of
       netlist before converting to Ngspice Netlist.
     """
-    modelxmlDIR = '../modelParamXML'
+    modelxmlDIR = 'library/modelParamXML'
 
     def __init__(self):
         pass
diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py
index 08ad7332..35b876f0 100644
--- a/src/kicadtoNgspice/SubcircuitTab.py
+++ b/src/kicadtoNgspice/SubcircuitTab.py
@@ -141,9 +141,9 @@ class SubcircuitTab(QtGui.QWidget):
 
         self.subfile = str(
             QtGui.QFileDialog.getExistingDirectory(
-                self,
-                "Open Subcircuit",
-                "../SubcircuitLibrary"))
+                self, "Open Subcircuit",
+                "library/SubcircuitLibrary")
+            )
         self.reply = self.obj_validation.validateSub(
             self.subfile, self.numPorts[self.widgetObjCount - 1])
         if self.reply == "True":
diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py
index 7db35251..c5bd310a 100644
--- a/src/modelEditor/ModelEditor.py
+++ b/src/modelEditor/ModelEditor.py
@@ -10,7 +10,7 @@ class ModelEditorclass(QtGui.QWidget):
     - Initialise the layout for dockarea
     - Use QVBoxLayout, QSplitter, QGridLayout to define the layout
     - Initalise directory to save new models,
-      savepathtest = '../deviceModelLibrary'
+      savepathtest = 'library/deviceModelLibrary'
     - Initialise buttons and options ====>
         - Name            Function Called
     ========================================
@@ -30,7 +30,7 @@ class ModelEditorclass(QtGui.QWidget):
 
     def __init__(self):
         QtGui.QWidget.__init__(self)
-        self.savepathtest = '../deviceModelLibrary'
+        self.savepathtest = 'library/deviceModelLibrary'
         self.obj_appconfig = Appconfig()
         self.newflag = 0
         self.layout = QtGui.QVBoxLayout()
@@ -252,7 +252,7 @@ class ModelEditorclass(QtGui.QWidget):
         - Accordingly call `createtable(path)` to draw tables usingg QTable
         - Check for the state of button before rendering
         '''
-        self.path = '../deviceModelLibrary/Templates'
+        self.path = 'library/deviceModelLibrary/Templates'
         if self.diode.isChecked():
             if filetype == 'Diode':
                 path = os.path.join(self.path, 'D.xml')
@@ -327,7 +327,7 @@ class ModelEditorclass(QtGui.QWidget):
                 QtGui.QFileDialog.getOpenFileName(
                     self,
                     "Open Library Directory",
-                    "../deviceModelLibrary",
+                    "library/deviceModelLibrary",
                     "*.lib"))
             self.createtable(self.editfile)
         except BaseException:
@@ -473,7 +473,7 @@ class ModelEditorclass(QtGui.QWidget):
             ET.SubElement(param, tags).text = text
         tree = ET.ElementTree(root)
         defaultcwd = os.getcwd()
-        self.savepath = '../deviceModelLibrary'
+        self.savepath = 'library/deviceModelLibrary'
         if self.diode.isChecked():
             savepath = os.path.join(self.savepath, 'Diode')
             os.chdir(savepath)
@@ -687,7 +687,7 @@ class ModelEditorclass(QtGui.QWidget):
             QtGui.QFileDialog.getOpenFileName(
                 self,
                 "Open Library Directory",
-                "../deviceModelLibrary",
+                "library/deviceModelLibrary",
                 "*.lib"))
         libopen = open(self.libfile)
         filedata = libopen.read().split()
diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py
index 168b5c14..aa7cb330 100644
--- a/src/ngspicetoModelica/ModelicaUI.py
+++ b/src/ngspicetoModelica/ModelicaUI.py
@@ -1,9 +1,9 @@
 import os
-from subprocess import Popen, PIPE, STDOUT
 from PyQt4 import QtGui, QtCore
 from configuration.Appconfig import Appconfig
 from projManagement import Worker
 from projManagement.Validation import Validation
+from .NgspicetoModelica import NgMoConverter
 
 BROWSE_LOCATION = '/home'
 
@@ -49,45 +49,172 @@ class OpenModelicaEditor(QtGui.QWidget):
         self.FileEdit.setText(self.ngspiceNetlist)
 
     def callConverter(self):
+
+        dir_name = os.path.dirname(os.path.realpath(self.ngspiceNetlist))
+        # file_basename = os.path.basename(self.ngspiceNetlist)
+
+        cwd = os.getcwd()
+        os.chdir(dir_name)
+
+        obj_NgMoConverter = NgMoConverter(self.map_json)
+
         try:
-            self.cmd1 = (
-                "python3 ../ngspicetoModelica/NgspicetoModelica.py " +
-                self.ngspiceNetlist + ' ' +
-                self.map_json
-            )
-            # self.obj_workThread1 = Worker.WorkerThread(self.cmd1)
-            # self.obj_workThread1.start()
-            convert_process = Popen(
-                self.cmd1,
-                shell=True,
-                stdin=PIPE,
-                stdout=PIPE,
-                stderr=STDOUT,
-                close_fds=True)
-            error_code = convert_process.stdout.read()
-
-            if not error_code:
-                self.msg = QtGui.QMessageBox()
-                self.msg.setText(
-                    "Ngspice netlist successfully converted to OpenModelica" +
-                    "netlist"
+            # Getting all the require information
+            lines = obj_NgMoConverter.readNetlist(self.ngspiceNetlist)
+            # print("Complete Lines of Ngspice netlist : " +
+            # "lines ---------------->", lines)
+            optionInfo, schematicInfo = \
+                obj_NgMoConverter.separateNetlistInfo(lines)
+            # print("All option details like analysis,subckt,.ic,.model  :" +
+            # "OptionInfo------------------->", optionInfo)
+            # print("Schematic connection info :schematicInfo", schematicInfo)
+            modelName, modelInfo, subcktName, paramInfo, transInfo,\
+                inbuiltModelDict = (
+                    obj_NgMoConverter.addModel(optionInfo)
                 )
-                self.obj_appconfig.print_info(
-                    "Ngspice netlist successfully converted to OpenModelica" +
-                    "netlist"
+            # print("Name of Model : " +
+            # "modelName-------------------->", modelName)
+            # print("Model Information : " +
+            # "modelInfo--------------------->", modelInfo)
+            # print("Subcircuit Name : " +
+            # "subcktName------------------------>", subcktName)
+            # print("Parameter Information : " +
+            # "paramInfo---------------------->", paramInfo)
+            # print("InBuilt Model ---------------------->", inbuiltModelDict)
+
+            modelicaParamInit = obj_NgMoConverter.processParam(paramInfo)
+            # print("Make modelicaParamInit from paramInfo : " +
+            # "processParamInit------------->", modelicaParamInit)
+            compInfo, plotInfo = obj_NgMoConverter.separatePlot(schematicInfo)
+            # print("Plot info like plot,print etc :plotInfo",plotInfo)
+            IfMOS = '0'
+
+            for eachline in compInfo:
+                # words = eachline.split()
+                if eachline[0] == 'm':
+                    IfMOS = '1'
+                    break
+
+            subOptionInfo = []
+            subSchemInfo = []
+            if len(subcktName) > 0:
+                # subOptionInfo = []
+                # subSchemInfo = []
+                for eachsub in subcktName:
+                    filename_temp = eachsub + '.sub'
+                    data = obj_NgMoConverter.readNetlist(filename_temp)
+                    # print "Data---------->",data
+                    subOptionInfo, subSchemInfo = (
+                        obj_NgMoConverter.separateNetlistInfo(data)
+                    )
+                    for eachline in subSchemInfo:
+                        # words = eachline.split()
+                        if eachline[0] == 'm':
+                            IfMOS = '1'
+                            break
+            # print("Subcircuit OptionInfo :" +
+            # "subOptionInfo------------------->", subOptionInfo)
+            # print("Subcircuit Schematic Info :" +
+            # "subSchemInfo-------------------->", subSchemInfo)
+
+            node, nodeDic, pinInit, pinProtectedInit = \
+                obj_NgMoConverter.nodeSeparate(
+                    compInfo, '0', [], subcktName, []
                 )
-                self.msg.exec_()
-            else:
-                self.err_msg = QtGui.QErrorMessage()
-                self.msg.setModal(True)
-                self.msg.setWindowTitle(
-                    "Ngspice to Modelica conversion error")
-                self.err_msg.showMessage(
-                    'Unable to convert NgSpice netlist to Modelica netlist.' +
-                    'Check the netlist :' +
-                    error_code)
-                self.err_msg.exec_()
-                self.obj_appconfig.print_error(error_code)
+            # print("All nodes in the netlist :node---------------->", node)
+            # print("NodeDic which will be used for modelica :" +
+            # "nodeDic------------->", nodeDic)
+            # print("PinInit-------------->", pinInit)
+            # print("pinProtectedInit----------->", pinProtectedInit)
+
+            modelicaCompInit, numNodesSub = obj_NgMoConverter.compInit(
+                compInfo,
+                node,
+                modelInfo,
+                subcktName,
+                dir_name,
+                transInfo,
+                inbuiltModelDict
+            )
+            # print("ModelicaComponents :" +
+            # "modelicaCompInit----------->", modelicaCompInit)
+            # print("SubcktNumNodes :" +
+            # "numNodesSub---------------->", numNodesSub)
+
+            connInfo = obj_NgMoConverter.connectInfo(
+                compInfo, node, nodeDic, numNodesSub, subcktName)
+
+            # print("ConnInfo------------------>", connInfo)
+
+            # After Sub Ckt Func
+            if len(subcktName) > 0:
+                data, subOptionInfo, subSchemInfo, subModel, subModelInfo,\
+                    subsubName, subParamInfo, modelicaSubCompInit,\
+                    modelicaSubParam, nodeSubInterface, nodeSub, nodeDicSub,\
+                    pinInitSub, connSubInfo = (
+                        obj_NgMoConverter.procesSubckt(
+                            subcktName, numNodesSub, dir_name
+                        )
+                    )  # Adding 'numNodesSub' by Fahim
+
+            # Creating Final Output file
+            newfile = self.ngspiceNetlist.split('.')
+            newfilename = newfile[0]
+            outfile = newfilename + ".mo"
+            out = open(outfile, "w")
+            out.writelines('model ' + os.path.basename(newfilename))
+            out.writelines('\n')
+            if IfMOS == '0':
+                out.writelines('import Modelica.Electrical.*;')
+            elif IfMOS == '1':
+                out.writelines('import BondLib.Electrical.*;')
+                # out.writelines('import Modelica.Electrical.*;')
+            out.writelines('\n')
+
+            for eachline in modelicaParamInit:
+                if len(paramInfo) == 0:
+                    continue
+                else:
+                    out.writelines(eachline)
+                    out.writelines('\n')
+            for eachline in modelicaCompInit:
+                if len(compInfo) == 0:
+                    continue
+                else:
+                    out.writelines(eachline)
+                    out.writelines('\n')
+
+            out.writelines('protected')
+            out.writelines('\n')
+            out.writelines(pinInit)
+            out.writelines('\n')
+            out.writelines('equation')
+            out.writelines('\n')
+
+            for eachline in connInfo:
+                if len(connInfo) == 0:
+                    continue
+                else:
+                    out.writelines(eachline)
+                    out.writelines('\n')
+
+            out.writelines('end ' + os.path.basename(newfilename) + ';')
+            out.writelines('\n')
+
+            out.close()
+
+            os.chdir(cwd)
+
+            self.msg = QtGui.QMessageBox()
+            self.msg.setText(
+                "Ngspice netlist successfully converted to OpenModelica" +
+                "netlist"
+            )
+            self.obj_appconfig.print_info(
+                "Ngspice netlist successfully converted to OpenModelica" +
+                "netlist"
+            )
+            self.msg.exec_()
 
         except Exception as e:
             self.msg = QtGui.QErrorMessage()
diff --git a/src/ngspicetoModelica/NgspicetoModelica.py b/src/ngspicetoModelica/NgspicetoModelica.py
index bdbd6ac2..a78bad1b 100644
--- a/src/ngspicetoModelica/NgspicetoModelica.py
+++ b/src/ngspicetoModelica/NgspicetoModelica.py
@@ -1,8 +1,6 @@
-import sys
 import os
 import re
 import json
-from string import maketrans
 
 
 class NgMoConverter:
@@ -31,10 +29,9 @@ class NgMoConverter:
             except Exception as e:
                 print("Error in opening file")
                 print(str(e))
-                sys.exit()
+                raise
         else:
-            print(filename + " does not exist")
-            sys.exit()
+            raise FileNotFoundError(filename + " does not exist")
 
         data = f.read()
         data = data.splitlines()
@@ -150,10 +147,10 @@ class NgMoConverter:
                     f = open(filename)
                 except BaseException:
                     print("Error in opening file")
-                    sys.exit()
+                    raise
             else:
-                print(filename + " does not exist")
-                sys.exit()
+                raise FileNotFoundError(filename + " does not exist")
+
             data = f.read()
             data = data.replace(
                 '+',
@@ -206,7 +203,7 @@ class NgMoConverter:
             line = line.split()
             final_line = ','.join(line)
             stat = 'parameter Real ' + final_line + ';'
-            stat = stat.translate(maketrans('{}', '  '))
+            stat = stat.translate(str.maketrans('{}', '  '))
             modelicaParam.append(stat)
         return modelicaParam
 
@@ -481,8 +478,7 @@ class NgMoConverter:
                         ["import"]
                     ) + ".PNP"
                 else:
-                    print("Transistor " + str(trans) + " Not found")
-                    sys.exit(1)
+                    raise NameError("Transistor " + str(trans) + " Not found")
 
                 stat = start + " " + words[0] + "("
                 tempstatList = []
@@ -576,8 +572,7 @@ class NgMoConverter:
                         ["import"]
                     ) + ".Mp"
                 else:
-                    print("MOSFET " + str(trans) + " not found")
-                    sys.exit(1)
+                    raise NameError("MOSFET " + str(trans) + " not found")
 
                 stat = start + " " + words[0] + "("
                 tempstatList = []
@@ -684,8 +679,7 @@ class NgMoConverter:
                                             ["import"]
                                             )+".J_PJFJFET"
                 else:
-                    print "JFET "+str(trans)+" Not found"
-                    sys.exit(1)
+                    raise NameError("JFET " + str(trans) + " Not found")
                 """
                 start = self.mappingData["Devices"][deviceName]["import"]
 
@@ -894,7 +888,7 @@ class NgMoConverter:
             appen_line = intLine[newindex:len(intLine)]
             appen_param = ','.join(appen_line)
             paramLine = 'parameter Real ' + appen_param + ';'
-            paramLine = paramLine.translate(maketrans('{}', '  '))
+            paramLine = paramLine.translate(str.maketrans('{}', '  '))
             subParamInfo.append(paramLine)
         return subParamInfo
 
@@ -1257,166 +1251,3 @@ class NgMoConverter:
             pinInitSub,
             connSubInfo
         )
-
-
-def main(args):
-    """
-    It is main function of module Ngspice to Modelica converter
-    """
-    if len(sys.argv) == 3:
-        filename = sys.argv[1]
-        map_json = sys.argv[2]
-    else:
-        print("USAGE:")
-        print("python3 NgspicetoModelica.py <filename>")
-        sys.exit()
-
-    dir_name = os.path.dirname(os.path.realpath(filename))
-    # file_basename = os.path.basename(filename)
-
-    cwd = os.getcwd()
-    os.chdir(dir_name)
-
-    obj_NgMoConverter = NgMoConverter(map_json)
-
-    # Getting all the require information
-    lines = obj_NgMoConverter.readNetlist(filename)
-    # print "Complete Lines of Ngspice netlist :lines ---------------->",lines
-    optionInfo, schematicInfo = obj_NgMoConverter.separateNetlistInfo(lines)
-    # print "All option details like analysis,subckt,.ic,.model  :
-    # OptionInfo------------------->",optionInfo
-    # print "Schematic connection info :schematicInfo",schematicInfo
-    modelName, modelInfo, subcktName, paramInfo, transInfo,\
-        inbuiltModelDict = (
-            obj_NgMoConverter.addModel(optionInfo)
-        )
-    # print "Name of Model : modelName-------------------->",modelName
-    # print "Model Information :modelInfo--------------------->",modelInfo
-    # print "Subcircuit Name :subcktName------------------------>",subcktName
-    # print "Parameter Information :paramInfo---------------------->",paramInfo
-    # print "InBuilt Model ---------------------->",inbuiltModelDict
-
-    modelicaParamInit = obj_NgMoConverter.processParam(paramInfo)
-    # print "Make modelicaParamInit from paramInfo
-    # : processParamInit------------->",modelicaParamInit
-    compInfo, plotInfo = obj_NgMoConverter.separatePlot(schematicInfo)
-    # print "Plot info like plot,print etc :plotInfo",plotInfo
-    IfMOS = '0'
-
-    for eachline in compInfo:
-        # words = eachline.split()
-        if eachline[0] == 'm':
-            IfMOS = '1'
-            break
-
-    subOptionInfo = []
-    subSchemInfo = []
-    if len(subcktName) > 0:
-        # subOptionInfo = []
-        # subSchemInfo = []
-        for eachsub in subcktName:
-            filename_temp = eachsub + '.sub'
-            data = obj_NgMoConverter.readNetlist(filename_temp)
-            # print "Data---------->",data
-            subOptionInfo, subSchemInfo = (
-                obj_NgMoConverter.separateNetlistInfo(data)
-            )
-            for eachline in subSchemInfo:
-                # words = eachline.split()
-                if eachline[0] == 'm':
-                    IfMOS = '1'
-                    break
-    # print "Subcircuit OptionInfo
-    # : subOptionInfo------------------->",subOptionInfo
-    # print "Subcircuit Schematic Info
-    # : subSchemInfo-------------------->",subSchemInfo
-
-    node, nodeDic, pinInit, pinProtectedInit = obj_NgMoConverter.nodeSeparate(
-        compInfo, '0', [], subcktName, [])
-    # print "All nodes in the netlist :node---------------->",node
-    # print "NodeDic which will be used for modelica
-    # : nodeDic------------->",nodeDic
-    # print "PinInit-------------->",pinInit
-    # print "pinProtectedInit----------->",pinProtectedInit
-
-    modelicaCompInit, numNodesSub = obj_NgMoConverter.compInit(
-        compInfo,
-        node,
-        modelInfo,
-        subcktName,
-        dir_name,
-        transInfo,
-        inbuiltModelDict
-    )
-    # print "ModelicaComponents
-    # : modelicaCompInit----------->",modelicaCompInit
-    # print "SubcktNumNodes
-    # : numNodesSub---------------->",numNodesSub
-
-    connInfo = obj_NgMoConverter.connectInfo(
-        compInfo, node, nodeDic, numNodesSub, subcktName)
-
-    # print "ConnInfo------------------>",connInfo
-
-    # After Sub Ckt Func
-    if len(subcktName) > 0:
-        data, subOptionInfo, subSchemInfo, subModel, subModelInfo,\
-            subsubName, subParamInfo, modelicaSubCompInit, modelicaSubParam,\
-            nodeSubInterface, nodeSub, nodeDicSub, pinInitSub, connSubInfo = (
-                obj_NgMoConverter.procesSubckt(
-                    subcktName, numNodesSub, dir_name
-                )
-            )  # Adding 'numNodesSub' by Fahim
-
-    # Creating Final Output file
-    newfile = filename.split('.')
-    newfilename = newfile[0]
-    outfile = newfilename + ".mo"
-    out = open(outfile, "w")
-    out.writelines('model ' + os.path.basename(newfilename))
-    out.writelines('\n')
-    if IfMOS == '0':
-        out.writelines('import Modelica.Electrical.*;')
-    elif IfMOS == '1':
-        out.writelines('import BondLib.Electrical.*;')
-        # out.writelines('import Modelica.Electrical.*;')
-    out.writelines('\n')
-
-    for eachline in modelicaParamInit:
-        if len(paramInfo) == 0:
-            continue
-        else:
-            out.writelines(eachline)
-            out.writelines('\n')
-    for eachline in modelicaCompInit:
-        if len(compInfo) == 0:
-            continue
-        else:
-            out.writelines(eachline)
-            out.writelines('\n')
-
-    out.writelines('protected')
-    out.writelines('\n')
-    out.writelines(pinInit)
-    out.writelines('\n')
-    out.writelines('equation')
-    out.writelines('\n')
-
-    for eachline in connInfo:
-        if len(connInfo) == 0:
-            continue
-        else:
-            out.writelines(eachline)
-            out.writelines('\n')
-
-    out.writelines('end ' + os.path.basename(newfilename) + ';')
-    out.writelines('\n')
-
-    out.close()
-
-    os.chdir(cwd)
-
-
-# Call main function
-if __name__ == '__main__':
-    main(sys.argv)
diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py
index f4b3100c..5e98d24a 100644
--- a/src/subcircuit/newSub.py
+++ b/src/subcircuit/newSub.py
@@ -31,7 +31,7 @@ class NewSub(QtGui.QWidget):
         # Checking if Workspace already exist or not
         self.schematic_path = (
             os.path.join(
-                os.path.abspath('..'),
+                os.path.abspath('library'),
                 'SubcircuitLibrary',
                 self.create_schematic))
 
diff --git a/src/subcircuit/openSub.py b/src/subcircuit/openSub.py
index dd6e31ac..6cb4fe3e 100644
--- a/src/subcircuit/openSub.py
+++ b/src/subcircuit/openSub.py
@@ -18,7 +18,7 @@ class openSub(QtGui.QWidget):
     def body(self):
         self.editfile = str(
             QtGui.QFileDialog.getExistingDirectory(
-                None, "Open File", "../SubcircuitLibrary"))
+                None, "Open File", "library/SubcircuitLibrary"))
         if self.editfile:
             self.obj_Appconfig = Appconfig()
             self.obj_Appconfig.current_subcircuit['SubcircuitName'] \
diff --git a/src/subcircuit/uploadSub.py b/src/subcircuit/uploadSub.py
index 4bb8df34..25a6e7d4 100644
--- a/src/subcircuit/uploadSub.py
+++ b/src/subcircuit/uploadSub.py
@@ -7,9 +7,9 @@ import shutil
 
 class UploadSub(QtGui.QWidget):
     """
-    This class contain function for ulaoding subcircuits
-    in Subcircuit library present in src folder.
-        A folder is created in src/SubcircuitLibrary
+    This class contain function for uploading subcircuits
+    in SubcircuitLibrary present in src folder.
+    A folder is created in library/SubcircuitLibrary
     and desired file is moved to that folder.
     """
 
@@ -64,7 +64,9 @@ class UploadSub(QtGui.QWidget):
             return
 
         subcircuit_path = os.path.join(
-            os.path.abspath('..'), 'SubcircuitLibrary', create_subcircuit)
+            os.path.abspath('library'),
+            'SubcircuitLibrary', create_subcircuit
+        )
 
         reply = self.obj_validation.validateNewproj(subcircuit_path)
 
-- 
cgit 


From de3096c51107371de2361921dca8ee785e643fc3 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Sun, 23 Feb 2020 17:06:49 +0530
Subject: revert to xml from json

---
 src/kicadtoNgspice/Analysis.py       | 168 +++++------
 src/kicadtoNgspice/DeviceModel.py    |  87 +++---
 src/kicadtoNgspice/KicadtoNgspice.py | 566 ++++++++++++++++++++---------------
 src/kicadtoNgspice/Model.py          |  49 ++-
 src/kicadtoNgspice/Source.py         | 122 +++-----
 src/kicadtoNgspice/SubcircuitTab.py  |  31 +-
 src/modelEditor/ModelEditor.py       |   1 -
 7 files changed, 522 insertions(+), 502 deletions(-)

(limited to 'src')

diff --git a/src/kicadtoNgspice/Analysis.py b/src/kicadtoNgspice/Analysis.py
index 9e91cca9..da030153 100644
--- a/src/kicadtoNgspice/Analysis.py
+++ b/src/kicadtoNgspice/Analysis.py
@@ -1,7 +1,7 @@
 from PyQt4 import QtGui, QtCore
 from . import TrackWidget
 import os
-import json
+from xml.etree import ElementTree as ET
 
 
 class Analysis(QtGui.QWidget):
@@ -198,7 +198,7 @@ class Analysis(QtGui.QWidget):
         - 3 radio buttons - Lin | Dec | Oct
         - 3 input boxes, with top 2 combos
         - If previous values exist then fill default values from
-          previous value json file
+          previous value xml file
         """
         kicadFile = self.clarg1
         (projpath, filename) = os.path.split(kicadFile)
@@ -210,13 +210,16 @@ class Analysis(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "analysis":
+                    root = child
         except BaseException:
             check = 0
-            print("AC Previous Values JSON is Empty")
+            print("AC Previous Values XML is Empty")
 
         self.acbox = QtGui.QGroupBox()
         self.acbox.setTitle("AC Analysis")
@@ -274,8 +277,7 @@ class Analysis(QtGui.QWidget):
 
         # Try setting to default value from anaylsis file
         try:
-            self.ac_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["ac"]["Start Fre Combo"])
+            self.ac_parameter[self.parameter_cnt] = str(root[0][6].text)
         except BaseException:
             self.ac_parameter[self.parameter_cnt] = "Hz"
 
@@ -294,8 +296,7 @@ class Analysis(QtGui.QWidget):
         self.ac_parameter[1] = "Hz"
 
         try:
-            self.ac_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["ac"]["Stop Fre Combo"])
+            self.ac_parameter[self.parameter_cnt] = str(root[0][7].text)
         except BaseException:
             self.ac_parameter[self.parameter_cnt] = "Hz"
 
@@ -313,36 +314,29 @@ class Analysis(QtGui.QWidget):
         ")
         if check:
             try:
-                if json_data["analysis"]["ac"]["Lin"] == "true":
+                if root[0][0].text == "true":
                     self.Lin.setChecked(True)
                     self.Dec.setChecked(False)
                     self.Oct.setChecked(False)
-                elif json_data["analysis"]["ac"]["Dec"] == "true":
+                elif root[0][1].text == "true":
                     self.Lin.setChecked(False)
                     self.Dec.setChecked(True)
                     self.Oct.setChecked(False)
-                elif json_data["analysis"]["ac"]["Oct"] == "true":
+                elif root[0][2].text == "true":
                     self.Lin.setChecked(False)
                     self.Dec.setChecked(False)
                     self.Oct.setChecked(True)
-                else:
-                    pass
-
-                self.ac_entry_var[0].setText(
-                    json_data["analysis"]["ac"]["Start Frequency"])
-                self.ac_entry_var[1].setText(
-                    json_data["analysis"]["ac"]["Stop Frequency"])
-                self.ac_entry_var[2].setText(
-                    json_data["analysis"]["ac"]["No. of points"])
-                index = self.start_fre_combo.findText(
-                    json_data["analysis"]["ac"]["Start Fre Combo"])
+
+                self.ac_entry_var[0].setText(root[0][3].text)
+                self.ac_entry_var[1].setText(root[0][4].text)
+                self.ac_entry_var[2].setText(root[0][5].text)
+                index = self.start_fre_combo.findText(root[0][6].text)
                 self.start_fre_combo.setCurrentIndex(index)
-                index = self.stop_fre_combo.findText(
-                    json_data["analysis"]["ac"]["Stop Fre Combo"])
+                index = self.stop_fre_combo.findText(root[0][7].text)
                 self.stop_fre_combo.setCurrentIndex(index)
 
             except BaseException:
-                print("AC Analysis JSON Parse Error")
+                print("AC Analysis XML Parse Error")
 
         return self.acbox
 
@@ -402,13 +396,16 @@ class Analysis(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "analysis":
+                    root = child
         except BaseException:
             check = 0
-            print("DC Previous Values JSON is empty")
+            print("DC Previous Values XML is empty")
 
         self.dcbox = QtGui.QGroupBox()
         self.dcbox.setTitle("DC Analysis")
@@ -497,8 +494,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.start_combo, 2, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Start Combo"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][5].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -515,8 +511,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.increment_combo, 3, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Increment Combo"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][6].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -533,8 +528,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.stop_combo, 4, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Stop Combo"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][7].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -551,8 +545,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.start_combo2, 6, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Start Combo2"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][12].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -569,8 +562,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.increment_combo2, 7, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Increment Combo2"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][13].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -588,8 +580,7 @@ class Analysis(QtGui.QWidget):
         self.dcgrid.addWidget(self.stop_combo2, 8, 2)
 
         try:
-            self.dc_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["dc"]["Stop Combo2"])
+            self.dc_parameter[self.parameter_cnt] = str(root[1][14].text)
         except BaseException:
             self.dc_parameter[self.parameter_cnt] = "Volts or Amperes"
 
@@ -599,7 +590,7 @@ class Analysis(QtGui.QWidget):
         self.check = QtGui.QCheckBox('Operating Point Analysis', self)
         try:
             self.track_obj.op_check.append(
-                str(json_data["analysis"]["dc"]["Operating Point"]))
+                str(root[1][4].text()))
         except BaseException:
             self.track_obj.op_check.append('0')
 
@@ -621,47 +612,33 @@ class Analysis(QtGui.QWidget):
         ")
         if check:
             try:
-                self.dc_entry_var[0].setText(
-                    json_data["analysis"]["dc"]["Source 1"])
-                self.dc_entry_var[1].setText(
-                    json_data["analysis"]["dc"]["Start"])
-                self.dc_entry_var[2].setText(
-                    json_data["analysis"]["dc"]["Increment"])
-                self.dc_entry_var[3].setText(
-                    json_data["analysis"]["dc"]["Stop"])
-                index = self.start_combo.findText(
-                    json_data["analysis"]["dc"]["Start Combo"])
+                self.dc_entry_var[0].setText(root[1][0].text)
+                self.dc_entry_var[1].setText(root[1][1].text)
+                self.dc_entry_var[2].setText(root[1][2].text)
+                self.dc_entry_var[3].setText(root[1][3].text)
+                index = self.start_combo.findText(root[1][5].text)
                 self.start_combo.setCurrentIndex(index)
-                index = self.increment_combo.findText(
-                    json_data["analysis"]["dc"]["Increment Combo"])
+                index = self.increment_combo.findText(root[1][6].text)
                 self.increment_combo.setCurrentIndex(index)
-                index = self.stop_combo.findText(
-                    json_data["analysis"]["dc"]["Stop Combo"])
+                index = self.stop_combo.findText(root[1][7].text)
                 self.stop_combo.setCurrentIndex(index)
-                self.dc_entry_var[4].setText(
-                    json_data["analysis"]["dc"]["Source 2"])
-                self.dc_entry_var[5].setText(
-                    json_data["analysis"]["dc"]["Start2"])
-                self.dc_entry_var[6].setText(
-                    json_data["analysis"]["dc"]["Increment2"])
-                self.dc_entry_var[7].setText(
-                    json_data["analysis"]["dc"]["Stop2"])
-                index = self.start_combo2.findText(
-                    json_data["analysis"]["dc"]["Start Combo2"])
+                self.dc_entry_var[4].setText(root[1][8].text)
+                self.dc_entry_var[5].setText(root[1][9].text)
+                self.dc_entry_var[6].setText(root[1][10].text)
+                self.dc_entry_var[7].setText(root[1][11].text)
+                index = self.start_combo2.findText(root[1][12].text)
                 self.start_combo2.setCurrentIndex(index)
-                index = self.increment_combo2.findText(
-                    json_data["analysis"]["dc"]["Increment Combo2"])
+                index = self.increment_combo2.findText(root[1][13].text)
                 self.increment_combo2.setCurrentIndex(index)
-                index = self.stop_combo2.findText(
-                    json_data["analysis"]["dc"]["Stop Combo2"])
+                index = self.stop_combo2.findText(root[1][14].text)
                 self.stop_combo2.setCurrentIndex(index)
 
-                if json_data["analysis"]["dc"]["Operating Point"] == 1:
+                if root[1][4].text == 1:
                     self.check.setChecked(True)
                 else:
                     self.check.setChecked(False)
             except BaseException:
-                print("DC Analysis JSON Parse Error")
+                print("DC Analysis XML Parse Error")
 
         return self.dcbox
 
@@ -719,17 +696,21 @@ class Analysis(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "analysis":
+                    root = child
         except BaseException:
             check = 0
-            print("Transient Previous Values JSON is Empty")
+            print("Transient Previous Values XML is Empty")
 
         self.trbox = QtGui.QGroupBox()
         self.trbox.setTitle("Transient Analysis")
         # self.trbox.setDisabled(True)
+        # self.trbox.setVisible(False)
         self.trgrid = QtGui.QGridLayout()
         self.trbox.setLayout(self.trgrid)
 
@@ -745,12 +726,10 @@ class Analysis(QtGui.QWidget):
         self.trgrid.addWidget(self.tran_entry_var[self.count], 1, 1)
         self.tran_entry_var[self.count].setMaximumWidth(150)
         self.count += 1
-
         self.tran_entry_var[self.count] = QtGui.QLineEdit()
         self.trgrid.addWidget(self.tran_entry_var[self.count], 2, 1)
         self.tran_entry_var[self.count].setMaximumWidth(150)
         self.count += 1
-
         self.tran_entry_var[self.count] = QtGui.QLineEdit()
         self.trgrid.addWidget(self.tran_entry_var[self.count], 3, 1)
         self.tran_entry_var[self.count].setMaximumWidth(150)
@@ -766,8 +745,7 @@ class Analysis(QtGui.QWidget):
         self.trgrid.addWidget(self.start_combobox, 1, 3)
 
         try:
-            self.tran_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["tran"]["Start Combo"])
+            self.tran_parameter[self.parameter_cnt] = str(root[2][3].text)
         except BaseException:
             self.tran_parameter[self.parameter_cnt] = "Sec"
 
@@ -782,8 +760,7 @@ class Analysis(QtGui.QWidget):
         self.step_combobox.addItem("ps")
         self.trgrid.addWidget(self.step_combobox, 2, 3)
         try:
-            self.tran_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["tran"]["Step Combo"])
+            self.tran_parameter[self.parameter_cnt] = str(root[2][4].text)
         except BaseException:
             self.tran_parameter[self.parameter_cnt] = "Sec"
 
@@ -798,8 +775,7 @@ class Analysis(QtGui.QWidget):
         self.stop_combobox.addItem("ps")
         self.trgrid.addWidget(self.stop_combobox, 3, 3)
         try:
-            self.tran_parameter[self.parameter_cnt] = str(
-                json_data["analysis"]["tran"]["Stop Combo"])
+            self.tran_parameter[self.parameter_cnt] = str(root[2][5].text)
         except BaseException:
             self.tran_parameter[self.parameter_cnt] = "Sec"
 
@@ -818,23 +794,17 @@ class Analysis(QtGui.QWidget):
         ")
         if check:
             try:
-                self.tran_entry_var[0].setText(
-                    json_data["analysis"]["tran"]["Start Time"])
-                self.tran_entry_var[1].setText(
-                    json_data["analysis"]["tran"]["Step Time"])
-                self.tran_entry_var[2].setText(
-                    json_data["analysis"]["tran"]["Stop Time"])
-                index = self.start_combobox.findText(
-                    json_data["analysis"]["tran"]["Start Combo"])
+                self.tran_entry_var[0].setText(root[2][0].text)
+                self.tran_entry_var[1].setText(root[2][1].text)
+                self.tran_entry_var[2].setText(root[2][2].text)
+                index = self.start_combobox.findText(root[2][3].text)
                 self.start_combobox.setCurrentIndex(index)
-                index = self.step_combobox.findText(
-                    json_data["analysis"]["tran"]["Step Combo"])
+                index = self.step_combobox.findText(root[2][4].text)
                 self.step_combobox.setCurrentIndex(index)
-                index = self.stop_combobox.findText(
-                    json_data["analysis"]["tran"]["Stop Combo"])
+                index = self.stop_combobox.findText(root[2][5].text)
                 self.stop_combobox.setCurrentIndex(index)
             except BaseException:
-                print("Transient Analysis JSON Parse Error")
+                print("Transient Analysis XML Parse Error")
 
         return self.trbox
 
diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py
index 65e09753..d548f289 100644
--- a/src/kicadtoNgspice/DeviceModel.py
+++ b/src/kicadtoNgspice/DeviceModel.py
@@ -1,6 +1,6 @@
 from PyQt4 import QtGui
 import os
-import json
+from xml.etree import ElementTree as ET
 from . import TrackWidget
 
 
@@ -32,12 +32,15 @@ class DeviceModel(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "devicemodel":
+                    root = child
         except BaseException:
-            print("Device Model Previous JSON is Empty")
+            print("Device Model Previous XML is Empty")
 
         QtGui.QWidget.__init__(self)
 
@@ -82,16 +85,16 @@ class DeviceModel(QtGui.QWidget):
                 global path_name
 
                 try:
-                    for key in json_data["deviceModel"]:
-                        if key == words[0]:
+                    for child in root:
+                        if child.tag[0] == eachline[0] \
+                                and child.tag[1] == eachline[1]:
+                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
+                            #       child.tag[1], eachline[0], eachline[1])
                             try:
-                                if os.path.exists(
-                                        json_data["deviceModel"][key][0]):
-                                    self.entry_var[self.count].setText(
-                                        json_data["deviceModel"][key][0])
-                                    path_name = (
-                                        json_data["deviceModel"][key][0]
-                                    )
+                                if os.path.exists(child[0].text):
+                                    self.entry_var[self.count] \
+                                        .setText(child[0].text)
+                                    path_name = child[0].text
                                 else:
                                     self.entry_var[self.count].setText("")
                             except BaseException:
@@ -146,16 +149,16 @@ class DeviceModel(QtGui.QWidget):
                 self.entry_var[self.count].setText("")
                 # global path_name
                 try:
-                    for key in json_data["deviceModel"]:
-                        if key == words[0]:
+                    for child in root:
+                        if child.tag[0] == eachline[0] \
+                                and child.tag[1] == eachline[1]:
+                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
+                            #  child.tag[1], eachline[0], eachline[1])
                             try:
-                                if os.path.exists(
-                                        json_data["deviceModel"][key][0]):
-                                    path_name = (
-                                        json_data["deviceModel"][key][0]
-                                    )
-                                    self.entry_var[self.count].setText(
-                                        json_data["deviceModel"][key][0])
+                                if os.path.exists(child[0].text):
+                                    path_name = child[0].text
+                                    self.entry_var[self.count] \
+                                        .setText(child[0].text)
                                 else:
                                     self.entry_var[self.count].setText("")
                             except BaseException:
@@ -209,16 +212,16 @@ class DeviceModel(QtGui.QWidget):
                 self.entry_var[self.count].setText("")
                 # global path_name
                 try:
-                    for key in json_data["deviceModel"]:
-                        if key == words[0]:
+                    for child in root:
+                        if child.tag[0] == eachline[0] \
+                                and child.tag[1] == eachline[1]:
+                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
+                            #       child.tag[1], eachline[0], eachline[1])
                             try:
-                                if os.path.exists(
-                                        json_data["deviceModel"][key][0]):
-                                    self.entry_var[self.count].setText(
-                                        json_data["deviceModel"][key][0])
-                                    path_name = (
-                                        json_data["deviceModel"][key][0]
-                                    )
+                                if os.path.exists(child[0].text):
+                                    self.entry_var[self.count] \
+                                        .setText(child[0].text)
+                                    path_name = child[0].text
                                 else:
                                     self.entry_var[self.count].setText("")
                             except BaseException:
@@ -319,19 +322,21 @@ class DeviceModel(QtGui.QWidget):
                 self.devicemodel_dict_end[words[0]] = self.count
                 self.count = self.count + 1
                 mosfetbox.setLayout(mosfetgrid)
+
                 # global path_name
                 try:
-                    for key in json_data["deviceModel"]:
-                        if key == words[0]:
+                    for child in root:
+                        if child.tag[0] == eachline[0] \
+                                and child.tag[1] == eachline[1]:
+                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
+                            #       child.tag[1], eachline[0], eachline[1])
                             while i <= end:
-                                self.entry_var[i].setText(
-                                    json_data["deviceModel"][key][i - beg])
+                                self.entry_var[i].setText(child[i-beg].text)
                                 if (i - beg) == 0:
-                                    if os.path.exists(
-                                            json_data["deviceModel"][key][0]):
-                                        path_name = (
-                                            json_data["deviceModel"][key][0]
-                                        )
+                                    if os.path.exists(child[0].text):
+                                        self.entry_var[i] \
+                                            .setText(child[i-beg].text)
+                                        path_name = child[i-beg].text
                                     else:
                                         self.entry_var[i].setText("")
                                 i = i + 1
diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index 18701c43..8a4d746d 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -27,7 +27,7 @@ from . import DeviceModel
 from . import SubcircuitTab
 from . import Convert
 from . import TrackWidget
-import json
+from xml.etree import ElementTree as ET
 
 
 class MainWindow(QtGui.QWidget):
@@ -44,7 +44,7 @@ class MainWindow(QtGui.QWidget):
     def __init__(self, clarg1, clarg2=None):
         QtGui.QWidget.__init__(self)
         print("==================================")
-        print("Kicad to Ngspice netlist converter ")
+        print("Kicad to Ngspice netlist converter")
         print("==================================")
         global kicadNetlist, schematicInfo
         global infoline, optionInfo
@@ -232,8 +232,8 @@ class MainWindow(QtGui.QWidget):
         """
         - This function called when convert button clicked
         - Extracting data from the objs created above
-        - Pushing this data to json, and dumping it finally
-        - Written to a ..._Previous_Values.json file in the projDirectory
+        - Pushing this data to xml, and writing it finally
+        - Written to a ..._Previous_Values.xml file in the projDirectory
         - Finally, call createNetListFile, with the converted schematic
         """
         global schematicInfo
@@ -242,294 +242,366 @@ class MainWindow(QtGui.QWidget):
         store_schematicInfo = list(schematicInfo)
         (projpath, filename) = os.path.split(self.kicadFile)
         project_name = os.path.basename(projpath)
+        check = 1
+
+        try:
+            fr = open(
+                    os.path.join(
+                        projpath, project_name + "_Previous_Values.xml"), 'r'
+                )
+            temp_tree = ET.parse(fr)
+            temp_root = temp_tree.getroot()
+        except BaseException:
+            check = 0
 
         # Opening previous value file pertaining to the selected project
         fw = open(
             os.path.join(
                 projpath,
                 project_name +
-                "_Previous_Values.json"),
+                "_Previous_Values.xml"),
             'w')
 
-        # Creating a dictionary to map the json data
-        json_data = {}
+        if check == 0:
+            attr_parent = ET.Element("KicadtoNgspice")
+        if check == 1:
+            attr_parent = temp_root
 
-        # Writing analysis values
-        json_data["analysis"] = {}
+        for child in attr_parent:
+            if child.tag == "analysis":
+                attr_parent.remove(child)
+
+        attr_analysis = ET.SubElement(attr_parent, "analysis")
+        attr_ac = ET.SubElement(attr_analysis, "ac")
 
-        json_data["analysis"]["ac"] = {}
         if obj_analysis.Lin.isChecked():
-            json_data["analysis"]["ac"]["Lin"] = "true"
-            json_data["analysis"]["ac"]["Dec"] = "false"
-            json_data["analysis"]["ac"]["Oct"] = "false"
+            ET.SubElement(attr_ac, "field1", name="Lin").text = "true"
+            ET.SubElement(attr_ac, "field2", name="Dec").text = "false"
+            ET.SubElement(attr_ac, "field3", name="Oct").text = "false"
         elif obj_analysis.Dec.isChecked():
-            json_data["analysis"]["ac"]["Lin"] = "false"
-            json_data["analysis"]["ac"]["Dec"] = "true"
-            json_data["analysis"]["ac"]["Oct"] = "false"
+            ET.SubElement(attr_ac, "field1", name="Lin").text = "false"
+            ET.SubElement(attr_ac, "field2", name="Dec").text = "true"
+            ET.SubElement(attr_ac, "field3", name="Oct").text = "false"
         if obj_analysis.Oct.isChecked():
-            json_data["analysis"]["ac"]["Lin"] = "false"
-            json_data["analysis"]["ac"]["Dec"] = "false"
-            json_data["analysis"]["ac"]["Oct"] = "true"
-
-        json_data["analysis"]["ac"]["Start Frequency"] = str(
-            obj_analysis.ac_entry_var[0].text())
-        json_data["analysis"]["ac"]["Stop Frequency"] = str(
-            obj_analysis.ac_entry_var[1].text())
-        json_data["analysis"]["ac"]["No. of points"] = str(
-            obj_analysis.ac_entry_var[2].text())
-        json_data["analysis"]["ac"]["Start Fre Combo"] = (
-            obj_analysis.ac_parameter[0]
-        )
-        json_data["analysis"]["ac"]["Stop Fre Combo"] = (
-            obj_analysis.ac_parameter[1]
-        )
-
-        json_data["analysis"]["dc"] = {}
-        json_data["analysis"]["dc"]["Source 1"] = str(
-            obj_analysis.dc_entry_var[0].text())
-        json_data["analysis"]["dc"]["Start"] = str(
-            obj_analysis.dc_entry_var[1].text())
-        json_data["analysis"]["dc"]["Increment"] = str(
-            obj_analysis.dc_entry_var[2].text())
-        json_data["analysis"]["dc"]["Stop"] = str(
-            obj_analysis.dc_entry_var[3].text())
-        json_data["analysis"]["dc"]["Operating Point"] = str(
-            self.obj_track.op_check[-1])
-        json_data["analysis"]["dc"]["Start Combo"] = (
-            obj_analysis.dc_parameter[0]
-        )
-        json_data["analysis"]["dc"]["Increment Combo"] = (
-            obj_analysis.dc_parameter[1]
-        )
-        json_data["analysis"]["dc"]["Stop Combo"] = (
-            obj_analysis.dc_parameter[2]
-        )
-        json_data["analysis"]["dc"]["Source 2"] = str(
-            obj_analysis.dc_entry_var[4].text())
-        json_data["analysis"]["dc"]["Start2"] = str(
-            obj_analysis.dc_entry_var[5].text())
-        json_data["analysis"]["dc"]["Increment2"] = str(
-            obj_analysis.dc_entry_var[6].text())
-        json_data["analysis"]["dc"]["Stop2"] = str(
-            obj_analysis.dc_entry_var[7].text())
-        json_data["analysis"]["dc"]["Start Combo2"] = (
-            obj_analysis.dc_parameter[3]
-        )
-        json_data["analysis"]["dc"]["Increment Combo2"] = (
-            obj_analysis.dc_parameter[4]
-        )
-        json_data["analysis"]["dc"]["Stop Combo2"] = (
-            obj_analysis.dc_parameter[5]
-        )
-
-        json_data["analysis"]["tran"] = {}
-        json_data["analysis"]["tran"]["Start Time"] = str(
-            obj_analysis.tran_entry_var[0].text())
-        json_data["analysis"]["tran"]["Step Time"] = str(
-            obj_analysis.tran_entry_var[1].text())
-        json_data["analysis"]["tran"]["Stop Time"] = str(
-            obj_analysis.tran_entry_var[2].text())
-        json_data["analysis"]["tran"]["Start Combo"] = (
-            obj_analysis.tran_parameter[0]
-        )
-        json_data["analysis"]["tran"]["Step Combo"] = (
-            obj_analysis.tran_parameter[1]
-        )
-        json_data["analysis"]["tran"]["Stop Combo"] = (
-            obj_analysis.tran_parameter[2]
-        )
+            ET.SubElement(attr_ac, "field1", name="Lin").text = "false"
+            ET.SubElement(attr_ac, "field2", name="Dec").text = "false"
+            ET.SubElement(attr_ac, "field3", name="Oct").text = "true"
+
+        ET.SubElement(
+            attr_ac, "field4", name="Start Frequency"
+        ).text = str(obj_analysis.ac_entry_var[0].text())
+        ET.SubElement(
+            attr_ac, "field5", name="Stop Frequency"
+        ).text = str(obj_analysis.ac_entry_var[1].text())
+        ET.SubElement(
+            attr_ac, "field6", name="No. of points"
+        ).text = str(obj_analysis.ac_entry_var[2].text())
+        ET.SubElement(
+            attr_ac, "field7", name="Start Fre Combo"
+        ).text = obj_analysis.ac_parameter[0]
+        ET.SubElement(
+            attr_ac, "field8", name="Stop Fre Combo"
+        ).text = obj_analysis.ac_parameter[1]
+
+        attr_dc = ET.SubElement(attr_analysis, "dc")
+
+        ET.SubElement(
+            attr_dc, "field1", name="Source 1"
+        ).text = str(obj_analysis.dc_entry_var[0].text())
+        ET.SubElement(
+            attr_dc, "field2", name="Start"
+        ).text = str(obj_analysis.dc_entry_var[1].text())
+        ET.SubElement(
+            attr_dc, "field3", name="Increment"
+        ).text = str(obj_analysis.dc_entry_var[2].text())
+        ET.SubElement(
+            attr_dc, "field4", name="Stop"
+        ).text = str(obj_analysis.dc_entry_var[3].text())
+        # print("OBJ_ANALYSIS.CHECK -----", self.obj_track.op_check[-1])
+        ET.SubElement(
+            attr_dc, "field5", name="Operating Point"
+        ).text = str(self.obj_track.op_check[-1])
+        ET.SubElement(
+            attr_dc, "field6", name="Start Combo"
+        ).text = obj_analysis.dc_parameter[0]
+        ET.SubElement(
+            attr_dc, "field7", name="Increment Combo"
+        ).text = obj_analysis.dc_parameter[1]
+        ET.SubElement(
+            attr_dc, "field8", name="Stop Combo"
+        ).text = obj_analysis.dc_parameter[2]
+        ET.SubElement(
+            attr_dc, "field9", name="Source 2"
+        ).text = str(obj_analysis.dc_entry_var[4].text())
+        ET.SubElement(
+            attr_dc, "field10", name="Start"
+        ).text = str(obj_analysis.dc_entry_var[5].text())
+        ET.SubElement(
+            attr_dc, "field11", name="Increment"
+        ).text = str(obj_analysis.dc_entry_var[6].text())
+        ET.SubElement(
+            attr_dc, "field12", name="Stop"
+        ).text = str(obj_analysis.dc_entry_var[7].text())
+        ET.SubElement(
+            attr_dc, "field13", name="Start Combo"
+        ).text = obj_analysis.dc_parameter[3]
+        ET.SubElement(
+            attr_dc, "field14", name="Increment Combo"
+        ).text = obj_analysis.dc_parameter[4]
+        ET.SubElement(
+            attr_dc, "field15", name="Stop Combo"
+        ).text = obj_analysis.dc_parameter[5]
+
+        attr_tran = ET.SubElement(attr_analysis, "tran")
+        ET.SubElement(
+            attr_tran, "field1", name="Start Time"
+        ).text = str(obj_analysis.tran_entry_var[0].text())
+        ET.SubElement(
+            attr_tran, "field2", name="Step Time"
+        ).text = str(obj_analysis.tran_entry_var[1].text())
+        ET.SubElement(
+            attr_tran, "field3", name="Stop Time"
+        ).text = str(obj_analysis.tran_entry_var[2].text())
+        ET.SubElement(
+            attr_tran, "field4", name="Start Combo"
+        ).text = obj_analysis.tran_parameter[0]
+        ET.SubElement(
+            attr_tran, "field5", name="Step Combo"
+        ).text = obj_analysis.tran_parameter[1]
+        ET.SubElement(
+            attr_tran, "field6", name="Stop Combo"
+        ).text = obj_analysis.tran_parameter[2]
+        # print("TRAN PARAMETER 2-----",obj_analysis.tran_parameter[2])
+
+        if check == 0:
+            attr_source = ET.SubElement(attr_parent, "source")
+        if check == 1:
+            for child in attr_parent:
+                if child.tag == "source":
+                    attr_source = child
 
-        # Writing source values
-        json_data["source"] = {}
         count = 1
+        grand_child_count = 1
 
-        for line in store_schematicInfo:
-            words = line.split(' ')
+        for i in store_schematicInfo:
+            tmp_check = 0
+            words = i.split(' ')
             wordv = words[0]
-
-            if wordv[0] == "v" or wordv[0] == "i":
-                json_data["source"][wordv] = {}
-                json_data["source"][wordv]["type"] = words[len(words) - 1]
-                json_data["source"][wordv]["values"] = []
-
-            if words[len(words) - 1] == "ac":
-                amp = {"Amplitude": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(amp)
-
-                phase = {"Phase": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(phase)
-
-            elif words[len(words) - 1] == "dc":
-                value = {"Value": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(value)
-
-            elif words[len(words) - 1] == "sine":
-                offset = {
-                    "Offset Value": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(offset)
-
-                amp = {"Amplitude": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(amp)
-
-                freq = {"Freuency": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(freq)
-
-                delay = {"Delay Time": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(delay)
-
-                damp = {
-                    "Damping Factor": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(damp)
-
-            elif words[len(words) - 1] == "pulse":
-                initial = {
-                    "Initial Value": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(initial)
-
-                pulse = {
-                    "Pulse Value": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(pulse)
-
-                delay = {"Delay Time": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(delay)
-
-                rise = {"Rise Time": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(rise)
-
-                fall = {"Fall Time": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(fall)
-
-                width = {
-                    "Pulse width": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(width)
-
-                period = {"Period": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(period)
-
-            elif words[len(words) - 1] == "pwl":
-                pwl = {
-                    "Enter in pwl format": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(pwl)
-
-            elif words[len(words) - 1] == "exp":
-                initial = {
-                    "Initial Value": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(initial)
-
-                pulsed = {
-                    "Pulsed Value": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(pulsed)
-
-                rise = {
-                    "Rise Delay Time": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(rise)
-
-                fall = {"Fall Time": str(obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(fall)
-
-                fallConstant = {
-                    "Fall Time Constant": str(
-                        obj_source.entry_var[count].text())}
-                count += 1
-                json_data["source"][wordv]["values"].append(fallConstant)
-
-            else:
-                pass
-
-        # Writing Model values
-
+            for child in attr_source:
+                if child.tag == wordv and child.text == words[len(words) - 1]:
+                    tmp_check = 1
+                    for grand_child in child:
+                        grand_child.text = \
+                            str(obj_source.entry_var[grand_child_count].text())
+                        grand_child_count += 1
+                    grand_child_count += 1
+            if tmp_check == 0:
+                words = i.split(' ')
+                wordv = words[0]
+                if wordv[0] == "v" or wordv[0] == "i":
+                    attr_var = ET.SubElement(
+                        attr_source, words[0], name="Source type"
+                    )
+                    attr_var.text = words[len(words) - 1]
+                    # ET.SubElement(
+                    #     attr_ac, "field1", name="Lin").text = "true"
+                if words[len(words) - 1] == "ac":
+                    # attr_ac = ET.SubElement(attr_var, "ac")
+                    ET.SubElement(
+                        attr_var, "field1", name="Amplitude"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field2", name="Phase"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+                elif words[len(words) - 1] == "dc":
+                    # attr_dc = ET.SubElement(attr_var, "dc")
+                    ET.SubElement(
+                        attr_var, "field1", name="Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+                elif words[len(words) - 1] == "sine":
+                    # attr_sine = ET.SubElement(attr_var, "sine")
+                    ET.SubElement(
+                        attr_var, "field1", name="Offset Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field2", name="Amplitude"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field3", name="Frequency"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field4", name="Delay Time"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field5", name="Damping Factor"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+                elif words[len(words) - 1] == "pulse":
+                    # attr_pulse=ET.SubElement(attr_var,"pulse")
+                    ET.SubElement(
+                        attr_var, "field1", name="Initial Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field2", name="Pulse Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field3", name="Delay Time"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field4", name="Rise Time"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field5", name="Fall Time"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field5", name="Pulse width"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field5", name="Period"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+                elif words[len(words) - 1] == "pwl":
+                    # attr_pwl=ET.SubElement(attr_var,"pwl")
+                    ET.SubElement(
+                        attr_var, "field1", name="Enter in pwl format"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+                elif words[len(words) - 1] == "exp":
+                    # attr_exp=ET.SubElement(attr_var,"exp")
+                    ET.SubElement(
+                        attr_var, "field1", name="Initial Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field2", name="Pulsed Value"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field3", name="Rise Delay Time"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field4", name="Rise Time Constant"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field5", name="Fall TIme"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 1
+                    ET.SubElement(
+                        attr_var, "field6", name="Fall Time Constant"
+                    ).text = str(obj_source.entry_var[count].text())
+                    count += 2
+
+        if check == 0:
+            attr_model = ET.SubElement(attr_parent, "model")
+        if check == 1:
+            for child in attr_parent:
+                if child.tag == "model":
+                    attr_model = child
         i = 0
-        json_data["model"] = {}
+
+        # tmp_check is a variable to check for duplicates in the xml file
+        tmp_check = 0
+        # tmp_i is the iterator in case duplicates are there;
+        # then in that case we need to replace only the child node and
+        # not create a new parent node
 
         for line in modelList:
+            tmp_check = 0
             for rand_itr in obj_model.obj_trac.modelTrack:
                 if rand_itr[2] == line[2] and rand_itr[3] == line[3]:
                     start = rand_itr[7]
                     end = rand_itr[8]
-            i = start
 
-            json_data["model"][line[3]] = {}
-            json_data["model"][line[3]]["type"] = line[2]
-            json_data["model"][line[3]]["values"] = []
-
-            for key, value in line[7].items():
-                if(
-                    hasattr(value, '__iter__') and
-                    i <= end and not isinstance(value, str)
-                ):
-                    for item in value:
-                        fields = {
-                            item: str(
-                                obj_model.obj_trac.model_entry_var[i].text())}
-                        json_data["model"][line[3]]["values"].append(fields)
+            i = start
+            for child in attr_model:
+                if child.text == line[2] and child.tag == line[3]:
+                    for grand_child in child:
+                        if i <= end:
+                            grand_child.text = \
+                              str(obj_model.obj_trac.model_entry_var[i].text())
+                            i = i + 1
+                    tmp_check = 1
+
+            if tmp_check == 0:
+                attr_ui = ET.SubElement(attr_model, line[3], name="type")
+                attr_ui.text = line[2]
+                for key, value in line[7].items():
+                    if(
+                        hasattr(value, '__iter__') and
+                        i <= end and not isinstance(value, str)
+                    ):
+                        for item in value:
+                            ET.SubElement(
+                                attr_ui, "field" + str(i + 1), name=item
+                            ).text = str(
+                                  obj_model.obj_trac.model_entry_var[i].text()
+                                )
+                            i = i + 1
+
+                    else:
+                        ET.SubElement(
+                            attr_ui, "field" + str(i + 1), name=value
+                        ).text = str(
+                                obj_model.obj_trac.model_entry_var[i].text()
+                            )
                         i = i + 1
 
-                else:
-                    fields = {
-                        value: str(
-                            obj_model.obj_trac.model_entry_var[i].text())}
-                    json_data["model"][line[3]]["values"].append(fields)
-                    i = i + 1
-
         # Writing Device Model values
-
-        json_data["deviceModel"] = {}
+        if check == 0:
+            attr_devicemodel = ET.SubElement(attr_parent, "devicemodel")
+        if check == 1:
+            for child in attr_parent:
+                if child.tag == "devicemodel":
+                    del child[:]
+                    attr_devicemodel = child
 
         for device in obj_devicemodel.devicemodel_dict_beg:
-            json_data["deviceModel"][device] = []
+            attr_var = ET.SubElement(attr_devicemodel, device)
             it = obj_devicemodel.devicemodel_dict_beg[device]
             end = obj_devicemodel.devicemodel_dict_end[device]
 
             while it <= end:
-                json_data["deviceModel"][device].append(
-                    str(obj_devicemodel.entry_var[it].text()))
+                ET.SubElement(attr_var, "field").text = \
+                        str(obj_devicemodel.entry_var[it].text())
                 it = it + 1
 
         # Writing Subcircuit values
+        if check == 0:
+            attr_subcircuit = ET.SubElement(attr_parent, "subcircuit")
+        if check == 1:
+            for child in attr_parent:
+                if child.tag == "subcircuit":
+                    del child[:]
+                    attr_subcircuit = child
 
-        json_data["subcircuit"] = {}
         for subckt in obj_subcircuitTab.subcircuit_dict_beg:
-            json_data["subcircuit"][subckt] = []
+            attr_var = ET.SubElement(attr_subcircuit, subckt)
             it = obj_subcircuitTab.subcircuit_dict_beg[subckt]
             end = obj_subcircuitTab.subcircuit_dict_end[subckt]
 
             while it <= end:
-                json_data["subcircuit"][subckt].append(
-                    str(obj_subcircuitTab.entry_var[it].text()))
+                ET.SubElement(attr_var, "field").text = \
+                        str(obj_subcircuitTab.entry_var[it].text())
                 it = it + 1
 
-        # json dumped and written to previous value file for the project
-        write_data = json.dumps(json_data)
-        fw.write(write_data)
+        # xml written to previous value file for the project
+        tree = ET.ElementTree(attr_parent)
+        tree.write(fw)
 
         # Create Convert object with the source details & the schematic details
         print("=============================================================")
diff --git a/src/kicadtoNgspice/Model.py b/src/kicadtoNgspice/Model.py
index 3cc3a0cb..6de6d8df 100644
--- a/src/kicadtoNgspice/Model.py
+++ b/src/kicadtoNgspice/Model.py
@@ -1,6 +1,6 @@
 from PyQt4 import QtGui
-import json
 from . import TrackWidget
+from xml.etree import ElementTree as ET
 import os
 
 
@@ -18,18 +18,23 @@ class Model(QtGui.QWidget):
         kicadFile = clarg1
         (projpath, filename) = os.path.split(kicadFile)
         project_name = os.path.basename(projpath)
-
+        check = 1
         try:
             f = open(
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "model":
+                    root = child
+
         except BaseException:
-            print("Model Previous Values JSON is Empty")
+            check = 0
+            print("Model Previous Values XML is Empty")
 
         # Creating track widget object
         self.obj_trac = TrackWidget.TrackWidget()
@@ -73,17 +78,12 @@ class Model(QtGui.QWidget):
                             [self.nextcount], self.nextrow, 1)
 
                         try:
-                            for mod in json_data["model"]:
-                                if json_data["model"][mod]["type"] ==\
-                                        line[2] and mod == line[3]:
-                                    (
-                                        self.obj_trac.model_entry_var
-                                        [self.nextcount].setText(
-                                            str(list(
-                                                json_data
-                                                ["model"][mod]["values"]
-                                                [i].values())[0]))
-                                    )
+                            for child in root:
+                                if child.text == line[2] \
+                                        and child.tag == line[3]:
+                                    self.obj_trac.model_entry_var
+                                    [self.nextcount].setText(
+                                                        str(child[i].text))
                                     i = i + 1
                         except BaseException:
                             pass
@@ -105,20 +105,13 @@ class Model(QtGui.QWidget):
                     )
 
                     try:
-                        for mod in json_data["model"]:
-                            if json_data["model"][mod]["type"] ==\
-                                    line[2] and mod == line[3]:
-                                (
-                                    self.obj_trac.model_entry_var
-                                    [self.nextcount].setText(
-                                        str(list(json_data
-                                                 ["model"][mod]["values"]
-                                                 [i].values())[0]))
-                                )
+                        for child in root:
+                            if child.text == line[2] and child.tag == line[3]:
+                                self.obj_trac.model_entry_var[self.nextcount] \
+                                                .setText(str(child[i].text))
                                 i = i + 1
                     except BaseException:
                         pass
-
                     tag_dict[key] = self.nextcount
                     self.nextcount = self.nextcount + 1
                     self.nextrow = self.nextrow + 1
diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py
index e76118d4..fdcd4adc 100644
--- a/src/kicadtoNgspice/Source.py
+++ b/src/kicadtoNgspice/Source.py
@@ -1,7 +1,7 @@
 import os
 from PyQt4 import QtGui
 from . import TrackWidget
-import json
+from xml.etree import ElementTree as ET
 
 
 class Source(QtGui.QWidget):
@@ -57,16 +57,19 @@ class Source(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
-
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "source":
+                    root = child
         except BaseException:
-            print("Source Previous Values JSON is Empty")
+            print("Source Previous Values XML is Empty")
 
         self.grid = QtGui.QGridLayout()
         self.setLayout(self.grid)
+        xml_num = 0
 
         if sourcelist:
             for line in sourcelist:
@@ -85,34 +88,23 @@ class Source(QtGui.QWidget):
                     self.entry_var[self.count] = QtGui.QLineEdit()
                     self.entry_var[self.count].setMaximumWidth(150)
                     acgrid.addWidget(self.entry_var[self.count], self.row, 1)
-                    self.entry_var[self.count].setText("")
-                    self.count += 1
-
-                    self.entry_var[self.count] = QtGui.QLineEdit()
-                    self.entry_var[self.count].setMaximumWidth(150)
+                    self.entry_var[self.count + 1] = QtGui.QLineEdit()
+                    self.entry_var[self.count + 1].setMaximumWidth(150)
                     acgrid.addWidget(
-                        self.entry_var[self.count], self.row + 1, 1)
+                        self.entry_var[self.count+1], self.row + 1, 1)
                     self.entry_var[self.count].setText("")
-                    self.count += 1
-
+                    self.entry_var[self.count+1].setText("")
                     try:
-                        for key in json_data["source"]:
+                        for child in root:
                             templist1 = line[1]
                             templist2 = templist1.split(' ')
 
-                            if key == templist2[0] and \
-                                    json_data["source"][key]["type"]\
-                                    == line[2]:
-                                self.entry_var[self.count - 2].setText(
-                                    str(
-                                        json_data
-                                        ["source"][key]["values"][0]
-                                        ["Amplitude"]))
-                                self.entry_var[self.count - 1].setText(
-                                    str(
-                                        json_data["source"][key]
-                                        ["values"][1]["Phase"]))
-
+                            if child.tag == templist2[0] and \
+                                    child.text == line[2]:
+                                self.entry_var[self.count] \
+                                    .setText(str(child[0].text))
+                                self.entry_var[self.count + 1] \
+                                    .setText(str(child[1].text))
                     except BaseException:
                         pass
                     # Value Need to check previuouse value
@@ -138,6 +130,7 @@ class Source(QtGui.QWidget):
                     dcbox = QtGui.QGroupBox()
                     dcbox.setTitle(line[3])
                     dcgrid = QtGui.QGridLayout()
+                    self.row = self.row + 1
                     self.start = self.count
                     label = QtGui.QLabel(line[4])
                     dcgrid.addWidget(label, self.row, 0)
@@ -148,18 +141,14 @@ class Source(QtGui.QWidget):
                     self.entry_var[self.count].setText("")
 
                     try:
-                        for key in json_data["source"]:
+                        for child in root:
                             templist1 = line[1]
                             templist2 = templist1.split(' ')
 
-                            if key == templist2[0] and \
-                                    json_data["source"][key]["type"]\
-                                    == line[2]:
-                                self.entry_var[self.count].setText(
-                                    str(
-                                        json_data["source"][key]
-                                        ["values"][0]["Value"]))
-
+                            if child.tag == templist2[0] \
+                                    and child.text == line[2]:
+                                self.entry_var[self.count] \
+                                    .setText(str(child[0].text))
                     except BaseException:
                         pass
 
@@ -197,17 +186,13 @@ class Source(QtGui.QWidget):
                         self.entry_var[self.count].setText("")
 
                         try:
-                            for key in json_data["source"]:
+                            for child in root:
                                 templist1 = line[1]
                                 templist2 = templist1.split(' ')
-                                if key == templist2[0] and \
-                                        json_data["source"][key]["type"]\
-                                        == line[2]:
-                                    self.entry_var[self.count].setText(
-                                        str(
-                                            list(json_data["source"]
-                                                 [key]["values"]
-                                                 [it - 4].values())[0]))
+                                if child.tag == templist2[0] \
+                                        and child.text == line[2]:
+                                    self.entry_var[self.count] \
+                                        .setText(str(child[it-4].text))
                         except BaseException:
                             pass
 
@@ -244,17 +229,13 @@ class Source(QtGui.QWidget):
                         self.entry_var[self.count].setText("")
 
                         try:
-                            for key in json_data["source"]:
+                            for child in root:
                                 templist1 = line[1]
                                 templist2 = templist1.split(' ')
-
-                                if key == templist2[0] and \
-                                        json_data["source"][key]["type"]\
-                                        == line[2]:
-                                    self.entry_var[self.count].setText(
-                                        str(list(
-                                            json_data["source"][key]
-                                            ["values"][it - 4].values())[0]))
+                                if child.tag == templist2[0] \
+                                        and child.text == line[2]:
+                                    self.entry_var[self.count] \
+                                        .setText(str(child[it-4].text))
                         except BaseException:
                             pass
 
@@ -288,15 +269,13 @@ class Source(QtGui.QWidget):
                     self.entry_var[self.count].setText("")
 
                     try:
-                        for key in json_data["source"]:
+                        for child in root:
                             templist1 = line[1]
                             templist2 = templist1.split(' ')
-                            if key == templist2[0] and \
-                                    json_data["source"][key]["type"] \
-                                    == line[2]:
-                                self.entry_var[self.count].setText(
-                                    str(json_data["source"][key]
-                                        ["values"][0]["Enter in pwl format"]))
+                            if child.tag == templist2[0] \
+                                    and child.text == line[2]:
+                                self.entry_var[self.count] \
+                                    .setText(str(child[0].text))
                     except BaseException:
                         pass
 
@@ -333,19 +312,13 @@ class Source(QtGui.QWidget):
                         self.entry_var[self.count].setText("")
 
                         try:
-                            for key in json_data["source"]:
+                            for child in root:
                                 templist1 = line[1]
                                 templist2 = templist1.split(' ')
-                                if key == templist2[0] and \
-                                        json_data["source"][key]["type"]\
-                                        == line[2]:
-                                    self.entry_var[self.count].setText(
-                                        str(
-                                            list(
-                                                json_data["source"][key]
-                                                ["values"][it - 4].values())[0]
-                                        )
-                                    )
+                                if child.tag == templist2[0] \
+                                        and child.text == line[2]:
+                                    self.entry_var[self.count] \
+                                        .setText(str(child[it-4].text))
                         except BaseException:
                             pass
 
@@ -366,6 +339,9 @@ class Source(QtGui.QWidget):
                     sourcelisttrack.append(
                         [track_id, 'exp', self.start, self.end])
 
+                self.count = self.count + 1
+                xml_num = xml_num + 1
+
         else:
             print("No source is present in your circuit")
 
diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py
index 35b876f0..a191c639 100644
--- a/src/kicadtoNgspice/SubcircuitTab.py
+++ b/src/kicadtoNgspice/SubcircuitTab.py
@@ -1,8 +1,8 @@
 from PyQt4 import QtGui
-import json
 from . import TrackWidget
 from projManagement import Validation
 import os
+from xml.etree import ElementTree as ET
 
 
 class SubcircuitTab(QtGui.QWidget):
@@ -11,7 +11,7 @@ class SubcircuitTab(QtGui.QWidget):
     - It dynamically creates the widget for subcircuits,
       according to the .cir file
     - Creates `lineEdit` and `Add` button, which triggers `fileSelector`
-    - Also, checks `Previous_value.json` for previous subcircuit value
+    - Also, checks `Previous_value.xml` for previous subcircuit value
       to autofill, the `lineEdit`
     - Add button is bind to `trackSubcircuit`
     - Also `trackSubcircuit` without button is triggered if `lineEdit` filled
@@ -27,12 +27,15 @@ class SubcircuitTab(QtGui.QWidget):
                 os.path.join(
                     projpath,
                     project_name +
-                    "_Previous_Values.json"),
+                    "_Previous_Values.xml"),
                 'r')
-            data = f.read()
-            json_data = json.loads(data)
+            tree = ET.parse(f)
+            parent_root = tree.getroot()
+            for child in parent_root:
+                if child.tag == "subcircuit":
+                    root = child
         except BaseException:
-            print("Subcircuit Previous values JSON is Empty")
+            print("Subcircuit Previous values XML is Empty")
 
         QtGui.QWidget.__init__(self)
 
@@ -71,14 +74,16 @@ class SubcircuitTab(QtGui.QWidget):
 
                 global path_name
                 try:
-                    for key in json_data["subcircuit"]:
-                        if key == words[0]:
+                    for child in root:
+                        if child.tag[0] == eachline[0] \
+                                and child.tag[1] == eachline[1]:
+                            # print("Subcircuit MATCHING---", child.tag[0], \
+                            #       child.tag[1], eachline[0],eachline[1])
                             try:
-                                if os.path.exists(
-                                        json_data["subcircuit"][key][0]):
-                                    self.entry_var[self.count].setText(
-                                        json_data["subcircuit"][key][0])
-                                    path_name = json_data["subcircuit"][key][0]
+                                if os.path.exists(child[0].text):
+                                    self.entry_var[self.count] \
+                                        .setText(child[0].text)
+                                    path_name = child[0].text
                                 else:
                                     self.entry_var[self.count].setText("")
                             except BaseException:
diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py
index c5bd310a..d42e3120 100644
--- a/src/modelEditor/ModelEditor.py
+++ b/src/modelEditor/ModelEditor.py
@@ -332,7 +332,6 @@ class ModelEditorclass(QtGui.QWidget):
             self.createtable(self.editfile)
         except BaseException:
             print("No File selected for edit")
-            pass
 
     def createtable(self, modelfile):
         '''
-- 
cgit 


From 4fce8a8c01e2892b12cd194cb90ca999822eb6c5 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Wed, 26 Feb 2020 16:10:58 +0530
Subject: minor updates

---
 src/frontEnd/Application.py          | 4 ++--
 src/kicadtoNgspice/KicadtoNgspice.py | 7 +------
 2 files changed, 3 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py
index 3ecf9941..92013409 100644
--- a/src/frontEnd/Application.py
+++ b/src/frontEnd/Application.py
@@ -188,7 +188,7 @@ class Application(QtGui.QMainWindow):
         self.model.triggered.connect(self.open_modelEditor)
 
         self.subcircuit = QtGui.QAction(
-            QtGui.QIcon('images/subckt.png'),'<b>Subcircuit</b>', self
+            QtGui.QIcon('images/subckt.png'), '<b>Subcircuit</b>', self
         )
         self.subcircuit.triggered.connect(self.open_subcircuit)
 
@@ -518,7 +518,7 @@ class Application(QtGui.QMainWindow):
 
                 # Fail Safe ===>
                 count += 1
-                if count >= 100:
+                if count >= 10:
                     raise Exception(
                         "Ngspice taking too long for simulation. "
                         "Check netlist file to change simulation parameters."
diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index 8a4d746d..b47f2c38 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -255,12 +255,7 @@ class MainWindow(QtGui.QWidget):
             check = 0
 
         # Opening previous value file pertaining to the selected project
-        fw = open(
-            os.path.join(
-                projpath,
-                project_name +
-                "_Previous_Values.xml"),
-            'w')
+        fw = os.path.join(projpath, project_name + "_Previous_Values.xml")
 
         if check == 0:
             attr_parent = ET.Element("KicadtoNgspice")
-- 
cgit 


From 0652aab53f84c5b25d489dd85742130425a1c1c9 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Mon, 2 Mar 2020 16:20:31 +0530
Subject: show manual for help option

---
 src/browser/UserManual.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py
index f733bb93..2ab15ef6 100644
--- a/src/browser/UserManual.py
+++ b/src/browser/UserManual.py
@@ -13,9 +13,9 @@ class UserManual(QtGui.QWidget):
 
         self.vlayout = QtGui.QVBoxLayout()
 
-        self.url = "library/browser/User-Manual/eSim.html"
+        self.url = "library/browser/User-Manual/eSim_Manual_2019_Dec_31.pdf"
         self.test = webbrowser.open(
-            "library/browser/User-Manual/eSim.html", new=2)
+            "library/browser/User-Manual/eSim_Manual_2019_Dec_31.pdf", new=2)
 
         self.setLayout(self.vlayout)
         self.show()
-- 
cgit 


From 656357024fc225c79b7273ed05672f2d4d797f73 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Mon, 2 Mar 2020 16:22:43 +0530
Subject: resolve issue with changing dir

---
 src/modelEditor/ModelEditor.py | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py
index d42e3120..0b6990f3 100644
--- a/src/modelEditor/ModelEditor.py
+++ b/src/modelEditor/ModelEditor.py
@@ -121,7 +121,7 @@ class ModelEditorclass(QtGui.QWidget):
             self.modeltable.setHidden(True)
         except BaseException:
             pass
-        os.chdir(self.savepathtest)
+
         # Opens new dialog box
         text, ok = QtGui.QInputDialog.getText(
             self, 'New Model', 'Enter Model Name:')
@@ -312,7 +312,6 @@ class ModelEditorclass(QtGui.QWidget):
             `self.createtable(path)`
         - Handle exception of no file selected
         '''
-        os.chdir(self.savepathtest)
         self.newflag = 0
         self.addbtn.setHidden(True)
         self.types.setHidden(True)
@@ -600,6 +599,12 @@ class ModelEditorclass(QtGui.QWidget):
                 ' library created at ' +
                 os.getcwd())
         txtfile.close()
+
+        msg = "Model saved successfully!"
+        QtGui.QMessageBox.information(
+            self, "Information", msg, QtGui.QMessageBox.Ok
+        )
+
         os.chdir(defaultcwd)
 
     def validation(self, text):
@@ -654,6 +659,11 @@ class ModelEditorclass(QtGui.QWidget):
 
         self.obj_appconfig.print_info('Updated library ' + libpath)
 
+        msg = "Model saved successfully!"
+        QtGui.QMessageBox.information(
+            self, "Information", msg, QtGui.QMessageBox.Ok
+        )
+
     def removeparameter(self):
         '''
         - Get the index of the current selected item
@@ -676,7 +686,6 @@ class ModelEditorclass(QtGui.QWidget):
         - Save it in `User Libraries` with the given name,
         and input from uploaded file
         '''
-        os.chdir(self.savepathtest)
         self.addbtn.setHidden(True)
         self.removebtn.setHidden(True)
         self.modeltable.setHidden(True)
-- 
cgit 


From 9fcc73d1b18aa763bb918a392a152688cf1fb1ea Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Mon, 2 Mar 2020 16:25:34 +0530
Subject: resolve issue with incorrect library paths

---
 src/kicadtoNgspice/DeviceModel.py | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py
index d548f289..c4ea9a22 100644
--- a/src/kicadtoNgspice/DeviceModel.py
+++ b/src/kicadtoNgspice/DeviceModel.py
@@ -86,10 +86,9 @@ class DeviceModel(QtGui.QWidget):
 
                 try:
                     for child in root:
-                        if child.tag[0] == eachline[0] \
-                                and child.tag[1] == eachline[1]:
-                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
-                            #       child.tag[1], eachline[0], eachline[1])
+                        if child.tag == words[0]:
+                            # print("DEVICE MODEL MATCHING---", \
+                            #       child.tag, words[0])
                             try:
                                 if os.path.exists(child[0].text):
                                     self.entry_var[self.count] \
@@ -150,10 +149,9 @@ class DeviceModel(QtGui.QWidget):
                 # global path_name
                 try:
                     for child in root:
-                        if child.tag[0] == eachline[0] \
-                                and child.tag[1] == eachline[1]:
-                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
-                            #  child.tag[1], eachline[0], eachline[1])
+                        if child.tag == words[0]:
+                            # print("DEVICE MODEL MATCHING---", \
+                            #       child.tag, words[0])
                             try:
                                 if os.path.exists(child[0].text):
                                     path_name = child[0].text
@@ -213,10 +211,9 @@ class DeviceModel(QtGui.QWidget):
                 # global path_name
                 try:
                     for child in root:
-                        if child.tag[0] == eachline[0] \
-                                and child.tag[1] == eachline[1]:
-                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
-                            #       child.tag[1], eachline[0], eachline[1])
+                        if child.tag == words[0]:
+                            # print("DEVICE MODEL MATCHING---", \
+                            #       child.tag, words[0])
                             try:
                                 if os.path.exists(child[0].text):
                                     self.entry_var[self.count] \
@@ -326,10 +323,9 @@ class DeviceModel(QtGui.QWidget):
                 # global path_name
                 try:
                     for child in root:
-                        if child.tag[0] == eachline[0] \
-                                and child.tag[1] == eachline[1]:
-                            # print("DEVICE MODEL MATCHING---", child.tag[0], \
-                            #       child.tag[1], eachline[0], eachline[1])
+                        if child.tag == words[0]:
+                            # print("DEVICE MODEL MATCHING---", \
+                            #       child.tag, words[0])
                             while i <= end:
                                 self.entry_var[i].setText(child[i-beg].text)
                                 if (i - beg) == 0:
-- 
cgit 


From a62f5472f9220e51ede51c4d2b98ec154b08f4eb Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Mon, 2 Mar 2020 16:28:11 +0530
Subject: removed str displaying 'None' on fields

---
 src/kicadtoNgspice/KicadtoNgspice.py |  2 +-
 src/kicadtoNgspice/Model.py          |  5 ++---
 src/kicadtoNgspice/Source.py         | 14 +++++++-------
 3 files changed, 10 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py
index b47f2c38..c1421829 100644
--- a/src/kicadtoNgspice/KicadtoNgspice.py
+++ b/src/kicadtoNgspice/KicadtoNgspice.py
@@ -217,7 +217,7 @@ class MainWindow(QtGui.QWidget):
         # self.tabWidget.TabShape(QtGui.QTabWidget.Rounded)
         self.tabWidget.addTab(self.analysisTab, "Analysis")
         self.tabWidget.addTab(self.sourceTab, "Source Details")
-        self.tabWidget.addTab(self.modelTab, "NgSpice Model")
+        self.tabWidget.addTab(self.modelTab, "Ngspice Model")
         self.tabWidget.addTab(self.deviceModelTab, "Device Modeling")
         self.tabWidget.addTab(self.subcircuitTab, "Subcircuits")
         self.mainLayout = QtGui.QVBoxLayout()
diff --git a/src/kicadtoNgspice/Model.py b/src/kicadtoNgspice/Model.py
index 6de6d8df..a5757702 100644
--- a/src/kicadtoNgspice/Model.py
+++ b/src/kicadtoNgspice/Model.py
@@ -82,8 +82,7 @@ class Model(QtGui.QWidget):
                                 if child.text == line[2] \
                                         and child.tag == line[3]:
                                     self.obj_trac.model_entry_var
-                                    [self.nextcount].setText(
-                                                        str(child[i].text))
+                                    [self.nextcount].setText(child[i].text)
                                     i = i + 1
                         except BaseException:
                             pass
@@ -108,7 +107,7 @@ class Model(QtGui.QWidget):
                         for child in root:
                             if child.text == line[2] and child.tag == line[3]:
                                 self.obj_trac.model_entry_var[self.nextcount] \
-                                                .setText(str(child[i].text))
+                                                .setText(child[i].text)
                                 i = i + 1
                     except BaseException:
                         pass
diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py
index fdcd4adc..e42899e3 100644
--- a/src/kicadtoNgspice/Source.py
+++ b/src/kicadtoNgspice/Source.py
@@ -102,9 +102,9 @@ class Source(QtGui.QWidget):
                             if child.tag == templist2[0] and \
                                     child.text == line[2]:
                                 self.entry_var[self.count] \
-                                    .setText(str(child[0].text))
+                                    .setText(child[0].text)
                                 self.entry_var[self.count + 1] \
-                                    .setText(str(child[1].text))
+                                    .setText(child[1].text)
                     except BaseException:
                         pass
                     # Value Need to check previuouse value
@@ -148,7 +148,7 @@ class Source(QtGui.QWidget):
                             if child.tag == templist2[0] \
                                     and child.text == line[2]:
                                 self.entry_var[self.count] \
-                                    .setText(str(child[0].text))
+                                    .setText(child[0].text)
                     except BaseException:
                         pass
 
@@ -192,7 +192,7 @@ class Source(QtGui.QWidget):
                                 if child.tag == templist2[0] \
                                         and child.text == line[2]:
                                     self.entry_var[self.count] \
-                                        .setText(str(child[it-4].text))
+                                        .setText(child[it-4].text)
                         except BaseException:
                             pass
 
@@ -235,7 +235,7 @@ class Source(QtGui.QWidget):
                                 if child.tag == templist2[0] \
                                         and child.text == line[2]:
                                     self.entry_var[self.count] \
-                                        .setText(str(child[it-4].text))
+                                        .setText(child[it-4].text)
                         except BaseException:
                             pass
 
@@ -275,7 +275,7 @@ class Source(QtGui.QWidget):
                             if child.tag == templist2[0] \
                                     and child.text == line[2]:
                                 self.entry_var[self.count] \
-                                    .setText(str(child[0].text))
+                                    .setText(child[0].text)
                     except BaseException:
                         pass
 
@@ -318,7 +318,7 @@ class Source(QtGui.QWidget):
                                 if child.tag == templist2[0] \
                                         and child.text == line[2]:
                                     self.entry_var[self.count] \
-                                        .setText(str(child[it-4].text))
+                                        .setText(child[it-4].text)
                         except BaseException:
                             pass
 
-- 
cgit 


From 13f3bcfda9416624cebbf5705de398e8efcad344 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Wed, 4 Mar 2020 14:47:28 +0530
Subject: display manual - os specific

---
 src/browser/UserManual.py | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py
index 2ab15ef6..f31af29d 100644
--- a/src/browser/UserManual.py
+++ b/src/browser/UserManual.py
@@ -1,5 +1,7 @@
 from PyQt4 import QtGui
-import webbrowser
+import subprocess
+import platform
+import os
 
 
 class UserManual(QtGui.QWidget):
@@ -13,9 +15,14 @@ class UserManual(QtGui.QWidget):
 
         self.vlayout = QtGui.QVBoxLayout()
 
-        self.url = "library/browser/User-Manual/eSim_Manual_2019_Dec_31.pdf"
-        self.test = webbrowser.open(
-            "library/browser/User-Manual/eSim_Manual_2019_Dec_31.pdf", new=2)
+        file = os.path.realpath(
+            'library/browser/User-Manual/eSim_Manual_2019_Dec_31.pdf'
+        )
+
+        if 'Win' in platform.system():
+            os.startfile(file)
+        else:
+            subprocess.Popen(['xpdf.real', file], shell=False)
 
         self.setLayout(self.vlayout)
         self.show()
-- 
cgit