From 5000da993e5d83bc4306a556da4ccc254145bd31 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 00:15:25 +0530 Subject: Restructured Verilator libraries --- src/maker/Maker.py | 2 +- src/maker/ModelGeneration.py | 31 +++++++++++----- src/maker/NgVeri.py | 24 +++++++++--- src/maker/lint_off.txt | 29 --------------- src/maker/tlv/clk_gate.v | 40 -------------------- src/maker/tlv/pseudo_rand.m4out.tlv | 69 ---------------------------------- src/maker/tlv/pseudo_rand.sv | 70 ----------------------------------- src/maker/tlv/pseudo_rand_gen.sv | 46 ----------------------- src/maker/tlv/sandpiper.vh | 72 ------------------------------------ src/maker/tlv/sandpiper_gen.vh | 4 -- src/maker/tlv/sp_default.vh | 66 --------------------------------- src/maker/verilated.o | Bin 144712 -> 0 bytes 12 files changed, 41 insertions(+), 412 deletions(-) delete mode 100755 src/maker/lint_off.txt delete mode 100755 src/maker/tlv/clk_gate.v delete mode 100755 src/maker/tlv/pseudo_rand.m4out.tlv delete mode 100755 src/maker/tlv/pseudo_rand.sv delete mode 100755 src/maker/tlv/pseudo_rand_gen.sv delete mode 100755 src/maker/tlv/sandpiper.vh delete mode 100755 src/maker/tlv/sandpiper_gen.vh delete mode 100755 src/maker/tlv/sp_default.vh delete mode 100755 src/maker/verilated.o (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index f4c696f6..78fd13b2 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -228,7 +228,7 @@ class Maker(QtWidgets.QWidget): code = code.replace(" reg ", " ") vlog_ex = vlog.VerilogExtractor() vlog_mods = vlog_ex.extract_objects_from_source(code) - lint_off = open("../maker/lint_off.txt").readlines() + lint_off = open(init_path + "library/tlv/lint_off.txt").readlines() string = '''\\TLV_version 1d: tl-x.org\n\\SV\n''' for item in lint_off: string += "/* verilator lint_off " + \ diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index caafe3c8..e7bbe9c9 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -106,12 +106,15 @@ class ModelGeneration(QtWidgets.QWidget): # This function is call the sandpiper to convert .tlv file to .sv file def sandpiper(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' # Text="Running Sandpiper............" print("Running Sandpiper-Saas for TLV to SV Conversion") - self.cmd = "cp ../maker/tlv/clk_gate.v ../maker/tlv/pseudo_rand.sv \ -../maker/tlv/sandpiper.vh ../maker/tlv/sandpiper_gen.vh \ -../maker/tlv/sp_default.vh ../maker/tlv/pseudo_rand_gen.sv \ -../maker/tlv/pseudo_rand.m4out.tlv " + self.file + " " + self.modelpath + self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + init_path + "library/tlv/pseudo_rand.sv "\ + + init_path + "library/tlv/sandpiper.vh " + init_path + "library/tlv/sandpiper_gen.vh "\ + + init_path + "library/tlv/sp_default.vh " + init_path + "library/tlv/pseudo_rand_gen.sv "\ + + init_path + "library/tlv/pseudo_rand.m4out.tlv " + self.file + " " + self.modelpath self.process = QtCore.QProcess(self) self.args = ['-c', self.cmd] @@ -790,8 +793,12 @@ and set the load for input ports */ # This function is used to run the Verilator using the verilator commands def run_verilator(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' + self.cur_dir = os.getcwd() - file = open("../maker/lint_off.txt").readlines() + file = open(init_path + "library/tlv/lint_off.txt").readlines() wno = " " for item in file: wno += " -Wno-" + item.strip("\n") @@ -823,10 +830,14 @@ and set the load for input ports */ self.cur_dir = os.getcwd() print("Make Verilator.............") os.chdir(self.modelpath) + + if os.path.exists(self.modelpath + "../verilated.o"): + os.remove(self.modelpath + "../verilated.o") + self.cmd = "make -f V" + self.fname.split('.')[0]\ + ".mk V" + self.fname.split( '.')[0] + "__ALL.a sim_main_" \ - + self.fname.split('.')[0] + ".o verilated.o" + + self.fname.split('.')[0] + ".o ../verilated.o" self.process = QtCore.QProcess(self) self.process.readyReadStandardOutput.connect(self.readAllStandard) self.process.start('sh', ['-c', self.cmd]) @@ -861,9 +872,9 @@ and set the load for input ports */ os.remove(path_icm + "sim_main_" + self.fname.split('.')[0] + ".o") if os.path.exists( self.release_home + - "src/xspice/icm/" + + "src/xspice/icm/Ngveri/" + "verilated.o"): - os.remove(self.release_home + "src/xspice/icm/" + "verilated.o") + os.remove(self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o") if os.path.exists( path_icm + "V" + @@ -886,8 +897,8 @@ and set the load for input ports */ self.termtext("Current Directory: " + self.modelpath) self.termtext("Command: " + self.cmd) self.process.waitForFinished(50000) - self.cmd = "cp verilated.o " + self.release_home \ - + "/src/xspice/icm/" + self.cmd = "cp ../verilated.o " + self.release_home \ + + "/src/xspice/icm/Ngveri/" self.process.start('sh', ['-c', self.cmd]) self.termtext("Command: " + self.cmd) self.process \ diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index d26c9338..5f0e1bcb 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -252,6 +252,10 @@ class NgVeri(QtWidgets.QWidget): # This is to remove lint_off comments needed by the verilator warnings # This function writes to the lint_off.txt here in the same folder def lint_off_edit(self, text): + init_path = '../../' + if os.name == 'nt': + init_path = '' + if text == "Edit lint_off": return index = self.entry_var[2].findText(text) @@ -260,17 +264,18 @@ class NgVeri(QtWidgets.QWidget): ret = QtWidgets.QMessageBox.warning( None, "Warning", - '''Do you want to remove the lint off error:''' + + '''Do you want to remove the lint off error: ''' + text, QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel) + if ret == QtWidgets.QMessageBox.Ok: - file = open("../maker/lint_off.txt", 'r') + file = open(init_path + "library/tlv/lint_off.txt", 'r') data = file.readlines() file.close() data.remove(text + "\n") - file = open("../maker/lint_off.txt", 'w') + file = open(init_path + "library/tlv/lint_off.txt", 'w') for item in data: file.write(item) return @@ -281,11 +286,15 @@ class NgVeri(QtWidgets.QWidget): # This is to add lint_off comments needed by the verilator warnings # This function writes to the lint_off.txt here in the same folder def add_lint_off(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' + text = self.entry_var[3].text() if self.entry_var[2].findText(text) == -1: self.entry_var[2].addItem(text) - file = open("../maker/lint_off.txt", 'a+') + file = open(init_path + "library/tlv/lint_off.txt", 'a+') file.write(text + "\n") file.close() self.entry_var[3].setText("") @@ -325,7 +334,12 @@ class NgVeri(QtWidgets.QWidget): self.count += 1 self.entry_var[self.count] = QtWidgets.QComboBox() self.entry_var[self.count].addItem("Edit lint_off") - self.lint_off = open("../maker/lint_off.txt", 'r') + + init_path = '../../' + if os.name == 'nt': + init_path = '' + self.lint_off = open(init_path + "library/tlv/lint_off.txt", 'r') + self.data = self.lint_off.readlines() self.lint_off.close() for item in self.data: diff --git a/src/maker/lint_off.txt b/src/maker/lint_off.txt deleted file mode 100755 index 5d4b7f0a..00000000 --- a/src/maker/lint_off.txt +++ /dev/null @@ -1,29 +0,0 @@ -UNUSED -DECLFILENAME -BLKSEQ -WIDTH -SELRANGE -PINCONNECTEMPTY -DEFPARAM -IMPLICIT -COMBDLY -SYNCASYNCNET -UNOPTFLAT -UNSIGNED -CASEINCOMPLETE -UNDRIVEN -VARHIDDEN -CASEX -CASEOVERLAP -PINMISSING -LATCH -BLKANDNBLK -MULTIDRIVEN -NULLPORT -EOFNEWLINE -WIDTHCONCAT -ASSIGNDLY -MODDUP -STMTDLY -LITENDIAN -INITIALDLY diff --git a/src/maker/tlv/clk_gate.v b/src/maker/tlv/clk_gate.v deleted file mode 100755 index 77e9186d..00000000 --- a/src/maker/tlv/clk_gate.v +++ /dev/null @@ -1,40 +0,0 @@ -/* -Copyright (c) 2015, Steven F. Hoover - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * The name of Steven F. Hoover - may not be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -`include "sp_default.vh" -/* verilator lint_off LATCH */ - -// Clock gate module used by SandPiper default project. - -module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); - wire clk_en; - reg latched_clk_en /*verilator clock_enable*/; - assign clk_en = func_en & (pwr_en | gating_override); - `TLV_BLATCH(latched_clk_en, clk_en, free_clk) - assign gated_clk = latched_clk_en & free_clk; -endmodule - diff --git a/src/maker/tlv/pseudo_rand.m4out.tlv b/src/maker/tlv/pseudo_rand.m4out.tlv deleted file mode 100755 index cb0d6149..00000000 --- a/src/maker/tlv/pseudo_rand.m4out.tlv +++ /dev/null @@ -1,69 +0,0 @@ -\m4_TLV_version 1b: tl-x.org -\SV -/* -Copyright (c) 2014, Steven F. Hoover - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * The name of Steven F. Hoover - may not be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module pseudo_rand - #(parameter WIDTH=257) // Random vector width, to a max of 257. - (input logic clk, - input logic reset, - output logic [WIDTH-1:0] rand_vect - ); - -// Currently, this implements a Galois LFSR. -// TODO: It should be XORed with something else so it doesn't just shift. -// Using polynomials with maximal number of taps would have less regular shifting behavior. - -// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. - -// Choose optimal parameters for given WIDTH. -localparam LFSR_WIDTH = - (WIDTH <= 64) ? 64 : - (WIDTH <= 128) ? 128 : - (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. -// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf -localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, - (LFSR_WIDTH == 64) ? 8'b00011011 : - (LFSR_WIDTH == 128) ? 8'b10000111 : - (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; - -bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; - - - -\TLV - |default - @0 - $reset = reset; - @1 - $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); - @2 - *rand_vect = $lfsr[WIDTH-1:0]; - -\SV - -endmodule diff --git a/src/maker/tlv/pseudo_rand.sv b/src/maker/tlv/pseudo_rand.sv deleted file mode 100755 index a9988b58..00000000 --- a/src/maker/tlv/pseudo_rand.sv +++ /dev/null @@ -1,70 +0,0 @@ -`line 2 "pseudo_rand.m4out.tlv" 0 //_\TLV_version 1b: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta -`include "sp_default.vh" //_\SV -/* -Copyright (c) 2014, Steven F. Hoover - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * The name of Steven F. Hoover - may not be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -module pseudo_rand - #(parameter WIDTH=257) // Random vector width, to a max of 257. - (input logic clk, - input logic reset, - output logic [WIDTH-1:0] rand_vect - ); - -// Currently, this implements a Galois LFSR. -// TODO: It should be XORed with something else so it doesn't just shift. -// Using polynomials with maximal number of taps would have less regular shifting behavior. - -// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. - -// Choose optimal parameters for given WIDTH. -localparam LFSR_WIDTH = - (WIDTH <= 64) ? 64 : - (WIDTH <= 128) ? 128 : - (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. -// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf -localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, - (LFSR_WIDTH == 64) ? 8'b00011011 : - (LFSR_WIDTH == 128) ? 8'b10000111 : - (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; - -bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; - - - -`include "pseudo_rand_gen.sv" //_\TLV - //_|default - //_@0 - assign DEFAULT_reset_a0 = reset; - //_@1 - assign DEFAULT_lfsr_a1[LFSR_WIDTH-1:0] = DEFAULT_reset_a1 ? SEED : {DEFAULT_lfsr_a2[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{DEFAULT_lfsr_a2[LFSR_WIDTH-1]}} & LFSR_POLY); - //_@2 - assign rand_vect = DEFAULT_lfsr_a2[WIDTH-1:0]; endgenerate - -//_\SV - -endmodule - diff --git a/src/maker/tlv/pseudo_rand_gen.sv b/src/maker/tlv/pseudo_rand_gen.sv deleted file mode 100755 index ec008179..00000000 --- a/src/maker/tlv/pseudo_rand_gen.sv +++ /dev/null @@ -1,46 +0,0 @@ -// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. -// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. - - -`include "sandpiper_gen.vh" - - - - - -// -// Signals declared top-level. -// - -// For |default$lfsr. -logic [LFSR_WIDTH-1:0] DEFAULT_lfsr_a1, - DEFAULT_lfsr_a2; - -// For |default$reset. -logic DEFAULT_reset_a0, - DEFAULT_reset_a1; - - - -generate - - - // - // Scope: |default - // - - // For $lfsr. - always_ff @(posedge clk) DEFAULT_lfsr_a2[LFSR_WIDTH-1:0] <= DEFAULT_lfsr_a1[LFSR_WIDTH-1:0]; - - // For $reset. - always_ff @(posedge clk) DEFAULT_reset_a1 <= DEFAULT_reset_a0; - - - - -endgenerate - - - - -generate // This is awkward, but we need to go into 'generate' context in the line that `includes the declarations file. diff --git a/src/maker/tlv/sandpiper.vh b/src/maker/tlv/sandpiper.vh deleted file mode 100755 index ccba8b0e..00000000 --- a/src/maker/tlv/sandpiper.vh +++ /dev/null @@ -1,72 +0,0 @@ -/* -Copyright (c) 2015, Steven F. Hoover - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * The name of Steven F. Hoover - may not be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// Project-independent SandPiper header file. - -`ifndef SANDPIPER_VH -`define SANDPIPER_VH - - -// Note, these have no SP prefix, so collisions are possible. - - -`ifdef WHEN - // Make sure user definition does not collide. - !!!ERROR: WHEN macro already defined -`else - `ifdef SP_PHYS - // Phys compilation disabled X-injection. - `define WHEN(valid_sig) - `else - // Inject X. - `define WHEN(valid_sig) !valid_sig ? 'x : - `endif -`endif - - -// SandPiper does not generate set/reset flops. Reset is implemented as combinational -// logic, and it is up to synthesis to infer set/reset flops when possible. -//`ifdef RESET -// // Make sure user definition does not collide. -// !!!ERROR: RESET macro already defined -//`else -// `define RESET(i, reset) ((reset) ? '0 : i) -//`endif -// -//`ifdef SET -// // Make sure user definition does not collide. -// !!!ERROR: SET macro already defined -//`else -// `define SET(i, set) ((set) ? '1 : i) -//`endif - -// Since SandPiper required use of all signals, this is useful to create a -// bogus use and keep SandPiper happy when a signal, by intent, has no uses. -`define BOGUS_USE(ignore) - -`endif // SANDPIPER_VH - diff --git a/src/maker/tlv/sandpiper_gen.vh b/src/maker/tlv/sandpiper_gen.vh deleted file mode 100755 index d063661a..00000000 --- a/src/maker/tlv/sandpiper_gen.vh +++ /dev/null @@ -1,4 +0,0 @@ -// This just verifies that sandpiper.vh has been included. -`ifndef SANDPIPER_VH - !!!ERROR: SandPiper project's sp_.vh file must include sandpiper.vh. -`endif diff --git a/src/maker/tlv/sp_default.vh b/src/maker/tlv/sp_default.vh deleted file mode 100755 index 5e74259a..00000000 --- a/src/maker/tlv/sp_default.vh +++ /dev/null @@ -1,66 +0,0 @@ -`ifndef SP_DEFAULT -`define SP_DEFAULT -/* -Copyright (c) 2015, Steven F. Hoover - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * The name of Steven F. Hoover - may not be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - - -// File included by SandPiper-generated code for the default project configuration. -`include "sandpiper.vh" - - -// Latch macros. Inject 'x in simulation for clk === 'x. - -// A-phase latch. -`ifdef SP_PHYS -`define TLV_LATCH(in, out, clk) \ -always @ (in, clk) begin \ - if (clk === 1'b1) \ - out <= in; \ - else if (clk === 1'bx) \ - out <= 'x; \ -end -`else -`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; -`endif // SP_PHYS - -// B-phase latch. -`ifdef SP_PHYS -`define TLV_BLATCH(out, in, clk) \ -always @ (in, clk) begin \ - if (!clk === 1'b1) \ - out <= in; \ - else if (!clk === 1'bx) \ - out <= 'x; \ -end -`else -`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; -`endif // SP_PHYS - - - -`endif // SP_DEFAULT - diff --git a/src/maker/verilated.o b/src/maker/verilated.o deleted file mode 100755 index db5f1163..00000000 Binary files a/src/maker/verilated.o and /dev/null differ -- cgit From 0817c3856b05037037f9fe5fe54f233e913a97bd Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 00:40:05 +0530 Subject: Updated MSYS paths --- src/maker/ModelGeneration.py | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'src/maker') diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index e7bbe9c9..208664f8 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -834,7 +834,14 @@ and set the load for input ports */ if os.path.exists(self.modelpath + "../verilated.o"): os.remove(self.modelpath + "../verilated.o") - self.cmd = "make -f V" + self.fname.split('.')[0]\ + if os.name == 'nt': + # path to msys home directory + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe" + else: + self.cmd = "make" + + self.cmd = self.cmd + " -f V" + self.fname.split('.')[0]\ + ".mk V" + self.fname.split( '.')[0] + "__ALL.a sim_main_" \ + self.fname.split('.')[0] + ".o ../verilated.o" @@ -918,9 +925,9 @@ and set the load for input ports */ try: if os.name == 'nt': - # path to msys bin directory where make is located - self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') - self.cmd = self.msys_bin + "\\make.exe" + # path to msys home directory + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe" else: self.cmd = "make" @@ -953,8 +960,8 @@ and set the load for input ports */ try: if os.name == 'nt': - self.msys_bin = self.parser.get('COMPILER', 'MSYS_HOME') - self.cmd = self.msys_bin + "\\make.exe install" + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe install" else: self.cmd = "make install" print("Running Make Install") -- cgit From faadcb72916d269aeabbaa23f799962b6b99c45c Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 00:59:17 +0530 Subject: Replaced SafeConfigParser alias with ConfigParser --- src/maker/Appconfig.py | 6 +++--- src/maker/ModelGeneration.py | 5 ++--- src/maker/NgVeri.py | 3 +-- 3 files changed, 6 insertions(+), 8 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Appconfig.py b/src/maker/Appconfig.py index efeac75a..45d28e62 100755 --- a/src/maker/Appconfig.py +++ b/src/maker/Appconfig.py @@ -1,11 +1,11 @@ import os.path -from configparser import SafeConfigParser +from configparser import ConfigParser class Appconfig: home = os.path.expanduser("~") # Reading all variables from eSim config.ini - parser_esim = SafeConfigParser() + parser_esim = ConfigParser() parser_esim.read(os.path.join(home, os.path.join('.esim', 'config.ini'))) try: src_home = parser_esim.get('eSim', 'eSim_HOME') @@ -16,7 +16,7 @@ class Appconfig: esimFlag = 0 # Reading all variables from ngveri config.ini - # parser_ngveri = SafeConfigParser() + # parser_ngveri = ConfigParser() # parser_ngveri.read(os.path.join(home, # os.path.join('.ngveri', 'config.ini'))) diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 208664f8..54b91d50 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -35,11 +35,10 @@ import shutil # noqa:F401 import subprocess # noqa:F401 from PyQt5 import QtGui, QtCore, QtWidgets # noqa:F401 from PyQt5.QtGui import * # noqa:F401 F403 -from configparser import ConfigParser # noqa:F401 +from configparser import ConfigParser from configuration import Appconfig from . import createkicad import hdlparse.verilog_parser as vlog -from configparser import SafeConfigParser # noqa:F401 # Class is used to generate the Ngspice Model @@ -59,7 +58,7 @@ class ModelGeneration(QtWidgets.QWidget): self.fname = self.fname.lower() print("Verilog/SystemVerilog/TL Verilog filename is : ", self.fname) self.home = os.path.expanduser("~") - self.parser = SafeConfigParser() + self.parser = ConfigParser() self.parser.read(os.path.join( self.home, os.path.join('.nghdl', 'config.ini'))) self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index 5f0e1bcb..4e3e37da 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -34,7 +34,6 @@ from . import ModelGeneration import os import subprocess from configuration.Appconfig import Appconfig -from configparser import SafeConfigParser from configparser import ConfigParser @@ -48,7 +47,7 @@ class NgVeri(QtWidgets.QWidget): # Maker.addverilog(self) self.obj_Appconfig = Appconfig() self.home = os.path.expanduser("~") - self.parser = SafeConfigParser() + self.parser = ConfigParser() self.parser.read(os.path.join( self.home, os.path.join('.nghdl', 'config.ini'))) self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') -- cgit From 1b42df112e9d13afd092d9f415e7e446a2102e85 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:07:20 +0530 Subject: Restructured config paths and other path issues --- src/maker/Appconfig.py | 6 +++++- src/maker/Maker.py | 2 +- src/maker/ModelGeneration.py | 42 +++++++++++++++++++++++++----------------- src/maker/NgVeri.py | 18 +++++++++++------- 4 files changed, 42 insertions(+), 26 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Appconfig.py b/src/maker/Appconfig.py index 45d28e62..06758898 100755 --- a/src/maker/Appconfig.py +++ b/src/maker/Appconfig.py @@ -3,7 +3,11 @@ from configparser import ConfigParser class Appconfig: - home = os.path.expanduser("~") + if os.name == 'nt': + home = os.path.join('library', 'config') + else: + home = os.path.expanduser('~') + # Reading all variables from eSim config.ini parser_esim = ConfigParser() parser_esim.read(os.path.join(home, os.path.join('.esim', 'config.ini'))) diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 78fd13b2..60087018 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -82,7 +82,7 @@ class Maker(QtWidgets.QWidget): # This function is to Add new verilog file def addverilog(self): - init_path = '../../../' + init_path = '../../' if os.name == 'nt': init_path = '' self.verilogfile = QtCore.QDir.toNativeSeparators( diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 54b91d50..0f0f5c58 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -51,23 +51,31 @@ class ModelGeneration(QtWidgets.QWidget): super().__init__() self.obj_Appconfig = Appconfig.Appconfig() print("Argument is : ", file) - self.file = file + + if os.name == 'nt': + self.file = file.replace('\\', '/') + else: + self.file = file + self.termedit = termedit self.cur_dir = os.getcwd() self.fname = os.path.basename(file) self.fname = self.fname.lower() print("Verilog/SystemVerilog/TL Verilog filename is : ", self.fname) - self.home = os.path.expanduser("~") + + if os.name == 'nt': + self.home = os.path.join('library', 'config') + else: + self.home = os.path.expanduser('~') + self.parser = ConfigParser() self.parser.read(os.path.join( self.home, os.path.join('.nghdl', 'config.ini'))) - self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') - self.release_dir = self.parser.get('NGSPICE', 'RELEASE') + self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME') + self.release_dir = self.parser.get('NGHDL', 'RELEASE') self.src_home = self.parser.get('SRC', 'SRC_HOME') self.licensefile = self.parser.get('SRC', 'LICENSE') - self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL') - - self.digital_home = self.digital_home.split("/ghdl")[0] + "/Ngveri" + self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + "/Ngveri" # # #### Creating connection_info.txt file from verilog file #### # # Readinf the file and performing operations and copying it in the Ngspice @@ -441,7 +449,7 @@ and set the load for input ports */ cfunc.write("\n") # if os.name == 'nt': - # digital_home = parser.get('NGSPICE', 'DIGITAL_MODEL') + # digital_home = parser.get('NGHDL', 'DIGITAL_MODEL') # msys_home = parser.get('COMPILER', 'MSYS_HOME') # cmd_str2 = "/start_server.sh %d %s & read" + "\\" + "\"" + "\"" # cmd_str1 = os.path.normpath( @@ -458,7 +466,7 @@ and set the load for input ports */ # else: # cfunc.write( # '\t\tsnprintf(command,1024,"' + home + - # '/ngspice-nghdl/src/xspice/icm/ghdl/' + + # '/nghdl-simulator/src/xspice/icm/ghdl/' + # fname.split('.')[0] + # '/DUTghdl/start_server.sh %d %s &", sock_port, my_ip);' # ) @@ -803,7 +811,7 @@ and set the load for input ports */ wno += " -Wno-" + item.strip("\n") print("Running Verilator.............") os.chdir(self.modelpath) - self.release_home = self.parser.get('NGSPICE', 'RELEASE') + self.release_home = self.parser.get('NGHDL', 'RELEASE') # print(self.modelpath) self.cmd = "verilator -Wall " + wno + "\ @@ -865,8 +873,8 @@ and set the load for input ports */ self.cur_dir = os.getcwd() print("Copying the required files to Release Folder.............") os.chdir(self.modelpath) - self.release_home = self.parser.get('NGSPICE', 'RELEASE') - path_icm = os.path.join(self.release_home, "src/xspice/icm/Ngveri/") + self.release_home = self.parser.get('NGHDL', 'RELEASE') + path_icm = self.release_home + "/src/xspice/icm/Ngveri/" if not os.path.isdir(path_icm + self.fname.split('.')[0]): os.mkdir(path_icm + self.fname.split('.')[0]) path_icm = path_icm + self.fname.split('.')[0] @@ -918,7 +926,7 @@ and set the load for input ports */ # Running the make command for Ngspice def runMake(self): print("run Make Called") - self.release_home = self.parser.get('NGSPICE', 'RELEASE') + self.release_home = self.parser.get('NGHDL', 'RELEASE') path_icm = os.path.join(self.release_home, "src/xspice/icm") os.chdir(path_icm) @@ -953,7 +961,7 @@ and set the load for input ports */ def runMakeInstall(self): self.cur_dir = os.getcwd() print("run Make Install Called") - self.release_home = self.parser.get('NGSPICE', 'RELEASE') + self.release_home = self.parser.get('NGHDL', 'RELEASE') path_icm = os.path.join(self.release_home, "src/xspice/icm") os.chdir(path_icm) @@ -994,7 +1002,7 @@ and set the load for input ports */ def addfile(self): print("Adding the files required by the top level module file") - init_path = '../../../' + init_path = '../../' if os.name == 'nt': init_path = '' includefile = QtCore.QDir.toNativeSeparators( @@ -1037,7 +1045,7 @@ and set the load for input ports */ # self.cur_dir = os.getcwd() print("Adding the folder required by the top level module file") - init_path = '../../../' + init_path = '../../' if os.name == 'nt': init_path = '' # noqa:F841 includefolder = QtCore.QDir.toNativeSeparators( @@ -1152,7 +1160,7 @@ and set the load for input ports */ # Text += "" # self.termedit.append(Text+"\n") - # init_path = '../../../' + # init_path = '../../' # if os.name == 'nt': # init_path = '' # includefile = QtCore.QDir.toNativeSeparators(\ diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index 4e3e37da..496782f9 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -46,16 +46,21 @@ class NgVeri(QtWidgets.QWidget): QtWidgets.QWidget.__init__(self) # Maker.addverilog(self) self.obj_Appconfig = Appconfig() - self.home = os.path.expanduser("~") + + if os.name == 'nt': + self.home = os.path.join('library', 'config') + else: + self.home = os.path.expanduser('~') + self.parser = ConfigParser() self.parser.read(os.path.join( self.home, os.path.join('.nghdl', 'config.ini'))) - self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') - self.release_dir = self.parser.get('NGSPICE', 'RELEASE') + self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME') + self.release_dir = self.parser.get('NGHDL', 'RELEASE') self.src_home = self.parser.get('SRC', 'SRC_HOME') self.licensefile = self.parser.get('SRC', 'LICENSE') - self.digital_home = self.parser.get('NGSPICE', 'DIGITAL_MODEL') - self.digital_home = self.digital_home.split("/ghdl")[0] + "/Ngveri" + self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + self.digital_home = self.digital_home + "/Ngveri" self.count = 0 self.text = "" self.entry_var = {} @@ -77,8 +82,7 @@ class NgVeri(QtWidgets.QWidget): # Adding the verilog file in Maker tab to Ngveri Tab automatically def addverilog(self): - - init_path = '../../../' + init_path = '../../' if os.name == 'nt': init_path = '' # b=Maker.Maker(self) -- cgit From 5f60ee2aa4f865a9ea005d69d30e51e771050d66 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:09:58 +0530 Subject: Updated Verilator and Sandpiper-SaaS commands to work on Windows OS --- src/maker/ModelGeneration.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src/maker') diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 0f0f5c58..a87a04e1 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -137,8 +137,9 @@ class ModelGeneration(QtWidgets.QWidget): self.cmd = "sandpiper-saas -i " + \ self.fname.split('.')[0] + ".tlv -o "\ + self.fname.split('.')[0] + ".sv" - self.args = ['-c', self.cmd] - self.process.start('sh', self.args) + # self.args = ['-c', self.cmd] + # self.process.start('sh', self.args) + self.process.start(self.cmd) self.termtitle("RUN SANDPIPER-SAAS") self.termtext("Current Directory: " + self.modelpath) self.termtext("Command: " + self.cmd) @@ -814,8 +815,14 @@ and set the load for input ports */ self.release_home = self.parser.get('NGHDL', 'RELEASE') # print(self.modelpath) - self.cmd = "verilator -Wall " + wno + "\ - --cc --exe --no-MMD --Mdir . -CFLAGS -fPIC sim_main_" + \ + if os.name == 'nt': + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = "export VERILATOR_ROOT=" + self.msys_home + "/mingw64; " + else: + self.cmd = '' + + self.cmd = self.cmd + "verilator -Wall " + wno + " \ + --cc --exe --no-MMD --Mdir . -CFLAGS -fPIC sim_main_" + \ self.fname.split('.')[0] + ".cpp " + self.fname self.process = QtCore.QProcess(self) self.process.readyReadStandardOutput.connect(self.readAllStandard) -- cgit From 43ff549b6fa887f532d0944bc4fa0c745f915447 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:17:16 +0530 Subject: Fixed crash due to Appconfig attribute error --- src/maker/createkicad.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/maker') diff --git a/src/maker/createkicad.py b/src/maker/createkicad.py index dcde5526..c8b14b6e 100755 --- a/src/maker/createkicad.py +++ b/src/maker/createkicad.py @@ -48,7 +48,7 @@ class AutoSchematic: self.lib_loc = self.App_obj.lib_loc self.modelpath = modelpath if os.name == 'nt': - eSim_src = Appconfig.src_home + eSim_src = self.App_obj.src_home inst_dir = eSim_src.replace('\\eSim', '') self.kicad_ngveri_lib = \ inst_dir + '/KiCad/share/kicad/library/eSim_Ngveri.lib' -- cgit From 7aa5afaeb6ac078d233383663ec6f96e20420b43 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:15:43 +0530 Subject: Prompt ToS if Sandpiper-SaaS directly invoked --- src/maker/Maker.py | 61 ++++++++++++++++++++++------------------------------- src/maker/NgVeri.py | 11 ++++++++++ 2 files changed, 36 insertions(+), 36 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 60087018..01095d91 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -50,9 +50,31 @@ home = expanduser("~") verilogFile = [] toggle_flag = [] -# beginning class Maker. This class create the Maker Tab + +# This function is called to accept TOS of makerchip +def makerchipTOSAccepted(display=True): + if not os.path.isfile(home + "/.makerchip_accepted"): + if display: + reply = QtWidgets.QMessageBox.warning( + None, "Terms of Service", "Please review the Makerchip \ + Terms of Service \ + (\ + https://www.makerchip.com/terms/). \ + Have you read and do you \ + accept these Terms of Service?", + QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No + ) + + if reply == QtWidgets.QMessageBox.Yes: + f = open(home + "/.makerchip_accepted", "w") + f.close() + return True + + return False + return True +# beginning class Maker. This class create the Maker Tab class Maker(QtWidgets.QWidget): # initailising the varaibles @@ -177,22 +199,9 @@ class Maker(QtWidgets.QWidget): if os.name == 'nt': init_path = '' # noqa:F841 try: - if not os.path.isfile(home + "/.makerchip_accepted"): - reply = QtWidgets.QMessageBox.warning( - None, "Terms of Services", "Please review the makerchip\ - Terms of Service \ - (\ - https://www.makerchip.com/terms/ ).\ - Have you read and do you accept \ - these Terms of Service? [y/N]:", - QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No - ) + if not makerchipTOSAccepted(True): + return - if reply == QtWidgets.QMessageBox.Yes: - f = open(home + "/.makerchip_accepted", "w") - f.close() - else: - return print("Running Makerchip..............................") # self.file = open(self.verilogfile,"w") # self.file.write(self.entry_var[1].toPlainText()) @@ -372,27 +381,7 @@ Please check if Verilog File Chosen.") self.optionsbox.setLayout(self.optionsgrid) return self.optionsbox - # This function is called to accept TOS of makerchip - - def makerchipaccepted(self): - reply = QtWidgets.QMessageBox.warning( - None, "Terms of Services", "Please review the makerchip\ - Terms of Service \ - (\ - https://www.makerchip.com/terms/ ).\ - Have you read and do you \ - accept these Terms of Service? [y/N]:", - QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No - ) - - if reply == QtWidgets.QMessageBox.Yes: - f = open(home + "/.makerchip_accepted", "w") - f.close() - # else: - # return - # This function adds the other parts of widget like text box - def creategroup(self): self.trbox = QtWidgets.QGroupBox() diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index 496782f9..3a1cc845 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -104,6 +104,17 @@ class NgVeri(QtWidgets.QWidget): file = (os.path.basename(self.fname)).split('.')[0] if self.entry_var[1].findText(file) == -1: self.entry_var[1].addItem(file) + + if not Maker.makerchipTOSAccepted(True): + QtWidgets.QMessageBox.warning( + None, "Warning Message", + "Please accept the Makerchip Terms of Service " + "to proceed further.", + QtWidgets.QMessageBox.Ok + ) + + return + model.verilogfile() error = model.verilogParse() if error != "Error": -- cgit From c1dcf941062f7c900d6cdb3a40205f3c77d949e4 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:22:05 +0530 Subject: Updated Ngspice 'make' commands for Windows OS --- src/maker/NgVeri.py | 94 ++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 29 deletions(-) (limited to 'src/maker') diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index 3a1cc845..c3c4d07c 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -32,6 +32,7 @@ from PyQt5 import QtCore, QtWidgets, QtGui from . import Maker from . import ModelGeneration import os +import shutil import subprocess from configuration.Appconfig import Appconfig from configparser import ConfigParser @@ -115,30 +116,53 @@ class NgVeri(QtWidgets.QWidget): return - model.verilogfile() - error = model.verilogParse() - if error != "Error": - model.getPortInfo() - model.cfuncmod() - model.ifspecwrite() - model.sim_main_header() - model.sim_main() - model.modpathlst() - model.run_verilator() - model.make_verilator() - model.copy_verilator() - model.runMake() - model.runMakeInstall() - txt = self.entry_var[0].toPlainText() - if "error" not in txt.lower(): - self.entry_var[0].append(''' -

- Model Created Successfully ! -

- ''') - else: - self.entry_var[0].append(''' -

+ try: + model.verilogfile() + error = model.verilogParse() + if error != "Error": + model.getPortInfo() + model.cfuncmod() + model.ifspecwrite() + model.sim_main_header() + model.sim_main() + model.modpathlst() + model.run_verilator() + model.make_verilator() + model.copy_verilator() + model.runMake() + + if os.name != 'nt': + model.runMakeInstall() + else: + try: + shutil.copy( + self.release_dir + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.nghdl_home + "/lib/ngspice/" + ) + except FileNotFoundError as err: + self.entry_var[0].append( + "Error in copying Ngveri code model: " + str(err) + ) + + terminalLog = self.entry_var[0].toPlainText() + if "error" not in terminalLog.lower(): + self.entry_var[0].append(''' +

+ Model Created Successfully! +

+ ''') + + return + + except BaseException as err: + self.entry_var[0].append( + "Error in Ngspice code model generation from Verilog: " + str(err) + ) + + terminalLog = self.entry_var[0].toPlainText() + if "error" in terminalLog.lower(): + self.entry_var[0].append(''' +

There was an error during model creation,
Please rectify the error and try again ! @@ -256,12 +280,24 @@ class NgVeri(QtWidgets.QWidget): self.fname = Maker.verilogFile[self.filecount] model = ModelGeneration.ModelGeneration( self.fname, self.entry_var[0]) - model.runMake() - model.runMakeInstall() - return - # else: - # return + try: + model.runMake() + + if os.name != 'nt': + model.runMakeInstall() + else: + shutil.copy( + self.release_dir + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.nghdl_home + "/lib/ngspice/" + ) + except BaseException as err: + QtWidgets.QMessageBox.critical( + None, "Error Message", + "The verilog model '" + str(text) + + "' could not be removed: " + str(err), + QtWidgets.QMessageBox.Ok) + # This is to remove lint_off comments needed by the verilator warnings # This function writes to the lint_off.txt here in the same folder -- cgit From 9fcfe12644a7aa88d9f43025eb2065252d4d40e6 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:34:24 +0530 Subject: Check for ToS using defined function --- src/maker/Maker.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 01095d91..4e71d7fd 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -371,10 +371,10 @@ Please check if Verilog File Chosen.") self.optionsgrid.addWidget(self.runoptions, 0, 4) # self.optionsbox.setLayout(self.optionsgrid) # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) - if not os.path.isfile(home + "/.makerchip_accepted"): + if not makerchipTOSAccepted(False): self.acceptTOS = QtWidgets.QPushButton("Accept Makerchip TOS") self.optionsgroupbtn.addButton(self.acceptTOS) - self.acceptTOS.clicked.connect(self.makerchipaccepted) + self.acceptTOS.clicked.connect(lambda: makerchipTOSAccepted(True)) self.optionsgrid.addWidget(self.acceptTOS, 0, 5) # self.optionsbox.setLayout(self.optionsgrid) # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) -- cgit From b6dcef53727c4a216d7b80d3085c1c0e4651a95a Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:38:49 +0530 Subject: Fix crash issue due to recursive file/directory access --- src/maker/Maker.py | 4 ++++ src/maker/ModelGeneration.py | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 4e71d7fd..f3f8b93e 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -125,6 +125,10 @@ class Maker(QtWidgets.QWidget): QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel) if reply == QtWidgets.QMessageBox.Ok: self.addverilog() + + if self.verilogfile == "": + return + self.obj_Appconfig.print_info('Add Verilog File Called') elif reply == QtWidgets.QMessageBox.Cancel: diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index a87a04e1..0a6df82c 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -1012,23 +1012,32 @@ and set the load for input ports */ init_path = '../../' if os.name == 'nt': init_path = '' + includefile = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getOpenFileName( self, "Open adding other necessary files to be included", init_path + "home")[0]) + if includefile == "": reply = QtWidgets.QMessageBox.critical( None, "Error Message", "Error: No File Chosen. Please chose a file", QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel ) + if reply == QtWidgets.QMessageBox.Ok: self.addfile() + + if includefile == "": + return + self.obj_Appconfig.print_info('Add Other Files Called') elif reply == QtWidgets.QMessageBox.Cancel: self.obj_Appconfig.print_info('No File Chosen') + return + filename = os.path.basename(includefile) self.modelpath = self.digital_home + \ "/" + self.fname.split('.')[0] + "/" @@ -1045,9 +1054,9 @@ and set the load for input ports */ print("Added the File:" + filename) self.termtitle("Added the File:" + filename) + # This function is used to add additional folder required by the verilog # top module - def addfolder(self): # self.cur_dir = os.getcwd() print("Adding the folder required by the top level module file") @@ -1055,23 +1064,31 @@ and set the load for input ports */ init_path = '../../' if os.name == 'nt': init_path = '' # noqa:F841 + includefolder = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getExistingDirectory( self, "open", "home" ) ) + if includefolder == "": reply = QtWidgets.QMessageBox.critical( None, "Error Message", "Error: No Folder Chosen. Please chose a folder", QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel ) + if reply == QtWidgets.QMessageBox.Ok: self.addfolder() + + if includefolder == "": + return + self.obj_Appconfig.print_info('Add Folder Called') elif reply == QtWidgets.QMessageBox.Cancel: self.obj_Appconfig.print_info('No File Chosen') + return self.modelpath = self.digital_home + \ "/" + self.fname.split('.')[0] + "/" -- cgit From 2b0b878d72c74e3a335b346362eaa533c5459821 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:39:49 +0530 Subject: Fix empty line lint_off crash issues --- src/maker/ModelGeneration.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/maker') diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 0a6df82c..cbb268af 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -806,10 +806,12 @@ and set the load for input ports */ init_path = '' self.cur_dir = os.getcwd() - file = open(init_path + "library/tlv/lint_off.txt").readlines() wno = " " - for item in file: - wno += " -Wno-" + item.strip("\n") + with open(init_path + "library/tlv/lint_off.txt") as file: + for item in file.readlines(): + if item and item.strip(): + wno += " -Wno-" + item.strip("\n") + print("Running Verilator.............") os.chdir(self.modelpath) self.release_home = self.parser.get('NGHDL', 'RELEASE') -- cgit From ab7dd7ed89899e2a17f70262e83437f50f2a924f Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:42:24 +0530 Subject: Fixed saving empty file crash issue --- src/maker/Maker.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index f3f8b93e..6d97e4d3 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -194,8 +194,18 @@ class Maker(QtWidgets.QWidget): # This function is used to save the edited file in eSim def save(self): - wr = self.entry_var[1].toPlainText() - open(self.verilogfile, "w+").write(wr) + try: + wr = self.entry_var[1].toPlainText() + open(self.verilogfile, "w+").write(wr) + except BaseException as err: + self.msg = QtWidgets.QErrorMessage(self) + self.msg.setModal(True) + self.msg.setWindowTitle("Error Message") + self.msg.showMessage( + "Error in saving verilog file. Please check if it is chosen." + ) + self.msg.exec_() + print("Error in saving verilog file: " + str(err)) # This is used to run the makerchip-app def runmakerchip(self): -- cgit From 272bf20219595c3c541797b1045ce9c400ab02d6 Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 01:50:56 +0530 Subject: Added a note and tooltip for Makerchip requirements --- src/maker/Maker.py | 21 +++++++++++++-------- src/maker/NgVeri.py | 4 ++++ 2 files changed, 17 insertions(+), 8 deletions(-) (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 6d97e4d3..9f4263c2 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -224,14 +224,15 @@ class Maker(QtWidgets.QWidget): if self.verilogfile.split('.')[-1] != "tlv": reply = QtWidgets.QMessageBox.warning( None, - "Do you want to automate top module?", - "Click on YES if you want top module \ - to be automatically added. \ - NOTE: a .tlv file will be created \ - in the directory of current verilog file\ - and the makerchip will be running on \ - this file. Otherwise click on NO.
\ - To not open Makerchip, click CANCEL", + "Do you want to automate the top module? ", + "Click on YES button if you want the top module \ + to be added automatically. A .tlv file will be created \ + in the directory of current verilog file \ + and the Makerchip IDE will be running on \ + this file. Otherwise click on NO button. \ + To not open Makerchip IDE, click on CANCEL button. \ +

NOTE: Makerchip IDE requires an active \ + internet connection and a browser.", QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No | QtWidgets.QMessageBox.Cancel) @@ -380,6 +381,10 @@ Please check if Verilog File Chosen.") # self.optionsbox.setLayout(self.optionsgrid) # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) self.runoptions = QtWidgets.QPushButton("Edit in Makerchip") + self.runoptions.setToolTip( + "Requires internet connection and a browser" + ) + self.runoptions.setToolTipDuration(5000) self.optionsgroupbtn.addButton(self.runoptions) self.runoptions.clicked.connect(self.runmakerchip) self.optionsgrid.addWidget(self.runoptions, 0, 4) diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index c3c4d07c..c1fbcb4e 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -226,6 +226,10 @@ class NgVeri(QtWidgets.QWidget): self.addverilogbutton = QtWidgets.QPushButton( "Run Verilog to NgSpice Converter") + self.addverilogbutton.setToolTip( + "Requires internet connection for converting TL-Verilog models" + ) + self.addverilogbutton.setToolTipDuration(5000) self.optionsgroupbtn.addButton(self.addverilogbutton) self.addverilogbutton.clicked.connect(self.addverilog) self.optionsgrid.addWidget(self.addverilogbutton, 0, 1) -- cgit From 87bc2c82192c948ddb88c52dfcd5213920920c2f Mon Sep 17 00:00:00 2001 From: rahulp13 Date: Tue, 22 Feb 2022 02:31:30 +0530 Subject: Fixed typos and resolved flake8 issues --- src/maker/Maker.py | 44 +++++++++++------------- src/maker/ModelGeneration.py | 55 ++++++++++++++---------------- src/maker/NgVeri.py | 81 ++++++++++++++++++++++---------------------- src/maker/createkicad.py | 15 ++++---- src/maker/makerchip.py | 10 +----- 5 files changed, 95 insertions(+), 110 deletions(-) mode change 100755 => 100644 src/maker/createkicad.py (limited to 'src/maker') diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 9f4263c2..c7a66204 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -27,17 +27,11 @@ # ========================================================================= # importing the files and libraries -from xml.etree import ElementTree as ET # noqa:F401 import hdlparse.verilog_parser as vlog -import time # noqa:F401 from PyQt5 import QtCore, QtWidgets -from PyQt5.QtCore import QThread, Qt # noqa:F401 -from PyQt5.QtWidgets \ - import QApplication, \ - QWidget, QLabel, QVBoxLayout # noqa:F401 +from PyQt5.QtCore import QThread from configuration.Appconfig import Appconfig import os -import subprocess # noqa:F401 import watchdog.events import watchdog.observers from os.path import expanduser @@ -101,7 +95,7 @@ class Maker(QtWidgets.QWidget): # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) self.show() - # This function is to Add new verilog file + # This function is to Add new verilog file def addverilog(self): init_path = '../../' @@ -109,7 +103,7 @@ class Maker(QtWidgets.QWidget): init_path = '' self.verilogfile = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getOpenFileName( - self, "Open verilog Directory", + self, "Open Verilog Directory", init_path + "home", "*v" )[0] ) @@ -120,9 +114,10 @@ class Maker(QtWidgets.QWidget): reply = QtWidgets.QMessageBox.critical( None, "Error Message", - "Error: No Verilog File Chosen.\ - Please chose a Verilog file", + "No Verilog File Chosen. \ + Please choose a verilog file.", QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel) + if reply == QtWidgets.QMessageBox.Ok: self.addverilog() @@ -211,12 +206,12 @@ class Maker(QtWidgets.QWidget): def runmakerchip(self): init_path = '../../' if os.name == 'nt': - init_path = '' # noqa:F841 + init_path = '' try: if not makerchipTOSAccepted(True): return - print("Running Makerchip..............................") + print("Running Makerchip IDE...........................") # self.file = open(self.verilogfile,"w") # self.file.write(self.entry_var[1].toPlainText()) # self.file.close() @@ -246,13 +241,13 @@ class Maker(QtWidgets.QWidget): file = os.path.basename('.'.join( self.verilogfile.split('.')[:-1])) f = open(filename, 'w') - flag = 1 # noqa F841 - ports = "" # noqa F841 code = code.replace(" wire ", " ") code = code.replace(" reg ", " ") vlog_ex = vlog.VerilogExtractor() vlog_mods = vlog_ex.extract_objects_from_source(code) - lint_off = open(init_path + "library/tlv/lint_off.txt").readlines() + lint_off = open( + init_path + "library/tlv/lint_off.txt" + ).readlines() string = '''\\TLV_version 1d: tl-x.org\n\\SV\n''' for item in lint_off: string += "/* verilator lint_off " + \ @@ -281,11 +276,11 @@ output logic passed, output logic failed);\n''' "Error Message", "Error: File name and module \ name are not same. Please \ - ensure that they are same", + ensure that they are same.", QtWidgets.QMessageBox.Ok) self.obj_Appconfig.print_info( - 'NgVeri Stopped due to File \ + 'NgVeri stopped due to file \ name and module name not matching error') return string += "//The $random() can be replaced \ @@ -325,7 +320,7 @@ Add \\TLV here if desired\ print("File: " + filename) self.process.start(cmd) print( - "Makerchip command process pid ---------- >", + "Makerchip IDE command process pid ---------->", self.process.pid()) except BaseException as e: print(e) @@ -333,11 +328,11 @@ Add \\TLV here if desired\ self.msg.setModal(True) self.msg.setWindowTitle("Error Message") self.msg.showMessage( - "Error in running Makerchip. \ -Please check if Verilog File Chosen.") + "Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") self.msg.exec_() - print("Error in running Makerchip. \ -Please check if Verilog File Chosen.") + print("Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") # initial = self.read_file() # while True: @@ -402,7 +397,6 @@ Please check if Verilog File Chosen.") # This function adds the other parts of widget like text box def creategroup(self): - self.trbox = QtWidgets.QGroupBox() self.trbox.setTitle(".tlv file") # self.trbox.setDisabled(True) @@ -413,7 +407,7 @@ Please check if Verilog File Chosen.") self.start = QtWidgets.QLabel("Path to .tlv file") self.trgrid.addWidget(self.start, 1, 0) self.count = 0 - self.entry_var[self.count] = QtWidgets.QLabel(" - ") + self.entry_var[self.count] = QtWidgets.QLabel() self.trgrid.addWidget(self.entry_var[self.count], 1, 1) self.entry_var[self.count].setMaximumWidth(1000) self.count += 1 diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index cbb268af..49d5da0b 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -30,19 +30,14 @@ # importing the files and libraries import re import os -import sys # noqa:F401 -import shutil # noqa:F401 -import subprocess # noqa:F401 -from PyQt5 import QtGui, QtCore, QtWidgets # noqa:F401 -from PyQt5.QtGui import * # noqa:F401 F403 +from PyQt5 import QtCore, QtWidgets from configparser import ConfigParser from configuration import Appconfig from . import createkicad import hdlparse.verilog_parser as vlog -# Class is used to generate the Ngspice Model - +# Class is used to generate the Ngspice Model class ModelGeneration(QtWidgets.QWidget): # initialising the variables @@ -75,11 +70,12 @@ class ModelGeneration(QtWidgets.QWidget): self.release_dir = self.parser.get('NGHDL', 'RELEASE') self.src_home = self.parser.get('SRC', 'SRC_HOME') self.licensefile = self.parser.get('SRC', 'LICENSE') - self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + "/Ngveri" + self.digital_home = self.parser.get( + 'NGHDL', 'DIGITAL_MODEL') + "/Ngveri" # # #### Creating connection_info.txt file from verilog file #### # - # Readinf the file and performing operations and copying it in the Ngspice - # folder + # Reading the file and performing operations and + # copying it in the Ngspice folder def verilogfile(self): Text = "" @@ -111,17 +107,21 @@ class ModelGeneration(QtWidgets.QWidget): f.write("\n") f.close() - # This function is call the sandpiper to convert .tlv file to .sv file + # This function calls the sandpiper to convert .tlv file to .sv file def sandpiper(self): init_path = '../../' if os.name == 'nt': init_path = '' # Text="Running Sandpiper............" print("Running Sandpiper-Saas for TLV to SV Conversion") - self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + init_path + "library/tlv/pseudo_rand.sv "\ - + init_path + "library/tlv/sandpiper.vh " + init_path + "library/tlv/sandpiper_gen.vh "\ - + init_path + "library/tlv/sp_default.vh " + init_path + "library/tlv/pseudo_rand_gen.sv "\ - + init_path + "library/tlv/pseudo_rand.m4out.tlv " + self.file + " " + self.modelpath + self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + \ + init_path + "library/tlv/pseudo_rand.sv " + \ + init_path + "library/tlv/sandpiper.vh " + \ + init_path + "library/tlv/sandpiper_gen.vh " + \ + init_path + "library/tlv/sp_default.vh " + \ + init_path + "library/tlv/pseudo_rand_gen.sv " + \ + init_path + "library/tlv/pseudo_rand.m4out.tlv " + \ + self.file + " " + self.modelpath self.process = QtCore.QProcess(self) self.args = ['-c', self.cmd] @@ -207,7 +207,7 @@ class ModelGeneration(QtWidgets.QWidget): QtWidgets.QMessageBox.Ok) self.obj_Appconfig.print_info( - 'NgVeri Stopped due to File \ + 'NgVeri stopped due to file \ name and module name not matching error') return "Error" modelname = str(m.name) @@ -897,7 +897,9 @@ and set the load for input ports */ self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o"): - os.remove(self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o") + os.remove( + self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o" + ) if os.path.exists( path_icm + "V" + @@ -948,7 +950,6 @@ and set the load for input ports */ self.cmd = "make" print("Running Make command in " + path_icm) - path = os.getcwd() # noqa self.process = QtCore.QProcess(self) self.process.start('sh', ['-c', self.cmd]) print("make command process pid ---------- >", self.process.pid()) @@ -977,11 +978,11 @@ and set the load for input ports */ try: if os.name == 'nt': self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') - self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe install" + self.cmd = self.msys_home + \ + "/mingw64/bin/mingw32-make.exe install" else: self.cmd = "make install" print("Running Make Install") - path = os.getcwd() # noqa try: self.process.close() except BaseException: @@ -1056,17 +1057,14 @@ and set the load for input ports */ print("Added the File:" + filename) self.termtitle("Added the File:" + filename) - - # This function is used to add additional folder required by the verilog - # top module def addfolder(self): + ''' + This function is used to add additional folder required + by the verilog top module + ''' # self.cur_dir = os.getcwd() print("Adding the folder required by the top level module file") - init_path = '../../' - if os.name == 'nt': - init_path = '' # noqa:F841 - includefolder = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getExistingDirectory( self, "open", "home" @@ -1089,7 +1087,7 @@ and set the load for input ports */ self.obj_Appconfig.print_info('Add Folder Called') elif reply == QtWidgets.QMessageBox.Cancel: - self.obj_Appconfig.print_info('No File Chosen') + self.obj_Appconfig.print_info('No Folder Chosen') return self.modelpath = self.digital_home + \ @@ -1123,7 +1121,6 @@ and set the load for input ports */ # os.chdir(self.cur_dir) # This function is used to print the titles in the terminal of Ngveri tab - def termtitle(self, textin): Text = "Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab", + Please choose a verilog file in Makerchip Tab", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please add a File in Makerchip Tab') + 'No Verilog File Chosen. ' + 'Please choose a verilog file in Makerchip Tab' + ) return self.fname = Maker.verilogFile[self.filecount] @@ -136,7 +134,8 @@ class NgVeri(QtWidgets.QWidget): else: try: shutil.copy( - self.release_dir + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.release_dir + + "/src/xspice/icm/Ngveri/Ngveri.cm", self.nghdl_home + "/lib/ngspice/" ) except FileNotFoundError as err: @@ -147,8 +146,8 @@ class NgVeri(QtWidgets.QWidget): terminalLog = self.entry_var[0].toPlainText() if "error" not in terminalLog.lower(): self.entry_var[0].append(''' -

- Model Created Successfully! +

Model Created Successfully!

''') @@ -156,35 +155,37 @@ class NgVeri(QtWidgets.QWidget): except BaseException as err: self.entry_var[0].append( - "Error in Ngspice code model generation from Verilog: " + str(err) + "Error in Ngspice code model generation " + + "from Verilog: " + str(err) ) terminalLog = self.entry_var[0].toPlainText() if "error" in terminalLog.lower(): self.entry_var[0].append(''' -

- There was an error during model creation, -
- Please rectify the error and try again ! +

There was an error during model creation, +
Please rectify the error and try again!

- ''') - - # This function is used to add additional files required by the verilog - # top module + ''') def addfile(self): + ''' + This function is used to add additional files required + by the verilog top module + ''' if len(Maker.verilogFile) < (self.filecount + 1): reply = QtWidgets.QMessageBox.critical( None, "Error Message", "Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab", + Please choose a verilog file in Makerchip Tab", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please chose\ - a Verilog File in Makerchip Tab') + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') return + self.fname = Maker.verilogFile[self.filecount] model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) # model.verilogfile() @@ -198,12 +199,12 @@ class NgVeri(QtWidgets.QWidget): None, "Error Message", "Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab", + Please choose a verilog file in Makerchip Tab", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please chose \ - a Verilog File in Makerchip Tab') + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') return self.fname = Maker.verilogFile[self.filecount] model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) @@ -260,7 +261,7 @@ class NgVeri(QtWidgets.QWidget): return self.optionsbox # This function is used to remove models in modlst of Ngspice folder if - # the user wants to remove a model.Note: files do not get removed + # the user wants to remove a model. Note: files do not get removed def edit_modlst(self, text): if text == "Edit modlst": return @@ -268,7 +269,7 @@ class NgVeri(QtWidgets.QWidget): self.entry_var[1].removeItem(index) self.entry_var[1].setCurrentIndex(0) ret = QtWidgets.QMessageBox.warning( - None, "Warning", '''Do you want to remove model:''' + + None, "Warning", '''Do you want to remove the model: ''' + text, QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel ) @@ -297,15 +298,17 @@ class NgVeri(QtWidgets.QWidget): ) except BaseException as err: QtWidgets.QMessageBox.critical( - None, "Error Message", - "The verilog model '" + str(text) + - "' could not be removed: " + str(err), - QtWidgets.QMessageBox.Ok) - + None, "Error Message", + "The verilog model '" + str(text) + + "' could not be removed: " + str(err), + QtWidgets.QMessageBox.Ok + ) - # This is to remove lint_off comments needed by the verilator warnings - # This function writes to the lint_off.txt here in the same folder def lint_off_edit(self, text): + ''' + This is to remove lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' init_path = '../../' if os.name == 'nt': init_path = '' @@ -332,14 +335,12 @@ class NgVeri(QtWidgets.QWidget): file = open(init_path + "library/tlv/lint_off.txt", 'w') for item in data: file.write(item) - return - - # else: - # return - # This is to add lint_off comments needed by the verilator warnings - # This function writes to the lint_off.txt here in the same folder def add_lint_off(self): + ''' + This is to add lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' init_path = '../../' if os.name == 'nt': init_path = '' diff --git a/src/maker/createkicad.py b/src/maker/createkicad.py old mode 100755 new mode 100644 index c8b14b6e..af30cee0 --- a/src/maker/createkicad.py +++ b/src/maker/createkicad.py @@ -30,7 +30,6 @@ from . import Appconfig import re import os -import sys # noqa F401 import xml.etree.cElementTree as ET from PyQt5 import QtWidgets @@ -68,40 +67,43 @@ class AutoSchematic: if (str(self.modelname) + '.xml') in files: xmlFound = root print(xmlFound) + break + if xmlFound is None: self.getPortInformation() self.createXML() self.createLib() + elif (xmlFound == os.path.join(self.xml_loc, 'Ngveri')): print('Library already exists...') ret = QtWidgets.QMessageBox.warning( None, "Warning", '''Library files for this model''' + ''' already exist. Do you want to overwrite it?
If yes press ok, else cancel it and ''' + - '''change the name of your vhdl file.''', + '''change the name of your verilog model.''', QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel ) + if ret == QtWidgets.QMessageBox.Ok: print("Overwriting existing libraries") self.getPortInformation() self.createXML() - self.removeOldLibrary() # Removes the exisitng library + self.removeOldLibrary() # Removes the existng library self.createLib() else: print("Library Creation Cancelled") return "Error" else: - print('Pre existing library...') + print('Pre-existing library...') ret = QtWidgets.QMessageBox.critical( self.parent, "Error", '''A standard library already ''' + '''exists with this name.
Please change the ''' + - '''name of your vhdl file and upload it again''', + '''name of your verilog model and add it again.''', QtWidgets.QMessageBox.Ok ) # getting the port information here - def getPortInformation(self): portInformation = PortInfo(self, self.modelpath) portInformation.getPortInfo() @@ -267,7 +269,6 @@ class AutoSchematic: port_list = [] j = 0 - k = 0 # noqa F841 for i in range(total): if (i < inputs): input_port[1] = inputName[i] diff --git a/src/maker/makerchip.py b/src/maker/makerchip.py index 29e1421d..152c6cbb 100755 --- a/src/maker/makerchip.py +++ b/src/maker/makerchip.py @@ -27,23 +27,15 @@ # ========================================================================= # importing the files and libraries -import sys -import os from PyQt5 import QtWidgets -from configuration.Appconfig import Appconfig -from projManagement.Validation import Validation -# from .Processing import PrcocessNetlist from . import Maker from . import NgVeri -from xml.etree import ElementTree as ET - # filecount is used to count thenumber of objects created filecount = 0 -# this class creates objects for creating the Maker and the Ngveri tabs - +# This class creates objects for creating the Maker and the Ngveri tabs class makerchip(QtWidgets.QWidget): # initialising the variables -- cgit