-
eSim
-An open source EDA tool for circuit design,
-simulation, analysis and PCB design
-
-
-
-
-Indian Institute of Technology Bombay
-August 2015
-
-
eSim
-An open source EDA tool for circuit design,
-simulation, analysis and PCB design
-
-
-
-
-Indian Institute of Technology Bombay
-August 2015
-
To
-Mr. Narendra Kumar Sinha, IAS
-An Electronics Engineer and a Bureaucrat,
-Who dreamt of educating all Indians through NMEICT and
-Who envisioned and made possible the Aakash Tablet
-
eSim was formerlly known as freeEDA/Oscad. Seeds for eSim were sown when the National -Mission on Education through ICT (NMEICT) was launched: the mission document identified -Adaption & deployment of open source simulation packages equivalent to Matlab, -OrCAD, etc., as one of the areas NMEICT would concentrate on. The FOSSEE -(free and open source software in science and engineering education) group at IIT -Bombay, of which we are a part of, initially started working on Python and Scilab. The -Standing Committee of NMEICT encouraged us to contribute to other open source -software as well. This push helped us develop eSim, an open source alternative to -OrCAD. -
eSim is an electronic design automation (EDA) tool, developed using KiCad and Ngspice. -We have made the netlist files generated by KiCad suitable for simulation through -Ngspice. In order to provide an explanation facility, we have developed a method to -automatically generate differential equations that describe a given analog circuit. -Once satisfied with simulation results, the user can create a Gerber file for PCB -fabrication. -
The FOSSEE team has also created more than 160 Scilab Textbook Companions, -each of which contains Scilab code for worked out examples of standard textbooks, -mostly in engineering and science. These have been created by the students and -professors from various educational institutions in India. These textbooks can be -downloaded free of cost from [?]. They can also be executed remotely on GARUDA cloud - [?]. -
We are embarking on a similar methodology for eSim as well: we have solved most of the -worked out examples of [?] and given the solution in Appendix A. We hope to create eSim -Textbook Companions for all other relevant standard textbooks as well in the near future, -once again through students and other volunteers. -
Solving the worked out examples of [?] was a good exercise, as it helped identify and -include some missing features. The yet to be created eSim Textbook Companions -are expected to help in this regard, while simultaneously increasing the available -documentation. -
Lab migration is another important activity that the FOSSEE team is involved in. It -provides equivalent Scilab code for Matlab based labs. This is also carried out through -students and volunteers. We are starting this activity for eSim as well: we will try to provide - -equivalent eSim based solution to all circuit design labs that currently use proprietary -software. -
Another important project supported by NMEICT is the Teach 10,000 Teachers (T10KT) -programme. This methodology, pioneered at IIT Bombay [?, ?] has demonstrated that it is -possible for the best people in the field to provide extremely high quality training -to a large number of learners simultaneously. eSim is expected to be used in the -forthcoming T10KT course on Analog Electronics, organised by IIT Kharagpur - [?]. -
We invite all EDA enthusiasts to work with us through the following resources: -1. URL for all FOSSEE activities: http://fossee.in 2. URL for all eSim resources: -http://oscad.in 3. Textbook companion: textbook-companion@oscad.in 4. Lab migration: -lab-migration@oscad.in 5. SELF workshops: SELF-workshop@oscad.in 6. eSim -development and enhancing its capabilities: Oscad-dev@oscad.in 7. Feedback on this book: -Oscad-textbook@oscad.in. -We also hope to establish forum based discussion services for eSim. -
Finally, an electronic version of this book is available for noncommercial purposes at -http://oscad.in. -
We would first like to thank Mr. N. K. Sinha, IAS, for without him, there would -have been no National Mission on Education through ICT (NMEICT), without -which, there would have been no FOSSEE, without which, there would have been -no eSim. The idealistic guiding principles of NMEICT, namely, reliance on open -source software, providing free access to e-content and Internet connectivity for all -educational institutions, egged us to contribute our best and one of the outcomes is -eSim. -
We would like to thank the former Human Resource Development Minister (HRM) Mr. -Arjun Singh for getting NMEICT started. We would like to acknowledge the former HRM Mr. -Kapil Sibal for his unstinting support and the faith he had in the NMEICT administration -team. We would like to thank the current HRM Dr. Pallam Raju for extending the tenure of -NMEICT by five more years. -
We want to thank the Members of the Standing Committee of NMEICT who met once in -two weeks for almost two years to review project proposals and to recommend them for -funding or giving suggestions for improvement. We also want to thank them for urging us to -work on more FOSS systems than what we were prepared for. Without this kind of active -support, the ecosystem required for projects like eSim to flourish, established at IIT -Bombay through the many projects funded through NMEICT, would not have -materialised. -
We want to thank the FOSSEE faculty members Profs. Prabhu Ramachandran, Madhu -Belur, Mani Bhushan, Shiva Gopalakrishnan, Jayendran Venkateswaran, Ashutosh -Mahajan and Supratik Chakraborty for establishing a vibrant FOSSEE group at -IIT Bombay. We want to thank Prof. D. B. Phatak for being a constant source -of inspiration and encouragement and for supporting our activities. We want to -thank other faculty members with NMEICT projects at IIT Bombay, namely, Profs. -Kavi Arya, Ravi Poovaiah, Santosh Noronha, Anil Kulkarni, Sridhar Iyer, Sahana -Murthy and Shishir Jha for sharing their dreams, processes and facilities. We want to -thank the staff members of all NMEICT projects at IIT Bombay in general and of -FOSSEE and Spoken Tutorial projects in particular, for providing a wonderful work -environment. -
We want to thank the IIT Bombay administration in general and R&D office in particular -for providing us with an excellent environment to make us work efficiently. We want to thank -the researchers and faculty members in our departments for providing us with necessary space -and for putting up with our tantrums. -
We would like to thank the professors, staff and students affiliated with the Wadhwani
-Electronics lab at IIT Bombay for trying out eSim in lab courses and for the useful
-suggestions. We would like to thank Abhishek Pawar for creating Spoken Tutorials on KiCad.
-We would like to thank Saket Choudhary for making the netlist files generated by KiCad
-
-compatible with Ngspice.
-
-
Let us see the steps involved in EDA. In the first stage, the specifications of the system are + id="dx1-3002"> In the first stage, the specifications of the system are laid out. These specifications are then converted to a design. The design could be in the form of a circuit schematic, logical description using an HDL language, etc. The design is then simulated and re-designed, if needed, to achieve the desired results. Once simulation achieves the specifications, the design is either converted to a PCB, a chip layout, or ported to an FPGA. The final product is again tested for specifications. The whole cycle is repeated until desired results are obtained - [?]. + [9].
A person who builds an electronic system has to first design the circuit, produce a virtual representation of it through a schematic for easy comprehension, simulate it and finally convert it into a Printed Circuit Board (PCB). There are various tools available that help do + id="dx1-3003">There are various tools available that help do this. Some of the popular EDA tools are those of Cadence, Synopys, Mentor Graphics and Xilinx. Although these are fairly comprehensive and high end, their licences are expensive, +class="cmtt-10x-x-109">Xilinx. Although these are fairly comprehensive and high end, their licenses are expensive, being proprietary.
There are some free and open source EDA tools like gEDA, computer class="cmbx-10x-x-109">aided design. eSim is created using open source software packages, such as KiCad, Ngspice, Scilab and Python. Using eSim, one can create circuit schematics, perform simulations -and design PCB layouts. It can create or edit new device models, and create or -edit subcircuits for simulation. It also has a Scilab based Mini Circuit Simulator -(SMCSim), which is capable of giving the circuit equations for each simulation -step. This feature is unique to eSim. Because of these reasons, eSim is expected to + id="dx1-3004"> Using eSim, one can create circuit schematics, perform simulations and +design PCB layouts. It can create or edit new device models, and create or edit subcircuits for +simulation. This feature is unique to eSim. Because of these reasons, eSim is expected to be useful to students, teachers and other professionals who would want to study and/or design electronic systems. eSim is also useful for entrepreneurs and small scale enterprises who do not have the capability to invest in heavily priced proprietary tools. -
This book introduces eSim to the reader and illustrates all the features of eSim with -examples. Chapter ?? gives step by step instructions to install eSim on a typical computer - +
This book introduces eSim to the reader and illustrates all the features of eSim with +examples. Chapter 2 gives step by step instructions to install eSim on a typical computer system and to validate the installation. The software architecture of eSim is presented in Chapter 3. Chapter 4 gets the user started with eSim. It takes them through a tour of eSim +href="#x1-50003">3. Chapter 4 gets the user started with eSim. It takes them through a tour of eSim + with the help of a simple RC circuit example. Chapter 5 explains how to create circuit +href="#x1-300005">5 explains how to create circuit schematics using eSim, in detail using examples. Chapter 6 illustrates how to simulate +href="#x1-430006">6 illustrates how to simulate circuits using eSim. Chapter 7 explains PCB design using eSim, in detail. The advanced -features of eSim such as Model Builder covered in Chapter ?? and Sub circuiting is -covered in Chapter ??. Appendix A presents examples, that have been worked +href="#x1-580007">7 explains PCB design using eSim, in detail. The advanced +features of eSim such as Model Builder covered in Chapter 8 and Sub circuiting +is covered in Chapter 9. Appendix A presents examples, that have been worked out using eSim, from the book Microelectronic Circuits by Sedra and Smith - [?]. Appendix ?? explains the resources available for the use and promotion of -eSim. -
The following convention has been adopted throughout this book. All the menu names, + [1]. +
The following convention has been adopted throughout this book. All the menu names, options under each menu item, tool names, certain points to be noted, etc., are given in italics. Some keywords, names of certain windows/dialog boxes, names of some @@ -602,14 +410,33 @@ yes, etc., are also mentioned in typewriter font.
To install eSim and other dependecies run the following command.
$ ../install-linux.sh –install
Above script will install eSim along with dependencies.
+
eSim will be installed to /opt/eSim +
To run eSim you can directly run it from terminal as
$ esim
or you can double click on eSim icon created on desktop after installation.
eSim is a CAD tool that helps electronic system designers to design, test and analyse their + id="dx1-5001">tool that helps electronic system designers to design, test and analyse their circuits. But the important feature of this tool is that it is open source and hence the user can modify the source as per his/her need. The software provides a generic, modular and extensible platform for experiment with electronic circuits. This software runs on all @@ -627,61 +454,61 @@ have the capability to explain the circuit by giving symbolic equations and nume values. The architecture of eSim has been designed by keeping these objectives in mind.
Various open-source tools have been used for the underlying build-up of eSim. In this section we will give a brief idea about all the modules used in eSim.
EEschema is an integrated software where all functions of circuit drawing, control, layout,
library management and access to the PCB design software are carried out within itself. It is
-the schematic editor tool used in KiCad [?]. EEschema is intended to work with PCB layout
-software such as Pcbnew. It provides netlist that describes the electrical connections of the
-PCB. EEschema also integrates a component editor which allows the creation, editing and
-visualisation of components. It also allows the user to effectively handle the symbol
+the schematic editor tool used in KiCad [11]. EEschema is intended to work with PCB
+layout software such as Pcbnew. It provides netlist that describes the electrical connections of
+the PCB. EEschema also integrates a component editor which allows the creation, editing and
+visualization of components. It also allows the user to effectively handle the symbol
libraries i.e; import, export, addition and deletion of library components. EEschema
also integrates the following additional but essential functions needed for a modern
schematic capture software: 1. Design rules check (1. Design rules check (DRC) for the automatic control of
incorrect connections and inputs of components left unconnected. 2. Generation of
+ id="x1-7005r2">2. Generation of
layout files in POSTSCRIPT or or HPGL format. 3. Generation of layout files printable via
+ id="dx1-7007">format. 3. Generation of layout files printable via
printer. 4. Bill of material generation. 5. Netlist generation for PCB layout or for
+ id="x1-7009r4">4. Bill of material generation. 5. Netlist generation for PCB layout or for
simulation.
This module is indicated by the label 1 in Fig. 3.1.
+href="#x1-200011">3.1.
As Eeschema is originally intended for PCB Design, there are no fictitious
components1
+href="oscad2.html#fn1x3">1 CvPcb is a tool that allows the user to associate components in the schematic to component
footprints when designing the printed circuit board. CvPcb is the footprint editor tool in
-KiCad [?]. Typically the netlist file generated by EEschema does not specify which printed
+KiCad [11]. Typically the netlist file generated by EEschema does not specify which printed
circuit board footprint is associated with each component in the schematic. However, this is
not always the case as component footprints can be associated during schematic capture by
setting the component’s footprint field. CvPcb provides a convenient method of associating
@@ -695,15 +522,15 @@ This is because CvPcb not only allows automatic association, but also allows to
see the list of available footprints and displays them on the screen to ensure the
correct footprint is being associated. This module is indicated by the label 3 in
Fig. 3.1.
+href="#x1-200011">3.1.
Pcbnew is a powerful printed circuit board software tool. It is the layout editor tool
-used in KiCad [?]. It is used in association with the schematic capture software
+used in KiCad [11]. It is used in association with the schematic capture software
EEschema, which provides the netlist. Netlist describes the electrical connections of
the circuit. CvPcb is used to assign each component, in the netlist produced by
EEschema, to a module that is used by Pcbnew. The features of Pcbnew are given
@@ -712,7 +539,7 @@ below:
3.1.2 CvPcb
+ id="x1-80003.1.2">CvPcb
+ id="dx1-8001">
3.1.3 Pcbnew
+ id="x1-90003.1.3">Pcbnew
+ id="dx1-9001">
dsn format allows to use more advanced
This module is indicated by the label 4 in Fig. 3.1. +href="#x1-200011">3.1.
It converts KiCad generated netlists to Ngspice compatible format. Also it facilitates adding model library of components and subcircuits. Following are the different functionality lies under conversion.
This feature helps the user to perform different types of analysis such as Operating point analysis, DC analysis, AC analysis, transient analysis, etc. It has the facility + id="dx1-11001">DC analysis, AC analysis, transient analysis, etc. It has the facility to
eSim sources are added from eSim-sources package. Sources auch as SINE, AC, DC, PULSE -are in this lobrary. Input to allthe sources adde in the circuit are given in source +are in this library. Input to all the sources added in the circuit are given in source details.
eSim adds Ngspice model using this facility.
Devices like Diode, JFET, MOSFET, IGBT, MOS etc added in the circut can be modeled -using device model libraries. eSim also proveides editing and adding new model libraries. -While converting Kicad to Ngspice these library files added to the corresponding devices uesd -in the circuit. + id="x1-140003.1.4">Device Modeling +
Devices like Diode, JFET, MOSFET, IGBT, MOS etc added in the circuit can be modeled +using device model libraries. eSim also provides editing and adding new model libraries. While +converting Kicad to Ngspice these library files added to the corresponding devices used in the +circuit.
Subcircuits are the circuits within a circuits. Subcircuiting helps to reuse the part of the circuits. The sub circuit in the main circuits are added using this facility. Also, eSim provides -us with editing the already exixting subcircuits. Sub circuits are saved separately in different +us with editing the already existing subcircuits. Sub circuits are saved separately in different folders.
This tool provides the facility to define a new model for devices such as, 1. Diode 2. Bipolar + id="x1-16002r1">1. Diode 2. Bipolar Junction Transistor (BJT) 3. Metal Oxide Semiconductor Field Effect Transistor + id="x1-16004r3">3. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 4. Junction Field Effect Transistor (JFET) 5. IGBT and 6. Magnetic + id="x1-16005r4">4. Junction Field Effect Transistor (JFET) 5. IGBT and 6. Magnetic core. This module also helps edit existing models. It is developed by us for eSim and it is indicated by the label 5 in Fig. 3.1. +href="#x1-200011">3.1.
This module allows the user to create a subcircuit for a component. Once the subcircuit for a component is created, the user can use it in other circuits. It has the facility to define new components such as, Op-amps and IC-555. This component also helps edit existing subcircuits. This module is developed by us for eSim and it is indicated by the label 6 in Fig. 3.1. +href="#x1-200011">3.1.
It converts KiCad generated netlists to Ngspice (see Sec. 3.1.8) compatible format. It has the +href="#x1-190003.1.8">3.1.8) compatible format. It has the capability to 1. Insert parameters for fictitious components 2. Convert IC into discrete + id="x1-18004r1">1. Insert parameters for fictitious components 2. Convert IC into discrete blocks 3. Insert D-A and A-D converter at appropriate places 4. Insert plotting + id="x1-18006r3">3. Insert D-A and A-D converter at appropriate places 4. Insert plotting and printing statements in netlist and 5. Find current through all components. + id="x1-18008r5">5. Find current through all components.
This module is developed by us for eSim and it is indicated by the label 7 in Fig. 3.1. +href="#x1-200011">3.1.
Ngspice is a general purpose circuit simulation program for nonlinear dc, nonlinear transient, -and linear ac analyses [?]. Circuits may contain resistors, capacitors, inductors, mutual +and linear ac analyses [12]. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFET. This module is indicated by the label 9 in + id="dx1-19002">BJTs, JFETs, MESFETs, and MOSFET. This module is indicated by the label 9 in Fig. 3.1. +href="#x1-200011">3.1.
Fig. 3.1 shows the work flow in eSim. The block diagram consists of mainly three +href="#x1-200011">3.1 shows the work flow in eSim. The block diagram consists of mainly three parts:
Here we explain the role of each block in designing electronic systems. Circuit design is the @@ -892,7 +719,7 @@ first step in the design of an electronic circuit. Generally a circuit diagram i paper, and then entered into a computer using a schematic editor. EEschema is the schematic editor for eSim. Thus all the functionalities of EEschema are naturally available in eSim. + id="dx1-20002">
Libraries for components, explicitly or implicitly supported by Ngspice, have been created using the features of EEschema. As EEschema is originally intended for PCB design, there are no fictitious components such as voltage or current sources. Thus, a new library for different @@ -917,8 +744,8 @@ format. The type of simulation to be performed and the corresponding options are provided through a graphical user interface (GUI). This is called Analysis Inserter in eSim.
eSim uses Ngspice for analog, digital, mixed-level/mixed-signal circuit simulation. Ngspice -is based on three open source software packages [?]: +is based on three open source software packages [14]:
It is a part of gEDA project. Ngspice is capable of simulating devices with BSIM, EKV, HICUM, + id="dx1-20003">project. Ngspice is capable of simulating devices with BSIM, EKV, HICUM, HiSim, PSP, and PTM models. It is widely used due to its accuracy even for the latest + id="dx1-20007">PSP, and PTM models. It is widely used due to its accuracy even for the latest technology devices.
In this chapter we will get started with eSim. We will run through the various options available with an example circuit. Referring to this chapter will make one familiar with eSim and will help plan the project before actually designing a circuit. Lets get started.
After installtion is completed, when the eSim is run the first window that appears is + id="x1-230004.1.1">Workspace +
After installation is completed, when the eSim is run the first window that appears is workspace dialog as shown in Fig. 4.1.
The defalut eSim-Workspace can be chosen if the The default eSim-Workspace can be chosen if the ok or cancel button is clicked. Else to
create new workspace browse button is used.
The main GUI window of eSim is as shown in Fig. 4.2 The eSim main GUI window consists the following symbols.
@@ -1006,56 +833,56 @@ class="enumerate">Dockarea
5. However, if an already existing project is opened, one would get the schematic
editor window along with a Load error. This is illustrated in Fig. 4.4. This
+ id="dx1-25003">. This is illustrated in Fig. 4.4. This
error occurs because the schematic that is opened has not been loaded with
the libraries mentioned in the Load Error message. Close the Load Error
message by clicking on the Close button. The RC circuit diagram opens up
as shown in Fig. 4.5. Now the circuit schematic can be created/edited. To
+href="#x1-250055">4.5. Now the circuit schematic can be created/edited. To
know how to use the schematic editor to create circuit schematics, refer to
Chapter 5.
+href="#x1-300005">5.
4.1.2 Main-GUI
+ id="x1-240004.1.2">Main-GUI
Toolbar
+ id="x1-250004.1.2">Toolbar
. This file is
stimulated using Ngspice tool. Clicking on this tool Simulation, Ngspice and
- Pthon plotting window will open, as shown in Fig. 4.6. It shows the output
- waweform of project.
Figure 4.4: Schematic Editor Window of an existing Project
+class="content">Schematic Editor Window of an existing Project
Figure 4.5: Schematic Editor Window of an existing Project
+class="content">Schematic Editor Window of an existing Project
Open the project RC_pcb available in the Examples folder downloaded from the eSim website. On clicking the Footprint Editor tool, we see the corresponding RC_pcb.net file for RC circuit. This window is shown in Fig. 4.7. The main purpose of this window is to +href="#x1-250107">4.7. The main purpose of this window is to let one choose the footprints for the various components in the circuit. Let us view the footprint C1 for capacitor C1. Click on C1 from the right hand side of CvPcb window. Click on View Selected Footprint tool from the tool bar of CvPcb + id="dx1-25008"> window. This will show the footprint corresponding to C1. This is illustrated in Fig. 4.8. To know more about how to assign footprints to components, see +href="#x1-250118">4.8. To know more about how to assign footprints to components, see Chapter 7. +href="#x1-580007">7.
To create a new model library New button is clicked which then opens the template library folder. We can choose from the template library that can be edited, to create the new library and the click on Save to save the edited model library. Also the existing - library can be edited usind Edit option. The user can also use their own library by uploading it using Upload button.
Project explorer has tree of all the project previously added in it. On right clicking the project we can simply remove or refresh the project in the explorer. Also on right clicking the project file can be opened in the text editor which can then be @@ -1255,37 +1082,37 @@ edited.
Console area provides with the errors and active commands running.
Fig. 5.1 shows the schematic editor and the various menu and toolbars. We will explain them +href="#x1-310011">5.1 shows the schematic editor and the various menu and toolbars. We will explain them briefly in this section.
The top menu bar will be available at the top left corner. Some of the important menu options in the top menu bar are:
@@ -1347,14 +1174,14 @@ src="figures/print.png" alt="PIC"
>
Some of the important tools in the top toolbar are discussed below. They are marked in Fig. 5.3.
The toolbar on the right side of the schematic editor window has many important tools. Some of them are marked in Fig. 5.4.
Let us now look at each of these tools and their uses.
Some of the important tools in the toolbar on the left are discussed below. They are marked in Fig. 5.5.
A set of keyboard keys are associated with various operations in the schematic editor. These
-keys save time and make it easy to switch from one operation to another. The list of hotkeys
-can be viewed by going to Preferences in the top menu bar. Choose Hotkeys and
-select List current keys. The hotkeys can also be edited by selecting the option
-Hotkeys
+ !Schematic Editor A set of keyboard keys are associated with various operations in the
+schematic editor. These keys save time and make it easy to switch from one operation to
+another. The list of hotkeys can be viewed by going to Preferences in the top menu bar.
+Choose Hotkeys and select List current keys. The hotkeys can also be edited by selecting the
+option Edit Hotkeys. Some frequently used hotkeys, along with their functions, are given
below:
@@ -1558,8 +1383,8 @@ below:
.
There are certain differences between the schematic created for simulation and that created for PCB design. We need certain components like plots and current sources. for simulation whereas these are not needed for PCB design. For PCB design, we would require connectors (e.g. DB15 and 2 pin connector) for taking signals in and out of the PCB whereas these have no meaning in simulation. This section covers schematic creation for simulation. Refer to Chapter 7 to know how to create schematic for PCB +href="#x1-580007">7 to know how to create schematic for PCB design.
The first step in the creation of circuit schematic is the selection and placement of required components. Let us see this using an example. Let us create the circuit schematic of an RC filter given in Fig. 5.6 and do a transient simulation.
We would need a resistor, a capacitor, a voltage source, ground terminal and some plot components. To place a resistor on the schematic editor window, select the R in the field Name of the component selection window as shown in Fig. 5.7. Click on OK. A resistor +href="#x1-380027">5.7. Click on OK. A resistor will be tied to the cursor. Place the resistor on the schematic editor by a single click.
To place the next component, i.e., capacitor, click again on the schematic editor. Type List all and choose gnd. Once all the components are placed, the schematic editor would look like the Fig. 5.8.
Let us rotate the resistor to complete the circuit as shown in Fig. 5.6. To rotate the +href="#x1-370026">5.6. To rotate the resistor, place the cursor on the resistor and press the key R. Note that if the cursor is placed above the letter R?) on the resistor, it asks to clarify selection. Component R. This can be avoided by placing the cursor slightly away from the letter R as shown in Fig. 5.9. This applies to all components.
If one wants to move a component, place the cursor on top of the component and press the key M. The component will be tied to the cursor and can be moved in any direction. + id="dx1-38006">
The next step is to wire the connections. Let us connect the resistor to the capacitor. To do so, point the cursor to the terminal of resistor to be connected and press the key W. It has now changed to the wiring mode. Move the cursor towards the terminal of the capacitor and click on it. A wire is formed as shown in Fig. 5.10a. +href="#x1-39002r1">5.10a.
@@ -1725,7 +1550,7 @@ class="cmr-9">(a)
class="cmr-9">Initial
stages
(b)
class="cmr-9">Wiring
done
PWR_FLAG
Similarly connect the wires between all terminals and the final schematic would look like Fig. 5.10b. +href="#x1-39003r2">5.10b.
We need to assign values to the components in our circuit i.e., resistor and capacitor. Note that the sine voltage source has been placed for simulation. The specifications of sine source will be given during simulation. To assign value to the resistor, place the cursor above the @@ -1771,7 +1596,7 @@ class="cmti-10x-x-109">Field value
. Type 1k in the Edit value field box as shown in Fig. 5.11. 1k means 15.11. 1k means 1kΩ. Similarly give the value 1u for the capacitor. 1u means 1μF. > + id="x1-4000211">
The next step is to annotate the schematic. Annotation gives unique references to the components. To annotate the schematic, click on Annotate schematic tool from the top toolbar. Click on annotation, then click on OK and finally click on close as shown in Fig. 5.13. The schematic is now annotated. The question marks next to +href="#x1-4100813">5.13. The schematic is now annotated. The question marks next to component references have been replaced by unique numbers. If there are more than one instance of a component (say resistor), the annotation will be done as R1, R2, etc. @@ -1817,14 +1642,14 @@ class="cmti-10x-x-109">Perform electric rules check tool from the top toolbar. Click on Test Erc button. The error as shown in Fig. 5.12 +href="#x1-4100712">5.12 may be displayed. Click on close in the test erc window.
There will be a green arrow pointing to the source of error in the schematic. Here it points to the ground terminal. This is shown in Fig. 5.14.
To correct this error, place a PWR_FLAG from the EEschema library power. Connect the + id="dx1-41010">Connect the power flag to the ground terminal as shown in Fig. 5.10c. More information about +href="#x1-39004r3">5.10c. More information about PWR_FLAG is given in Sec. ??. One needs to place PWR_FLAG wherever the error shown in Fig. 5.12 is obtained. Repeat the ERC. Now there are no errors. With this we have created +href="#x1-4100712">5.12 is obtained. Repeat the ERC. Now there are no errors. With this we have created the schematic for simulation.
To simulate the circuit that has been created in the previous section, we need to generate its
netlist. Netlist is a list of components in the schematic along with their connection
information. To do so, click on the To do so, click on the Generate netlist tool from the top toolbar. Click on spice
from the window that opens up. Uncheck the option Default Format. Then click on Netlist.
This is shown in Fig. 5.15. Save the netlist. This will be a 5.15. Save the netlist. This will be a .cir file. Do not change the
directory while saving.
+class="cmtt-10x-x-109">Default Format then 3. Click on Netlist
Now the netlist is ready to be simulated. Chapter 6 explains how to perform simulations. -Refer to [?] or [?] to know more about EEschema. +href="#x1-430006">6 explains how to perform simulations. +Refer to [15] or [16] to know more about EEschema.
In the following sections, we shall describe each of the above steps.
In order to simulate a circuit, the user must define the type of analysis to be done on the
circuit. The types of analysis include include Operating point analysis, DC analysis,
Kicad to
Ngspice from the eSim toolbar, one gets the Analysis Inserter GUI as shown in Fig. 6.1. The
+href="#x1-440031">6.1. The
various tabs in this GUI correspond to the various types of analysis. The user can enter
the details, needed to perform simulation, in the corresponding fields under these
tabs.
@@ -2000,7 +1825,7 @@ tabs.
>
+ id="x1-440031">
Figure 6.1: Analysis Insertor GUI
+class="content">Analysis Inserter GUI
eSim supports three types of analyses: 1. DC Analysis (Operating Point and DC Sweep) + id="x1-45002r1">1. DC Analysis (Operating Point and DC Sweep) 2. AC Small-signal Analysis 3. Transient Analysis. + id="dx1-45003">2. AC Small-signal Analysis 3. Transient Analysis. Other analysis in the Analysis Inserter are currently under progress. The different types of -analyses supported in eSim are explained below [?]. +analyses supported in eSim are explained below [17].
The DC analysis determines the dc operating point of the circuit with inductors shorted and
capacitors opened. The DC analysis options are specified on the .dc and and .op control
+ id="dx1-46003"> control
lines.
There is assumed to be no time dependence on any of the sources within the system
description. The simulator algorithm subdivides the circuit into those portions which require
@@ -2061,9 +1886,9 @@ user-specified range and the dc output variables are stored for each sequential
value.
AC analysis is limited to analog nodes. It represents the small signal, sinusoidal
solution of the analog system described at a particular frequency or set of frequencies.
@@ -2081,9 +1906,9 @@ unity and zero phase, so that output variables have the same value as the transf
function.
Transient analysis is an extension of DC analysis to the time domain. A .tran control
line.
By default DC analysis option appears when one clicks on Analysis Inserter. Here we need
@@ -2114,7 +1939,7 @@ class="cmti-10x-x-109">stop AC small-signal analysis
+ id="x1-470006.1.1">AC small-signal analysis
+ id="dx1-47001">
Transient analysis
+ id="x1-480006.1.1">Transient analysis
+ id="dx1-48001">
6.1.2 DC analysis inserter
+ id="x1-490006.1.2">DC analysis inserter
Fig. 6.2 gives an example of 6.2 gives an example of DC analysis inserter. In this example, v1 is the input
voltage source which Add Simulation Data, the analysis command is gener
When we check the option Operating Point analysis on the DC analysis window, on the DC analysis window, .op gets
appended to the analysis statement. The inclusion of the line .op in the analysis file directs Ngspice to determine the dc
operating point of the circuit with inductors shorted and capacitors opened.
When one clicks on the option AC in the Analysis Inserter GUI, the window given in
Fig. 6.3 appears. Here one needs to enter the details of .ac oct no fstart fstop When one clicks on the option Transient in the Analysis Inserter GUI, the window given in
Fig. 6.4 appears. Here one needs to enter the details of 6.4 appears. Here one needs to enter the details of start time, step time, and stop time.
@@ -2246,7 +2071,7 @@ class="cmti-10x-x-109">Add Simulation Data. The analysis statement is
generated. It is of the form:
.tran tstep tstop tstart
+ id="dx1-51002">
Here, tstep is the printing or plotting increment for line-printer output. For use
with the post-processor, >, the circuit is analyzed and outputs are
>
+ id="x1-510034">
Source details is basically a dynamic tab, i.e. the feilds are added as per the circuit. The
+ id="x1-520006.2">Adding Source Details
+ Source details is basically a dynamic tab, i.e. the fields are added as per the circuit. The
number of sources schematic has like AC,DC is the number of fields that get added in the
GUI. Consider a Half-Adder circuit as shown in Fig. 6.5 Here, total three DC input source are used and hence the source detail GUI wuould be
+ Here, total three DC input source are used and hence the source detail GUI would be
having three input fields as shown is Fig. 6.6
Spice based simulators include a feature which allows accurate modeling of semiconductor
devices such as diodes, transistors etc. Model libraries holds these features to define
models for devices such as diodes, MOSFET, BJT, JFET, IGBT, Magnetic core
etc.
The fields in this tab are added for each such device in the circuit and the corresponding
model library is added. In the example of bridgerectifier as shown in Fig. 6.7 for four diodes
-library files are added as in Fig. ?? Sub-circuiting is the way of hierarchical modeling. The sub circuit file in the main circuits
needs to be added before converting it. Let us consider the simple example of Full-Adder
circuit containing two half adder sub circuits.
After Filling up the values in all the above mentioned fields the convert button is pressed for
the conversion process to finish. If all the files are added the successful messege box is
+class="cmtt-10x-x-109">successful
.dc sourcename vstart vstop vincr
The .dc line defines the dc transfer curve source and sweep limits (with capacitors open and
@@ -2142,13 +1967,13 @@ class="cmtt-10x-x-109">vincr are the starting, final, and incrementing va
source.
6.1.3 AC analysis inserter
+ id="x1-500006.1.3">AC analysis inserter
+ id="dx1-50001">
.ac lin np fstart fstop
Here, dec stands for decade variation and nd is the number of points per decade. AC from the
sourcesSpice library.
6.1.4 Transient analysis inserter
+ id="x1-510006.1.4">Transient analysis inserter
+ id="dx1-51001">
Figure 6.4: Transient Analysis GUI
+class="content">Transient Analysis GUI
6.2 Adding Source Details
-
-6.6
+ id="x1-520026">
Figure 6.6: Source Details of Half-Adder
+class="content">Source Details of Half-Adder
6.3 Adding Ngspice Model
+ id="x1-530006.3">Adding Ngspice Model
6.4 Adding Device Model Library
+ id="x1-540006.4">Adding Device Model Library
6.7 for four diodes
+library files are added as in Fig. 6.8
+ id="x1-540017">
Figure 6.7: Schematic of Bridge Rectifier
+class="content">Schematic of Bridge Rectifier
6.5 Adding Sub Circuit
+ id="x1-550006.5">Adding Sub Circuit
6.6 Kicad to Ngspice Conversion
+ id="x1-560006.6">Kicad to Ngspice Conversion
Figure 6.9: Successful Conversion Pop-Up Window
+class="content">Successful Conversion Pop-Up Window
After the Kicad to Ngspice conversion is successfully completed simulation tab on the toolbar is clicked to check the output waveform of the project. The windows shown if Fig. 6.10 and +href="#x1-5700110">6.10 and Fig. 6.11 are opned in dockarea. +href="#x1-5700211">6.11 are opned in dockarea.
Following are the commands to be given in Ngspice window. @@ -2435,11 +2260,11 @@ class="cmtt-10x-x-109">plot allv - Plots all the voltage waveforms.
The output in the ngspice window is shown in Fig. 6.12
Likewise, in the pythonplot window the checkbox of a perticular source can be chosen +
Likewise, in the pythonplot window the checkbox of a particular source can be chosen and then PLOT button is clicked. Ths output in pythonplot window is shown in +class="cmtt-10x-x-109">PLOT button is clicked. This output in pythonplot window is shown in Fig. 6.13 +href="#x1-5700413">6.13
In Chapter 5, we have seen the differences between schematic for simulation and schematic +href="#x1-300005">5, we have seen the differences between schematic for simulation and schematic for PCB design. Let us design the PCB for an RC circuit. A resistor, capacitor, ground, power flag and a connector are required. Connectors are used to take signals in and out of the PCB.
Create the circuit schematic as shown in Fig. 7.1. The two pin connector (7.1. The two pin connector (CONN_2) can
be placed from the EEschema library conn. See Sec. ?? to know more about EEschema
library conn. Do the annotation and test for ERC. Refer to Chapter 5 to know more about
+href="#x1-300005">5 to know more about
basic steps in schematic creation.
The netlist for PCB is different from that for simulation. To generate netlist for PCB, click on
the Generate netlist tool from the top toolbar in Schematic editor. In the Netlist window,
under the tab Pcbnew, click on the button click on the button Netlist. This is shown in Fig. 7.2. Click on
+href="#x1-600042">7.2. Click on
Save in the Save netlist file dialog box that opens up. Do not change the directory
or the name of the netlist file. Save the schematic and close the schematic editor.
@@ -2537,7 +2362,7 @@ or the name of the netlist file. Save the schematic and close the schematic edit
>
+ id="x1-600042">
. The netlist created for simulation
class="cmti-10x-x-109">has an extension
+ id="x1-590011">
Figure 7.1: Final circuit schematic for RC low pass circuit
+class="content">Final circuit schematic for RC low pass circuit
7.1.1 Netlist generation for PCB
+ id="x1-600007.1.1">Netlist generation for PCB
+ id="dx1-60001">
+ id="dx1-60002">
Figure 7.2: Netlist generation for PCB
+class="content">Netlist generation for PCB
Once the netlist for PCB is created, one needs to map each component in the netlist to a footprint. The tool Footprint Editor is used for this. eSim uses CvPcb as its footprint editor. CvPcb is the footprint editor tool in KiCad. + id="dx1-61004">
If one opens the Footprint Editor after creating the .net netlist file, the Footprint editor as shown in Fig. 7.3 will be obtained. The menu bar and toolbars and the panes are marked in +href="#x1-620023">7.3 will be obtained. The menu bar and toolbars and the panes are marked in this figure. The menu bar will be available in the top left corner. The left pane has a list of components in the netlist file and the right pane has a list of available footprints for each component.
Note that if the Footprint Editor is opened before creati
right panes will be empty.
Some of the important tools in the toolbar are shown in Fig. 7.4. They are explained below:
+href="#x1-630014">7.4. They are explained below:
To view a footprint in 2D, select it from the right pane and click on View selected footprint
from the menu bar. Let us view the footprint for SM1210. Choose SM1210 from
the right pane as shown in Fig. 7.5. On clicking the 7.5. On clicking the View selected footprint tool,
the Footprint window with the view in 2D will be displayed. Click on the 3D
tool in the Footprint window, as shown in Fig. 7.6. A top view of the selected
+href="#x1-640046">7.6. A top view of the selected
footprint in 3D is obtained. Click on the footprint and rotate it using mouse to get 3D
views from various angles. One such side view of the footprint in 3D is shown in
Fig. 7.7.
+href="#x1-640057">7.7.
Toolbar
+ id="x1-630007.1.3">Toolbar
+ id="x1-630014">
Figure 7.4: Some important tools in the toolbar
+class="content">Some important tools in the toolbar
7.1.4 Viewing footprints in 2D and 3D
+ id="x1-640007.1.4">Viewing footprints in 2D and 3D
+ id="dx1-64001">
+ id="dx1-64002">
+class="cmti-10x-x-109">View selected footprint
Click on C1 from the left pane. Choose the footprint C1 from the right pane by double
@@ -2729,7 +2554,7 @@ right pane by double clicking on it. Similarly choose the footprint R3 for the resistor R1. The
footprint mapping is shown in Fig. 7.8. Save the footprint association by clicking on the 7.8. Save the footprint association by clicking on the Save
netlist and footprint files tool from the Footprint Editor window closes automatically.
>
+ id="x1-650018">
Figure 7.8: Footprint mapping done
+class="content">Footprint mapping done
Note that one needs to browse to the directory where the
the ‘.net’ file in the same directory.
The next step is to place the footprints and lay tracks between them to get the layout. This is
done using the Layout Editor tool. eSim uses Pcbnew, the layout creation tool in KiCad, as its
layout editor.
The layout editor with the various menu bar and toolbars is shown in Fig. 7.9.
+href="#x1-670029">7.9.
Some of the important menu options in the top menu bar are shown in Fig. 7.10. They are
+href="#x1-6700310">7.10. They are
explained below:
A list of hotkeys are given below:
7.2 Creation of PCB layout
+ id="x1-660007.2">Creation of PCB layout
+ id="dx1-66001">
+ id="dx1-66002">
7.2.1 Familiarising the Layout Editor tool
+ id="x1-670007.2.1">Familiarizing the Layout Editor tool
+ id="dx1-67001">
+ id="x1-670029">
Figure 7.9: Layout editor with menu bar, toolbars and layer options marked
+class="content">Layout editor with menu bar, toolbars and layer options marked
+ id="x1-6700310">
Figure 7.10: Top toolbar with important tools marked
+class="content">Top toolbar with important tools marked
Top toolbar
+ id="x1-680007.2.1">Top toolbar
7.2.2 Hotkeys
+ id="x1-690007.2.2">Hotkeys
+ id="dx1-69001">
from the option Hotkeys.
Click on Layout Editor from the eSim toolbar. Click on Read Netlist tool from the top @@ -2897,14 +2722,14 @@ class="cmti-10x-x-109">Read Current Netlist on the Netlist window. The message area in the Netlist window says that the RC_pcb.net has been read. The sequence of operations is shown in Fig. 7.11. +href="#x1-7000411">7.11.
The footprint modules will now be imported to the top left hand corner of the layout editor window. This is shown in Fig. 7.12.
Zoom in to the top left corner by pressing the key F1 or using the scroll button of the mouse. The zoomed in version of the imported netlist is shown in Fig. 7.13. +href="#x1-7000613">7.13.
Let us now place this in the center of the layout editor window.
Click on Glob move and place. Choose move all modules. The sequence of operations is shown in Fig. 7.14. +href="#x1-7000714">7.14. Click on Yes on the confirmation window to move the modules. Zoom in using the F1 key. The current placement of components after zooming in is shown in Fig. 7.15a. +href="#x1-70008r1">7.15a.
@@ -3027,7 +2852,7 @@ class="cmr-9">of the
class="cmr-9">layout
editor
moving
class="cmr-9">P1
We need to arrange the modules properly to lay tracks. Rotate the connector P1 by placing the cursor on top of P1 and pressing R. Move it by placing the cursor on top of it and pressing M. The final placement is shown in Fig. 7.15b. +href="#x1-70009r2">7.15b.
Let us now lay the tracks. Let us first change the track width. Click on Design rules from
the top menu bar. Click on Design rules. This is shown in Fig. 7.16. The 7.16. The Design Rules Editor
window opens up. Here one can edit the various design rules. Double click on the track width
field to edit it. Type 0.8 and press Enter. Click on OK. Fig. 7.17 shows the sequence of
+href="#x1-7001517">7.17 shows the sequence of
operations.
+class="cmti-10x-x-109">OK
Click on Back from the Layer options as shown in Fig. 7.18.
Let us now start laying the tracks. Place the cursor above the left terminal of R1 in the layout editor window. Press the key x. Move the cursor down and double click on the left terminal of C1. A track is formed. This is shown in Fig. 7.19a. +href="#x1-70018r1">7.19a.
@@ -3157,7 +2982,7 @@ class="cmr-9">resistor
class="cmr-9">and
capacitor
capacitor
class="cmr-9">and
connector
and
class="cmr-9">resistor
Similarly lay the track between capacitor C1 and connector P1 as shown in Fig. 7.19b. The last track needs to be laid at an angle. To do so, place the cursor +href="#x1-70019r2">7.19b. The last track needs to be laid at an angle. To do so, place the cursor above the second terminal of R1. Press the key x and move the cursor diagonally down. Double click on the other terminal of the connector. The track will be laid as shown in Fig. 7.19c. All tracks are now laid. The next step is to create PCB +href="#x1-70020r3">7.19c. All tracks are now laid. The next step is to create PCB edges.
Choose PCBLayer options to add edges. Click on Add graphic line or polygon from the toolbar on the left. Fig. 7.20 shows the sequence of operations. Let us now +href="#x1-7002320">7.20 shows the sequence of operations. Let us now start drawing edges for PCB.
Click to the left of the layout. Move cursor horizontally to the right. Click once to change orientation. Move cursor vertically down. Draw the edges as shown in Fig. 7.21. Double click +href="#x1-7002421">7.21. Double click to finish drawing the edges.
Click on Error messages tab. Click on OK to close DRC control window. Fig. 7.22 shows the sequence of +href="#x1-7002622">7.22 shows the sequence of operations.
Click on Save board on the top toolbar. class="cmti-10x-x-109">File from the top menu bar. Click on Plot. This is shown in Fig. 7.23. The plot window opens up. One can choose which layers to plot by +href="#x1-7002823">7.23. The plot window opens up. One can choose which layers to plot by selecting/deselecting them from the Layers pane on the left side. One can also choose the format used to plot them. Choose Plot. The message window shows the location in which the Gerber files are created. Click on Close. This is shown in Fig. 7.24. +href="#x1-7002924">7.24.
Creating Gerber files: 1. Choose Gerber as the plot format, 2. Click on
Plot. Message window shows location in which Gerber files are created, 3. Click on Close
The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to [?] -or [?]. +
The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to + [15] or [16].
Spice based simulators include a feature which allows accurate modeling of semiconductor + id="x1-710008">Model Editor +
Spice based simulators include a feature which allows accurate modeling of semiconductor devices such as diodes, transistors etc. eSim Model Builder provides a facility to define a new model for devices such as diodes, MOSFET, BJT, JFET, IGBT, Magnetic core etc. Model Builder in eSim lets the user enter the values of parameters depending on the type of device @@ -3349,140 +3174,140 @@ of the device. A newly created model can be exported to the model library and one can import it for different projects, whenever required. Model Builder also provides a facility to edit existing models. The GUI of the model editor is as shown in Fig. 8.1 -
eSim lets used create new model libraries based on the template model libraries. on selecting + id="x1-720008.1">Creating New Model Library +
eSim lets used create new model libraries based on the template model libraries. on selecting New button the window is popped to name the new library file. The library file has to be unique otherwise the error message appears on the window. -
After the OK button is pressed the type of model library to be created is chosen by +
After the OK button is pressed the type of model library to be created is chosen by selecting one of the types on the left hand side i.e. Diode, BJT, MOS, JFET, IGBT, Magnetic Core. The template model library is then opened in the tabular form. As shown in Fig. 8.3 -
The new parameters can be added or a current parameters can be removed using The new parameters can be added or a current parameters can be removed using ADD
and REMOVE buttons. Also the values of parameters can be changed in the table. The
adding and removing of the parameters in a library files is as shown in the Fig. 8.4 and
+href="#x1-720034">8.4 and
Fig. 8.5
- After the editing of the model library is done the file can be saved selecting the After the editing of the model library is done the file can be saved selecting the SAVE
button. These libraries are saved in the Use Libraries folder under DecviceModelLibrary folder
in the project folder.
The current model library can be saved using Editing Current Model Library
+ The current model library can be saved using EDIT option. On clicking the EDIT button the
file dialog opens where all the library files are saved as shown in Fig. 8.6
- Further on clicking the Further on clicking the SAVE button the edited model library is saved in the Use
Libraries folder under DecviceModelLibrary folder in the project folder.
eSim can not read the model library file in the .lib form. The file needs to be converted into
+ id="x1-740008.3">Converting Library file to XML file
+ eSim can not read the model library file in the .lib form. The file needs to be converted into
XML so as to make it readable and editable in model editor. Any new netlist that user wants
to use in the eSim need to be convertedinto xml before using it in a project. hence eSim
provides us to upload the new netlist which converts in into xml. on clicking UPLOAD button
@@ -3493,16 +3318,16 @@ folder with different name.
Subcircuit is a way to implement hierarchical modeling. Once a subcircuit for a compo- nent
-is created, it can be used in other circuits. eSim provides an easy way to create a subcircuit.
-Thw Following Fig. 9.1 shows the window that is opened when the Sub-CIrcuit tool is chosen
-from the toolbar. Let us take an example of Half-adder circuit. To create a new sub circuit select the New
Subcircuit Schematic.Fig. 9.2 shows the half-adder circuit and Fig. 9.3 shows the block of the
+href="#x1-760012">9.2 shows the half-adder circuit and Fig. 9.3 shows the block of the
sub circuit included in the main circuit. NOTE: All the input and output of the sub circuits are connected to the port component.
@@ -3539,7 +3364,7 @@ class="content">Half-Adder Sub-circuit After creating the schematic kicad netlist is generated as explained in section and convert
@@ -3558,17 +3383,17 @@ Also the respective input and output ports can be checked by reading the .sub
file.
+ id="x1-76003r147">
Plot the Input and Output Waveform of RC ckt where the input voltage (Vs) is
50Hz, 3V peak to peak. Value for Resistor (R) and Capacitor(C) is 1k and 1uf
respectively.
Draw the schematic and label the nodes as shown in Fig. A.1a using the schematic editor.
Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor.
Perform Electric Rules check using the Perform electric rules check tool from the top toolbar.
Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for
simulation using the Generate Netlist tool from the top toolbar. This is shown
Fig. A.1.
+href="#x1-810011">A.1.
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.2.
+href="#x1-810022">A.2.
Enter start time = 0ms, step time = 1ms, stop time = 100ms.
Now Click on Sources Details Tab to Enter Sine Source Values as shown in
Fig. A.4.
+href="#x1-810044">A.4.
Then Press Convert Button which will generate Ngspice Netlist (rc.cir.out)
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.5
+href="#x1-810055">A.5
And Fig. A.6.
-
+href="#x1-810066">A.6.
+ id="x1-82000A.1.2">Half Wave Rectifier
+
Plot the Input and Output Waveform of Half Wave Rectifier ckt where the input voltage (Vs)
+ id="x1-83000A.1.2">Problem Statement-
+ Plot the Input and Output Waveform of Half Wave Rectifier ckt where the input voltage (Vs)
is 50Hz, 2V peak to peak. Value for Resistor (R) is 1k respectively
-
+
+
Draw the schematic and label the nodes as shown in Fig. A.7 using the schematic editor.
+ id="x1-84000A.1.2">Solution-
+ Draw the schematic and label the nodes as shown in Fig. A.7 using the schematic editor.
Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor.
Perform Electric Rules check using the Perform electric rules check tool from the top toolbar.
Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for
simulation using the Generate Netlist tool from the top toolbar. This is shown in
Fig. A.8.
- Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
+href="#x1-840028">A.8.
+ Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.9.
+href="#x1-840039">A.9.
Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now Click on Sources Details
Tab to Enter Sine Source Values as shown in Fig. A.10. Now Click on Device Model Tab to
+href="#x1-8400410">A.10. Now Click on Device Model Tab to
ADD Diode model to the circuit shown in Fig. A.11. (Note Details about Device Model is
+href="#x1-8400511">A.11. (Note Details about Device Model is
expained in earlier chapter Model Builder.)
- Then Press Convert Button which will generate Ngspice Netlist (Halfwave-Rectifier.cir.out)
- Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.12
+ Then Press Convert Button which will generate Ngspice Netlist (Halfwave-Rectifier.cir.out)
+ Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.12
And Fig. A.13
-
-
Plot the Input and Output Waveform of Inverting Amplifier ckt where the input voltage (Vs)
is 50Hz, 2V peak to peak and gain is 2.
Draw the schematic and label the nodes as shown in Fig. A.14. using the schematic editor.
+href="#x1-8700114">A.14. using the schematic editor.
Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor.
Perform Electric Rules check using the Perform electric rules check tool from the top toolbar.
Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for
simulation using the Generate Netlist tool from the top toolbar. This is shown in
Fig. A.15.
+href="#x1-8700215">A.15.
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
Ngspice. Then Fill the Analysis tab with Transisent option selected as given in
Fig. A.16. Enter start time = 0A.16. Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now
Click on Sources Details Tab to Enter Sine Source Values as shown in Fig. A.17.
+href="#x1-8700417">A.17.
Now Click on Subciruits Tab to ADD UA741 Subcircut to the circuit shown in
Fig. A.18 (Note Details about Subcircuit is expained in earlier chapter Subcircuit
+href="#x1-8700518">A.18 (Note Details about Subcircuit is expained in earlier chapter Subcircuit
Builder.)
Then Press Convert Button which will generate Ngspice Netlist (Inverting-Amplifier.cir.out)
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.20
+href="#x1-8700720">A.20
and Fig. A.19.
-
+href="#x1-8700619">A.19.
Plot the Input and Output Waveform of Precision Reectifier ckt where the input voltage (Vs)
is 50Hz, 3V peak to peak.
Draw the schematic and label the nodes as shown in Fig. D.1a using the schematic editor.
Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor.
Perform Electric Rules check using the Perform electric rules check tool from the top toolbar.
Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for
simulation using the Generate Netlist tool from the top toolbar. This is shown in
Fig. A.22.
+href="#x1-9000222">A.22.
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
Ngspice. Then Fill the Analysis tab with Transisent option selected as given in
Fig. A.23. Enter start time = 0ms, step time = 1 ms, stop time = 100 ms. Now Click
+href="#x1-9000323">A.23. Enter start time = 0ms, step time = 1 ms, stop time = 100 ms. Now Click
on Sources Details Tab to Enter Sine Source Values as shown in Fig. A.24. Now
+href="#x1-9000424">A.24. Now
Click on Device Model Tab to ADD Diode model to the circuit shown in Fig. A.25.
+href="#x1-9000525">A.25.
(Note Details about Device Model is expained in earlier chapter Model Builder.)
Then Click on Subciruits Tab to ADD UA741 Subcircut to the circuit shown in
Fig. A.26. (Note Details about Subcircuit is expained in earlier chapter Subcircuit
+href="#x1-9000626">A.26. (Note Details about Subcircuit is expained in earlier chapter Subcircuit
Builder.)
Then Press Convert Button which will generate Ngspice Netlist (Precision-Rectifier.cir.out)
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.27
+href="#x1-9000727">A.27
and Fig. A.28.
-
+href="#x1-9000828">A.28.
Plot the Input and Output Waveform of Half Adder ckt.
Draw the schematic and label the nodes as shown in Fig. A.29 using the schematic editor.
+href="#x1-9300129">A.29 using the schematic editor.
[Note : To create any Digital Circuits ADCs and DACs must be connected to input and
output of the circuit.] Annotate the schematic using the Annotate tool from the top toolbar in
Schematic editor. Perform Electric Rules check using the Perform electric rules check tool
from the top toolbar. Ensure that there are no errors in the circuit schematic. Now generate
Spice netlist for simulation using the Generate Netlist tool from the top toolbar. This is
shown in Fig. A.30.
+href="#x1-9300230">A.30.
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to
Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.31.
+href="#x1-9300331">A.31.
Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now Click on Sources Details
Tab to Enter Sine Source Values as shown in Fig. A.32. Click on Ngspice Model Tab and
+href="#x1-9300432">A.32. Click on Ngspice Model Tab and
Enter the Details of Ngspice Models else keep it empty where it will select default values as
shown in Fig. A.33 Then Click on Subciruits Tab to ADD half-adder Subcircut to the circuit
+href="#x1-9300533">A.33 Then Click on Subciruits Tab to ADD half-adder Subcircut to the circuit
shown in Fig. A.34. (Note Details about Subcircuit is expained in earlier chapter Subcircuit
+href="#x1-9300634">A.34. (Note Details about Subcircuit is expained in earlier chapter Subcircuit
Builder.)
Then Press Convert Button which will generate Ngspice Netlist (Half-Adder.cir.out)
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.35
+href="#x1-9300735">A.35
and Fig. A.36.
-
+href="#x1-9300836">A.36.
+
+
+ [1] A. S. Sedra and K. C. Smith, Microelectronic Circuits - Theory and
+ Applications. Oxford University Press, 2009.
+
+ [2] K. M. Moudgalya, “Spoken Tutorial: A Collaborative and Scalable Education
+ Technology,” CSI Communications, vol. 35, no. 6, pp. 10–12, September 2011,
+ available at http://spoken-_tutorial.org/CSI.pdf.
+
+ [3] (2013, May). [Online]. Available: http://www.scilab.org/
+
+ [4] (2013, May). [Online]. Available:
+ http://scilab-_test.garudaindia.in/scilab_in/,_http://scilab-_test.garudaindia.in/cloud
+
+ [5] D. B. Phatak. (2013, May) Teach 10,000 teacher programme. [Online].
+ Available: http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do
+
+ [6] K. Kannan and K. Narayanan, “Ict-enabled scalable workshops for engineering
+ college teachers in india,” in Post-Secondary Education and Technology: A Global
+ Perspective on Opportunities and Obstacles to Development (International and
+ Development Education), R. Clohey, S. Austin-Li, and J. C. Weldman, Eds.
+ Palgrave Macmillan, 2012.
+
+
+ [7] (2013, May) Teach 10,000 teacher programme on analog electronics. [Online].
+ Available: http://www.nmeict.iitkgp.ernet.in/Analogmain.htm
+
+ [8] (2013, May). [Online]. Available: http://www.aakashlabs.org/
+
+ [9] (2013, May). [Online]. Available:
+ http://en.wikipedia.org/wiki/Electronic_design_automation
+
+ [10] (2013, May) Synaptic Package Manager Spoken Tutorial. [Online]. Available:
+ http://www.spoken-_tutorial.org/list_videos?view=1&foss=Linux&language=English
+
+ [11] (2013, May). [Online]. Available:
+ http://www.kicad-_pcb.org/display/KICAD/KiCad+EDA+Software+Suite
+
+ [12] (2013, May). [Online]. Available: http://ngspice.sourceforge.net/
+
+ [13] (2013, May). [Online]. Available: http://scilab.in/
+
+ [14] S. M. Sandler and C. Hymowitz, SPICE Circuit Handbook. New York:
+ McGraw-Hill Professional, 2006.
+
+ [15] J.-P. Charras and F. Tappero. (2013, May). [Online]. Available:
+ http://www.kicad-_pcb.org/display/KICAD/KiCad+Documentation
+
+
+ [16] D. Jahshan and P. Hutchinson. (2013, May). [Online]. Available:
+ http://bazaar.launchpad.net/∼kicad-_developers/kicad/doc/files/head:/doc/tutorials/
+
+ [17] P. Nenzi and H. Vogt. (2013) Ngspice users manual version 25plus. [Online].
+ Available: http://ngspice.sourceforge.net/docs/ngspice-_manual.pdf
+
+ [18] K. M. Moudgalya, “LATEX Training through Spoken Tutorials,” TUGboat,
+ vol. 32, no. 3, pp. 251–257, 2011.
+
+ [19] (2013, May). [Online]. Available: http://www.spoken-_tutorial.org/
+
+ [20] (2013, May). [Online]. Available: http://oscad.in/
+
+8.5
+
+ id="x1-720034">
-
-
Figure 8.4: Adding the Paramter in a Library
+class="content">Adding the Parameter in a Library
-
+
+ id="x1-720045">
-
-
Figure 8.5: Removing a Parameter from a Library
+class="content">Removing a Parameter from a Library
-
+8.2 Editing Current Model Library
-8.6
+
+ id="x1-730016">
-
-
Figure 8.6: Editing Existing Model Library
+class="content">Editing Existing Model Library
-
+8.3 Converting Library file to XML file
-Chapter 9
-
Sub-Circuit BuilderSub-Circuit Builder Subcircuit is a way to implement hierarchical modeling.
+Once a subcircuit for a compo- nent is created, it can be used in other circuits.
+eSim provides an easy way to create a subcircuit. Thw Following Fig. 9.1 shows
+the window that is opened when the Sub-CIrcuit tool is chosen from the toolbar.
+
-
+
9.1 Creating a Sub-Circuit
+ id="x1-760009.1">Creating a Sub-Circuit
Figure 9.3: Half-Adder Sub-circuit Block
+class="content">Half-Adder Sub-circuit Block
Appendix A
+ id="x1-77000A">Solved Examples
Solved ExamplesA.1 Solved Examples
+ id="x1-78000A.1">Solved Examples
A.1.1 Basic RC Circuit
+ id="x1-79000A.1.1">Basic RC Circuit
Problem Statement-
+ id="x1-80000A.1.1">Problem Statement-
Solution-
+ id="x1-81000A.1.1">Solution-
+ id="x1-810022">
Figure A.2: RC circuit Netlist Generation
+class="content">RC circuit Netlist Generation
+ id="x1-810033">
Figure A.3: RC Circuit Analysis Insertor
+class="content">RC Circuit Analysis Insertor
+ id="x1-810055">
Figure A.5: Ngspice Plot of RC circuit
+class="content">Ngspice Plot of RC circuit
A.1.2 Half Wave Rectifier
-Problem Statement-
-Solution-
-A.13
+
+ id="x1-840017">
-
-
Figure A.7: Schematic of Halfwave Rectifier circuit
+class="content">Schematic of Halfwave Rectifier circuit
-
+
+ id="x1-840028">
-
-
Figure A.8: Halfwave Rectifier circuit Netlist Generation
+class="content">Halfwave Rectifier circuit Netlist Generation
-
+
+ id="x1-840039">
-
-
Figure A.9: Halfwave Rectifier Circuit Analysis Insertor
+class="content">Halfwave Rectifier Circuit Analysis Insertor
-
+
+ id="x1-8400410">
-
-
Figure A.10: Halfwave Rectifier Source Details
+class="content">Halfwave Rectifier Source Details
-
+
+ id="x1-8400511">
-
-
Figure A.11: Device Modeling of Halfwave Rectifier circuit
+class="content">Device Modeling of Halfwave Rectifier circuit
-
+
+ id="x1-8400612">
-
-
Figure A.12: Ngspice Plot of Halfwave Rectifier circuit
+class="content">Ngspice Plot of Halfwave Rectifier circuit
-
+
+ id="x1-8400713">
-
+
+
Figure A.13: Python Plot of Halfwave Rectifier Circuit
+class="content">Python Plot of Halfwave Rectifier Circuit
-
A.1.3 Inverting Amplifier
+ id="x1-85000A.1.3">Inverting Amplifier
Problem Statement-
+ id="x1-86000A.1.3">Problem Statement-
Solution-
+ id="x1-87000A.1.3">Solution-
+ id="x1-8700114">
Figure A.14: Schematic of Inverting Amplifier circuit
+class="content">Schematic of Inverting Amplifier circuit
+ id="x1-8700215">
Figure A.15: Inverting Amplifier circuit Netlist Generation
+class="content">Inverting Amplifier circuit Netlist Generation
+ id="x1-8700316">
Figure A.16: Inverting Amplifier circuit Analysis Tab
+class="content">Inverting Amplifier circuit Analysis Tab
+ id="x1-8700417">
Figure A.17: Inverting Amplifier Source Details
+class="content">Inverting Amplifier Source Details
+ id="x1-8700518">
Figure A.18: Sub Circuit Tab of Inverting Amplifier
+class="content">Sub Circuit Tab of Inverting Amplifier
+ id="x1-8700619">
Figure A.19: Ngspice Plot of Inverting Amplifier circuit
+class="content">Ngspice Plot of Inverting Amplifier circuit
+ id="x1-8700720">
Figure A.20: Python Plot of Inverting Amplifier Circuit
+class="content">Python Plot of Inverting Amplifier Circuit
+
A.1.4 Precision Rectifier
+ id="x1-88000A.1.4">Precision Rectifier
Problem Statement-
+ id="x1-89000A.1.4">Problem Statement-
Solution -
+ id="x1-90000A.1.4">Solution -
+ id="x1-9000121">
Figure A.21: Schematic of Precision Rectifier circuit
+class="content">Schematic of Precision Rectifier circuit
+ id="x1-9000222">
Figure A.22: Precision Rectifier circuit Netlist Generation
+class="content">Precision Rectifier circuit Netlist Generation
+ id="x1-9000323">
Figure A.23: Precision Rectifier Circuit Analysis Insertor
+class="content">Precision Rectifier Circuit Analysis Insertor
+ id="x1-9000424">
Figure A.24: Precision Rectifier Source Details
+class="content">Precision Rectifier Source Details
+ id="x1-9000525">
Figure A.25: Device Modelling of Precision Rectifier circuit
+class="content">Device Modelling of Precision Rectifier circuit
+ id="x1-9000626">
Figure A.26: Precision Rectifier Sub-circuit
+class="content">Precision Rectifier Sub-circuit
+ id="x1-9000727">
Figure A.27: Ngspice Plot of Precision Rectifier circuit
+class="content">Ngspice Plot of Precision Rectifier circuit
+ id="x1-9000828">
Figure A.28: Python Plot of Precision Rectifier Circuit
+class="content">Python Plot of Precision Rectifier Circuit
+
A.1.5 Half Adder Example
+ id="x1-91000A.1.5">Half Adder Example
Problem Statement-
+ id="x1-92000A.1.5">Problem Statement-
Solution -
+ id="x1-93000A.1.5">Solution -
+ id="x1-9300129">
Figure A.29: Schematic of Half Adder circuit
+class="content">Schematic of Half Adder circuit
+ id="x1-9300230">
Figure A.30: Half Adder circuit Netlist Generation
+class="content">Half Adder circuit Netlist Generation
+ id="x1-9300331">
Figure A.31: Half Adder Circuit Analysis Insertor
+class="content">Half Adder Circuit Analysis Insertor
+ id="x1-9300432">
Figure A.32: Half Adder Source Details
+class="content">Half Adder Source Details
+ id="x1-9300533">
Figure A.33: Ngspice Plot of Half Adder circuit
+class="content">Ngspice Plot of Half Adder circuit
+ id="x1-9300634">
Figure A.34: Ngspice Plot of Half Adder circuit
+class="content">Ngspice Plot of Half Adder circuit
+ id="x1-9300735">
Figure A.35: Ngspice Plot of Half Adder circuit
+class="content">Ngspice Plot of Half Adder circuit
+ id="x1-9300836">
Figure A.36: Python Plot of Half Adder Circuit
+class="content">Python Plot of Half Adder Circuit
+
+References
+
+
Changing the track width: 1. Double click on 
