+
eSim
+An open source EDA tool for circuit design,
+simulation, analysis and PCB design
+
+
+
+
+Indian Institute of Technology Bombay
+August 2015
+ +
+
eSim
+An open source EDA tool for circuit design,
+simulation, analysis and PCB design
+
+
+
+
+Indian Institute of Technology Bombay
+August 2015
+
To
+Mr. Narendra Kumar Sinha, IAS
+An Electronics Engineer and a Bureaucrat,
+Who dreamt of educating all Indians through NMEICT and
+Who envisioned and made possible the Aakash Tablet
+ + +
+ +
eSim was formerlly known as freeEDA/Oscad. Seeds for eSim were sown when the National +Mission on Education through ICT (NMEICT) was launched: the mission document identified +Adaption & deployment of open source simulation packages equivalent to Matlab, +OrCAD, etc., as one of the areas NMEICT would concentrate on. The FOSSEE +(free and open source software in science and engineering education) group at IIT +Bombay, of which we are a part of, initially started working on Python and Scilab. The +Standing Committee of NMEICT encouraged us to contribute to other open source +software as well. This push helped us develop eSim, an open source alternative to +OrCAD. +
eSim is an electronic design automation (EDA) tool, developed using KiCad and Ngspice. +We have made the netlist files generated by KiCad suitable for simulation through +Ngspice. In order to provide an explanation facility, we have developed a method to +automatically generate differential equations that describe a given analog circuit. +Once satisfied with simulation results, the user can create a Gerber file for PCB +fabrication. +
The FOSSEE team has also created more than 160 Scilab Textbook Companions, +each of which contains Scilab code for worked out examples of standard textbooks, +mostly in engineering and science. These have been created by the students and +professors from various educational institutions in India. These textbooks can be +downloaded free of cost from [?]. They can also be executed remotely on GARUDA cloud + [?]. +
We are embarking on a similar methodology for eSim as well: we have solved most of the +worked out examples of [?] and given the solution in Appendix A. We hope to create eSim +Textbook Companions for all other relevant standard textbooks as well in the near future, +once again through students and other volunteers. +
Solving the worked out examples of [?] was a good exercise, as it helped identify and +include some missing features. The yet to be created eSim Textbook Companions +are expected to help in this regard, while simultaneously increasing the available +documentation. +
Lab migration is another important activity that the FOSSEE team is involved in. It +provides equivalent Scilab code for Matlab based labs. This is also carried out through +students and volunteers. We are starting this activity for eSim as well: we will try to provide + +equivalent eSim based solution to all circuit design labs that currently use proprietary +software. +
Another important project supported by NMEICT is the Teach 10,000 Teachers (T10KT) +programme. This methodology, pioneered at IIT Bombay [?, ?] has demonstrated that it is +possible for the best people in the field to provide extremely high quality training +to a large number of learners simultaneously. eSim is expected to be used in the +forthcoming T10KT course on Analog Electronics, organised by IIT Kharagpur + [?]. +
We invite all EDA enthusiasts to work with us through the following resources: +1. URL for all FOSSEE activities: http://fossee.in 2. URL for all eSim resources: +http://oscad.in 3. Textbook companion: textbook-companion@oscad.in 4. Lab migration: +lab-migration@oscad.in 5. SELF workshops: SELF-workshop@oscad.in 6. eSim +development and enhancing its capabilities: Oscad-dev@oscad.in 7. Feedback on this book: +Oscad-textbook@oscad.in. +We also hope to establish forum based discussion services for eSim. +
Finally, an electronic version of this book is available for noncommercial purposes at +http://oscad.in. + +
We would first like to thank Mr. N. K. Sinha, IAS, for without him, there would +have been no National Mission on Education through ICT (NMEICT), without +which, there would have been no FOSSEE, without which, there would have been +no eSim. The idealistic guiding principles of NMEICT, namely, reliance on open +source software, providing free access to e-content and Internet connectivity for all +educational institutions, egged us to contribute our best and one of the outcomes is +eSim. +
We would like to thank the former Human Resource Development Minister (HRM) Mr. +Arjun Singh for getting NMEICT started. We would like to acknowledge the former HRM Mr. +Kapil Sibal for his unstinting support and the faith he had in the NMEICT administration +team. We would like to thank the current HRM Dr. Pallam Raju for extending the tenure of +NMEICT by five more years. +
We want to thank the Members of the Standing Committee of NMEICT who met once in +two weeks for almost two years to review project proposals and to recommend them for +funding or giving suggestions for improvement. We also want to thank them for urging us to +work on more FOSS systems than what we were prepared for. Without this kind of active +support, the ecosystem required for projects like eSim to flourish, established at IIT +Bombay through the many projects funded through NMEICT, would not have +materialised. +
We want to thank the FOSSEE faculty members Profs. Prabhu Ramachandran, Madhu +Belur, Mani Bhushan, Shiva Gopalakrishnan, Jayendran Venkateswaran, Ashutosh +Mahajan and Supratik Chakraborty for establishing a vibrant FOSSEE group at +IIT Bombay. We want to thank Prof. D. B. Phatak for being a constant source +of inspiration and encouragement and for supporting our activities. We want to +thank other faculty members with NMEICT projects at IIT Bombay, namely, Profs. +Kavi Arya, Ravi Poovaiah, Santosh Noronha, Anil Kulkarni, Sridhar Iyer, Sahana +Murthy and Shishir Jha for sharing their dreams, processes and facilities. We want to +thank the staff members of all NMEICT projects at IIT Bombay in general and of +FOSSEE and Spoken Tutorial projects in particular, for providing a wonderful work +environment. +
We want to thank the IIT Bombay administration in general and R&D office in particular +for providing us with an excellent environment to make us work efficiently. We want to thank +the researchers and faculty members in our departments for providing us with necessary space +and for putting up with our tantrums. +
We would like to thank the professors, staff and students affiliated with the Wadhwani
+Electronics lab at IIT Bombay for trying out eSim in lab courses and for the useful
+suggestions. We would like to thank Abhishek Pawar for creating Spoken Tutorials on KiCad.
+We would like to thank Saket Choudhary for making the netlist files generated by KiCad
+
+compatible with Ngspice.
+
+
| Kannan M. Moudgalya | +||
| IIT Bombay | +||
| 22 August 2015 |
| ADC | Analog to Digital Converter |
+
| BJT | Bipolar Junction Transistor |
+
| BV | Breakdown Voltage |
+
| CCCS | Current Controlled Current Source |
| CCVS | Current Controlled Voltage Source |
+
| CPU | Central Processing Unit |
+
| DAC | Digital to Analog Converter |
+
| DRC | Design Rules Check |
+
| DXF | Drawing Interchange Format or Drawing Exchange Format |
+
| EDA | Electronic Design Automation |
+
| ERC | Electric Rules Check |
| FOSS | Free and Open Source Software |
+
| FPGA | Field Programmable Gate Array |
+
| gEDA | Electronic Design Automation released under GPL |
+
| GUI | Graphical User Interface |
+
| HDL | Hardware Descrition Language |
+
| HPGL | Hewlett-Packard Graphics Language |
+
| IC | Integrated Circuit |
+
| ICT | Information and Communication Technology |
+
| IGBT | Insulated Gate Bipolar Transistor |
+
| JFET | Junction Field Effect Transistor |
| KCE | Kirchoff’s Current Law |
+
| KVE | Kirchoff’s Voltage Law |
+
| LXDE | Lightweight X11 Desktop Environment |
+
| MNA | Modified Nodal Analysis |
+
| MOSFET | Metal Oxide Semiconductor Field Effect Transistor |
| NMEICT | National Mission on Education through ICT |
+
| Op-amp | Operational Amplifier |
+
| OTC | Oscad Textbook Companion |
+
| PCB | Printed Circuit Board |
| RS | Ohmic Resistance |
+
| SELF | Spoken Tutorial based Education and Learning through Free +FOSS study |
+
| SMCSim | Scilab based Mini Circuit Simulator |
| SVF | Serial Vector Format |
+
| T10KT | Teach 10,000 Teachers |
+
| VCCS | Voltage Controlled Current Source |
+
| VCVS | Voltage Controlled Voltage source |
+
+ + +
+ +
Let us see the steps involved in EDA. In the first stage, the specifications of the system are +laid out. These specifications are then converted to a design. The design could be in +the form of a circuit schematic, logical description using an HDL language, etc. +The design is then simulated and re-designed, if needed, to achieve the desired +results. Once simulation achieves the specifications, the design is either converted to +a PCB, a chip layout, or ported to an FPGA. The final product is again tested +for specifications. The whole cycle is repeated until desired results are obtained + [?]. +
A person who builds an electronic system has to first design the circuit, produce a virtual +representation of it through a schematic for easy comprehension, simulate it and finally +convert it into a Printed Circuit Board (PCB). There are various tools available that help do +this. Some of the popular EDA tools are those of Cadence, Synopys, Mentor Graphics and +Xilinx. Although these are fairly comprehensive and high end, their licences are expensive, +being proprietary. +
There are some free and open source EDA tools like gEDA, KiCad and Ngspice. The main +drawback of these open source tools is that they are not comprehensive. Some of them are +capable of PCB design (e.g. KiCad) while some of them are capable of performing simulations +(e.g. gEDA). To the best of our knowledge, there is no open source software that can perform +circuit design, simulation and layout design together. eSim is capable of doing all of the +above. +
eSim is a free and open source EDA tool. It is an acronym for Open source computer +aided design. eSim is created using open source software packages, such as KiCad, Ngspice, +Scilab and Python. Using eSim, one can create circuit schematics, perform simulations +and design PCB layouts. It can create or edit new device models, and create or +edit subcircuits for simulation. It also has a Scilab based Mini Circuit Simulator +(SMCSim), which is capable of giving the circuit equations for each simulation +step. This feature is unique to eSim. Because of these reasons, eSim is expected to +be useful to students, teachers and other professionals who would want to study +and/or design electronic systems. eSim is also useful for entrepreneurs and small scale +enterprises who do not have the capability to invest in heavily priced proprietary +tools. +
This book introduces eSim to the reader and illustrates all the features of eSim with +examples. Chapter ?? gives step by step instructions to install eSim on a typical computer + +system and to validate the installation. The software architecture of eSim is presented in +Chapter 3. Chapter 4 gets the user started with eSim. It takes them through a tour of eSim +with the help of a simple RC circuit example. Chapter 5 explains how to create circuit +schematics using eSim, in detail using examples. Chapter 6 illustrates how to simulate +circuits using eSim. Chapter 7 explains PCB design using eSim, in detail. The advanced +features of eSim such as Model Builder covered in Chapter ?? and Sub circuiting is +covered in Chapter ??. Appendix A presents examples, that have been worked +out using eSim, from the book Microelectronic Circuits by Sedra and Smith + [?]. Appendix ?? explains the resources available for the use and promotion of +eSim. +
The following convention has been adopted throughout this book. All the menu names, +options under each menu item, tool names, certain points to be noted, etc., are given in +italics. Some keywords, names of certain windows/dialog boxes, names of some +files/projects/folders, messages displayed during an activity, names of websites, component +references, etc., are given in typewriter font. Some key presses, e.g. Enter key, F1 key, y for +yes, etc., are also mentioned in typewriter font. + +
+ +
eSim is a CAD tool that helps electronic system designers to design, test and analyse their +circuits. But the important feature of this tool is that it is open source and hence the user can +modify the source as per his/her need. The software provides a generic, modular and +extensible platform for experiment with electronic circuits. This software runs on all +Ubuntu Linux distributions. It uses Python, KiCad, Ngspice and Scilab (5.4.0 or +above). +
The objective behind the development of eSim is to provide an open source EDA solution +for electronics and electrical engineers. The software should be capable of performing +schematic creation, PCB design and circuit simulation (analog, digital and mixed signal). It +should provide facilities to create new models and components. In addition to this, it should +have the capability to explain the circuit by giving symbolic equations and numerical +values. The architecture of eSim has been designed by keeping these objectives in +mind. +
Various open-source tools have been used for the underlying build-up of eSim. In this section +we will give a brief idea about all the modules used in eSim. +
+
EEschema is an integrated software where all functions of circuit drawing, control, layout, +library management and access to the PCB design software are carried out within itself. It is +the schematic editor tool used in KiCad [?]. EEschema is intended to work with PCB layout +software such as Pcbnew. It provides netlist that describes the electrical connections of the +PCB. EEschema also integrates a component editor which allows the creation, editing and +visualisation of components. It also allows the user to effectively handle the symbol +libraries i.e; import, export, addition and deletion of library components. EEschema +also integrates the following additional but essential functions needed for a modern +schematic capture software: 1. Design rules check (DRC) for the automatic control of +incorrect connections and inputs of components left unconnected. 2. Generation of +layout files in POSTSCRIPT or HPGL format. 3. Generation of layout files printable via +printer. 4. Bill of material generation. 5. Netlist generation for PCB layout or for +simulation. +This module is indicated by the label 1 in Fig. 3.1. +
As Eeschema is originally intended for PCB Design, there are no fictitious + +components1 +such as voltage or current sources. Thus, we have added a new library for different types of +voltage and current sources such as sine, pulse and square wave. We have also built a library +which gives printing and plotting solutions. This extension, developed by us for eSim, is +indicated by the label 2 in Fig. 3.1. +
CvPcb is a tool that allows the user to associate components in the schematic to component +footprints when designing the printed circuit board. CvPcb is the footprint editor tool in +KiCad [?]. Typically the netlist file generated by EEschema does not specify which printed +circuit board footprint is associated with each component in the schematic. However, this is +not always the case as component footprints can be associated during schematic capture by +setting the component’s footprint field. CvPcb provides a convenient method of associating +footprints to components. It provides footprint list filtering, footprint viewing, and 3D +component model viewing to help ensure that the correct footprint is associated with each +component. Components can be assigned to their corresponding footprints manually or +automatically by creating equivalence files. Equivalence files are look up tables +associating each component with its footprint. This interactive approach is simpler +and less error prone than directly associating footprints in the schematic editor. +This is because CvPcb not only allows automatic association, but also allows to +see the list of available footprints and displays them on the screen to ensure the +correct footprint is being associated. This module is indicated by the label 3 in +Fig. 3.1. +
+
Pcbnew is a powerful printed circuit board software tool. It is the layout editor tool +used in KiCad [?]. It is used in association with the schematic capture software +EEschema, which provides the netlist. Netlist describes the electrical connections of +the circuit. CvPcb is used to assign each component, in the netlist produced by +EEschema, to a module that is used by Pcbnew. The features of Pcbnew are given +below: + +
This module is indicated by the label 4 in Fig. 3.1. +
It converts KiCad generated netlists to Ngspice compatible format. Also it facilitates adding +model library of components and subcircuits. Following are the different functionality lies +under conversion. +
This feature helps the user to perform different types of analysis such as Operating +point analysis, DC analysis, AC analysis, transient analysis, etc. It has the facility +to +
+
eSim sources are added from eSim-sources package. Sources auch as SINE, AC, DC, PULSE +are in this lobrary. Input to allthe sources adde in the circuit are given in source +details. +
eSim adds Ngspice model using this facility. +
Devices like Diode, JFET, MOSFET, IGBT, MOS etc added in the circut can be modeled +using device model libraries. eSim also proveides editing and adding new model libraries. +While converting Kicad to Ngspice these library files added to the corresponding devices uesd +in the circuit. + +
Subcircuits are the circuits within a circuits. Subcircuiting helps to reuse the part of the +circuits. The sub circuit in the main circuits are added using this facility. Also, eSim provides +us with editing the already exixting subcircuits. Sub circuits are saved separately in different +folders. +
This tool provides the facility to define a new model for devices such as, 1. Diode 2. Bipolar +Junction Transistor (BJT) 3. Metal Oxide Semiconductor Field Effect Transistor +(MOSFET) 4. Junction Field Effect Transistor (JFET) 5. IGBT and 6. Magnetic +core. +This module also helps edit existing models. It is developed by us for eSim and it is indicated +by the label 5 in Fig. 3.1. +
+
This module allows the user to create a subcircuit for a component. Once the subcircuit for a +component is created, the user can use it in other circuits. It has the facility to define new +components such as, Op-amps and IC-555. This component also helps edit existing +subcircuits. This module is developed by us for eSim and it is indicated by the label 6 in +Fig. 3.1. +
+
It converts KiCad generated netlists to Ngspice (see Sec. 3.1.8) compatible format. It has the +capability to 1. Insert parameters for fictitious components 2. Convert IC into discrete +blocks 3. Insert D-A and A-D converter at appropriate places 4. Insert plotting +and printing statements in netlist and 5. Find current through all components. +
This module is developed by us for eSim and it is indicated by the label 7 in +Fig. 3.1. + +
+
Ngspice is a general purpose circuit simulation program for nonlinear dc, nonlinear transient, +and linear ac analyses [?]. Circuits may contain resistors, capacitors, inductors, mutual +inductors, independent voltage and current sources, four types of dependent sources, lossless +and lossy transmission lines (two separate implementations), switches, uniform +distributed RC lines, and the five most common semiconductor devices: diodes, +BJTs, JFETs, MESFETs, and MOSFET. This module is indicated by the label 9 in +Fig. 3.1. +
+
Fig. 3.1 shows the work flow in eSim. The block diagram consists of mainly three +parts: +
+
Here we explain the role of each block in designing electronic systems. Circuit design is the +first step in the design of an electronic circuit. Generally a circuit diagram is drawn on a +paper, and then entered into a computer using a schematic editor. EEschema is the schematic +editor for eSim. Thus all the functionalities of EEschema are naturally available in eSim. + +
Libraries for components, explicitly or implicitly supported by Ngspice, have been created +using the features of EEschema. As EEschema is originally intended for PCB design, there are +no fictitious components such as voltage or current sources. Thus, a new library for different +types of voltage and current sources such as sine, pulse and square wave, has been added in +eSim. A library which gives the functionality of printing and plotting has also been +created. +
The schematic editor provides a netlist file, which describes the electrical connections of +the design. In order to create a PCB layout, physical components are required to be mapped +into their footprints. To perform component to footprint mapping, CvPcb is used. Footprints +have been created for the components in the newly created libraries. Pcbnew is used to draw +a PCB layout. +
After designing a circuit, it is essential to check the integrity of the circuit design. In the +case of large electronic circuits, breadboard testing is impractical. In such cases, electronic +system designers rely heavily on simulation. The accuracy of the simulation results can be +increased by accurate modeling of the circuit elements. Model Builder provides the facility to +define a new model for devices and edit existing models. Complex circuit elements can be +created by hierarchical modeling. Subcircuit Builder provides an easy way to create a +subcircuit. +
The netlist generated by Schematic Editor cannot be directly used for simulation +due to compatibility issues. Netlist Converter converts it into Ngspice compatible +format. The type of simulation to be performed and the corresponding options are +provided through a graphical user interface (GUI). This is called Analysis Inserter in +eSim. +
eSim uses Ngspice for analog, digital, mixed-level/mixed-signal circuit simulation. Ngspice +is based on three open source software packages [?]: +
It is a part of gEDA project. Ngspice is capable of simulating devices with BSIM, EKV, HICUM, + +HiSim, PSP, and PTM models. It is widely used due to its accuracy even for the latest +technology devices. + +
In this chapter we will get started with eSim. We will run through the various options +available with an example circuit. Referring to this chapter will make one familiar with +eSim and will help plan the project before actually designing a circuit. Lets get +started. +
+
After installtion is completed, when the eSim is run the first window that appears is +workspace dialog as shown in Fig. 4.1.
The defalut eSim-Workspace can be chosen if the ok or cancel button is clicked. Else to +create new workspace browse button is used. +
The main GUI window of eSim is as shown in Fig. 4.2
The eSim main GUI window consists the following symbols. +
However, if an already existing project is opened, one would get the schematic + editor window along with a Load error. This is illustrated in Fig. 4.4. This + error occurs because the schematic that is opened has not been loaded with + the libraries mentioned in the Load Error message. Close the Load Error + message by clicking on the Close button. The RC circuit diagram opens up + as shown in Fig. 4.5. Now the circuit schematic can be created/edited. To + know how to use the schematic editor to create circuit schematics, refer to + Chapter 5. +
Open the project RC_pcb available in the Examples folder downloaded from the eSim + website. On clicking the Footprint Editor tool, we see the corresponding RC_pcb.net file + for RC circuit. This window is shown in Fig. 4.7. The main purpose of this window is to + let one choose the footprints for the various components in the circuit. Let us view the + footprint C1 for capacitor C1. Click on C1 from the right hand side of CvPcb + window. Click on View Selected Footprint tool from the tool bar of CvPcb + window. This will show the footprint corresponding to C1. This is illustrated in + Fig. 4.8. To know more about how to assign footprints to components, see + Chapter 7. +
To create a new model library New button is clicked which then opens the template + library folder. We can choose from the template library that can be edited, to create the + new library and the click on Save to save the edited model library. Also the existing + library can be edited usind Edit option. The user can also use their own library by + uploading it using Upload button. +
+
+
Project explorer has tree of all the project previously added in it. On right clicking +the project we can simply remove or refresh the project in the explorer. Also on +right clicking the project file can be opened in the text editor which can then be +edited. + +
+
+
Console area provides with the errors and active commands running. + +
+ +
Fig. 5.1 shows the schematic editor and the various menu and toolbars. We will explain them +briefly in this section.
The top menu bar will be available at the top left corner. Some of the important menu +options in the top menu bar are: +
+
Some of the important tools in the top toolbar are discussed below. They are marked in +Fig. 5.3.
The toolbar on the right side of the schematic editor window has many important tools. Some +of them are marked in Fig. 5.4.
Let us now look at each of these tools and their uses. +
Some of the important tools in the toolbar on the left are discussed below. They are marked +in Fig. 5.5.
A set of keyboard keys are associated with various operations in the schematic editor. These +keys save time and make it easy to switch from one operation to another. The list of hotkeys +can be viewed by going to Preferences in the top menu bar. Choose Hotkeys and +select List current keys. The hotkeys can also be edited by selecting the option +Edit Hotkeys. Some frequently used hotkeys, along with their functions, are given +below: +
Note: Both lower and upper-case keys will work as hotkeys. +
+
There are certain differences between the schematic created for simulation and that created +for PCB design. We need certain components like plots and current sources. for simulation +whereas these are not needed for PCB design. For PCB design, we would require +connectors (e.g. DB15 and 2 pin connector) for taking signals in and out of the +PCB whereas these have no meaning in simulation. This section covers schematic +creation for simulation. Refer to Chapter 7 to know how to create schematic for PCB +design. +
The first step in the creation of circuit schematic is the selection and placement of +required components. Let us see this using an example. Let us create the circuit schematic of +an RC filter given in Fig. 5.6 and do a transient simulation.
We would need a resistor, a capacitor, a voltage source, ground terminal and some +plot components. To place a resistor on the schematic editor window, select the +Placea component tool from the toolbar on the right side and click anywhere on +the schematic editor. This opens up the component selection window. (The above +action can also be performed by pressing the key A.) Type R in the field Name of +the component selection window as shown in Fig. 5.7. Click on OK. A resistor +will be tied to the cursor. Place the resistor on the schematic editor by a single +click. +
To place the next component, i.e., capacitor, click again on the schematic editor. Type C +in the Name field of component selection window. Click on OK. Place the capacitor +on the schematic editor by a single click. Let us now place a sinusoidal voltage +source. This is required for performing transient analysis. To place it, click again +on the schematic editor. On the component selection window, click on List all. +Choose the library sourcesSpice by double clicking on it. Select the component +SINE and click on OK. Place the sine source on the schematic editor by a single +click. +
Place the component by clicking on the schematic editor. Similarly place a ground +terminal gnd from the library power. It can also be placed using the Place a power port tool +from the toolbar on the right. Click anywhere on the editor after selecting place a power port +tool. Click List all and choose gnd. Once all the components are placed, the schematic editor +would look like the Fig. 5.8.
Let us rotate the resistor to complete the circuit as shown in Fig. 5.6. To rotate the +resistor, place the cursor on the resistor and press the key R. Note that if the cursor is placed +above the letter R (not R?) on the resistor, it asks to clarify selection. Choose the option +Component R. This can be avoided by placing the cursor slightly away from the letter R as +shown in Fig. 5.9. This applies to all components.
If one wants to move a component, place the cursor on top of the component and press the +key M. The component will be tied to the cursor and can be moved in any direction. + +
The next step is to wire the connections. Let us connect the resistor to the capacitor. +To do so, point the cursor to the terminal of resistor to be connected and press +the key W. It has now changed to the wiring mode. Move the cursor towards the +terminal of the capacitor and click on it. A wire is formed as shown in Fig. 5.10a. +
+(a)
+Initial
+stages
+ (b)
+ Wiring
+ done
+ (c)
+ Final
+ schematic
+ with
+ PWR_FLAG
+
Similarly connect the wires between all terminals and the final schematic would look like +Fig. 5.10b. +
We need to assign values to the components in our circuit i.e., resistor and capacitor. Note +that the sine voltage source has been placed for simulation. The specifications of sine source +will be given during simulation. To assign value to the resistor, place the cursor above the +letter R (not R?) and press the key E. Choose Field value. Type 1k in the Edit value field box +as shown in Fig. 5.11. 1k means 1kΩ. Similarly give the value 1u for the capacitor. 1u means +1μF. +
The next step is to annotate the schematic. Annotation gives unique references to the +components. To annotate the schematic, click on Annotate schematic tool from the +top toolbar. Click on annotation, then click on OK and finally click on close as +shown in Fig. 5.13. The schematic is now annotated. The question marks next to +component references have been replaced by unique numbers. If there are more than +one instance of a component (say resistor), the annotation will be done as R1, R2, +etc. +
Let us now do ERC or Electric Rules Check. To do so, click on Perform electric rules +check tool from the top toolbar. Click on Test Erc button. The error as shown in Fig. 5.12 +may be displayed. Click on close in the test erc window.
+
There will be a green arrow pointing to the source of error in the schematic. Here it points +to the ground terminal. This is shown in Fig. 5.14.
To correct this error, place a PWR_FLAG from the EEschema library power. Connect the +power flag to the ground terminal as shown in Fig. 5.10c. More information about +PWR_FLAG is given in Sec. ??. One needs to place PWR_FLAG wherever the error shown in +Fig. 5.12 is obtained. Repeat the ERC. Now there are no errors. With this we have created +the schematic for simulation. +
To simulate the circuit that has been created in the previous section, we need to generate its +netlist. Netlist is a list of components in the schematic along with their connection +information. To do so, click on the Generate netlist tool from the top toolbar. Click on spice +from the window that opens up. Uncheck the option Default Format. Then click on Netlist. +This is shown in Fig. 5.15. Save the netlist. This will be a .cir file. Do not change the +directory while saving.
+
Now the netlist is ready to be simulated. Chapter 6 explains how to perform simulations. +Refer to [?] or [?] to know more about EEschema. + + +
In the following sections, we shall describe each of the above steps. +
In order to simulate a circuit, the user must define the type of analysis to be done on the +circuit. The types of analysis include Operating point analysis, DC analysis, +AC analysis, transient analysis, etc. The user should also specify the options + +corresponding to each analysis. This is facilitated by the Analysis Inserter tool in +eSim. +
Analysis Inserter generates the commands for Ngspice. When one clicks on Kicad to +Ngspice from the eSim toolbar, one gets the Analysis Inserter GUI as shown in Fig. 6.1. The +various tabs in this GUI correspond to the various types of analysis. The user can enter +the details, needed to perform simulation, in the corresponding fields under these +tabs. +
eSim supports three types of analyses: 1. DC Analysis (Operating Point and DC Sweep) +2. AC Small-signal Analysis 3. Transient Analysis. +Other analysis in the Analysis Inserter are currently under progress. The different types of +analyses supported in eSim are explained below [?]. +
+
The DC analysis determines the dc operating point of the circuit with inductors shorted and +capacitors opened. The DC analysis options are specified on the .dc and .op control +lines. +
There is assumed to be no time dependence on any of the sources within the system +description. The simulator algorithm subdivides the circuit into those portions which require +the analog simulator algorithm and those which require the event-driven algorithm. +Each subsystem block is then iterated to solution, with the interfaces between analog nodes +and event-driven nodes iterated for consistency across the entire system. Once stable values +are obtained for all nodes in the system, the analysis halts and the results could be displayed +or printed out. +
A DC analysis is automatically performed prior to a transient analysis to determine +the transient initial conditions, and prior to an ac small-signal analysis to determine the +linearised, small-signal models for nonlinear devices. The DC analysis can also be used to +generate dc transfer curves: a specified independent voltage or current source is stepped over a +user-specified range and the dc output variables are stored for each sequential source +value. +
+
AC analysis is limited to analog nodes. It represents the small signal, sinusoidal +solution of the analog system described at a particular frequency or set of frequencies. +This analysis is similar to the DC analysis in that it represents the steady-state +behaviour of the described system with a single input node at a given set of stimulus +frequencies. + +
The program first computes the dc operating point of the circuit and determines +linearised, small-signal models for all of the nonlinear devices in the circuit. The resultant +linear circuit is then analyzed over a user-specified range of frequencies. The desired output +of an ac small-signal analysis is usually a transfer function (voltage gain, trans +impedance, etc.). If the circuit has only one ac input, it is convenient to set that input to +unity and zero phase, so that output variables have the same value as the transfer +function. +
+
Transient analysis is an extension of DC analysis to the time domain. A transient +analysis begins by obtaining a DC solution to provide a point of departure for simulating +time-varying behaviour. Once the DC solution is obtained, the time-dependent aspects of the +system are reintroduced and the simulator algorithms incrementally solve for the time varying +behaviour of the entire system. Inconsistencies in node values are resolved by the simulation +algorithms such that the time-dependent waveforms created by the analysis are consistent +across the entire simulated time interval. +
Resulting time-varying descriptions of node behaviour for the specified time interval are +accessible. All sources which are not time dependent (for example, power supplies) are +set to their dc value. The transient time interval is specified on a .tran control +line. +
+
By default DC analysis option appears when one clicks on Analysis Inserter. Here we need +to give the details of input source name, start value of input, increment and stop value. Once +this is done, click on Add Simulation Data. +
Fig. 6.2 gives an example of DC analysis inserter. In this example, v1 is the input
+voltage source which starts at 0 Volt, increments by 1 Volt and stops at 10 Volt. On
+clicking Add Simulation Data, the analysis command is generated and is of the form:
+
.dc sourcename vstart vstop vincr
The .dc line defines the dc transfer curve source and sweep limits (with capacitors open and
+inductors shorted). srcnam is the name of an independent voltage or current source. vstart,
+vstop, and vincr are the starting, final, and incrementing values respectively, of the
+source.
+
When we check the option Operating Point analysis on the DC analysis window, .op gets +appended to the analysis statement.
The inclusion of the line .op in the analysis file directs Ngspice to determine the dc +operating point of the circuit with inductors shorted and capacitors opened. +
When one clicks on the option AC in the Analysis Inserter GUI, the window given in +Fig. 6.3 appears.
Here one needs to enter the details of scale, start frequency, stop frequency and Number of +points. +
After entering these values, click on Add Simulation Data. The analysis statement is
+generated. This is in one of the three forms listed below, depending on the type of scale that
+one chooses. The types of scale available are dec, oct, and lin, the usage of which is explained
+below:
.ac dec nd fstart fstop
.ac oct no fstart fstop
.ac lin np fstart fstop
Here, dec stands for decade variation and nd is the number of points per decade. oct stands
+for octave variation and no is the number of points per octave. lin stands for linear variation
+and np is the number of points. fstart is the starting frequency and fstop is the final
+frequency.
+
If the .ac analysis is included in the analysis file, Ngspice performs an AC analysis of the +circuit over the specified frequency range. Note that in order for this analysis to be +meaningful, at least one independent source must have been specified with an ac value. While +creating the schematic for performing ac analysis, add the component AC from the +sourcesSpice library. +
When one clicks on the option Transient in the Analysis Inserter GUI, the window given in +Fig. 6.4 appears. Here one needs to enter the details of start time, step time, and stop time. +After entering these values, click on Add Simulation Data. The analysis statement is +generated. It is of the form: +
Here, tstep is the printing or plotting increment for line-printer output. For use +with the post-processor, tstep is the suggested computing increment. tstop is the +final time, and tstart is the initial time. If tstart is omitted, it is assumed to be +zero. +
The transient analysis always begins at time zero. In the interval <zero, tstart>, the +circuit is analyzed (to reach a steady state), but no outputs are stored. In the interval +<tstart, tstop>, the circuit is analyzed and outputs are stored.
Source details is basically a dynamic tab, i.e. the feilds are added as per the circuit. The +number of sources schematic has like AC,DC is the number of fields that get added in the +GUI. Consider a Half-Adder circuit as shown in Fig. 6.5
Here, total three DC input source are used and hence the source detail GUI wuould be +having three input fields as shown is Fig. 6.6
+
Spice based simulators include a feature which allows accurate modeling of semiconductor +devices such as diodes, transistors etc. Model libraries holds these features to define +models for devices such as diodes, MOSFET, BJT, JFET, IGBT, Magnetic core +etc. +
The fields in this tab are added for each such device in the circuit and the corresponding +model library is added. In the example of bridgerectifier as shown in Fig. 6.7 for four diodes +library files are added as in Fig. ??
Sub-circuiting is the way of hierarchical modeling. The sub circuit file in the main circuits +needs to be added before converting it. Let us consider the simple example of Full-Adder +circuit containing two half adder sub circuits. +
+
After Filling up the values in all the above mentioned fields the convert button is pressed for +the conversion process to finish. If all the files are added the successful messege box is +popped on the screen as shown in Fig. 6.9. Then click ok, this will create the .cir.out, +analysis and other files in the project folders. +
After the Kicad to Ngspice conversion is successfully completed simulation tab on the toolbar +is clicked to check the output waveform of the project. The windows shown if Fig. 6.10 and +Fig. 6.11 are opned in dockarea. +
Following are the commands to be given in Ngspice window. +
The output in the ngspice window is shown in Fig. 6.12
Likewise, in the pythonplot window the checkbox of a perticular source can be chosen +and then PLOT button is clicked. Ths output in pythonplot window is shown in +Fig. 6.13 +
In Chapter 5, we have seen the differences between schematic for simulation and schematic +for PCB design. Let us design the PCB for an RC circuit. A resistor, capacitor, ground, power +flag and a connector are required. Connectors are used to take signals in and out of the +PCB. +
Create the circuit schematic as shown in Fig. 7.1. The two pin connector (CONN_2) can +be placed from the EEschema library conn. See Sec. ?? to know more about EEschema +library conn. Do the annotation and test for ERC. Refer to Chapter 5 to know more about +basic steps in schematic creation. +
The netlist for PCB is different from that for simulation. To generate netlist for PCB, click on +the Generate netlist tool from the top toolbar in Schematic editor. In the Netlist window, +under the tab Pcbnew, click on the button Netlist. This is shown in Fig. 7.2. Click on +Save in the Save netlist file dialog box that opens up. Do not change the directory +or the name of the netlist file. Save the schematic and close the schematic editor. +
Note that the netlist for PCB has an extension .net. The netlist created for simulation +has an extension .cir. +
Once the netlist for PCB is created, one needs to map each component in the netlist to a +footprint. The tool Footprint Editor is used for this. eSim uses CvPcb as its footprint editor. +CvPcb is the footprint editor tool in KiCad. +
+
If one opens the Footprint Editor after creating the .net netlist file, the Footprint editor as +shown in Fig. 7.3 will be obtained. The menu bar and toolbars and the panes are marked in +this figure. The menu bar will be available in the top left corner. The left pane has a list of +components in the netlist file and the right pane has a list of available footprints for each +component.
+
Note that if the Footprint Editor is opened before creating a ‘.net’ file, then the left and +right panes will be empty. +
Some of the important tools in the toolbar are shown in Fig. 7.4. They are explained below: +
To view a footprint in 2D, select it from the right pane and click on View selected footprint +from the menu bar. Let us view the footprint for SM1210. Choose SM1210 from +the right pane as shown in Fig. 7.5. On clicking the View selected footprint tool, +the Footprint window with the view in 2D will be displayed. Click on the 3D +tool in the Footprint window, as shown in Fig. 7.6. A top view of the selected +footprint in 3D is obtained. Click on the footprint and rotate it using mouse to get 3D +views from various angles. One such side view of the footprint in 3D is shown in +Fig. 7.7. +
+
Click on C1 from the left pane. Choose the footprint C1 from the right pane by double +clicking on it. Click on connector P1 from the left pane. Choose the footprint SIL-2 from the +right pane by double clicking on it. Similarly choose the footprint R3 for the resistor R1. The +footprint mapping is shown in Fig. 7.8. Save the footprint association by clicking on the Save +netlist and footprint files tool from the CvPcb toolbar. The Save Net and component List +window appears. Browse to the directory where the schematic file for this project is saved and +click on Save. The netlist gets saved and the Footprint Editor window closes automatically. +
Note that one needs to browse to the directory where the schematic file is saved and save +the ‘.net’ file in the same directory. +
The next step is to place the footprints and lay tracks between them to get the layout. This is +done using the Layout Editor tool. eSim uses Pcbnew, the layout creation tool in KiCad, as its +layout editor. +
+
The layout editor with the various menu bar and toolbars is shown in Fig. 7.9. +
Some of the important menu options in the top menu bar are shown in Fig. 7.10. They are +explained below: +
+
A list of hotkeys are given below: +
The list can be viewed by selecting Preferences from the top menu bar and choosing List Current +Keys from the option Hotkeys. +
+
Click on Layout Editor from the eSim toolbar. Click on Read Netlist tool from the top +toolbar. Click on Browse Netlist files on the Netlist window that opens up. Select the .net file +that was modified after assigning footprints. Click on Open. Now Click on Read Current +Netlist on the Netlist window. The message area in the Netlist window says that +the RC_pcb.net has been read. The sequence of operations is shown in Fig. 7.11. +
+
The footprint modules will now be imported to the top left hand corner of the layout +editor window. This is shown in Fig. 7.12.
Zoom in to the top left corner by pressing the key F1 or using the scroll button of the +mouse. The zoomed in version of the imported netlist is shown in Fig. 7.13. +
Let us now place this in the center of the layout editor window.
Click on Mode footprint: Manual/automatic move and place tool from the top toolbar. +Place the cursor near the center of the layout editor window. Right click and choose Glob +move and place. Choose move all modules. The sequence of operations is shown in Fig. 7.14. +Click on Yes on the confirmation window to move the modules. Zoom in using the F1 key. +The current placement of components after zooming in is shown in Fig. 7.15a. +
+
+(a)
+Zoomed
+in
+version
+of the
+current
+placement
+after
+moving
+modules
+to the
+center
+of the
+layout
+editor
+ (b)
+ Final
+ placement
+ of
+ footprints
+ after
+ rotating
+ and
+ moving
+ P1
+
We need to arrange the modules properly to lay tracks. Rotate the connector P1 by +placing the cursor on top of P1 and pressing R. Move it by placing the cursor on top of it and +pressing M. The final placement is shown in Fig. 7.15b. +
Let us now lay the tracks. Let us first change the track width. Click on Design rules from +the top menu bar. Click on Design rules. This is shown in Fig. 7.16. The Design Rules Editor +window opens up. Here one can edit the various design rules. Double click on the track width +field to edit it. Type 0.8 and press Enter. Click on OK. Fig. 7.17 shows the sequence of +operations.
+
Click on Back from the Layer options as shown in Fig. 7.18.
Let us now start laying the tracks. Place the cursor above the left terminal of R1 +in the layout editor window. Press the key x. Move the cursor down and double +click on the left terminal of C1. A track is formed. This is shown in Fig. 7.19a. +
+(a) A
+track
+formed
+between
+resistor
+and
+capacitor
+ (b) A
+ track
+ formed
+ between
+ capacitor
+ and
+ connector
+ (c) A
+ track
+ formed
+ between
+ connector
+ and
+ resistor
+
Similarly lay the track between capacitor C1 and connector P1 as shown in +Fig. 7.19b. The last track needs to be laid at an angle. To do so, place the cursor +above the second terminal of R1. Press the key x and move the cursor diagonally +down. Double click on the other terminal of the connector. The track will be laid +as shown in Fig. 7.19c. All tracks are now laid. The next step is to create PCB +edges. +
Choose PCB_edges from the Layer options to add edges. Click on Add graphic line or +polygon from the toolbar on the left. Fig. 7.20 shows the sequence of operations. Let us now +start drawing edges for PCB.
+
Click to the left of the layout. Move cursor horizontally to the right. Click once to change +orientation. Move cursor vertically down. Draw the edges as shown in Fig. 7.21. Double click +to finish drawing the edges.
Click on Perform design rules check from the top toolbar to check for design rules. The +DRC Control window opens up. Click on Start DRC. There are no errors under the Error +messages tab. Click on OK to close DRC control window. Fig. 7.22 shows the sequence of +operations.
Click on Save board on the top toolbar. +
To generate Gerber files, click on File from the top menu bar. Click on Plot. This is shown +in Fig. 7.23. The plot window opens up. One can choose which layers to plot by +selecting/deselecting them from the Layers pane on the left side. One can also choose the +format used to plot them. Choose Gerber. The output directory of the plots created +can also be chosen. By default, it is the project directory. Some more options can +be chosen in this window. Click on Plot. The message window shows the location +in which the Gerber files are created. Click on Close. This is shown in Fig. 7.24. +
+
The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to [?] +or [?]. + +
Spice based simulators include a feature which allows accurate modeling of semiconductor +devices such as diodes, transistors etc. eSim Model Builder provides a facility to define a new +model for devices such as diodes, MOSFET, BJT, JFET, IGBT, Magnetic core etc. Model +Builder in eSim lets the user enter the values of parameters depending on the type of device +for which a model is required. The parameter values can be obtained from the data-sheet +of the device. A newly created model can be exported to the model library and +one can import it for different projects, whenever required. Model Builder also +provides a facility to edit existing models. The GUI of the model editor is as shown in +Fig. 8.1 +
eSim lets used create new model libraries based on the template model libraries. on selecting +New button the window is popped to name the new library file. The library file has to be +unique otherwise the error message appears on the window. +
After the OK button is pressed the type of model library to be created is chosen by +selecting one of the types on the left hand side i.e. Diode, BJT, MOS, JFET, IGBT, +Magnetic Core. The template model library is then opened in the tabular form. As shown in +Fig. 8.3 +
The new parameters can be added or a current parameters can be removed using ADD +and REMOVE buttons. Also the values of parameters can be changed in the table. The +adding and removing of the parameters in a library files is as shown in the Fig. 8.4 and +Fig. 8.5 +
After the editing of the model library is done the file can be saved selecting the SAVE +button. These libraries are saved in the Use Libraries folder under DecviceModelLibrary folder +in the project folder. +
The current model library can be saved using EDIT option. On clicking the EDIT button the +file dialog opens where all the library files are saved as shown in Fig. 8.6 +
Further on clicking the SAVE button the edited model library is saved in the Use +Libraries folder under DecviceModelLibrary folder in the project folder. +
eSim can not read the model library file in the .lib form. The file needs to be converted into +XML so as to make it readable and editable in model editor. Any new netlist that user wants +to use in the eSim need to be convertedinto xml before using it in a project. hence eSim +provides us to upload the new netlist which converts in into xml. on clicking UPLOAD button +the netlist can be uploaded from any location and further on saving the file the model library +can be saved in the Use Libraries folder under DecviceModelLibrary folder in the project +folder with different name. + +
+ +
Subcircuit is a way to implement hierarchical modeling. Once a subcircuit for a compo- nent +is created, it can be used in other circuits. eSim provides an easy way to create a subcircuit. +Thw Following Fig. 9.1 shows the window that is opened when the Sub-CIrcuit tool is chosen +from the toolbar.
Let us take an example of Half-adder circuit. To create a new sub circuit select the New +Subcircuit Schematic.Fig. 9.2 shows the half-adder circuit and Fig. 9.3 shows the block of the +sub circuit included in the main circuit.
NOTE: All the input and output of the sub circuits are connected to the port component. +
After creating the schematic kicad netlist is generated as explained in section and convert +kicad to Ngspice where cir.out and .sub files are generated. The number of input and +output ports of the subcircuit is to matched with number of connections in the +main circuit. eSim provides this validation of mapping of the sub circuit ports. +Also the respective input and output ports can be checked by reading the .sub +file. + + +
+
+
Plot the Input and Output Waveform of RC ckt where the input voltage (Vs) is +50Hz, 3V peak to peak. Value for Resistor (R) and Capacitor(C) is 1k and 1uf +respectively. +
+
Draw the schematic and label the nodes as shown in Fig. A.1a using the schematic editor. +Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor. +Perform Electric Rules check using the Perform electric rules check tool from the top toolbar. +Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for +simulation using the Generate Netlist tool from the top toolbar. This is shown +Fig. A.1. +
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to +Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.2. +Enter start time = 0ms, step time = 1ms, stop time = 100ms. +
Now Click on Sources Details Tab to Enter Sine Source Values as shown in +Fig. A.4. +
Then Press Convert Button which will generate Ngspice Netlist (rc.cir.out) +
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.5 +And Fig. A.6. + +
+
Plot the Input and Output Waveform of Half Wave Rectifier ckt where the input voltage (Vs) +is 50Hz, 2V peak to peak. Value for Resistor (R) is 1k respectively +
+
Draw the schematic and label the nodes as shown in Fig. A.7 using the schematic editor. +Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor. +Perform Electric Rules check using the Perform electric rules check tool from the top toolbar. +Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for +simulation using the Generate Netlist tool from the top toolbar. This is shown in +Fig. A.8. +
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to +Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.9. +Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now Click on Sources Details +Tab to Enter Sine Source Values as shown in Fig. A.10. Now Click on Device Model Tab to +ADD Diode model to the circuit shown in Fig. A.11. (Note Details about Device Model is +expained in earlier chapter Model Builder.) +
Then Press Convert Button which will generate Ngspice Netlist (Halfwave-Rectifier.cir.out) +
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.12 +And Fig. A.13 + +
+
Plot the Input and Output Waveform of Inverting Amplifier ckt where the input voltage (Vs) +is 50Hz, 2V peak to peak and gain is 2. +
Draw the schematic and label the nodes as shown in Fig. A.14. using the schematic editor. +Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor. +Perform Electric Rules check using the Perform electric rules check tool from the top toolbar. +Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for +simulation using the Generate Netlist tool from the top toolbar. This is shown in +Fig. A.15. +
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to +Ngspice. Then Fill the Analysis tab with Transisent option selected as given in +Fig. A.16. Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now +Click on Sources Details Tab to Enter Sine Source Values as shown in Fig. A.17. +Now Click on Subciruits Tab to ADD UA741 Subcircut to the circuit shown in +Fig. A.18 (Note Details about Subcircuit is expained in earlier chapter Subcircuit +Builder.) +
Then Press Convert Button which will generate Ngspice Netlist (Inverting-Amplifier.cir.out) +
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.20 +and Fig. A.19. + +
+
Plot the Input and Output Waveform of Precision Reectifier ckt where the input voltage (Vs) +is 50Hz, 3V peak to peak. +
+
Draw the schematic and label the nodes as shown in Fig. D.1a using the schematic editor. +Annotate the schematic using the Annotate tool from the top toolbar in Schematic editor. +Perform Electric Rules check using the Perform electric rules check tool from the top toolbar. +Ensure that there are no errors in the circuit schematic. Now generate Spice netlist for +simulation using the Generate Netlist tool from the top toolbar. This is shown in +Fig. A.22. +
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to +Ngspice. Then Fill the Analysis tab with Transisent option selected as given in +Fig. A.23. Enter start time = 0ms, step time = 1 ms, stop time = 100 ms. Now Click +on Sources Details Tab to Enter Sine Source Values as shown in Fig. A.24. Now +Click on Device Model Tab to ADD Diode model to the circuit shown in Fig. A.25. +(Note Details about Device Model is expained in earlier chapter Model Builder.) +Then Click on Subciruits Tab to ADD UA741 Subcircut to the circuit shown in +Fig. A.26. (Note Details about Subcircuit is expained in earlier chapter Subcircuit +Builder.) +
Then Press Convert Button which will generate Ngspice Netlist (Precision-Rectifier.cir.out) +
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.27 +and Fig. A.28. + +
+
Plot the Input and Output Waveform of Half Adder ckt. +
+
Draw the schematic and label the nodes as shown in Fig. A.29 using the schematic editor. +[Note : To create any Digital Circuits ADCs and DACs must be connected to input and +output of the circuit.] Annotate the schematic using the Annotate tool from the top toolbar in +Schematic editor. Perform Electric Rules check using the Perform electric rules check tool +from the top toolbar. Ensure that there are no errors in the circuit schematic. Now generate +Spice netlist for simulation using the Generate Netlist tool from the top toolbar. This is +shown in Fig. A.30. +
Next step is to convert kicad netlist to ngspice netlist by click on icon Convert Kicad to +Ngspice. Then Fill the Analysis tab with Transisent option selected as given in Fig. A.31. +Enter start time = 0ms, step time = 1ms, stop time = 100ms. Now Click on Sources Details +Tab to Enter Sine Source Values as shown in Fig. A.32. Click on Ngspice Model Tab and +Enter the Details of Ngspice Models else keep it empty where it will select default values as +shown in Fig. A.33 Then Click on Subciruits Tab to ADD half-adder Subcircut to the circuit +shown in Fig. A.34. (Note Details about Subcircuit is expained in earlier chapter Subcircuit +Builder.) +
Then Press Convert Button which will generate Ngspice Netlist (Half-Adder.cir.out) +
Now Click on Simulation icon to open Ngspice Plot and Python Plot shown in Fig. A.35 +and Fig. A.36. + +