From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 src/SubcircuitLibrary/full_sub/half_sub.sub | 18 ------------------
 1 file changed, 18 deletions(-)
 delete mode 100644 src/SubcircuitLibrary/full_sub/half_sub.sub

(limited to 'src/SubcircuitLibrary/full_sub/half_sub.sub')

diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub
deleted file mode 100644
index a61a3409..00000000
--- a/src/SubcircuitLibrary/full_sub/half_sub.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4  net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_sub
\ No newline at end of file
-- 
cgit