From fe3bd934634bb2dae1cadf35e7c6d59facbedf66 Mon Sep 17 00:00:00 2001
From: fossee
Date: Thu, 29 Aug 2019 12:03:11 +0530
Subject: adding files

---
 src/SubcircuitLibrary/full_sub/full_sub.sub | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 src/SubcircuitLibrary/full_sub/full_sub.sub

(limited to 'src/SubcircuitLibrary/full_sub/full_sub.sub')

diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub
new file mode 100644
index 00000000..9c9dcc5a
--- /dev/null
+++ b/src/SubcircuitLibrary/full_sub/full_sub.sub
@@ -0,0 +1,13 @@
+* Subcircuit full_sub
+.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ 
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
+.include half_sub.sub
+* u3  net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
+x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
+x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
+a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends full_sub
\ No newline at end of file
-- 
cgit