From 206afcded42d55572509e3439d752c9a81c84785 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Wed, 30 Dec 2015 12:31:05 +0530
Subject: Added : 1. Power Examples 2. eSim_Power.lib 3. DeviceModel for
 Powerdiode and Zenerdiode 4. Subcicuit for scr, diac, triac

---
 src/SubcircuitLibrary/diac/diac.sub~ | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 src/SubcircuitLibrary/diac/diac.sub~

(limited to 'src/SubcircuitLibrary/diac/diac.sub~')

diff --git a/src/SubcircuitLibrary/diac/diac.sub~ b/src/SubcircuitLibrary/diac/diac.sub~
new file mode 100644
index 00000000..43c2d279
--- /dev/null
+++ b/src/SubcircuitLibrary/diac/diac.sub~
@@ -0,0 +1,18 @@
+* Subcircuit diac
+.subckt diac 1 2 
+* /opt/esim/src/subcircuitlibrary/diac/diac.cir
+* u1  1 1 2 aswitch
+* u2  1 1 2 aswitch
+a1 1 [1 2 ] u1
+a2 1 [1 2 ] u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
+* Control Statements
+
+.ends diac
\ No newline at end of file
-- 
cgit