From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub | 26 -----------------------
 1 file changed, 26 deletions(-)
 delete mode 100644 src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub

(limited to 'src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub')

diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub
deleted file mode 100644
index a1e1cfac..00000000
--- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub
+++ /dev/null
@@ -1,26 +0,0 @@
-* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry 
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2  a b net-_u2-pad3_ d_and
-* u4  net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3  a b net-_u3-pad3_ d_xor
-* u5  net-_u3-pad3_ cin sum d_xor
-* u6  net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file
-- 
cgit