From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001 From: nilshah98 Date: Tue, 2 Jul 2019 16:42:20 +0530 Subject: Subcircuit added by ECE fellows 2019 --- src/SubcircuitLibrary/LM3046/LM3046-cache.lib | 77 +++++ src/SubcircuitLibrary/LM3046/LM3046.cir | 16 + src/SubcircuitLibrary/LM3046/LM3046.cir.out | 18 ++ src/SubcircuitLibrary/LM3046/LM3046.pro | 73 +++++ src/SubcircuitLibrary/LM3046/LM3046.sch | 326 +++++++++++++++++++++ src/SubcircuitLibrary/LM3046/LM3046.sub | 12 + src/SubcircuitLibrary/LM3046/LM3046.xml | 177 +++++++++++ .../LM3046/LM3046_Previous_Values.xml | 1 + src/SubcircuitLibrary/LM3046/NPN.lib | 4 + src/SubcircuitLibrary/LM3046/analysis | 1 + 10 files changed, 705 insertions(+) create mode 100644 src/SubcircuitLibrary/LM3046/LM3046-cache.lib create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.cir create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.cir.out create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.pro create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.sch create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.sub create mode 100644 src/SubcircuitLibrary/LM3046/LM3046.xml create mode 100644 src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml create mode 100644 src/SubcircuitLibrary/LM3046/NPN.lib create mode 100644 src/SubcircuitLibrary/LM3046/analysis (limited to 'src/SubcircuitLibrary/LM3046') diff --git a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib new file mode 100644 index 00000000..27505ab7 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir b/src/SubcircuitLibrary/LM3046/LM3046.cir new file mode 100644 index 00000000..f9716c63 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.cir @@ -0,0 +1,16 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM3046/LM3046.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:57:18 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN +U1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ Net-_Q5-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ Net-_Q4-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ Net-_Q2-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir.out b/src/SubcircuitLibrary/LM3046/LM3046.cir.out new file mode 100644 index 00000000..801e68d2 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.cir.out @@ -0,0 +1,18 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir + +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ port +.tran 10e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.pro b/src/SubcircuitLibrary/LM3046/LM3046.pro new file mode 100644 index 00000000..38ae7a8e --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.pro @@ -0,0 +1,73 @@ +update=Fri Jun 21 16:28:59 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../eSim-1.1.2/kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Plot +LibName35=eSim_Power +LibName36=eSim_PSpice +LibName37=eSim_Sources +LibName38=eSim_Subckt +LibName39=eSim_User +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sch b/src/SubcircuitLibrary/LM3046/LM3046.sch new file mode 100644 index 00000000..3ba1a18a --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.sch @@ -0,0 +1,326 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Miscellaneous +LIBS:LM3046-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5C98EC0E +P 4150 3500 +F 0 "Q1" H 4050 3550 50 0000 R CNN +F 1 "eSim_NPN" H 4100 3650 50 0000 R CNN +F 2 "" H 4350 3600 29 0000 C CNN +F 3 "" H 4150 3500 60 0000 C CNN + 1 4150 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5C98EC83 +P 4200 2400 +F 0 "Q2" H 4100 2450 50 0000 R CNN +F 1 "eSim_NPN" H 4150 2550 50 0000 R CNN +F 2 "" H 4400 2500 29 0000 C CNN +F 3 "" H 4200 2400 60 0000 C CNN + 1 4200 2400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5C98ECC0 +P 5400 2400 +F 0 "Q4" H 5300 2450 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2550 50 0000 R CNN +F 2 "" H 5600 2500 29 0000 C CNN +F 3 "" H 5400 2400 60 0000 C CNN + 1 5400 2400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 5C98ED6B +P 6350 3450 +F 0 "Q5" H 6250 3500 50 0000 R CNN +F 1 "eSim_NPN" H 6300 3600 50 0000 R CNN +F 2 "" H 6550 3550 29 0000 C CNN +F 3 "" H 6350 3450 60 0000 C CNN + 1 6350 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5C98EDA0 +P 5150 3500 +F 0 "Q3" H 5050 3550 50 0000 R CNN +F 1 "eSim_NPN" H 5100 3650 50 0000 R CNN +F 2 "" H 5350 3600 29 0000 C CNN +F 3 "" H 5150 3500 60 0000 C CNN + 1 5150 3500 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4250 3700 5050 3700 +Wire Wire Line + 4650 3700 4650 4250 +Connection ~ 4650 3700 +Wire Wire Line + 5350 3500 5350 4250 +Wire Wire Line + 5050 3300 5700 3300 +Wire Wire Line + 5700 3300 5700 4250 +Wire Wire Line + 6150 3450 6000 3450 +Wire Wire Line + 6000 3450 6000 4250 +Wire Wire Line + 6450 3250 6450 1700 +Wire Wire Line + 6450 3650 6450 4250 +Wire Wire Line + 3950 3500 3950 4250 +Wire Wire Line + 4250 3300 4250 3200 +Wire Wire Line + 4250 3200 3500 3200 +Wire Wire Line + 3500 3200 3500 4250 +Wire Wire Line + 4100 2200 4100 1700 +Wire Wire Line + 4100 2600 3500 2600 +Wire Wire Line + 3500 2600 3500 1700 +Wire Wire Line + 4400 2400 4400 1700 +Wire Wire Line + 5300 2200 5300 1700 +Wire Wire Line + 5300 2600 4800 2600 +Wire Wire Line + 4800 2600 4800 1700 +Wire Wire Line + 5600 2400 5900 2400 +Wire Wire Line + 5900 2400 5900 1700 +$Comp +L PORT U1 +U 1 1 5C98EEE0 +P 3500 4500 +F 0 "U1" H 3550 4600 30 0000 C CNN +F 1 "PORT" H 3500 4500 30 0000 C CNN +F 2 "" H 3500 4500 60 0000 C CNN +F 3 "" H 3500 4500 60 0000 C CNN + 1 3500 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C98EF2D +P 3950 4500 +F 0 "U1" H 4000 4600 30 0000 C CNN +F 1 "PORT" H 3950 4500 30 0000 C CNN +F 2 "" H 3950 4500 60 0000 C CNN +F 3 "" H 3950 4500 60 0000 C CNN + 2 3950 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C98EF86 +P 4650 4500 +F 0 "U1" H 4700 4600 30 0000 C CNN +F 1 "PORT" H 4650 4500 30 0000 C CNN +F 2 "" H 4650 4500 60 0000 C CNN +F 3 "" H 4650 4500 60 0000 C CNN + 3 4650 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C98EFBD +P 5350 4500 +F 0 "U1" H 5400 4600 30 0000 C CNN +F 1 "PORT" H 5350 4500 30 0000 C CNN +F 2 "" H 5350 4500 60 0000 C CNN +F 3 "" H 5350 4500 60 0000 C CNN + 4 5350 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C98EFF0 +P 5700 4500 +F 0 "U1" H 5750 4600 30 0000 C CNN +F 1 "PORT" H 5700 4500 30 0000 C CNN +F 2 "" H 5700 4500 60 0000 C CNN +F 3 "" H 5700 4500 60 0000 C CNN + 5 5700 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C98F02D +P 6000 4500 +F 0 "U1" H 6050 4600 30 0000 C CNN +F 1 "PORT" H 6000 4500 30 0000 C CNN +F 2 "" H 6000 4500 60 0000 C CNN +F 3 "" H 6000 4500 60 0000 C CNN + 6 6000 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C98F05E +P 6450 4500 +F 0 "U1" H 6500 4600 30 0000 C CNN +F 1 "PORT" H 6450 4500 30 0000 C CNN +F 2 "" H 6450 4500 60 0000 C CNN +F 3 "" H 6450 4500 60 0000 C CNN + 7 6450 4500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C98F0C3 +P 6450 1450 +F 0 "U1" H 6500 1550 30 0000 C CNN +F 1 "PORT" H 6450 1450 30 0000 C CNN +F 2 "" H 6450 1450 60 0000 C CNN +F 3 "" H 6450 1450 60 0000 C CNN + 8 6450 1450 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5C9CD7BF +P 6050 4250 +F 0 "#FLG01" H 6050 4345 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 4430 50 0000 C CNN +F 2 "" H 6050 4250 50 0000 C CNN +F 3 "" H 6050 4250 50 0000 C CNN + 1 6050 4250 + 0 1 1 0 +$EndComp +Wire Wire Line + 6000 4250 6050 4250 +Wire Wire Line + 5600 2450 5600 2400 +$Comp +L PORT U1 +U 9 1 5D0CBFBB +P 5900 1450 +F 0 "U1" H 5950 1550 30 0000 C CNN +F 1 "PORT" H 5900 1450 30 0000 C CNN +F 2 "" H 5900 1450 60 0000 C CNN +F 3 "" H 5900 1450 60 0000 C CNN + 9 5900 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5D0CC62F +P 5300 1450 +F 0 "U1" H 5350 1550 30 0000 C CNN +F 1 "PORT" H 5300 1450 30 0000 C CNN +F 2 "" H 5300 1450 60 0000 C CNN +F 3 "" H 5300 1450 60 0000 C CNN + 10 5300 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5D0CC70E +P 4800 1450 +F 0 "U1" H 4850 1550 30 0000 C CNN +F 1 "PORT" H 4800 1450 30 0000 C CNN +F 2 "" H 4800 1450 60 0000 C CNN +F 3 "" H 4800 1450 60 0000 C CNN + 11 4800 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 5D0CC84E +P 4400 1450 +F 0 "U1" H 4450 1550 30 0000 C CNN +F 1 "PORT" H 4400 1450 30 0000 C CNN +F 2 "" H 4400 1450 60 0000 C CNN +F 3 "" H 4400 1450 60 0000 C CNN + 12 4400 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 5D0CC96F +P 3500 1450 +F 0 "U1" H 3550 1550 30 0000 C CNN +F 1 "PORT" H 3500 1450 30 0000 C CNN +F 2 "" H 3500 1450 60 0000 C CNN +F 3 "" H 3500 1450 60 0000 C CNN + 14 3500 1450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5D0CC9BD +P 4100 1450 +F 0 "U1" H 4150 1550 30 0000 C CNN +F 1 "PORT" H 4100 1450 30 0000 C CNN +F 2 "" H 4100 1450 60 0000 C CNN +F 3 "" H 4100 1450 60 0000 C CNN + 13 4100 1450 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sub b/src/SubcircuitLibrary/LM3046/LM3046.sub new file mode 100644 index 00000000..251364bb --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.sub @@ -0,0 +1,12 @@ +* Subcircuit LM3046 +.subckt LM3046 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 +* Control Statements + +.ends LM3046 \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/LM3046.xml b/src/SubcircuitLibrary/LM3046/LM3046.xml new file mode 100644 index 00000000..94884e43 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046.xml @@ -0,0 +1,177 @@ + + + + C:/esim_1/eSim/src/SubcircuitLibrary/LM3046/LM3046.sch + 03/27/19 23:15:04 + Eeschema 4.0.2-stable + + + + <company/> + <rev/> + <date/> + <source>LM3046.sch</source> + <comment number="1" value=""/> + <comment number="2" value=""/> + <comment number="3" value=""/> + <comment number="4" value=""/> + </title_block> + </sheet> + </design> + <components> + <comp ref="Q1"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EC0E</tstamp> + </comp> + <comp ref="Q2"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EC83</tstamp> + </comp> + <comp ref="Q4"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98ECC0</tstamp> + </comp> + <comp ref="Q5"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98ED6B</tstamp> + </comp> + <comp ref="Q3"> + <value>eSim_NPN</value> + <libsource lib="eSim_Devices" part="eSim_NPN"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EDA0</tstamp> + </comp> + <comp ref="U1"> + <value>PORT</value> + <libsource lib="eSim_Miscellaneous" part="PORT"/> + <sheetpath names="/" tstamps="/"/> + <tstamp>5C98EEE0</tstamp> + </comp> + </components> + <libparts> + <libpart lib="eSim_Miscellaneous" part="PORT"> + <fields> + <field name="Reference">U</field> + <field name="Value">PORT</field> + </fields> + <pins> + <pin num="1" name="~" type="BiDi"/> + <pin num="2" name="~" type="BiDi"/> + <pin num="3" name="~" type="BiDi"/> + <pin num="4" name="~" type="BiDi"/> + <pin num="5" name="~" type="BiDi"/> + <pin num="6" name="~" type="BiDi"/> + <pin num="7" name="~" type="BiDi"/> + <pin num="8" name="~" type="BiDi"/> + <pin num="9" name="~" type="BiDi"/> + <pin num="10" name="~" type="BiDi"/> + <pin num="11" name="~" type="BiDi"/> + <pin num="12" name="~" type="BiDi"/> + <pin num="13" name="~" type="BiDi"/> + <pin num="14" name="~" type="BiDi"/> + <pin num="15" name="~" type="BiDi"/> + <pin num="16" name="~" type="BiDi"/> + <pin num="17" name="~" type="BiDi"/> + <pin num="18" name="~" type="BiDi"/> + <pin num="19" name="~" type="BiDi"/> + <pin num="20" name="~" type="BiDi"/> + <pin num="21" name="~" type="BiDi"/> + <pin num="22" name="~" type="BiDi"/> + <pin num="23" name="~" type="BiDi"/> + <pin num="24" name="~" type="BiDi"/> + <pin num="25" name="~" type="BiDi"/> + <pin num="26" name="~" type="BiDi"/> + </pins> + </libpart> + <libpart lib="eSim_Devices" part="eSim_NPN"> + <aliases> + <alias>BC547</alias> + <alias>Q2N2222</alias> + </aliases> + <fields> + <field name="Reference">Q</field> + <field name="Value">eSim_NPN</field> + </fields> + <pins> + <pin num="1" name="C" type="openCol"/> + <pin num="2" name="B" type="input"/> + <pin num="3" name="E" type="openEm"/> + </pins> + </libpart> + </libparts> + <libraries> + <library logical="eSim_Miscellaneous"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri> + </library> + <library logical="eSim_Devices"> + <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri> + </library> + </libraries> + <nets> + <net code="1" name="Net-(Q1-Pad1)"> + <node ref="Q1" pin="1"/> + <node ref="U1" pin="1"/> + </net> + <net code="2" name="Net-(Q2-Pad3)"> + <node ref="Q2" pin="3"/> + <node ref="U1" pin="13"/> + </net> + <net code="3" name="Net-(Q2-Pad1)"> + <node ref="Q2" pin="1"/> + <node ref="U1" pin="14"/> + </net> + <net code="4" name="Net-(Q2-Pad2)"> + <node ref="Q2" pin="2"/> + <node ref="U1" pin="12"/> + </net> + <net code="5" name="Net-(Q4-Pad3)"> + <node ref="Q4" pin="3"/> + <node ref="U1" pin="10"/> + </net> + <net code="6" name="Net-(Q4-Pad1)"> + <node ref="Q4" pin="1"/> + <node ref="U1" pin="11"/> + </net> + <net code="7" name="Net-(Q4-Pad2)"> + <node ref="Q4" pin="2"/> + <node ref="U1" pin="9"/> + </net> + <net code="8" name="Net-(Q1-Pad3)"> + <node ref="Q3" pin="3"/> + <node ref="Q1" pin="3"/> + <node ref="U1" pin="3"/> + </net> + <net code="9" name="Net-(Q3-Pad2)"> + <node ref="Q3" pin="2"/> + <node ref="U1" pin="4"/> + </net> + <net code="10" name="Net-(Q1-Pad2)"> + <node ref="Q1" pin="2"/> + <node ref="U1" pin="2"/> + </net> + <net code="11" name="Net-(Q5-Pad1)"> + <node ref="Q5" pin="1"/> + <node ref="U1" pin="8"/> + </net> + <net code="12" name="Net-(Q5-Pad2)"> + <node ref="U1" pin="6"/> + <node ref="Q5" pin="2"/> + </net> + <net code="13" name="Net-(Q5-Pad3)"> + <node ref="U1" pin="7"/> + <node ref="Q5" pin="3"/> + </net> + <net code="14" name="Net-(Q3-Pad1)"> + <node ref="U1" pin="5"/> + <node ref="Q3" pin="1"/> + </net> + </nets> +</export> diff --git a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml new file mode 100644 index 00000000..0b34a8e5 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/NPN.lib b/src/SubcircuitLibrary/LM3046/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM3046/analysis b/src/SubcircuitLibrary/LM3046/analysis new file mode 100644 index 00000000..d5e13546 --- /dev/null +++ b/src/SubcircuitLibrary/LM3046/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-00 \ No newline at end of file -- cgit