From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 15:16:35 +0530
Subject: common code for Win and Linux, merged py2 changes
---
src/SubcircuitLibrary/74157/3_and-cache.lib | 122 +++---
src/SubcircuitLibrary/74157/3_and.cir | 26 +-
src/SubcircuitLibrary/74157/3_and.cir.out | 40 +-
src/SubcircuitLibrary/74157/3_and.pro | 102 +++--
src/SubcircuitLibrary/74157/3_and.sch | 251 ++++++-----
src/SubcircuitLibrary/74157/3_and.sub | 26 +-
src/SubcircuitLibrary/74157/74157-cache.lib | 16 +-
src/SubcircuitLibrary/74157/74157.cir | 34 +-
src/SubcircuitLibrary/74157/74157.cir.out | 44 +-
src/SubcircuitLibrary/74157/74157.pro | 39 +-
src/SubcircuitLibrary/74157/74157.sch | 467 ++++++++++-----------
src/SubcircuitLibrary/74157/74157.sub | 44 +-
.../74157/74157_Previous_Values.xml | 2 +-
13 files changed, 610 insertions(+), 603 deletions(-)
(limited to 'src/SubcircuitLibrary/74157')
diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib
index 0a3ccf7f..af058641 100644
--- a/src/SubcircuitLibrary/74157/3_and-cache.lib
+++ b/src/SubcircuitLibrary/74157/3_and-cache.lib
@@ -1,61 +1,61 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir
index 15f8954d..ba296cf0 100644
--- a/src/SubcircuitLibrary/74157/3_and.cir
+++ b/src/SubcircuitLibrary/74157/3_and.cir
@@ -1,13 +1,13 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out
index e3c96645..d7cf79a0 100644
--- a/src/SubcircuitLibrary/74157/3_and.cir.out
+++ b/src/SubcircuitLibrary/74157/3_and.cir.out
@@ -1,20 +1,20 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro
index 0fdf4d25..2c9ac554 100644
--- a/src/SubcircuitLibrary/74157/3_and.pro
+++ b/src/SubcircuitLibrary/74157/3_and.pro
@@ -1,44 +1,58 @@
-update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch
index c853bf49..86be0215 100644
--- a/src/SubcircuitLibrary/74157/3_and.sch
+++ b/src/SubcircuitLibrary/74157/3_and.sch
@@ -1,130 +1,121 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub
index b949ae4f..3d9120bb 100644
--- a/src/SubcircuitLibrary/74157/3_and.sub
+++ b/src/SubcircuitLibrary/74157/3_and.sub
@@ -1,14 +1,14 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib
index d72d1628..de171255 100644
--- a/src/SubcircuitLibrary/74157/74157-cache.lib
+++ b/src/SubcircuitLibrary/74157/74157-cache.lib
@@ -1,17 +1,17 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
-# 3_and-RESCUE-74157
+# 3_and
#
-DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N
+DEF 3_and X 0 40 Y Y 1 F N
F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN
+F1 "3_and" 950 500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
X in1 1 450 500 200 R 50 50 1 1 I
X in2 2 450 400 200 R 50 50 1 1 I
X in3 3 450 300 200 R 50 50 1 1 I
@@ -67,7 +67,7 @@ F1 "d_inverter" 0 150 60 H V C CNN
F2 "" 50 -50 60 H V C CNN
F3 "" 50 -50 60 H V C CNN
DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
X ~ 1 -300 0 200 R 50 50 1 1 I
X ~ 2 300 0 200 L 50 50 1 1 O I
ENDDRAW
@@ -84,8 +84,8 @@ DRAW
A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
A -25 -124 325 574 323 0 1 0 N 150 150 250 50
A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
X IN1 1 -450 100 215 R 50 50 1 1 I
X IN2 2 -450 0 215 R 50 50 1 1 I
X OUT 3 450 50 200 L 50 50 1 1 O
diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir
index cfd1c0e9..6920161c 100644
--- a/src/SubcircuitLibrary/74157/74157.cir
+++ b/src/SubcircuitLibrary/74157/74157.cir
@@ -1,25 +1,25 @@
-* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74157/74157.cir
+* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir
-* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 20:50:36 2019
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43
* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
* Sheet Name: /
-U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad4_ d_or
-U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad7_ d_or
-U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad9_ d_or
-U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad12_ d_or
-U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
-U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter
-X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad1_ 3_and
-X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U21-Pad1_ 3_and
-X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U22-Pad1_ 3_and
-X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U23-Pad1_ 3_and
-X6 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U20-Pad2_ 3_and
-X7 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad2_ 3_and
-X1 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad10_ Net-_U22-Pad2_ 3_and
-X8 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ Net-_U23-Pad2_ 3_and
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or
+U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and
+X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and
+X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and
+X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and
+X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and
+X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and
+X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and
+X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and
.end
diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out
index b9a19223..3a11a42d 100644
--- a/src/SubcircuitLibrary/74157/74157.cir.out
+++ b/src/SubcircuitLibrary/74157/74157.cir.out
@@ -1,27 +1,27 @@
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir
+* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
.include 3_and.sub
-* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or
-* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or
-* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or
-* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or
-* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23
-a5 net-_u1-pad1_ net-_u3-pad2_ u3
-a6 net-_u1-pad15_ net-_u2-pad2_ u2
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
+* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
+* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
+x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
+x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
+x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
+x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
+x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
+x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
+x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
+a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
+a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
+a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
+a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
+a5 net-_u1-pad10_ net-_u3-pad2_ u3
+a6 net-_u1-pad9_ net-_u2-pad2_ u2
* Schematic Name: d_or, NgSpice Name: d_or
.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: d_or, NgSpice Name: d_or
diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro
index 4042e1e9..fcbb1fc8 100644
--- a/src/SubcircuitLibrary/74157/74157.pro
+++ b/src/SubcircuitLibrary/74157/74157.pro
@@ -1,4 +1,4 @@
-update=Tue Jun 25 20:59:09 2019
+update=03/28/19 22:30:06
version=1
last_client=eeschema
[general]
@@ -29,16 +29,29 @@ version=1
NetIExt=net
[eeschema]
version=1
-LibDir=../../../kicadSchematicLibrary
+LibDir=
[eeschema/libraries]
-LibName1=74157-rescue
-LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog
-LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices
-LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital
-LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid
-LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot
-LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power
-LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources
-LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User
+LibName1=power
+LibName2=intel
+LibName3=audio
+LibName4=interface
+LibName5=digital-audio
+LibName6=philips
+LibName7=display
+LibName8=cypress
+LibName9=siliconi
+LibName10=opto
+LibName11=atmel
+LibName12=contrib
+LibName13=valves
+LibName14=eSim_Analog
+LibName15=eSim_Devices
+LibName16=eSim_Digital
+LibName17=eSim_Hybrid
+LibName18=eSim_Miscellaneous
+LibName19=eSim_Plot
+LibName20=eSim_Power
+LibName21=eSim_PSpice
+LibName22=eSim_Sources
+LibName23=eSim_User
+LibName24=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch
index c7c64ece..7fd3609e 100644
--- a/src/SubcircuitLibrary/74157/74157.sch
+++ b/src/SubcircuitLibrary/74157/74157.sch
@@ -1,5 +1,17 @@
EESchema Schematic File Version 2
-LIBS:74157-rescue
+LIBS:power
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
LIBS:eSim_Analog
LIBS:eSim_Devices
LIBS:eSim_Digital
@@ -7,9 +19,10 @@ LIBS:eSim_Hybrid
LIBS:eSim_Miscellaneous
LIBS:eSim_Plot
LIBS:eSim_Power
+LIBS:eSim_PSpice
LIBS:eSim_Sources
-LIBS:eSim_Subckt
LIBS:eSim_User
+LIBS:eSim_Subckt
LIBS:74157-cache
EELAYER 25 0
EELAYER END
@@ -25,6 +38,34 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
+Wire Wire Line
+ 1650 1850 2750 1850
+Wire Wire Line
+ 2750 3350 1650 3350
+Wire Wire Line
+ 2750 3050 2750 3350
+Wire Wire Line
+ 2800 4050 1650 4050
+Wire Wire Line
+ 2800 3550 2800 4050
+Wire Wire Line
+ 2200 2150 2200 4350
+Wire Wire Line
+ 2200 2150 1650 2150
+Wire Wire Line
+ 2150 2900 2150 4850
+Wire Wire Line
+ 2150 2900 1650 2900
+Wire Wire Line
+ 2100 3600 2100 5300
+Wire Wire Line
+ 2100 3600 1650 3600
+Wire Wire Line
+ 2050 4300 2050 5800
+Wire Wire Line
+ 1650 4300 2050 4300
+Wire Wire Line
+ 2200 5500 2200 6250
$Comp
L d_or U20
U 1 1 5C95E06C
@@ -69,6 +110,62 @@ F 3 "" H 6650 4750 60 0000 C CNN
1 6650 4750
1 0 0 -1
$EndComp
+Wire Wire Line
+ 6200 3200 5950 3200
+Wire Wire Line
+ 5950 3200 5950 2000
+Wire Wire Line
+ 5950 2000 4750 2000
+Wire Wire Line
+ 6200 3700 5850 3700
+Wire Wire Line
+ 5850 3700 5850 2500
+Wire Wire Line
+ 5850 2500 4750 2500
+Wire Wire Line
+ 6200 4150 5750 4150
+Wire Wire Line
+ 5750 4150 5750 2950
+Wire Wire Line
+ 5750 2950 4750 2950
+Wire Wire Line
+ 6200 4650 5650 4650
+Wire Wire Line
+ 5650 4650 5650 3450
+Wire Wire Line
+ 5650 3450 4750 3450
+Wire Wire Line
+ 4750 4250 5450 4250
+Wire Wire Line
+ 5450 4250 5450 3300
+Wire Wire Line
+ 5450 3300 6200 3300
+Wire Wire Line
+ 4750 4750 5550 4750
+Wire Wire Line
+ 5550 4750 5550 3800
+Wire Wire Line
+ 5550 3800 6200 3800
+Wire Wire Line
+ 4700 5200 5600 5200
+Wire Wire Line
+ 5600 5200 5600 4250
+Wire Wire Line
+ 5600 4250 6200 4250
+Wire Wire Line
+ 4750 5700 5700 5700
+Wire Wire Line
+ 5700 5700 5700 4750
+Wire Wire Line
+ 5700 4750 6200 4750
+Wire Wire Line
+ 7100 3250 8300 3250
+Wire Wire Line
+ 7100 3750 8300 3750
+Wire Wire Line
+ 7100 4200 8300 4200
+Wire Wire Line
+ 7100 4700 8250 4700
$Comp
L d_inverter U3
U 1 1 5C95E74D
@@ -80,154 +177,168 @@ F 3 "" H 2800 6200 60 0000 C CNN
1 2750 6250
1 0 0 -1
$EndComp
+Wire Wire Line
+ 1700 6250 2450 6250
+Connection ~ 2200 6250
$Comp
L PORT U1
-U 2 1 5C95E920
+U 1 1 5C95E920
P 1400 1850
F 0 "U1" H 1450 1950 30 0000 C CNN
F 1 "PORT" H 1400 1850 30 0000 C CNN
F 2 "" H 1400 1850 60 0000 C CNN
F 3 "" H 1400 1850 60 0000 C CNN
- 2 1400 1850
+ 1 1400 1850
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 3 1 5C95E9CF
+U 2 1 5C95E9CF
P 1400 2150
F 0 "U1" H 1450 2250 30 0000 C CNN
F 1 "PORT" H 1400 2150 30 0000 C CNN
F 2 "" H 1400 2150 60 0000 C CNN
F 3 "" H 1400 2150 60 0000 C CNN
- 3 1400 2150
+ 2 1400 2150
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 11 1 5C95EA28
+U 3 1 5C95EA28
+P 1400 2700
+F 0 "U1" H 1450 2800 30 0000 C CNN
+F 1 "PORT" H 1400 2700 30 0000 C CNN
+F 2 "" H 1400 2700 60 0000 C CNN
+F 3 "" H 1400 2700 60 0000 C CNN
+ 3 1400 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C95EA9C
+P 1400 2900
+F 0 "U1" H 1450 3000 30 0000 C CNN
+F 1 "PORT" H 1400 2900 30 0000 C CNN
+F 2 "" H 1400 2900 60 0000 C CNN
+F 3 "" H 1400 2900 60 0000 C CNN
+ 4 1400 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C95EAFD
P 1400 3350
F 0 "U1" H 1450 3450 30 0000 C CNN
F 1 "PORT" H 1400 3350 30 0000 C CNN
F 2 "" H 1400 3350 60 0000 C CNN
F 3 "" H 1400 3350 60 0000 C CNN
- 11 1400 3350
+ 5 1400 3350
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 10 1 5C95EA9C
+U 6 1 5C95EB63
P 1400 3600
F 0 "U1" H 1450 3700 30 0000 C CNN
F 1 "PORT" H 1400 3600 30 0000 C CNN
F 2 "" H 1400 3600 60 0000 C CNN
F 3 "" H 1400 3600 60 0000 C CNN
- 10 1400 3600
+ 6 1400 3600
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 5 1 5C95EAFD
-P 1400 2650
-F 0 "U1" H 1450 2750 30 0000 C CNN
-F 1 "PORT" H 1400 2650 30 0000 C CNN
-F 2 "" H 1400 2650 60 0000 C CNN
-F 3 "" H 1400 2650 60 0000 C CNN
- 5 1400 2650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C95EB63
-P 1400 2900
-F 0 "U1" H 1450 3000 30 0000 C CNN
-F 1 "PORT" H 1400 2900 30 0000 C CNN
-F 2 "" H 1400 2900 60 0000 C CNN
-F 3 "" H 1400 2900 60 0000 C CNN
- 6 1400 2900
+U 7 1 5C95EBC8
+P 1400 4050
+F 0 "U1" H 1450 4150 30 0000 C CNN
+F 1 "PORT" H 1400 4050 30 0000 C CNN
+F 2 "" H 1400 4050 60 0000 C CNN
+F 3 "" H 1400 4050 60 0000 C CNN
+ 7 1400 4050
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 13 1 5C95EC38
+U 8 1 5C95EC38
P 1400 4300
F 0 "U1" H 1450 4400 30 0000 C CNN
F 1 "PORT" H 1400 4300 30 0000 C CNN
F 2 "" H 1400 4300 60 0000 C CNN
F 3 "" H 1400 4300 60 0000 C CNN
- 13 1400 4300
+ 8 1400 4300
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 1 1 5C95ECA1
+U 10 1 5C95ECA1
P 1450 6250
F 0 "U1" H 1500 6350 30 0000 C CNN
F 1 "PORT" H 1450 6250 30 0000 C CNN
F 2 "" H 1450 6250 60 0000 C CNN
F 3 "" H 1450 6250 60 0000 C CNN
- 1 1450 6250
+ 10 1450 6250
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 15 1 5C95ED51
+U 9 1 5C95ED51
P 1400 6650
F 0 "U1" H 1450 6750 30 0000 C CNN
F 1 "PORT" H 1400 6650 30 0000 C CNN
F 2 "" H 1400 6650 60 0000 C CNN
F 3 "" H 1400 6650 60 0000 C CNN
- 15 1400 6650
+ 9 1400 6650
1 0 0 -1
$EndComp
$Comp
L PORT U1
-U 4 1 5C95EDCC
+U 12 1 5C95EDCC
P 8550 3250
F 0 "U1" H 8600 3350 30 0000 C CNN
F 1 "PORT" H 8550 3250 30 0000 C CNN
F 2 "" H 8550 3250 60 0000 C CNN
F 3 "" H 8550 3250 60 0000 C CNN
- 4 8550 3250
+ 12 8550 3250
-1 0 0 1
$EndComp
$Comp
L PORT U1
-U 7 1 5C95EEA6
+U 13 1 5C95EEA6
P 8550 3750
F 0 "U1" H 8600 3850 30 0000 C CNN
F 1 "PORT" H 8550 3750 30 0000 C CNN
F 2 "" H 8550 3750 60 0000 C CNN
F 3 "" H 8550 3750 60 0000 C CNN
- 7 8550 3750
+ 13 8550 3750
-1 0 0 1
$EndComp
$Comp
L PORT U1
-U 9 1 5C95EF2D
+U 14 1 5C95EF2D
P 8550 4200
F 0 "U1" H 8600 4300 30 0000 C CNN
F 1 "PORT" H 8550 4200 30 0000 C CNN
F 2 "" H 8550 4200 60 0000 C CNN
F 3 "" H 8550 4200 60 0000 C CNN
- 9 8550 4200
+ 14 8550 4200
-1 0 0 1
$EndComp
$Comp
L PORT U1
-U 12 1 5C95EFB5
+U 11 1 5C95EFB5
P 8500 4700
F 0 "U1" H 8550 4800 30 0000 C CNN
F 1 "PORT" H 8500 4700 30 0000 C CNN
F 2 "" H 8500 4700 60 0000 C CNN
F 3 "" H 8500 4700 60 0000 C CNN
- 12 8500 4700
+ 11 8500 4700
-1 0 0 1
$EndComp
Text Notes 1950 1800 0 60 ~ 12
A0\n
Text Notes 1950 2100 0 60 ~ 12
A1
-Text Notes 1900 2600 0 60 ~ 12
+Text Notes 1900 2650 0 60 ~ 12
B0
Text Notes 1900 2900 0 60 ~ 12
B1\n
@@ -254,6 +365,10 @@ F 3 "" H 2700 6600 60 0000 C CNN
1 2650 6650
1 0 0 -1
$EndComp
+Wire Wire Line
+ 3400 6650 2950 6650
+Wire Wire Line
+ 1650 6650 2350 6650
Text Notes 7850 3200 0 60 ~ 12
YA
Text Notes 7850 3700 0 60 ~ 12
@@ -262,8 +377,69 @@ Text Notes 7850 4200 2 60 ~ 12
YC
Text Notes 7800 4700 0 60 ~ 12
YD
+Wire Wire Line
+ 3450 2000 3900 2000
+Wire Wire Line
+ 3450 2000 3450 5700
+Wire Wire Line
+ 3450 2500 3900 2500
+Wire Wire Line
+ 3450 2950 3900 2950
+Connection ~ 3450 2500
+Wire Wire Line
+ 3450 3450 3900 3450
+Connection ~ 3450 2950
+Wire Wire Line
+ 3450 4250 3900 4250
+Connection ~ 3450 3450
+Wire Wire Line
+ 3450 4750 3900 4750
+Connection ~ 3450 4250
+Wire Wire Line
+ 3450 5200 3850 5200
+Connection ~ 3450 4750
+Wire Wire Line
+ 3400 5700 3900 5700
+Connection ~ 3450 5200
+Wire Wire Line
+ 3300 5600 3900 5600
+Wire Wire Line
+ 3300 4150 3300 5600
+Wire Wire Line
+ 3300 5100 3850 5100
+Wire Wire Line
+ 3300 4650 3900 4650
+Connection ~ 3300 5100
+Wire Wire Line
+ 3300 4150 3900 4150
+Connection ~ 3300 4650
+Wire Wire Line
+ 3250 3350 3900 3350
+Wire Wire Line
+ 3250 1900 3250 3350
+Wire Wire Line
+ 3250 2850 3900 2850
+Wire Wire Line
+ 3250 2400 3900 2400
+Connection ~ 3250 2850
+Wire Wire Line
+ 3250 1900 3900 1900
+Connection ~ 3250 2400
+Wire Wire Line
+ 3250 3000 3100 3000
+Wire Wire Line
+ 3100 3000 3100 6250
+Wire Wire Line
+ 3100 6250 3050 6250
+Connection ~ 3250 3000
+Wire Wire Line
+ 3300 5500 2200 5500
+Connection ~ 3300 5500
+Wire Wire Line
+ 3400 6650 3400 5700
+Connection ~ 3450 5700
$Comp
-L 3_and-RESCUE-74157 X2
+L 3_and X2
U 1 1 5C9D0110
P 3450 2400
F 0 "X2" H 4350 2700 60 0000 C CNN
@@ -274,7 +450,7 @@ F 3 "" H 3450 2400 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X3
+L 3_and X3
U 1 1 5C9D01B8
P 3450 2900
F 0 "X3" H 4350 3200 60 0000 C CNN
@@ -285,7 +461,7 @@ F 3 "" H 3450 2900 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X4
+L 3_and X4
U 1 1 5C9D0222
P 3450 3350
F 0 "X4" H 4350 3650 60 0000 C CNN
@@ -296,7 +472,7 @@ F 3 "" H 3450 3350 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X5
+L 3_and X5
U 1 1 5C9D0289
P 3450 3850
F 0 "X5" H 4350 4150 60 0000 C CNN
@@ -307,7 +483,7 @@ F 3 "" H 3450 3850 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X6
+L 3_and X6
U 1 1 5C9D0361
P 3450 4650
F 0 "X6" H 4350 4950 60 0000 C CNN
@@ -318,7 +494,7 @@ F 3 "" H 3450 4650 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X7
+L 3_and X7
U 1 1 5C9D0367
P 3450 5150
F 0 "X7" H 4350 5450 60 0000 C CNN
@@ -329,7 +505,7 @@ F 3 "" H 3450 5150 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X1
+L 3_and X1
U 1 1 5C9D036D
P 3400 5600
F 0 "X1" H 4300 5900 60 0000 C CNN
@@ -340,7 +516,7 @@ F 3 "" H 3400 5600 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L 3_and-RESCUE-74157 X8
+L 3_and X8
U 1 1 5C9D0373
P 3450 6100
F 0 "X8" H 4350 6400 60 0000 C CNN
@@ -350,180 +526,6 @@ F 3 "" H 3450 6100 60 0000 C CNN
1 3450 6100
1 0 0 -1
$EndComp
-$Comp
-L PORT U1
-U 8 1 5D123D14
-P 8450 1500
-F 0 "U1" H 8500 1600 30 0000 C CNN
-F 1 "PORT" H 8450 1500 30 0000 C CNN
-F 2 "" H 8450 1500 60 0000 C CNN
-F 3 "" H 8450 1500 60 0000 C CNN
- 8 8450 1500
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 16 1 5D123E38
-P 8450 1850
-F 0 "U1" H 8500 1950 30 0000 C CNN
-F 1 "PORT" H 8450 1850 30 0000 C CNN
-F 2 "" H 8450 1850 60 0000 C CNN
-F 3 "" H 8450 1850 60 0000 C CNN
- 16 8450 1850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 1650 1850 2750 1850
-Wire Wire Line
- 2750 3350 1650 3350
-Wire Wire Line
- 2750 3050 2750 3350
-Wire Wire Line
- 2800 4050 1650 4050
-Wire Wire Line
- 2800 3550 2800 4050
-Wire Wire Line
- 2200 2150 2200 4350
-Wire Wire Line
- 2200 2150 1650 2150
-Wire Wire Line
- 2150 2900 2150 4850
-Wire Wire Line
- 2150 2900 1650 2900
-Wire Wire Line
- 2100 3600 2100 5300
-Wire Wire Line
- 2100 3600 1650 3600
-Wire Wire Line
- 2050 4300 2050 5800
-Wire Wire Line
- 1650 4300 2050 4300
-Wire Wire Line
- 2200 5500 2200 6250
-Wire Wire Line
- 6200 3200 5950 3200
-Wire Wire Line
- 5950 3200 5950 2000
-Wire Wire Line
- 5950 2000 4750 2000
-Wire Wire Line
- 6200 3700 5850 3700
-Wire Wire Line
- 5850 3700 5850 2500
-Wire Wire Line
- 5850 2500 4750 2500
-Wire Wire Line
- 6200 4150 5750 4150
-Wire Wire Line
- 5750 4150 5750 2950
-Wire Wire Line
- 5750 2950 4750 2950
-Wire Wire Line
- 6200 4650 5650 4650
-Wire Wire Line
- 5650 4650 5650 3450
-Wire Wire Line
- 5650 3450 4750 3450
-Wire Wire Line
- 4750 4250 5450 4250
-Wire Wire Line
- 5450 4250 5450 3300
-Wire Wire Line
- 5450 3300 6200 3300
-Wire Wire Line
- 4750 4750 5550 4750
-Wire Wire Line
- 5550 4750 5550 3800
-Wire Wire Line
- 5550 3800 6200 3800
-Wire Wire Line
- 4700 5200 5600 5200
-Wire Wire Line
- 5600 5200 5600 4250
-Wire Wire Line
- 5600 4250 6200 4250
-Wire Wire Line
- 4750 5700 5700 5700
-Wire Wire Line
- 5700 5700 5700 4750
-Wire Wire Line
- 5700 4750 6200 4750
-Wire Wire Line
- 7100 3250 8300 3250
-Wire Wire Line
- 7100 3750 8300 3750
-Wire Wire Line
- 7100 4200 8300 4200
-Wire Wire Line
- 7100 4700 8250 4700
-Wire Wire Line
- 1700 6250 2450 6250
-Connection ~ 2200 6250
-Wire Wire Line
- 3400 6650 2950 6650
-Wire Wire Line
- 1650 6650 2350 6650
-Wire Wire Line
- 3450 2000 3900 2000
-Wire Wire Line
- 3450 2000 3450 5700
-Wire Wire Line
- 3450 2500 3900 2500
-Wire Wire Line
- 3450 2950 3900 2950
-Connection ~ 3450 2500
-Wire Wire Line
- 3450 3450 3900 3450
-Connection ~ 3450 2950
-Wire Wire Line
- 3450 4250 3900 4250
-Connection ~ 3450 3450
-Wire Wire Line
- 3450 4750 3900 4750
-Connection ~ 3450 4250
-Wire Wire Line
- 3450 5200 3850 5200
-Connection ~ 3450 4750
-Wire Wire Line
- 3400 5700 3900 5700
-Connection ~ 3450 5200
-Wire Wire Line
- 3300 5600 3900 5600
-Wire Wire Line
- 3300 4150 3300 5600
-Wire Wire Line
- 3300 5100 3850 5100
-Wire Wire Line
- 3300 4650 3900 4650
-Connection ~ 3300 5100
-Wire Wire Line
- 3300 4150 3900 4150
-Connection ~ 3300 4650
-Wire Wire Line
- 3250 3350 3900 3350
-Wire Wire Line
- 3250 1900 3250 3350
-Wire Wire Line
- 3250 2850 3900 2850
-Wire Wire Line
- 3250 2400 3900 2400
-Connection ~ 3250 2850
-Wire Wire Line
- 3250 1900 3900 1900
-Connection ~ 3250 2400
-Wire Wire Line
- 3250 3000 3100 3000
-Wire Wire Line
- 3100 3000 3100 6250
-Wire Wire Line
- 3100 6250 3050 6250
-Connection ~ 3250 3000
-Wire Wire Line
- 3300 5500 2200 5500
-Connection ~ 3300 5500
-Wire Wire Line
- 3400 6650 3400 5700
-Connection ~ 3450 5700
Wire Wire Line
3900 2100 2750 2100
Wire Wire Line
@@ -531,7 +533,7 @@ Wire Wire Line
Wire Wire Line
3900 2600 1650 2600
Wire Wire Line
- 1650 2600 1650 2650
+ 1650 2600 1650 2700
Wire Wire Line
3900 3050 2750 3050
Wire Wire Line
@@ -544,17 +546,4 @@ Wire Wire Line
2100 5300 3850 5300
Wire Wire Line
2050 5800 3900 5800
-$Comp
-L PORT U1
-U 14 1 5C95EBC8
-P 1400 4050
-F 0 "U1" H 1450 4150 30 0000 C CNN
-F 1 "PORT" H 1400 4050 30 0000 C CNN
-F 2 "" H 1400 4050 60 0000 C CNN
-F 3 "" H 1400 4050 60 0000 C CNN
- 14 1400 4050
- 1 0 0 -1
-$EndComp
-NoConn ~ 8200 1500
-NoConn ~ 8200 1850
$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub
index 54897c26..545741f5 100644
--- a/src/SubcircuitLibrary/74157/74157.sub
+++ b/src/SubcircuitLibrary/74157/74157.sub
@@ -1,27 +1,27 @@
* Subcircuit 74157
-.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
-* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir
+.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
.include 3_and.sub
-* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or
-* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or
-* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or
-* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or
-* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter
-* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23
-a5 net-_u1-pad1_ net-_u3-pad2_ u3
-a6 net-_u1-pad15_ net-_u2-pad2_ u2
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
+* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
+* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
+x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
+x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
+x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
+x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
+x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
+x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
+x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
+a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
+a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
+a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
+a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
+a5 net-_u1-pad10_ net-_u3-pad2_ u3
+a6 net-_u1-pad9_ net-_u2-pad2_ u2
* Schematic Name: d_or, NgSpice Name: d_or
.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: d_or, NgSpice Name: d_or
diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
index 6fa26ea2..85f14960 100644
--- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
+++ b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
@@ -1 +1 @@
-d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_ord_inverterd_inverter/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
+d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_ord_inverterd_inverterC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
--
cgit
From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries
---
src/SubcircuitLibrary/74157/3_and-cache.lib | 61 ---
src/SubcircuitLibrary/74157/3_and.cir | 13 -
src/SubcircuitLibrary/74157/3_and.cir.out | 20 -
src/SubcircuitLibrary/74157/3_and.pro | 58 ---
src/SubcircuitLibrary/74157/3_and.sch | 121 -----
src/SubcircuitLibrary/74157/3_and.sub | 14 -
.../74157/3_and_Previous_Values.xml | 1 -
src/SubcircuitLibrary/74157/74157-cache.lib | 95 ----
src/SubcircuitLibrary/74157/74157-rescue.lib | 22 -
src/SubcircuitLibrary/74157/74157.cir | 25 -
src/SubcircuitLibrary/74157/74157.cir.out | 45 --
src/SubcircuitLibrary/74157/74157.pro | 57 ---
src/SubcircuitLibrary/74157/74157.sch | 549 ---------------------
src/SubcircuitLibrary/74157/74157.sub | 39 --
.../74157/74157_Previous_Values.xml | 1 -
src/SubcircuitLibrary/74157/analysis | 1 -
16 files changed, 1122 deletions(-)
delete mode 100644 src/SubcircuitLibrary/74157/3_and-cache.lib
delete mode 100644 src/SubcircuitLibrary/74157/3_and.cir
delete mode 100644 src/SubcircuitLibrary/74157/3_and.cir.out
delete mode 100644 src/SubcircuitLibrary/74157/3_and.pro
delete mode 100644 src/SubcircuitLibrary/74157/3_and.sch
delete mode 100644 src/SubcircuitLibrary/74157/3_and.sub
delete mode 100644 src/SubcircuitLibrary/74157/3_and_Previous_Values.xml
delete mode 100644 src/SubcircuitLibrary/74157/74157-cache.lib
delete mode 100644 src/SubcircuitLibrary/74157/74157-rescue.lib
delete mode 100644 src/SubcircuitLibrary/74157/74157.cir
delete mode 100644 src/SubcircuitLibrary/74157/74157.cir.out
delete mode 100644 src/SubcircuitLibrary/74157/74157.pro
delete mode 100644 src/SubcircuitLibrary/74157/74157.sch
delete mode 100644 src/SubcircuitLibrary/74157/74157.sub
delete mode 100644 src/SubcircuitLibrary/74157/74157_Previous_Values.xml
delete mode 100644 src/SubcircuitLibrary/74157/analysis
(limited to 'src/SubcircuitLibrary/74157')
diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib
deleted file mode 100644
index af058641..00000000
--- a/src/SubcircuitLibrary/74157/3_and-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir
deleted file mode 100644
index ba296cf0..00000000
--- a/src/SubcircuitLibrary/74157/3_and.cir
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out
deleted file mode 100644
index d7cf79a0..00000000
--- a/src/SubcircuitLibrary/74157/3_and.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro
deleted file mode 100644
index 2c9ac554..00000000
--- a/src/SubcircuitLibrary/74157/3_and.pro
+++ /dev/null
@@ -1,58 +0,0 @@
-update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch
deleted file mode 100644
index 86be0215..00000000
--- a/src/SubcircuitLibrary/74157/3_and.sch
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub
deleted file mode 100644
index 3d9120bb..00000000
--- a/src/SubcircuitLibrary/74157/3_and.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml
deleted file mode 100644
index abc5faaa..00000000
--- a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib
deleted file mode 100644
index de171255..00000000
--- a/src/SubcircuitLibrary/74157/74157-cache.lib
+++ /dev/null
@@ -1,95 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/74157-rescue.lib b/src/SubcircuitLibrary/74157/74157-rescue.lib
deleted file mode 100644
index cac27fc1..00000000
--- a/src/SubcircuitLibrary/74157/74157-rescue.lib
+++ /dev/null
@@ -1,22 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-74157
-#
-DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir
deleted file mode 100644
index 6920161c..00000000
--- a/src/SubcircuitLibrary/74157/74157.cir
+++ /dev/null
@@ -1,25 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or
-U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or
-U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or
-U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or
-U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
-U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
-X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and
-X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and
-X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and
-X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and
-X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and
-X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and
-X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and
-X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and
-
-.end
diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out
deleted file mode 100644
index 3a11a42d..00000000
--- a/src/SubcircuitLibrary/74157/74157.cir.out
+++ /dev/null
@@ -1,45 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
-
-.include 3_and.sub
-* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
-* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
-* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
-* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
-* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
-a5 net-_u1-pad10_ net-_u3-pad2_ u3
-a6 net-_u1-pad9_ net-_u2-pad2_ u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro
deleted file mode 100644
index fcbb1fc8..00000000
--- a/src/SubcircuitLibrary/74157/74157.pro
+++ /dev/null
@@ -1,57 +0,0 @@
-update=03/28/19 22:30:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_User
-LibName24=eSim_Subckt
diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch
deleted file mode 100644
index 7fd3609e..00000000
--- a/src/SubcircuitLibrary/74157/74157.sch
+++ /dev/null
@@ -1,549 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:74157-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Wire Wire Line
- 1650 1850 2750 1850
-Wire Wire Line
- 2750 3350 1650 3350
-Wire Wire Line
- 2750 3050 2750 3350
-Wire Wire Line
- 2800 4050 1650 4050
-Wire Wire Line
- 2800 3550 2800 4050
-Wire Wire Line
- 2200 2150 2200 4350
-Wire Wire Line
- 2200 2150 1650 2150
-Wire Wire Line
- 2150 2900 2150 4850
-Wire Wire Line
- 2150 2900 1650 2900
-Wire Wire Line
- 2100 3600 2100 5300
-Wire Wire Line
- 2100 3600 1650 3600
-Wire Wire Line
- 2050 4300 2050 5800
-Wire Wire Line
- 1650 4300 2050 4300
-Wire Wire Line
- 2200 5500 2200 6250
-$Comp
-L d_or U20
-U 1 1 5C95E06C
-P 6650 3300
-F 0 "U20" H 6650 3300 60 0000 C CNN
-F 1 "d_or" H 6650 3400 60 0000 C CNN
-F 2 "" H 6650 3300 60 0000 C CNN
-F 3 "" H 6650 3300 60 0000 C CNN
- 1 6650 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U21
-U 1 1 5C95E114
-P 6650 3800
-F 0 "U21" H 6650 3800 60 0000 C CNN
-F 1 "d_or" H 6650 3900 60 0000 C CNN
-F 2 "" H 6650 3800 60 0000 C CNN
-F 3 "" H 6650 3800 60 0000 C CNN
- 1 6650 3800
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U22
-U 1 1 5C95E16E
-P 6650 4250
-F 0 "U22" H 6650 4250 60 0000 C CNN
-F 1 "d_or" H 6650 4350 60 0000 C CNN
-F 2 "" H 6650 4250 60 0000 C CNN
-F 3 "" H 6650 4250 60 0000 C CNN
- 1 6650 4250
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U23
-U 1 1 5C95E1C9
-P 6650 4750
-F 0 "U23" H 6650 4750 60 0000 C CNN
-F 1 "d_or" H 6650 4850 60 0000 C CNN
-F 2 "" H 6650 4750 60 0000 C CNN
-F 3 "" H 6650 4750 60 0000 C CNN
- 1 6650 4750
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6200 3200 5950 3200
-Wire Wire Line
- 5950 3200 5950 2000
-Wire Wire Line
- 5950 2000 4750 2000
-Wire Wire Line
- 6200 3700 5850 3700
-Wire Wire Line
- 5850 3700 5850 2500
-Wire Wire Line
- 5850 2500 4750 2500
-Wire Wire Line
- 6200 4150 5750 4150
-Wire Wire Line
- 5750 4150 5750 2950
-Wire Wire Line
- 5750 2950 4750 2950
-Wire Wire Line
- 6200 4650 5650 4650
-Wire Wire Line
- 5650 4650 5650 3450
-Wire Wire Line
- 5650 3450 4750 3450
-Wire Wire Line
- 4750 4250 5450 4250
-Wire Wire Line
- 5450 4250 5450 3300
-Wire Wire Line
- 5450 3300 6200 3300
-Wire Wire Line
- 4750 4750 5550 4750
-Wire Wire Line
- 5550 4750 5550 3800
-Wire Wire Line
- 5550 3800 6200 3800
-Wire Wire Line
- 4700 5200 5600 5200
-Wire Wire Line
- 5600 5200 5600 4250
-Wire Wire Line
- 5600 4250 6200 4250
-Wire Wire Line
- 4750 5700 5700 5700
-Wire Wire Line
- 5700 5700 5700 4750
-Wire Wire Line
- 5700 4750 6200 4750
-Wire Wire Line
- 7100 3250 8300 3250
-Wire Wire Line
- 7100 3750 8300 3750
-Wire Wire Line
- 7100 4200 8300 4200
-Wire Wire Line
- 7100 4700 8250 4700
-$Comp
-L d_inverter U3
-U 1 1 5C95E74D
-P 2750 6250
-F 0 "U3" H 2750 6150 60 0000 C CNN
-F 1 "d_inverter" H 2750 6400 60 0000 C CNN
-F 2 "" H 2800 6200 60 0000 C CNN
-F 3 "" H 2800 6200 60 0000 C CNN
- 1 2750 6250
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 1700 6250 2450 6250
-Connection ~ 2200 6250
-$Comp
-L PORT U1
-U 1 1 5C95E920
-P 1400 1850
-F 0 "U1" H 1450 1950 30 0000 C CNN
-F 1 "PORT" H 1400 1850 30 0000 C CNN
-F 2 "" H 1400 1850 60 0000 C CNN
-F 3 "" H 1400 1850 60 0000 C CNN
- 1 1400 1850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C95E9CF
-P 1400 2150
-F 0 "U1" H 1450 2250 30 0000 C CNN
-F 1 "PORT" H 1400 2150 30 0000 C CNN
-F 2 "" H 1400 2150 60 0000 C CNN
-F 3 "" H 1400 2150 60 0000 C CNN
- 2 1400 2150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C95EA28
-P 1400 2700
-F 0 "U1" H 1450 2800 30 0000 C CNN
-F 1 "PORT" H 1400 2700 30 0000 C CNN
-F 2 "" H 1400 2700 60 0000 C CNN
-F 3 "" H 1400 2700 60 0000 C CNN
- 3 1400 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C95EA9C
-P 1400 2900
-F 0 "U1" H 1450 3000 30 0000 C CNN
-F 1 "PORT" H 1400 2900 30 0000 C CNN
-F 2 "" H 1400 2900 60 0000 C CNN
-F 3 "" H 1400 2900 60 0000 C CNN
- 4 1400 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C95EAFD
-P 1400 3350
-F 0 "U1" H 1450 3450 30 0000 C CNN
-F 1 "PORT" H 1400 3350 30 0000 C CNN
-F 2 "" H 1400 3350 60 0000 C CNN
-F 3 "" H 1400 3350 60 0000 C CNN
- 5 1400 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C95EB63
-P 1400 3600
-F 0 "U1" H 1450 3700 30 0000 C CNN
-F 1 "PORT" H 1400 3600 30 0000 C CNN
-F 2 "" H 1400 3600 60 0000 C CNN
-F 3 "" H 1400 3600 60 0000 C CNN
- 6 1400 3600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C95EBC8
-P 1400 4050
-F 0 "U1" H 1450 4150 30 0000 C CNN
-F 1 "PORT" H 1400 4050 30 0000 C CNN
-F 2 "" H 1400 4050 60 0000 C CNN
-F 3 "" H 1400 4050 60 0000 C CNN
- 7 1400 4050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C95EC38
-P 1400 4300
-F 0 "U1" H 1450 4400 30 0000 C CNN
-F 1 "PORT" H 1400 4300 30 0000 C CNN
-F 2 "" H 1400 4300 60 0000 C CNN
-F 3 "" H 1400 4300 60 0000 C CNN
- 8 1400 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C95ECA1
-P 1450 6250
-F 0 "U1" H 1500 6350 30 0000 C CNN
-F 1 "PORT" H 1450 6250 30 0000 C CNN
-F 2 "" H 1450 6250 60 0000 C CNN
-F 3 "" H 1450 6250 60 0000 C CNN
- 10 1450 6250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C95ED51
-P 1400 6650
-F 0 "U1" H 1450 6750 30 0000 C CNN
-F 1 "PORT" H 1400 6650 30 0000 C CNN
-F 2 "" H 1400 6650 60 0000 C CNN
-F 3 "" H 1400 6650 60 0000 C CNN
- 9 1400 6650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5C95EDCC
-P 8550 3250
-F 0 "U1" H 8600 3350 30 0000 C CNN
-F 1 "PORT" H 8550 3250 30 0000 C CNN
-F 2 "" H 8550 3250 60 0000 C CNN
-F 3 "" H 8550 3250 60 0000 C CNN
- 12 8550 3250
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C95EEA6
-P 8550 3750
-F 0 "U1" H 8600 3850 30 0000 C CNN
-F 1 "PORT" H 8550 3750 30 0000 C CNN
-F 2 "" H 8550 3750 60 0000 C CNN
-F 3 "" H 8550 3750 60 0000 C CNN
- 13 8550 3750
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C95EF2D
-P 8550 4200
-F 0 "U1" H 8600 4300 30 0000 C CNN
-F 1 "PORT" H 8550 4200 30 0000 C CNN
-F 2 "" H 8550 4200 60 0000 C CNN
-F 3 "" H 8550 4200 60 0000 C CNN
- 14 8550 4200
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C95EFB5
-P 8500 4700
-F 0 "U1" H 8550 4800 30 0000 C CNN
-F 1 "PORT" H 8500 4700 30 0000 C CNN
-F 2 "" H 8500 4700 60 0000 C CNN
-F 3 "" H 8500 4700 60 0000 C CNN
- 11 8500 4700
- -1 0 0 1
-$EndComp
-Text Notes 1950 1800 0 60 ~ 12
-A0\n
-Text Notes 1950 2100 0 60 ~ 12
-A1
-Text Notes 1900 2650 0 60 ~ 12
-B0
-Text Notes 1900 2900 0 60 ~ 12
-B1\n
-Text Notes 1900 3350 0 60 ~ 12
-C0\n
-Text Notes 1900 3600 0 60 ~ 12
-C1\n
-Text Notes 1800 4050 0 60 ~ 12
-D0
-Text Notes 1800 4300 0 60 ~ 12
-D1
-Text Notes 1850 6250 0 60 ~ 12
-SEL\n
-Text Notes 1800 6650 0 60 ~ 12
-~EN
-$Comp
-L d_inverter U2
-U 1 1 5C95FD56
-P 2650 6650
-F 0 "U2" H 2650 6550 60 0000 C CNN
-F 1 "d_inverter" H 2650 6800 60 0000 C CNN
-F 2 "" H 2700 6600 60 0000 C CNN
-F 3 "" H 2700 6600 60 0000 C CNN
- 1 2650 6650
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3400 6650 2950 6650
-Wire Wire Line
- 1650 6650 2350 6650
-Text Notes 7850 3200 0 60 ~ 12
-YA
-Text Notes 7850 3700 0 60 ~ 12
-YB
-Text Notes 7850 4200 2 60 ~ 12
-YC
-Text Notes 7800 4700 0 60 ~ 12
-YD
-Wire Wire Line
- 3450 2000 3900 2000
-Wire Wire Line
- 3450 2000 3450 5700
-Wire Wire Line
- 3450 2500 3900 2500
-Wire Wire Line
- 3450 2950 3900 2950
-Connection ~ 3450 2500
-Wire Wire Line
- 3450 3450 3900 3450
-Connection ~ 3450 2950
-Wire Wire Line
- 3450 4250 3900 4250
-Connection ~ 3450 3450
-Wire Wire Line
- 3450 4750 3900 4750
-Connection ~ 3450 4250
-Wire Wire Line
- 3450 5200 3850 5200
-Connection ~ 3450 4750
-Wire Wire Line
- 3400 5700 3900 5700
-Connection ~ 3450 5200
-Wire Wire Line
- 3300 5600 3900 5600
-Wire Wire Line
- 3300 4150 3300 5600
-Wire Wire Line
- 3300 5100 3850 5100
-Wire Wire Line
- 3300 4650 3900 4650
-Connection ~ 3300 5100
-Wire Wire Line
- 3300 4150 3900 4150
-Connection ~ 3300 4650
-Wire Wire Line
- 3250 3350 3900 3350
-Wire Wire Line
- 3250 1900 3250 3350
-Wire Wire Line
- 3250 2850 3900 2850
-Wire Wire Line
- 3250 2400 3900 2400
-Connection ~ 3250 2850
-Wire Wire Line
- 3250 1900 3900 1900
-Connection ~ 3250 2400
-Wire Wire Line
- 3250 3000 3100 3000
-Wire Wire Line
- 3100 3000 3100 6250
-Wire Wire Line
- 3100 6250 3050 6250
-Connection ~ 3250 3000
-Wire Wire Line
- 3300 5500 2200 5500
-Connection ~ 3300 5500
-Wire Wire Line
- 3400 6650 3400 5700
-Connection ~ 3450 5700
-$Comp
-L 3_and X2
-U 1 1 5C9D0110
-P 3450 2400
-F 0 "X2" H 4350 2700 60 0000 C CNN
-F 1 "3_and" H 4400 2900 60 0000 C CNN
-F 2 "" H 3450 2400 60 0000 C CNN
-F 3 "" H 3450 2400 60 0000 C CNN
- 1 3450 2400
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X3
-U 1 1 5C9D01B8
-P 3450 2900
-F 0 "X3" H 4350 3200 60 0000 C CNN
-F 1 "3_and" H 4400 3400 60 0000 C CNN
-F 2 "" H 3450 2900 60 0000 C CNN
-F 3 "" H 3450 2900 60 0000 C CNN
- 1 3450 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X4
-U 1 1 5C9D0222
-P 3450 3350
-F 0 "X4" H 4350 3650 60 0000 C CNN
-F 1 "3_and" H 4400 3850 60 0000 C CNN
-F 2 "" H 3450 3350 60 0000 C CNN
-F 3 "" H 3450 3350 60 0000 C CNN
- 1 3450 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X5
-U 1 1 5C9D0289
-P 3450 3850
-F 0 "X5" H 4350 4150 60 0000 C CNN
-F 1 "3_and" H 4400 4350 60 0000 C CNN
-F 2 "" H 3450 3850 60 0000 C CNN
-F 3 "" H 3450 3850 60 0000 C CNN
- 1 3450 3850
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X6
-U 1 1 5C9D0361
-P 3450 4650
-F 0 "X6" H 4350 4950 60 0000 C CNN
-F 1 "3_and" H 4400 5150 60 0000 C CNN
-F 2 "" H 3450 4650 60 0000 C CNN
-F 3 "" H 3450 4650 60 0000 C CNN
- 1 3450 4650
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X7
-U 1 1 5C9D0367
-P 3450 5150
-F 0 "X7" H 4350 5450 60 0000 C CNN
-F 1 "3_and" H 4400 5650 60 0000 C CNN
-F 2 "" H 3450 5150 60 0000 C CNN
-F 3 "" H 3450 5150 60 0000 C CNN
- 1 3450 5150
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X1
-U 1 1 5C9D036D
-P 3400 5600
-F 0 "X1" H 4300 5900 60 0000 C CNN
-F 1 "3_and" H 4350 6100 60 0000 C CNN
-F 2 "" H 3400 5600 60 0000 C CNN
-F 3 "" H 3400 5600 60 0000 C CNN
- 1 3400 5600
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X8
-U 1 1 5C9D0373
-P 3450 6100
-F 0 "X8" H 4350 6400 60 0000 C CNN
-F 1 "3_and" H 4400 6600 60 0000 C CNN
-F 2 "" H 3450 6100 60 0000 C CNN
-F 3 "" H 3450 6100 60 0000 C CNN
- 1 3450 6100
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3900 2100 2750 2100
-Wire Wire Line
- 2750 2100 2750 1850
-Wire Wire Line
- 3900 2600 1650 2600
-Wire Wire Line
- 1650 2600 1650 2700
-Wire Wire Line
- 3900 3050 2750 3050
-Wire Wire Line
- 3900 3550 2800 3550
-Wire Wire Line
- 2200 4350 3900 4350
-Wire Wire Line
- 2150 4850 3900 4850
-Wire Wire Line
- 2100 5300 3850 5300
-Wire Wire Line
- 2050 5800 3900 5800
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub
deleted file mode 100644
index 545741f5..00000000
--- a/src/SubcircuitLibrary/74157/74157.sub
+++ /dev/null
@@ -1,39 +0,0 @@
-* Subcircuit 74157
-.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
-* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir
-.include 3_and.sub
-* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or
-* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or
-* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or
-* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or
-* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
-* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
-x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and
-x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and
-x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and
-x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and
-x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and
-x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and
-x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and
-x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and
-a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20
-a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21
-a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22
-a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23
-a5 net-_u1-pad10_ net-_u3-pad2_ u3
-a6 net-_u1-pad9_ net-_u2-pad2_ u2
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 74157
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
deleted file mode 100644
index 85f14960..00000000
--- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_ord_inverterd_inverterC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/74157/analysis b/src/SubcircuitLibrary/74157/analysis
deleted file mode 100644
index ebd5c0a9..00000000
--- a/src/SubcircuitLibrary/74157/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit