From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 .../5bit-Ripple_carry_adder-cache.lib              |  61 ----
 .../5bit-Ripple_carry_adder.cir                    |  16 -
 .../5bit-Ripple_carry_adder.cir.out                |  18 -
 .../5bit-Ripple_carry_adder.pro                    |  44 ---
 .../5bit-Ripple_carry_adder.sch                    | 386 ---------------------
 .../5bit-Ripple_carry_adder.sub                    |  12 -
 .../5bit-Ripple_carry_adder_Previous_Values.xml    |   1 -
 .../5bit-Ripple_carry_adder/Full-Adder-cache.lib   | 100 ------
 .../5bit-Ripple_carry_adder/Full-Adder.cir         |  16 -
 .../5bit-Ripple_carry_adder/Full-Adder.cir.out     |  32 --
 .../5bit-Ripple_carry_adder/Full-Adder.pro         |  74 ----
 .../5bit-Ripple_carry_adder/Full-Adder.sch         | 226 ------------
 .../5bit-Ripple_carry_adder/Full-Adder.sub         |  26 --
 .../Full-Adder_Previous_Values.xml                 |   1 -
 .../5bit-Ripple_carry_adder/analysis               |   1 -
 15 files changed, 1014 deletions(-)
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml
 delete mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis

(limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder')

diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib
deleted file mode 100644
index b75ae867..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# Full-Adder
-#
-DEF Full-Adder X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "Full-Adder" 0 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 200 300 -200 0 1 0 N
-X A 1 -500 150 200 R 50 50 1 1 I
-X B 2 -500 0 200 R 50 50 1 1 I
-X Cin 3 -500 -150 200 R 50 50 1 1 I
-X Out 4 500 100 200 L 50 50 1 1 I
-X Cout 5 500 -100 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir
deleted file mode 100644
index 84b7b723..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\5bit-Ripple_carry_adder\5bit-Ripple_carry_adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 02:16:47
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X4  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X4-Pad3_ Net-_U1-Pad4_ ? Full-Adder		
-X5  Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X5-Pad3_ Net-_U1-Pad7_ Net-_X4-Pad3_ Full-Adder		
-X6  Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X6-Pad3_ Net-_U1-Pad10_ Net-_X5-Pad3_ Full-Adder		
-X7  Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_X7-Pad3_ Net-_U1-Pad13_ Net-_X6-Pad3_ Full-Adder		
-X8  Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X7-Pad3_ Full-Adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out
deleted file mode 100644
index dfda0a3b..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro
deleted file mode 100644
index d3bfc6c4..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro
+++ /dev/null
@@ -1,44 +0,0 @@
-update=Sat Jun 22 12:25:13 2019
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../eSim-1.1.2/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=9bit-BoothMultiplier-cache
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch
deleted file mode 100644
index dd2e9165..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch
+++ /dev/null
@@ -1,386 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5bit-Ripple_carry_adder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L Full-Adder X4
-U 1 1 5C93C7FA
-P 3000 3550
-F 0 "X4" H 3000 3550 60  0000 C CNN
-F 1 "Full-Adder" H 3000 3550 60  0000 C CNN
-F 2 "" H 3000 3550 60  0000 C CNN
-F 3 "" H 3000 3550 60  0000 C CNN
-	1    3000 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L Full-Adder X5
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-F 3 "" H 4350 3550 60  0000 C CNN
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-L Full-Adder X6
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-F 2 "" H 5700 3550 60  0000 C CNN
-F 3 "" H 5700 3550 60  0000 C CNN
-	1    5700 3550
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-$EndComp
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-L Full-Adder X7
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-F 3 "" H 7000 3550 60  0000 C CNN
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-$EndComp
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-F 3 "" H 8250 3550 60  0000 C CNN
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-$EndComp
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diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub
deleted file mode 100644
index 675975d9..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit 5bit-Ripple_carry_adder
-.subckt 5bit-Ripple_carry_adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ 
-* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* Control Statements
-
-.ends 5bit-Ripple_carry_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml
deleted file mode 100644
index 8fbbb417..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x8><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x8><x6><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x6><x7><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x7><x4><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x4><x5><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x5></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib
deleted file mode 100644
index cba68b20..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib
+++ /dev/null
@@ -1,100 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  -250 -50  150 -50 N
-P 2 0 1 0  -250 150  150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
deleted file mode 100644
index ea7aed36..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
+++ /dev/null
@@ -1,16 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\Full-Adder\Full-Adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/19 17:15:52
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_xor		
-U5  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_xor		
-U4  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and		
-U6  Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_or		
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
deleted file mode 100644
index 086d8b71..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out
+++ /dev/null
@@ -1,32 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro
deleted file mode 100644
index 7089d69d..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=03/21/19 17:06:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
-LibName12=half-adder
-LibName13=power
-LibName14=device
-LibName15=transistors
-LibName16=conn
-LibName17=linear
-LibName18=regul
-LibName19=74xx
-LibName20=cmos4000
-LibName21=adc-dac
-LibName22=memory
-LibName23=xilinx
-LibName24=microcontrollers
-LibName25=dsp
-LibName26=microchip
-LibName27=analog_switches
-LibName28=motorola
-LibName29=texas
-LibName30=intel
-LibName31=audio
-LibName32=interface
-LibName33=digital-audio
-LibName34=philips
-LibName35=display
-LibName36=cypress
-LibName37=siliconi
-LibName38=opto
-LibName39=atmel
-LibName40=contrib
-LibName41=valves
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch
deleted file mode 100644
index 981e7cdb..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch
+++ /dev/null
@@ -1,226 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:half-adder
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:Full-Adder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L PORT U1
-U 1 1 5C93775D
-P 4100 2800
-F 0 "U1" H 4150 2900 30  0000 C CNN
-F 1 "PORT" H 4100 2800 30  0000 C CNN
-F 2 "" H 4100 2800 60  0000 C CNN
-F 3 "" H 4100 2800 60  0000 C CNN
-	1    4100 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9377A8
-P 4100 3100
-F 0 "U1" H 4150 3200 30  0000 C CNN
-F 1 "PORT" H 4100 3100 30  0000 C CNN
-F 2 "" H 4100 3100 60  0000 C CNN
-F 3 "" H 4100 3100 60  0000 C CNN
-	2    4100 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9377CD
-P 4100 3400
-F 0 "U1" H 4150 3500 30  0000 C CNN
-F 1 "PORT" H 4100 3400 30  0000 C CNN
-F 2 "" H 4100 3400 60  0000 C CNN
-F 3 "" H 4100 3400 60  0000 C CNN
-	3    4100 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9377F2
-P 8450 2900
-F 0 "U1" H 8500 3000 30  0000 C CNN
-F 1 "PORT" H 8450 2900 30  0000 C CNN
-F 2 "" H 8450 2900 60  0000 C CNN
-F 3 "" H 8450 2900 60  0000 C CNN
-	4    8450 2900
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C937851
-P 8450 3200
-F 0 "U1" H 8500 3300 30  0000 C CNN
-F 1 "PORT" H 8450 3200 30  0000 C CNN
-F 2 "" H 8450 3200 60  0000 C CNN
-F 3 "" H 8450 3200 60  0000 C CNN
-	5    8450 3200
-	-1   0    0    1   
-$EndComp
-$Comp
-L d_xor U2
-U 1 1 5C93788C
-P 5150 2900
-F 0 "U2" H 5150 2900 60  0000 C CNN
-F 1 "d_xor" H 5200 3000 47  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5C9378DF
-P 6400 2950
-F 0 "U5" H 6400 2950 60  0000 C CNN
-F 1 "d_xor" H 6450 3050 47  0000 C CNN
-F 2 "" H 6400 2950 60  0000 C CNN
-F 3 "" H 6400 2950 60  0000 C CNN
-	1    6400 2950
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C937928
-P 6150 3300
-F 0 "U4" H 6150 3300 60  0000 C CNN
-F 1 "d_and" H 6200 3400 60  0000 C CNN
-F 2 "" H 6150 3300 60  0000 C CNN
-F 3 "" H 6150 3300 60  0000 C CNN
-	1    6150 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9379CF
-P 5200 3500
-F 0 "U3" H 5200 3500 60  0000 C CNN
-F 1 "d_and" H 5250 3600 60  0000 C CNN
-F 2 "" H 5200 3500 60  0000 C CNN
-F 3 "" H 5200 3500 60  0000 C CNN
-	1    5200 3500
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5C937A14
-P 7250 3550
-F 0 "U6" H 7250 3550 60  0000 C CNN
-F 1 "d_or" H 7250 3650 60  0000 C CNN
-F 2 "" H 7250 3550 60  0000 C CNN
-F 3 "" H 7250 3550 60  0000 C CNN
-	1    7250 3550
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4350 2800 4700 2800
-Wire Wire Line
-	4350 3100 4700 3100
-Wire Wire Line
-	4700 3100 4700 2900
-Wire Wire Line
-	5600 2850 5950 2850
-Wire Wire Line
-	4350 3400 4400 3400
-Wire Wire Line
-	4400 3400 4400 3150
-Wire Wire Line
-	4400 3150 5450 3150
-Wire Wire Line
-	5450 3150 5450 2950
-Wire Wire Line
-	5450 2950 5950 2950
-Wire Wire Line
-	6850 2900 8200 2900
-Wire Wire Line
-	4450 2800 4450 3400
-Wire Wire Line
-	4450 3400 4750 3400
-Connection ~ 4450 2800
-Wire Wire Line
-	4600 3100 4600 3500
-Wire Wire Line
-	4600 3500 4750 3500
-Connection ~ 4600 3100
-Wire Wire Line
-	5650 3450 6800 3450
-Wire Wire Line
-	4400 3300 5700 3300
-Connection ~ 4400 3300
-Wire Wire Line
-	5700 3200 5700 2850
-Connection ~ 5700 2850
-Wire Wire Line
-	6600 3250 6650 3250
-Wire Wire Line
-	6650 3250 6650 3550
-Wire Wire Line
-	6650 3550 6800 3550
-Wire Wire Line
-	7700 3500 7700 3200
-Wire Wire Line
-	7700 3200 8200 3200
-Text Notes 4400 2750 0    60   ~ 0
-A
-Text Notes 4400 3050 0    60   ~ 0
-B
-Text Notes 4350 3500 0    60   ~ 0
-Cin
-Text Notes 7950 2850 0    60   ~ 0
-Sum
-Text Notes 7950 3150 0    60   ~ 0
-Cout
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub
deleted file mode 100644
index 0ea4496d..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub
+++ /dev/null
@@ -1,26 +0,0 @@
-* Subcircuit Full-Adder
-.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4  net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6  net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends Full-Adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml
deleted file mode 100644
index c7136641..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_xor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis
deleted file mode 100644
index 52ccc5ec..00000000
--- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.ac lin 0 0Hz 0Hz
\ No newline at end of file
-- 
cgit