From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001
From: nilshah98
Date: Tue, 2 Jul 2019 16:42:20 +0530
Subject: Subcircuit added by ECE fellows 2019

---
 .../5bit-Ripple_carry_adder/Full-Adder.cir               | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir

(limited to 'src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir')

diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
new file mode 100644
index 00000000..ea7aed36
--- /dev/null
+++ b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir
@@ -0,0 +1,16 @@
+* C:\esim\eSim\src\SubcircuitLibrary\Full-Adder\Full-Adder.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/19 17:15:52
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_xor		
+U5  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_xor		
+U4  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
+U3  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and		
+U6  Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_or		
+
+.end
-- 
cgit