From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001 From: nilshah98 Date: Tue, 2 Jul 2019 16:42:20 +0530 Subject: Subcircuit added by ECE fellows 2019 --- src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib | 61 ++ src/SubcircuitLibrary/4_bit_FA/3_and.cir | 13 + src/SubcircuitLibrary/4_bit_FA/3_and.cir.out | 20 + src/SubcircuitLibrary/4_bit_FA/3_and.pro | 58 ++ src/SubcircuitLibrary/4_bit_FA/3_and.sch | 121 +++ src/SubcircuitLibrary/4_bit_FA/3_and.sub | 14 + .../4_bit_FA/3_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib | 63 ++ src/SubcircuitLibrary/4_bit_FA/4_OR.cir | 14 + src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out | 24 + src/SubcircuitLibrary/4_bit_FA/4_OR.pro | 45 + src/SubcircuitLibrary/4_bit_FA/4_OR.sch | 150 ++++ src/SubcircuitLibrary/4_bit_FA/4_OR.sub | 18 + .../4_bit_FA/4_OR_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib | 79 ++ src/SubcircuitLibrary/4_bit_FA/4_and.cir | 13 + src/SubcircuitLibrary/4_bit_FA/4_and.cir.out | 18 + src/SubcircuitLibrary/4_bit_FA/4_and.pro | 57 ++ src/SubcircuitLibrary/4_bit_FA/4_and.sch | 139 +++ src/SubcircuitLibrary/4_bit_FA/4_and.sub | 12 + .../4_bit_FA/4_and_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib | 172 ++++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir | 48 ++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out | 151 ++++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro | 58 ++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch | 945 +++++++++++++++++++++ src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub | 145 ++++ .../4_bit_FA/4_bit_FA_Previous_Values.xml | 1 + src/SubcircuitLibrary/4_bit_FA/analysis | 1 + 29 files changed, 2443 insertions(+) create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and.cir create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and.cir.out create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and.pro create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and.sch create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and.sub create mode 100644 src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.cir create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.pro create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.sch create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.sub create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and.cir create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and.cir.out create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and.pro create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and.sch create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and.sub create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub create mode 100644 src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml create mode 100644 src/SubcircuitLibrary/4_bit_FA/analysis (limited to 'src/SubcircuitLibrary/4_bit_FA') diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir b/src/SubcircuitLibrary/4_bit_FA/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.pro b/src/SubcircuitLibrary/4_bit_FA/3_and.pro new file mode 100644 index 00000000..1b535492 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sch b/src/SubcircuitLibrary/4_bit_FA/3_and.sch new file mode 100644 index 00000000..6c8d3d4a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sub b/src/SubcircuitLibrary/4_bit_FA/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir new file mode 100644 index 00000000..7adbf177 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out new file mode 100644 index 00000000..4388b975 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro new file mode 100644 index 00000000..8bd4bbf5 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch new file mode 100644 index 00000000..2f28896c --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecd_ord_ord_or \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib new file mode 100644 index 00000000..4cf915be --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir b/src/SubcircuitLibrary/4_bit_FA/4_and.cir new file mode 100644 index 00000000..25e839cd --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.pro b/src/SubcircuitLibrary/4_bit_FA/4_and.pro new file mode 100644 index 00000000..cc0f1b93 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sch b/src/SubcircuitLibrary/4_bit_FA/4_and.sch new file mode 100644 index 00000000..bcc3cecf --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sub b/src/SubcircuitLibrary/4_bit_FA/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib new file mode 100644 index 00000000..f787854a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib @@ -0,0 +1,172 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir new file mode 100644 index 00000000..8fe97f7e --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir @@ -0,0 +1,48 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_bit_FA\4_bit_FA.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:04:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U16-Pad2_ d_or +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U24-Pad2_ d_and +U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U17-Pad2_ d_or +U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U26-Pad2_ d_and +U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U18-Pad2_ d_or +U7 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad2_ d_and +U8 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or +U9 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U31-Pad2_ d_and +U16 Net-_U1-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U24 Net-_U16-Pad3_ Net-_U24-Pad2_ Net-_U17-Pad1_ d_or +U33 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U33-Pad3_ d_or +U23 Net-_U16-Pad2_ Net-_U23-Pad2_ d_inverter +U38 Net-_U1-Pad1_ Net-_U33-Pad3_ Net-_U38-Pad3_ d_xor +U42 Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U26 Net-_U17-Pad3_ Net-_U26-Pad2_ Net-_U18-Pad1_ d_or +U34 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U34-Pad3_ d_or +U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter +U39 Net-_U17-Pad1_ Net-_U34-Pad3_ Net-_U39-Pad3_ d_xor +U44 Net-_U39-Pad3_ Net-_U1-Pad10_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U28 Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_or +U35 Net-_U27-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad3_ d_or +U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_inverter +U40 Net-_U18-Pad1_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_xor +U45 Net-_U40-Pad3_ Net-_U1-Pad11_ d_inverter +U31 Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or +U21 Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter +U37 Net-_U28-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_xor +U43 Net-_U37-Pad3_ Net-_U1-Pad12_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U32 Net-_U1-Pad1_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and +U41 Net-_U32-Pad3_ Net-_U41-Pad2_ Net-_U1-Pad14_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X1 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U32-Pad2_ 4_and +X4 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_X3-Pad3_ 3_and +X2 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U24-Pad2_ Net-_X2-Pad5_ 4_and +X3 Net-_U31-Pad2_ Net-_U10-Pad3_ Net-_X3-Pad3_ Net-_X2-Pad5_ Net-_U41-Pad2_ 4_OR + +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out new file mode 100644 index 00000000..4d05d64a --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out @@ -0,0 +1,151 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir + +.include 4_and.sub +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or +* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and +* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or +* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and +* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or +* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or +* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter +* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or +* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or +* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter +* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor +* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or +* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or +* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter +* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor +* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter +* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor +* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and +x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and +x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and +x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5 +a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6 +a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7 +a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8 +a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9 +a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24 +a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33 +a12 net-_u16-pad2_ net-_u23-pad2_ u23 +a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38 +a14 net-_u38-pad3_ net-_u1-pad13_ u42 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26 +a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34 +a18 net-_u17-pad2_ net-_u25-pad2_ u25 +a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39 +a20 net-_u39-pad3_ net-_u1-pad10_ u44 +a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35 +a24 net-_u18-pad2_ net-_u27-pad2_ u27 +a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a26 net-_u40-pad3_ net-_u1-pad11_ u45 +a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad1_ net-_u21-pad2_ u21 +a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a30 net-_u37-pad3_ net-_u1-pad12_ u43 +a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro new file mode 100644 index 00000000..2d0c38b5 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro @@ -0,0 +1,58 @@ +update=03/28/19 23:02:17 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch new file mode 100644 index 00000000..d3507ac7 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch @@ -0,0 +1,945 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid 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10750 3450 30 0000 C CNN +F 1 "PORT" H 10700 3350 30 0000 C CNN +F 2 "" H 10700 3350 60 0000 C CNN +F 3 "" H 10700 3350 60 0000 C CNN + 13 10700 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C96A464 +P 10650 4300 +F 0 "U1" H 10700 4400 30 0000 C CNN +F 1 "PORT" H 10650 4300 30 0000 C CNN +F 2 "" H 10650 4300 60 0000 C CNN +F 3 "" H 10650 4300 60 0000 C CNN + 10 10650 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C96A53A +P 10650 5100 +F 0 "U1" H 10700 5200 30 0000 C CNN +F 1 "PORT" H 10650 5100 30 0000 C CNN +F 2 "" H 10650 5100 60 0000 C CNN +F 3 "" H 10650 5100 60 0000 C CNN + 11 10650 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C96A619 +P 10650 6100 +F 0 "U1" H 10700 6200 30 0000 C CNN +F 1 "PORT" H 10650 6100 30 0000 C CNN +F 2 "" H 10650 6100 60 0000 C CNN +F 3 "" H 10650 6100 60 0000 C CNN + 12 10650 6100 + -1 0 0 1 +$EndComp +Text Notes 10200 3350 0 60 ~ 12 +S0 +Text Notes 10200 4300 0 60 ~ 12 +S1\n +Text Notes 10200 5100 0 60 ~ 12 +S2 +Text Notes 10150 6100 0 60 ~ 12 +S3 +Text Notes 10050 1450 0 60 ~ 12 +Cout\n +Text Notes 2250 750 0 60 ~ 12 +Cin\n +Text Notes 2050 2950 0 60 ~ 12 +A0\n +Text Notes 2050 3450 0 60 ~ 12 +B0\n +Text Notes 2050 3900 0 60 ~ 12 +A1 +Text Notes 2050 4400 0 60 ~ 12 +B1 +Text Notes 2050 4750 0 60 ~ 12 +A2 +Text Notes 2050 5250 0 60 ~ 12 +B2 +Text Notes 2100 5700 0 60 ~ 12 +A3 +Text Notes 2150 6200 0 60 ~ 12 +B3 +$Comp +L 4_and X1 +U 1 1 5C9D037C +P 4400 2250 +F 0 "X1" H 5900 3300 60 0000 C CNN +F 1 "4_and" H 5950 3450 60 0000 C CNN +F 2 "" H 4400 2250 60 0000 C CNN +F 3 "" H 4400 2250 60 0000 C CNN + 1 4400 2250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 5C9D0A45 +P 5500 2400 +F 0 "X4" H 6400 2700 60 0000 C CNN +F 1 "3_and" H 6450 2900 60 0000 C CNN +F 2 "" H 5500 2400 60 0000 C CNN +F 3 "" H 5500 2400 60 0000 C CNN + 1 5500 2400 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 5C9D0E20 +P 4400 3450 +F 0 "X2" H 5900 4500 60 0000 C CNN +F 1 "4_and" H 5950 4650 60 0000 C CNN +F 2 "" H 4400 3450 60 0000 C CNN +F 3 "" H 4400 3450 60 0000 C CNN + 1 4400 3450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 5C9D1513 +P 4450 4900 +F 0 "X3" H 8350 7950 60 0000 C CNN +F 1 "4_OR" H 8350 8150 60 0000 C CNN +F 2 "" H 4450 4900 60 0000 C CNN +F 3 "" H 4450 4900 60 0000 C CNN + 1 4450 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 1750 8750 1750 +Wire Wire Line + 7150 1500 7850 1500 +Wire Wire Line + 7850 1500 7850 1600 +Wire Wire Line + 7550 1600 7550 1700 +Wire Wire Line + 7550 1700 7850 1700 +Wire Wire Line + 6800 2000 6800 1800 +Wire Wire Line + 6800 1800 7850 1800 +Wire Wire Line + 6350 2350 7850 2350 +Wire Wire Line + 7850 2350 7850 1900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub new file mode 100644 index 00000000..2f2bc4ef --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub @@ -0,0 +1,145 @@ +* Subcircuit 4_bit_FA +.subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir +.include 4_and.sub +.include 3_and.sub +.include 4_OR.sub +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and +* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or +* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and +* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or +* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and +* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or +* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and +* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or +* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or +* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter +* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor +* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or +* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or +* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter +* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor +* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or +* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or +* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter +* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor +* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter +* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or +* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor +* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and +* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or +x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and +x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and +x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and +x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3 +a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5 +a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6 +a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7 +a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8 +a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9 +a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24 +a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33 +a12 net-_u16-pad2_ net-_u23-pad2_ u23 +a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38 +a14 net-_u38-pad3_ net-_u1-pad13_ u42 +a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26 +a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34 +a18 net-_u17-pad2_ net-_u25-pad2_ u25 +a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39 +a20 net-_u39-pad3_ net-_u1-pad10_ u44 +a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35 +a24 net-_u18-pad2_ net-_u27-pad2_ u27 +a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a26 net-_u40-pad3_ net-_u1-pad11_ u45 +a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad1_ net-_u21-pad2_ u21 +a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a30 net-_u37-pad3_ net-_u1-pad12_ u43 +a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_bit_FA \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml new file mode 100644 index 00000000..49a53e5c --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_andd_ord_andd_ord_andd_ord_andd_andd_ord_ord_inverterd_xord_inverterd_andd_ord_ord_inverterd_xord_inverterd_andd_ord_ord_inverterd_xord_inverterd_ord_inverterd_xord_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_ord_andd_orC:\Users\malli\eSim\src\SubcircuitLibrary\4_andC:\Users\malli\eSim\src\SubcircuitLibrary\4_ORC:\Users\malli\eSim\src\SubcircuitLibrary\4_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/analysis b/src/SubcircuitLibrary/4_bit_FA/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_bit_FA/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit