From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 src/SubcircuitLibrary/4_bit_FA/4_OR.sub | 18 ------------------
 1 file changed, 18 deletions(-)
 delete mode 100644 src/SubcircuitLibrary/4_bit_FA/4_OR.sub

(limited to 'src/SubcircuitLibrary/4_bit_FA/4_OR.sub')

diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
deleted file mode 100644
index 53fc8b33..00000000
--- a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_OR
\ No newline at end of file
-- 
cgit