From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 15:16:35 +0530
Subject: common code for Win and Linux, merged py2 changes

---
 src/SubcircuitLibrary/4_and/4_and.cir.out | 36 +++++++++++++++----------------
 1 file changed, 18 insertions(+), 18 deletions(-)

(limited to 'src/SubcircuitLibrary/4_and/4_and.cir.out')

diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out
index 6e35b18a..f40e5bc6 100644
--- a/src/SubcircuitLibrary/4_and/4_and.cir.out
+++ b/src/SubcircuitLibrary/4_and/4_and.cir.out
@@ -1,18 +1,18 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit