From b085a3df519debbc99acf4ded7e118a1690d6665 Mon Sep 17 00:00:00 2001
From: nilshah98
Date: Tue, 2 Jul 2019 16:42:20 +0530
Subject: Subcircuit added by ECE fellows 2019

---
 src/SubcircuitLibrary/4025/4025.sub | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 src/SubcircuitLibrary/4025/4025.sub

(limited to 'src/SubcircuitLibrary/4025/4025.sub')

diff --git a/src/SubcircuitLibrary/4025/4025.sub b/src/SubcircuitLibrary/4025/4025.sub
new file mode 100644
index 00000000..867617fd
--- /dev/null
+++ b/src/SubcircuitLibrary/4025/4025.sub
@@ -0,0 +1,30 @@
+* Subcircuit 4025
+.subckt 4025 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6  net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
+* u4  net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
+* u7  net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u5  net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
+a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
+a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
+a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
+a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4025
\ No newline at end of file
-- 
cgit