From cb55e59de7ee4383c04edfae7c39ad9ae9552b36 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 14 Feb 2020 15:16:35 +0530
Subject: common code for Win and Linux, merged py2 changes

---
 src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib | 154 +++----
 src/SubcircuitLibrary/2bitmul/2bitmul.cir       |  34 +-
 src/SubcircuitLibrary/2bitmul/2bitmul.cir.out   |  62 +--
 src/SubcircuitLibrary/2bitmul/2bitmul.pro       | 148 +++---
 src/SubcircuitLibrary/2bitmul/2bitmul.sch       | 568 ++++++++++++------------
 src/SubcircuitLibrary/2bitmul/2bitmul.sub       |  48 +-
 6 files changed, 507 insertions(+), 507 deletions(-)

(limited to 'src/SubcircuitLibrary/2bitmul')

diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
index 9d70ade9..e16831e4 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
@@ -1,77 +1,77 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
index 08e3ccc8..0f4deb6c 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
@@ -1,17 +1,17 @@
-* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
-U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
-U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
-X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
-X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
+U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
+U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
+U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
+X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
+X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
index 351629fd..71766bd8 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
@@ -1,31 +1,31 @@
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
+
+.include half_adder.sub
+* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
+x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
+x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
index 944ec056..eafbfb80 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
@@ -1,74 +1,74 @@
-update=03/07/19 09:55:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
+update=03/07/19 09:55:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+LibName39=eSim_PSpice
+LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
+
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
index 2629beec..0ba61912 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
@@ -1,284 +1,284 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:2bitmul-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-Comp ""
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-Comment4 ""
-$EndDescr
-$Comp
-L d_and U5
-U 1 1 5C7FC048
-P 8150 2950
-F 0 "U5" H 8150 2950 60  0000 C CNN
-F 1 "d_and" H 8200 3050 60  0000 C CNN
-F 2 "" H 8150 2950 60  0000 C CNN
-F 3 "" H 8150 2950 60  0000 C CNN
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-	1    6950 2950
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-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C7FC11D
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-F 1 "d_and" H 6450 3050 60  0000 C CNN
-F 2 "" H 6400 2950 60  0000 C CNN
-F 3 "" H 6400 2950 60  0000 C CNN
-	1    6400 2950
-	0    1    1    0   
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-	6500 2450 6500 2500
-$Comp
-L half_adder X2
-U 1 1 5C7FC23A
-P 7200 3350
-F 0 "X2" H 8100 3850 60  0000 C CNN
-F 1 "half_adder" H 8100 3750 60  0000 C CNN
-F 2 "" H 7200 3350 60  0000 C CNN
-F 3 "" H 7200 3350 60  0000 C CNN
-	1    7200 3350
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+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:2bitmul-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+Date ""
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+Comp ""
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+F 3 "" H 7200 3350 60  0000 C CNN
+	1    7200 3350
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+$EndComp
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+F 3 "" H 6050 3350 60  0000 C CNN
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+F 3 "" H 8200 5300 60  0000 C CNN
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+F 3 "" H 7300 5300 60  0000 C CNN
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+F 3 "" H 6750 5150 60  0000 C CNN
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+L PORT U1
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+F 3 "" H 6150 5250 60  0000 C CNN
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+F 2 "" H 8250 850 60  0000 C CNN
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+	1    8250 850 
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+$EndComp
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+F 3 "" H 7550 850 60  0000 C CNN
+	3    7550 850 
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+$EndComp
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+$Comp
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+	4    7200 800 
+	0    1    1    0   
+$EndComp
+Wire Wire Line
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diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
index ce0d022d..e77495a6 100644
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub
+++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
@@ -1,25 +1,25 @@
-* Subcircuit 2bitmul
-.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 2bitmul
+.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
+* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
+.include half_adder.sub
+* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
+* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
+* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
+* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
+x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
+x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
+a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
 .ends 2bitmul
\ No newline at end of file
-- 
cgit 


From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib    |  77 ------
 src/SubcircuitLibrary/2bitmul/2bitmul.cir          |  17 --
 src/SubcircuitLibrary/2bitmul/2bitmul.cir.out      |  31 ---
 src/SubcircuitLibrary/2bitmul/2bitmul.pro          |  74 ------
 src/SubcircuitLibrary/2bitmul/2bitmul.sch          | 284 ---------------------
 src/SubcircuitLibrary/2bitmul/2bitmul.sub          |  25 --
 .../2bitmul/2bitmul_Previous_Values.xml            |   1 -
 src/SubcircuitLibrary/2bitmul/analysis             |   1 -
 src/SubcircuitLibrary/2bitmul/half_adder-cache.lib |  63 -----
 src/SubcircuitLibrary/2bitmul/half_adder.cir       |  11 -
 src/SubcircuitLibrary/2bitmul/half_adder.cir.out   |  20 --
 src/SubcircuitLibrary/2bitmul/half_adder.pro       |  69 -----
 src/SubcircuitLibrary/2bitmul/half_adder.sch       | 152 -----------
 src/SubcircuitLibrary/2bitmul/half_adder.sub       |  14 -
 .../2bitmul/half_adder_Previous_Values.xml         |   1 -
 15 files changed, 840 deletions(-)
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul.cir
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul.pro
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul.sch
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul.sub
 delete mode 100644 src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml
 delete mode 100644 src/SubcircuitLibrary/2bitmul/analysis
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder-cache.lib
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder.cir
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder.cir.out
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder.pro
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder.sch
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder.sub
 delete mode 100644 src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml

(limited to 'src/SubcircuitLibrary/2bitmul')

diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
deleted file mode 100644
index e16831e4..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib
+++ /dev/null
@@ -1,77 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir
deleted file mode 100644
index 0f4deb6c..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U5  Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and		
-U4  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and		
-U3  Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and		
-U2  Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and		
-X2  Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder		
-X1  Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
deleted file mode 100644
index 71766bd8..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out
+++ /dev/null
@@ -1,31 +0,0 @@
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro
deleted file mode 100644
index eafbfb80..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=03/07/19 09:55:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
-[eeschema/libraries]
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-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch
deleted file mode 100644
index 0ba61912..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch
+++ /dev/null
@@ -1,284 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:2bitmul-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-$EndDescr
-$Comp
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-U 1 1 5C7FC048
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-F 3 "" H 7450 2950 60  0000 C CNN
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-$EndComp
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-L d_and U3
-U 1 1 5C7FC0F4
-P 6950 2950
-F 0 "U3" H 6950 2950 60  0000 C CNN
-F 1 "d_and" H 7000 3050 60  0000 C CNN
-F 2 "" H 6950 2950 60  0000 C CNN
-F 3 "" H 6950 2950 60  0000 C CNN
-	1    6950 2950
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-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C7FC11D
-P 6400 2950
-F 0 "U2" H 6400 2950 60  0000 C CNN
-F 1 "d_and" H 6450 3050 60  0000 C CNN
-F 2 "" H 6400 2950 60  0000 C CNN
-F 3 "" H 6400 2950 60  0000 C CNN
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-$EndComp
-Wire Wire Line
-	8150 2500 8150 2350
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-Wire Wire Line
-	7550 2150 7550 2500
-Wire Wire Line
-	7550 2450 6500 2450
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-	6500 2450 6500 2500
-$Comp
-L half_adder X2
-U 1 1 5C7FC23A
-P 7200 3350
-F 0 "X2" H 8100 3850 60  0000 C CNN
-F 1 "half_adder" H 8100 3750 60  0000 C CNN
-F 2 "" H 7200 3350 60  0000 C CNN
-F 3 "" H 7200 3350 60  0000 C CNN
-	1    7200 3350
-	0    1    1    0   
-$EndComp
-$Comp
-L half_adder X1
-U 1 1 5C7FC324
-P 6050 3350
-F 0 "X1" H 6950 3850 60  0000 C CNN
-F 1 "half_adder" H 6950 3750 60  0000 C CNN
-F 2 "" H 6050 3350 60  0000 C CNN
-F 3 "" H 6050 3350 60  0000 C CNN
-	1    6050 3350
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-$EndComp
-Wire Wire Line
-	7500 3400 7900 3400
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-	7000 3400 7300 3400
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-	7300 3400 7300 3650
-Wire Wire Line
-	7300 4800 7050 4800
-Wire Wire Line
-	7050 4800 7050 3600
-Wire Wire Line
-	7050 3600 6750 3600
-Wire Wire Line
-	6750 3600 6750 3650
-Wire Wire Line
-	6450 3400 6450 3650
-Wire Wire Line
-	6450 3650 6150 3650
-$Comp
-L PORT U1
-U 5 1 5C7FC4F8
-P 8200 5300
-F 0 "U1" H 8250 5400 30  0000 C CNN
-F 1 "PORT" H 8200 5300 30  0000 C CNN
-F 2 "" H 8200 5300 60  0000 C CNN
-F 3 "" H 8200 5300 60  0000 C CNN
-	5    8200 5300
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C7FC5D7
-P 7300 5300
-F 0 "U1" H 7350 5400 30  0000 C CNN
-F 1 "PORT" H 7300 5300 30  0000 C CNN
-F 2 "" H 7300 5300 60  0000 C CNN
-F 3 "" H 7300 5300 60  0000 C CNN
-	6    7300 5300
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C7FC641
-P 6750 5150
-F 0 "U1" H 6800 5250 30  0000 C CNN
-F 1 "PORT" H 6750 5150 30  0000 C CNN
-F 2 "" H 6750 5150 60  0000 C CNN
-F 3 "" H 6750 5150 60  0000 C CNN
-	7    6750 5150
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C7FC698
-P 6150 5250
-F 0 "U1" H 6200 5350 30  0000 C CNN
-F 1 "PORT" H 6150 5250 30  0000 C CNN
-F 2 "" H 6150 5250 60  0000 C CNN
-F 3 "" H 6150 5250 60  0000 C CNN
-	8    6150 5250
-	0    -1   -1   0   
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C7FC6EC
-P 8250 850
-F 0 "U1" H 8300 950 30  0000 C CNN
-F 1 "PORT" H 8250 850 30  0000 C CNN
-F 2 "" H 8250 850 60  0000 C CNN
-F 3 "" H 8250 850 60  0000 C CNN
-	1    8250 850 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C7FC815
-P 7900 850
-F 0 "U1" H 7950 950 30  0000 C CNN
-F 1 "PORT" H 7900 850 30  0000 C CNN
-F 2 "" H 7900 850 60  0000 C CNN
-F 3 "" H 7900 850 60  0000 C CNN
-	2    7900 850 
-	0    1    1    0   
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C7FC857
-P 7550 850
-F 0 "U1" H 7600 950 30  0000 C CNN
-F 1 "PORT" H 7550 850 30  0000 C CNN
-F 2 "" H 7550 850 60  0000 C CNN
-F 3 "" H 7550 850 60  0000 C CNN
-	3    7550 850 
-	0    1    1    0   
-$EndComp
-Connection ~ 8250 2250
-Wire Wire Line
-	7900 1100 7900 2150
-Wire Wire Line
-	7900 2150 7550 2150
-Connection ~ 7550 2450
-Wire Wire Line
-	7550 1100 7550 2100
-Wire Wire Line
-	7550 2100 7450 2100
-Connection ~ 7450 2350
-Wire Wire Line
-	7200 1050 7200 2100
-Wire Wire Line
-	7200 2100 6800 2100
-Wire Wire Line
-	6800 2100 6800 2350
-Connection ~ 6800 2350
-Wire Wire Line
-	8200 3400 8200 5050
-$Comp
-L PORT U1
-U 4 1 5C7FC898
-P 7200 800
-F 0 "U1" H 7250 900 30  0000 C CNN
-F 1 "PORT" H 7200 800 30  0000 C CNN
-F 2 "" H 7200 800 60  0000 C CNN
-F 3 "" H 7200 800 60  0000 C CNN
-	4    7200 800 
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	7300 5050 7300 4850
-Wire Wire Line
-	7300 4850 7900 4850
-Wire Wire Line
-	7900 4850 7900 4800
-Wire Wire Line
-	6750 4800 6750 4900
-Wire Wire Line
-	6150 4800 6150 5000
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub
deleted file mode 100644
index e77495a6..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub
+++ /dev/null
@@ -1,25 +0,0 @@
-* Subcircuit 2bitmul
-.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ 
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-.include half_adder.sub
-* u5  net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3  net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2  net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 2bitmul
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml
deleted file mode 100644
index 8a55af97..00000000
--- a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/analysis b/src/SubcircuitLibrary/2bitmul/analysis
deleted file mode 100644
index 660a46cc..00000000
--- a/src/SubcircuitLibrary/2bitmul/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib
deleted file mode 100644
index 68785220..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib
+++ /dev/null
@@ -1,63 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0  150 -50  -200 -50 N
-P 2 0 1 0  150 150  -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.cir
+++ /dev/null
@@ -1,11 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2  1 4 3 d_xor		
-U3  1 4 2 d_and		
-U1  1 4 3 2 PORT		
-
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.pro b/src/SubcircuitLibrary/2bitmul/half_adder.pro
deleted file mode 100644
index 695ae0f6..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 11:27:22 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sch b/src/SubcircuitLibrary/2bitmul/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.sch
+++ /dev/null
@@ -1,152 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U2
-U 1 1 558A946A
-P 5650 3050
-F 0 "U2" H 5650 3050 60  0000 C CNN
-F 1 "d_xor" H 5700 3150 47  0000 C CNN
-F 2 "" H 5650 3050 60  0000 C CNN
-F 3 "" H 5650 3050 60  0000 C CNN
-	1    5650 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 558A94D5
-P 5700 3800
-F 0 "U3" H 5700 3800 60  0000 C CNN
-F 1 "d_and" H 5750 3900 60  0000 C CNN
-F 2 "" H 5700 3800 60  0000 C CNN
-F 3 "" H 5700 3800 60  0000 C CNN
-	1    5700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558A94F6
-P 4150 3000
-F 0 "U1" H 4200 3100 30  0000 C CNN
-F 1 "PORT" H 4150 3000 30  0000 C CNN
-F 2 "" H 4150 3000 60  0000 C CNN
-F 3 "" H 4150 3000 60  0000 C CNN
-	1    4150 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558A9543
-P 4150 3450
-F 0 "U1" H 4200 3550 30  0000 C CNN
-F 1 "PORT" H 4150 3450 30  0000 C CNN
-F 2 "" H 4150 3450 60  0000 C CNN
-F 3 "" H 4150 3450 60  0000 C CNN
-	2    4150 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558A9573
-P 6650 3000
-F 0 "U1" H 6700 3100 30  0000 C CNN
-F 1 "PORT" H 6650 3000 30  0000 C CNN
-F 2 "" H 6650 3000 60  0000 C CNN
-F 3 "" H 6650 3000 60  0000 C CNN
-	3    6650 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558A9606
-P 6700 3750
-F 0 "U1" H 6750 3850 30  0000 C CNN
-F 1 "PORT" H 6700 3750 30  0000 C CNN
-F 2 "" H 6700 3750 60  0000 C CNN
-F 3 "" H 6700 3750 60  0000 C CNN
-	4    6700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5200 2950 4450 2950
-Wire Wire Line
-	4450 2950 4450 3000
-Wire Wire Line
-	4450 3000 4400 3000
-Wire Wire Line
-	4400 3450 4550 3450
-Wire Wire Line
-	4550 3450 4550 3050
-Wire Wire Line
-	4550 3050 5200 3050
-Wire Wire Line
-	5250 3700 5000 3700
-Wire Wire Line
-	5000 3700 5000 2950
-Connection ~ 5000 2950
-Wire Wire Line
-	5250 3800 4850 3800
-Wire Wire Line
-	4850 3800 4850 3050
-Connection ~ 4850 3050
-Wire Wire Line
-	6100 3000 6400 3000
-Wire Wire Line
-	6150 3750 6450 3750
-Text Notes 4550 2950 0    60   ~ 0
-IN1\n\n
-Text Notes 4600 3150 0    60   ~ 0
-IN2
-Text Notes 6200 2950 0    60   ~ 0
-SUM\n
-Text Notes 6200 3650 0    60   ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml
deleted file mode 100644
index b915f0da..00000000
--- a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
-- 
cgit