From fe3bd934634bb2dae1cadf35e7c6d59facbedf66 Mon Sep 17 00:00:00 2001
From: fossee
Date: Thu, 29 Aug 2019 12:03:11 +0530
Subject: adding files

---
 nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl

(limited to 'nghdl/Example/nghdl_half_adder')

diff --git a/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl b/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl
new file mode 100644
index 00000000..f9f2e929
--- /dev/null
+++ b/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity nghdl_ha is
+port (
+    	i_bit1  : in std_logic_vector(0 downto 0);
+	    i_bit2  : in std_logic_vector(0 downto 0);
+    	o_sum   : out std_logic_vector(0 downto 0);
+    	o_carry : out std_logic_vector(0 downto 0)
+    );
+end nghdl_ha;
+ 
+
+architecture rtl of nghdl_ha is
+
+begin
+ 
+  o_sum   <= i_bit1 xor i_bit2;
+  o_carry <= i_bit1 and i_bit2;
+
+end rtl;
\ No newline at end of file
-- 
cgit