From 07209ef9b945fe546b8c4fd7195b6762fb50ba41 Mon Sep 17 00:00:00 2001 From: Sumanto Kar Date: Tue, 21 Jun 2022 19:41:51 +0530 Subject: Update eSim_Sources.lib --- library/kicadLibrary/kicad_eSim-Library/eSim_Sources.lib | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'library') diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Sources.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Sources.lib index af2014ee..c1c62410 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Sources.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Sources.lib @@ -3,9 +3,9 @@ EESchema-LIBRARY Version 2.3 # # AC # -DEF eSim_AC v 0 40 Y Y 1 F N +DEF AC v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN -F1 "eSim_AC" -200 -50 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST -- cgit From b973e4d4ebc094e45d13d02d2c587f6db2553bdb Mon Sep 17 00:00:00 2001 From: dilipboidya Date: Fri, 29 Jul 2022 15:43:39 +0530 Subject: Added the Device models --- library/deviceModelLibrary/Diode/1N4148.lib | 0 library/deviceModelLibrary/Diode/1N4148.xml | 1 + library/deviceModelLibrary/Diode/DRB168MM200.lib | 2 ++ library/deviceModelLibrary/Diode/DRB168MM200.xml | 1 + library/deviceModelLibrary/Diode/DRN142S.lib | 3 +++ library/deviceModelLibrary/Diode/DRN142S.xml | 1 + library/deviceModelLibrary/MOS/MOSFET_2N7002.lib | 6 ++++++ library/deviceModelLibrary/MOS/MOSFET_2N7002.xml | 1 + library/deviceModelLibrary/User Libraries/GD_diode.lib | 1 + library/deviceModelLibrary/User Libraries/GD_diode.xml | 1 + library/deviceModelLibrary/User Libraries/GD_nfet.lib | 1 + library/deviceModelLibrary/User Libraries/GD_nfet.xml | 1 + library/deviceModelLibrary/User Libraries/GD_pfet.lib | 1 + library/deviceModelLibrary/User Libraries/GD_pfet.xml | 1 + library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib | 3 +++ library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml | 1 + library/deviceModelLibrary/User Libraries/eSim_RedLED.lib | 1 + library/deviceModelLibrary/User Libraries/eSim_RedLED.xml | 1 + library/deviceModelLibrary/User Libraries/switch1.lib | 3 +++ library/deviceModelLibrary/User Libraries/switch1.xml | 1 + library/deviceModelLibrary/User Libraries/ymod.lib | 1 + library/deviceModelLibrary/User Libraries/ymod.xml | 1 + 22 files changed, 33 insertions(+) create mode 100644 library/deviceModelLibrary/Diode/1N4148.lib create mode 100644 library/deviceModelLibrary/Diode/1N4148.xml create mode 100644 library/deviceModelLibrary/Diode/DRB168MM200.lib create mode 100644 library/deviceModelLibrary/Diode/DRB168MM200.xml create mode 100644 library/deviceModelLibrary/Diode/DRN142S.lib create mode 100644 library/deviceModelLibrary/Diode/DRN142S.xml create mode 100644 library/deviceModelLibrary/MOS/MOSFET_2N7002.lib create mode 100644 library/deviceModelLibrary/MOS/MOSFET_2N7002.xml create mode 100644 library/deviceModelLibrary/User Libraries/GD_diode.lib create mode 100644 library/deviceModelLibrary/User Libraries/GD_diode.xml create mode 100644 library/deviceModelLibrary/User Libraries/GD_nfet.lib create mode 100644 library/deviceModelLibrary/User Libraries/GD_nfet.xml create mode 100644 library/deviceModelLibrary/User Libraries/GD_pfet.lib create mode 100644 library/deviceModelLibrary/User Libraries/GD_pfet.xml create mode 100644 library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib create mode 100644 library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml create mode 100644 library/deviceModelLibrary/User Libraries/eSim_RedLED.lib create mode 100644 library/deviceModelLibrary/User Libraries/eSim_RedLED.xml create mode 100644 library/deviceModelLibrary/User Libraries/switch1.lib create mode 100644 library/deviceModelLibrary/User Libraries/switch1.xml create mode 100644 library/deviceModelLibrary/User Libraries/ymod.lib create mode 100644 library/deviceModelLibrary/User Libraries/ymod.xml (limited to 'library') diff --git a/library/deviceModelLibrary/Diode/1N4148.lib b/library/deviceModelLibrary/Diode/1N4148.lib new file mode 100644 index 00000000..e69de29b diff --git a/library/deviceModelLibrary/Diode/1N4148.xml b/library/deviceModelLibrary/Diode/1N4148.xml new file mode 100644 index 00000000..7c2a6799 --- /dev/null +++ b/library/deviceModelLibrary/Diode/1N4148.xml @@ -0,0 +1 @@ +D1N41485.4320E-91.97012.12338.01541.9768E-12.19.990075.2571025.949E-9 \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/DRB168MM200.lib b/library/deviceModelLibrary/Diode/DRB168MM200.lib new file mode 100644 index 00000000..5801102c --- /dev/null +++ b/library/deviceModelLibrary/Diode/DRB168MM200.lib @@ -0,0 +1,2 @@ +* Model Generated by ROHM +.MODEL DRB168MM200 D( IS=5.6001E-9 N=1.0413 RS=90.681E-3 IKF=2.9636E-3 XTI=2.0 EG=0.74 CJO=86.088E-12 M=0.4523 VJ=0.5 ISR=9.8101E-9 NR=1.3311 BV=200 TRS1=-3.7501E-3 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/DRB168MM200.xml b/library/deviceModelLibrary/Diode/DRB168MM200.xml new file mode 100644 index 00000000..3973f48f --- /dev/null +++ b/library/deviceModelLibrary/Diode/DRB168MM200.xml @@ -0,0 +1 @@ +DDRB168MM2005.6001E-91.041390.681E-32.9636E-32.00.7486.088E-120.45230.59.8101E-91.3311200-3.7501E-3 \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/DRN142S.lib b/library/deviceModelLibrary/Diode/DRN142S.lib new file mode 100644 index 00000000..25e7b6b2 --- /dev/null +++ b/library/deviceModelLibrary/Diode/DRN142S.lib @@ -0,0 +1,3 @@ +* DRN142S Diode model +* Date: 2008/12/24 +.MODEL DRN142S D( IS=127.76E-12 N=1.7346 RS=.1581 IKF=.14089 CJO=385.59E-15 M=.11823 VJ=.78827 ISR=139.38E-12 NR=3 BV=60 TT=275.00E-9 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/DRN142S.xml b/library/deviceModelLibrary/Diode/DRN142S.xml new file mode 100644 index 00000000..648e2440 --- /dev/null +++ b/library/deviceModelLibrary/Diode/DRN142S.xml @@ -0,0 +1 @@ +DDRN142S127.76E-121.7346.1581.14089385.59E-15.11823.78827139.38E-12360275.00E-9 \ No newline at end of file diff --git a/library/deviceModelLibrary/MOS/MOSFET_2N7002.lib b/library/deviceModelLibrary/MOS/MOSFET_2N7002.lib new file mode 100644 index 00000000..43600d05 --- /dev/null +++ b/library/deviceModelLibrary/MOS/MOSFET_2N7002.lib @@ -0,0 +1,6 @@ +* 115mA, 60V, N-channel Enhancement Mode MOSFET +.MODEL 2N7002 NMOS( LEVEL=1 VTO=1.50 KP=78.1m GAMMA=1.86 ++ PHI=.75 LAMBDA=97.2u RD=0.280 RS=0.280 ++ IS=140f PB=0.800 MJ=0.460 CBD=9.88p ++ CBS=11.9p CGSO=60.0n CGDO=50.0n CGBO=190n ) + diff --git a/library/deviceModelLibrary/MOS/MOSFET_2N7002.xml b/library/deviceModelLibrary/MOS/MOSFET_2N7002.xml new file mode 100644 index 00000000..dca33a4e --- /dev/null +++ b/library/deviceModelLibrary/MOS/MOSFET_2N7002.xml @@ -0,0 +1 @@ +NMOS2N700211.5078.1m1.86.7597.2u0.2800.280140f0.8000.4609.88p11.9p60.0n50.0n190n \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_diode.lib b/library/deviceModelLibrary/User Libraries/GD_diode.lib new file mode 100644 index 00000000..2e728e04 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_diode.lib @@ -0,0 +1 @@ +.model GD_diode D( rs=6 n=6 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_diode.xml b/library/deviceModelLibrary/User Libraries/GD_diode.xml new file mode 100644 index 00000000..9965d289 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_diode.xml @@ -0,0 +1 @@ +DGD_diode66 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_nfet.lib b/library/deviceModelLibrary/User Libraries/GD_nfet.lib new file mode 100644 index 00000000..0dafefd6 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_nfet.lib @@ -0,0 +1 @@ +.model GD_nfet njf( vto=-4 beta=0.07 cgs=0.05 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_nfet.xml b/library/deviceModelLibrary/User Libraries/GD_nfet.xml new file mode 100644 index 00000000..ae5413d4 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_nfet.xml @@ -0,0 +1 @@ +njfGD_nfet-40.070.05 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_pfet.lib b/library/deviceModelLibrary/User Libraries/GD_pfet.lib new file mode 100644 index 00000000..cf314100 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_pfet.lib @@ -0,0 +1 @@ +.model GD_pfet pjf( vto=-4 beta=0.07 cgs=0.05 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/GD_pfet.xml b/library/deviceModelLibrary/User Libraries/GD_pfet.xml new file mode 100644 index 00000000..8fc6456f --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/GD_pfet.xml @@ -0,0 +1 @@ +pjfGD_pfet-40.070.05 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib new file mode 100644 index 00000000..66bee13b --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib @@ -0,0 +1,3 @@ +.MODEL eSim_BlueLED D( Is=1e-10 Rs=0.1 N=6.68 tt=4e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Cp=0.0e-12 Isr=0.0 Nr=2.0 Temp=26.85 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 Ttt1=0.0 Ttt2=0.0 Tm1=0.0 Tm2=0.0 Tnom=26.85 Area=1.0 ) + + diff --git a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml new file mode 100644 index 00000000..65f54494 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml @@ -0,0 +1 @@ +DeSim_BlueLED1e-100.16.684e-63e-120.50.7510e-60.50.0e-120.02.026.850.01.01.03.01.110.00.00.00.00.00.026.851.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib b/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib new file mode 100644 index 00000000..1f852936 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib @@ -0,0 +1 @@ +.MODEL eSim_RedLED D( Is=1e-10 Rs=0.1 N=4.09 tt=4.0e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Isr=0.0 Nr=2.0 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 ) diff --git a/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml b/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml new file mode 100644 index 00000000..a8df3640 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml @@ -0,0 +1 @@ +DeSim_RedLED1e-100.14.094.0e-63e-120.50.7510e-60.50.02.00.01.01.03.01.110.00.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/switch1.lib b/library/deviceModelLibrary/User Libraries/switch1.lib new file mode 100644 index 00000000..3736c67f --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/switch1.lib @@ -0,0 +1,3 @@ +*****************Creation of lib file for switch**************************** + +.model switch1 sw( vt=0.05 vh=1 ron=1 roff=1e12 ) diff --git a/library/deviceModelLibrary/User Libraries/switch1.xml b/library/deviceModelLibrary/User Libraries/switch1.xml new file mode 100644 index 00000000..c38fe559 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/switch1.xml @@ -0,0 +1 @@ +swswitch10.05111e12 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/ymod.lib b/library/deviceModelLibrary/User Libraries/ymod.lib new file mode 100644 index 00000000..12ed776f --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/ymod.lib @@ -0,0 +1 @@ +.MODEL ymod txl( R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 ) diff --git a/library/deviceModelLibrary/User Libraries/ymod.xml b/library/deviceModelLibrary/User Libraries/ymod.xml new file mode 100644 index 00000000..0c9a1863 --- /dev/null +++ b/library/deviceModelLibrary/User Libraries/ymod.xml @@ -0,0 +1 @@ +txlymod12.458.972e-900.468e-1216 \ No newline at end of file -- cgit From 7f6a5a325b23e6818acb89d2b147387b4b441d63 Mon Sep 17 00:00:00 2001 From: dilipboidya Date: Thu, 11 Aug 2022 17:21:27 +0530 Subject: Added the Device Models --- library/deviceModelLibrary/Diode/DRN142S.lib | 3 - library/deviceModelLibrary/Diode/DRN142S.xml | 1 - .../deviceModelLibrary/Diode/RF Diode/DRN142S.lib | 3 + .../deviceModelLibrary/Diode/RF Diode/DRN142S.xml | 1 + library/deviceModelLibrary/LEDs/eSim_BlueLED.lib | 3 + library/deviceModelLibrary/LEDs/eSim_BlueLED.xml | 1 + library/deviceModelLibrary/LEDs/eSim_RedLED.lib | 1 + library/deviceModelLibrary/LEDs/eSim_RedLED.xml | 1 + library/deviceModelLibrary/Switch/switch1.lib | 3 + library/deviceModelLibrary/Switch/switch1.xml | 1 + .../deviceModelLibrary/Transmission Lines/ymod.lib | 1 + .../deviceModelLibrary/Transmission Lines/ymod.xml | 1 + .../User Libraries/eSim_BlueLED.lib | 3 - .../User Libraries/eSim_BlueLED.xml | 1 - .../User Libraries/eSim_RedLED.lib | 1 - .../User Libraries/eSim_RedLED.xml | 1 - .../deviceModelLibrary/User Libraries/switch1.lib | 3 - .../deviceModelLibrary/User Libraries/switch1.xml | 1 - library/deviceModelLibrary/User Libraries/ymod.lib | 1 - library/deviceModelLibrary/User Libraries/ymod.xml | 1 - .../kicad_eSim-Library/eSim_Subckt.lib | 679 --------------------- 21 files changed, 16 insertions(+), 695 deletions(-) delete mode 100644 library/deviceModelLibrary/Diode/DRN142S.lib delete mode 100644 library/deviceModelLibrary/Diode/DRN142S.xml create mode 100644 library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib create mode 100644 library/deviceModelLibrary/Diode/RF Diode/DRN142S.xml create mode 100644 library/deviceModelLibrary/LEDs/eSim_BlueLED.lib create mode 100644 library/deviceModelLibrary/LEDs/eSim_BlueLED.xml create mode 100644 library/deviceModelLibrary/LEDs/eSim_RedLED.lib create mode 100644 library/deviceModelLibrary/LEDs/eSim_RedLED.xml create mode 100644 library/deviceModelLibrary/Switch/switch1.lib create mode 100644 library/deviceModelLibrary/Switch/switch1.xml create mode 100644 library/deviceModelLibrary/Transmission Lines/ymod.lib create mode 100644 library/deviceModelLibrary/Transmission Lines/ymod.xml delete mode 100644 library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib delete mode 100644 library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml delete mode 100644 library/deviceModelLibrary/User Libraries/eSim_RedLED.lib delete mode 100644 library/deviceModelLibrary/User Libraries/eSim_RedLED.xml delete mode 100644 library/deviceModelLibrary/User Libraries/switch1.lib delete mode 100644 library/deviceModelLibrary/User Libraries/switch1.xml delete mode 100644 library/deviceModelLibrary/User Libraries/ymod.lib delete mode 100644 library/deviceModelLibrary/User Libraries/ymod.xml delete mode 100644 library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib (limited to 'library') diff --git a/library/deviceModelLibrary/Diode/DRN142S.lib b/library/deviceModelLibrary/Diode/DRN142S.lib deleted file mode 100644 index 25e7b6b2..00000000 --- a/library/deviceModelLibrary/Diode/DRN142S.lib +++ /dev/null @@ -1,3 +0,0 @@ -* DRN142S Diode model -* Date: 2008/12/24 -.MODEL DRN142S D( IS=127.76E-12 N=1.7346 RS=.1581 IKF=.14089 CJO=385.59E-15 M=.11823 VJ=.78827 ISR=139.38E-12 NR=3 BV=60 TT=275.00E-9 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/DRN142S.xml b/library/deviceModelLibrary/Diode/DRN142S.xml deleted file mode 100644 index 648e2440..00000000 --- a/library/deviceModelLibrary/Diode/DRN142S.xml +++ /dev/null @@ -1 +0,0 @@ -DDRN142S127.76E-121.7346.1581.14089385.59E-15.11823.78827139.38E-12360275.00E-9 \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib new file mode 100644 index 00000000..25e7b6b2 --- /dev/null +++ b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib @@ -0,0 +1,3 @@ +* DRN142S Diode model +* Date: 2008/12/24 +.MODEL DRN142S D( IS=127.76E-12 N=1.7346 RS=.1581 IKF=.14089 CJO=385.59E-15 M=.11823 VJ=.78827 ISR=139.38E-12 NR=3 BV=60 TT=275.00E-9 ) \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/RF Diode/DRN142S.xml b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.xml new file mode 100644 index 00000000..648e2440 --- /dev/null +++ b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.xml @@ -0,0 +1 @@ +DDRN142S127.76E-121.7346.1581.14089385.59E-15.11823.78827139.38E-12360275.00E-9 \ No newline at end of file diff --git a/library/deviceModelLibrary/LEDs/eSim_BlueLED.lib b/library/deviceModelLibrary/LEDs/eSim_BlueLED.lib new file mode 100644 index 00000000..66bee13b --- /dev/null +++ b/library/deviceModelLibrary/LEDs/eSim_BlueLED.lib @@ -0,0 +1,3 @@ +.MODEL eSim_BlueLED D( Is=1e-10 Rs=0.1 N=6.68 tt=4e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Cp=0.0e-12 Isr=0.0 Nr=2.0 Temp=26.85 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 Ttt1=0.0 Ttt2=0.0 Tm1=0.0 Tm2=0.0 Tnom=26.85 Area=1.0 ) + + diff --git a/library/deviceModelLibrary/LEDs/eSim_BlueLED.xml b/library/deviceModelLibrary/LEDs/eSim_BlueLED.xml new file mode 100644 index 00000000..65f54494 --- /dev/null +++ b/library/deviceModelLibrary/LEDs/eSim_BlueLED.xml @@ -0,0 +1 @@ +DeSim_BlueLED1e-100.16.684e-63e-120.50.7510e-60.50.0e-120.02.026.850.01.01.03.01.110.00.00.00.00.00.026.851.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/LEDs/eSim_RedLED.lib b/library/deviceModelLibrary/LEDs/eSim_RedLED.lib new file mode 100644 index 00000000..1f852936 --- /dev/null +++ b/library/deviceModelLibrary/LEDs/eSim_RedLED.lib @@ -0,0 +1 @@ +.MODEL eSim_RedLED D( Is=1e-10 Rs=0.1 N=4.09 tt=4.0e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Isr=0.0 Nr=2.0 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 ) diff --git a/library/deviceModelLibrary/LEDs/eSim_RedLED.xml b/library/deviceModelLibrary/LEDs/eSim_RedLED.xml new file mode 100644 index 00000000..a8df3640 --- /dev/null +++ b/library/deviceModelLibrary/LEDs/eSim_RedLED.xml @@ -0,0 +1 @@ +DeSim_RedLED1e-100.14.094.0e-63e-120.50.7510e-60.50.02.00.01.01.03.01.110.00.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/Switch/switch1.lib b/library/deviceModelLibrary/Switch/switch1.lib new file mode 100644 index 00000000..3736c67f --- /dev/null +++ b/library/deviceModelLibrary/Switch/switch1.lib @@ -0,0 +1,3 @@ +*****************Creation of lib file for switch**************************** + +.model switch1 sw( vt=0.05 vh=1 ron=1 roff=1e12 ) diff --git a/library/deviceModelLibrary/Switch/switch1.xml b/library/deviceModelLibrary/Switch/switch1.xml new file mode 100644 index 00000000..c38fe559 --- /dev/null +++ b/library/deviceModelLibrary/Switch/switch1.xml @@ -0,0 +1 @@ +swswitch10.05111e12 \ No newline at end of file diff --git a/library/deviceModelLibrary/Transmission Lines/ymod.lib b/library/deviceModelLibrary/Transmission Lines/ymod.lib new file mode 100644 index 00000000..12ed776f --- /dev/null +++ b/library/deviceModelLibrary/Transmission Lines/ymod.lib @@ -0,0 +1 @@ +.MODEL ymod txl( R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 ) diff --git a/library/deviceModelLibrary/Transmission Lines/ymod.xml b/library/deviceModelLibrary/Transmission Lines/ymod.xml new file mode 100644 index 00000000..0c9a1863 --- /dev/null +++ b/library/deviceModelLibrary/Transmission Lines/ymod.xml @@ -0,0 +1 @@ +txlymod12.458.972e-900.468e-1216 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib deleted file mode 100644 index 66bee13b..00000000 --- a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.lib +++ /dev/null @@ -1,3 +0,0 @@ -.MODEL eSim_BlueLED D( Is=1e-10 Rs=0.1 N=6.68 tt=4e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Cp=0.0e-12 Isr=0.0 Nr=2.0 Temp=26.85 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 Ttt1=0.0 Ttt2=0.0 Tm1=0.0 Tm2=0.0 Tnom=26.85 Area=1.0 ) - - diff --git a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml b/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml deleted file mode 100644 index 65f54494..00000000 --- a/library/deviceModelLibrary/User Libraries/eSim_BlueLED.xml +++ /dev/null @@ -1 +0,0 @@ -DeSim_BlueLED1e-100.16.684e-63e-120.50.7510e-60.50.0e-120.02.026.850.01.01.03.01.110.00.00.00.00.00.026.851.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib b/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib deleted file mode 100644 index 1f852936..00000000 --- a/library/deviceModelLibrary/User Libraries/eSim_RedLED.lib +++ /dev/null @@ -1 +0,0 @@ -.MODEL eSim_RedLED D( Is=1e-10 Rs=0.1 N=4.09 tt=4.0e-6 Cjo=3e-12 M=0.5 Vj=0.7 Bv=5 Ibv=10e-6 Fc=0.5 Isr=0.0 Nr=2.0 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 ) diff --git a/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml b/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml deleted file mode 100644 index a8df3640..00000000 --- a/library/deviceModelLibrary/User Libraries/eSim_RedLED.xml +++ /dev/null @@ -1 +0,0 @@ -DeSim_RedLED1e-100.14.094.0e-63e-120.50.7510e-60.50.02.00.01.01.03.01.110.00.0 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/switch1.lib b/library/deviceModelLibrary/User Libraries/switch1.lib deleted file mode 100644 index 3736c67f..00000000 --- a/library/deviceModelLibrary/User Libraries/switch1.lib +++ /dev/null @@ -1,3 +0,0 @@ -*****************Creation of lib file for switch**************************** - -.model switch1 sw( vt=0.05 vh=1 ron=1 roff=1e12 ) diff --git a/library/deviceModelLibrary/User Libraries/switch1.xml b/library/deviceModelLibrary/User Libraries/switch1.xml deleted file mode 100644 index c38fe559..00000000 --- a/library/deviceModelLibrary/User Libraries/switch1.xml +++ /dev/null @@ -1 +0,0 @@ -swswitch10.05111e12 \ No newline at end of file diff --git a/library/deviceModelLibrary/User Libraries/ymod.lib b/library/deviceModelLibrary/User Libraries/ymod.lib deleted file mode 100644 index 12ed776f..00000000 --- a/library/deviceModelLibrary/User Libraries/ymod.lib +++ /dev/null @@ -1 +0,0 @@ -.MODEL ymod txl( R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 ) diff --git a/library/deviceModelLibrary/User Libraries/ymod.xml b/library/deviceModelLibrary/User Libraries/ymod.xml deleted file mode 100644 index 0c9a1863..00000000 --- a/library/deviceModelLibrary/User Libraries/ymod.xml +++ /dev/null @@ -1 +0,0 @@ -txlymod12.458.972e-900.468e-1216 \ No newline at end of file diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib deleted file mode 100644 index ce0c8f05..00000000 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ /dev/null @@ -1,679 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 10bitDAC -# -DEF 10bitDAC X 0 40 Y Y 1 F N -F0 "X" 0 50 60 H V C CNN -F1 "10bitDAC" -50 -50 60 H V C CNN -F2 "" 0 50 60 H I C CNN -F3 "" 0 50 60 H I C CNN -DRAW -S -500 500 400 -600 0 1 0 N -X D0 1 -700 -500 200 R 50 50 1 1 I -X D1 2 -700 -400 200 R 50 50 1 1 I -X D2 3 -700 -300 200 R 50 50 1 1 I -X D3 4 -700 -200 200 R 50 50 1 1 I -X D4 5 -700 -100 200 R 50 50 1 1 I -X D5 6 -700 0 200 R 50 50 1 1 I -X D6 7 -700 100 200 R 50 50 1 1 I -X D7 8 -700 200 200 R 50 50 1 1 I -X D8 9 -700 300 200 R 50 50 1 1 I -X D9 10 -700 400 200 R 50 50 1 1 I -X AnalogOut 11 600 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# Clock_pulse_generator -# -DEF Clock_pulse_generator X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Clock_pulse_generator" 0 -100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 200 600 -300 0 1 0 N -X Vdd 1 -750 100 200 R 50 50 1 1 I -X R 2 -750 -50 200 R 50 50 1 1 I -X C 3 -750 -200 200 R 50 50 1 1 I -X Clkout 4 800 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 2BITMUL -# -DEF 2BITMUL X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "2BITMUL" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A0 1 -500 300 200 R 50 50 1 1 I -X A1 2 -500 150 200 R 50 50 1 1 I -X B0 3 -500 -50 200 R 50 50 1 1 I -X B1 4 -500 -250 200 R 50 50 1 1 I -X M0 5 500 250 200 L 50 50 1 1 O -X M1 6 500 100 200 L 50 50 1 1 O -X M2 7 500 -50 200 L 50 50 1 1 O -X M3 8 500 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_OR -# -DEF 4_OR X 0 40 Y Y 1 F N -F0 "X" 150 -100 60 H V C CNN -F1 "4_OR" 150 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 -A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 -A -30 -99 393 627 146 0 1 0 N 150 250 350 0 -P 2 0 1 0 -200 -250 150 -250 N -P 2 0 1 0 -200 250 150 250 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X in4 4 -350 -150 200 R 50 50 1 1 I -X out 5 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "4_and" 100 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 -P 2 0 1 0 -200 200 150 200 N -P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N -X in1 1 -400 150 200 R 50 50 1 1 I -X in2 2 -400 50 200 R 50 50 1 1 I -X in3 3 -400 -50 200 R 50 50 1 1 I -X in4 4 -400 -150 200 R 50 50 1 1 I -X out 5 500 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 556 -# -DEF 556 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "556" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 250 -550 0 1 0 N -X dis1 1 -500 150 200 R 50 50 1 1 I -X thr1 2 -500 -150 200 R 50 50 1 1 I -X cv1 3 -150 -750 200 U 50 50 1 1 I -X rst1 4 -200 600 200 D 50 50 1 1 I -X out1 5 -500 0 200 R 50 50 1 1 O -X trig1 6 -500 -300 200 R 50 50 1 1 I -X gnd 7 0 -750 200 U 50 50 1 1 I -X trig2 8 450 -300 200 L 50 50 1 1 I -X out2 9 450 0 200 L 50 50 1 1 O -X rst2 10 100 600 200 D 50 50 1 1 I -X cv2 11 150 -750 200 U 50 50 1 1 I -X thr2 12 450 -150 200 L 50 50 1 1 I -X dis2 13 450 150 200 L 50 50 1 1 I -X vcc 14 -50 600 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_4002 -# -DEF IC_4002 X 0 40 Y Y 1 F N -F0 "X" 0 150 60 H V C CNN -F1 "IC_4002" 0 0 60 H V C CNN -F2 "" 50 -150 60 H V C CNN -F3 "" 50 -150 60 H V C CNN -DRAW -S -250 350 250 -400 0 1 0 N -X 1Y 1 -450 250 200 R 50 50 1 1 O -X 1A 2 -450 150 200 R 50 50 1 1 I -X 1B 3 -450 50 200 R 50 50 1 1 I -X 1C 4 -450 -50 200 R 50 50 1 1 I -X 1D 5 -450 -150 200 R 50 50 1 1 I -X NC 6 -450 -250 200 R 50 50 1 1 I -X GND 7 -450 -350 200 R 50 50 1 1 I -X NC 8 450 -350 200 L 50 50 1 1 I -X 2A 9 450 -250 200 L 50 50 1 1 I -X 2B 10 450 -150 200 L 50 50 1 1 I -X 2C 11 450 -50 200 L 50 50 1 1 I -X 2D 12 450 50 200 L 50 50 1 1 I -X 2Y 13 450 150 200 L 50 50 1 1 O -X VCC 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# CMOS_NAND -# -DEF CMOS_NAND X 0 40 Y Y 1 F N -F0 "X" -100 -150 60 H V C CNN -F1 "CMOS_NAND" 0 -50 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 -C 550 0 50 0 1 0 N -P 2 0 1 0 -350 300 300 300 N -P 3 0 1 0 -350 300 -350 -400 300 -400 N -X in1 1 -550 250 200 R 50 50 1 1 I -X in2 2 -550 -300 200 R 50 50 1 1 I -X out 3 800 0 279 L 79 79 1 1 I -ENDDRAW -ENDDEF -# -# IC_4012 -# -DEF IC_4012 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4012" 0 200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 350 -400 0 1 0 N -X Q1 1 -500 300 200 R 50 50 1 1 O -X A1 2 -500 200 200 R 50 50 1 1 I -X B1 3 -500 100 200 R 50 50 1 1 I -X C1 4 -500 0 200 R 50 50 1 1 I -X D1 5 -500 -100 200 R 50 50 1 1 I -X NC 6 -500 -200 200 R 50 50 1 1 N -X VSS 7 -500 -300 200 R 50 50 1 1 I -X NC 8 550 -300 200 L 50 50 1 1 N -X A2 9 550 -200 200 L 50 50 1 1 I -X B2 10 550 -100 200 L 50 50 1 1 I -X C2 11 550 0 200 L 50 50 1 1 I -X D2 12 550 100 200 L 50 50 1 1 I -X Q2 13 550 200 200 L 50 50 1 1 O -X VDD 14 550 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4017 -# -DEF IC_4017 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4017" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -350 850 400 -850 0 1 0 N -X 1 1 600 650 200 L 50 50 1 1 O -X 2 2 600 500 200 L 50 50 1 1 O -X 3 3 600 350 200 L 50 50 1 1 O -X 4 4 600 200 200 L 50 50 1 1 O -X 5 5 600 50 200 L 50 50 1 1 O -X 6 6 600 -100 200 L 50 50 1 1 O -X 7 7 600 -250 200 L 50 50 1 1 O -X 8 8 600 -400 200 L 50 50 1 1 O -X 9 9 600 -600 200 L 50 50 1 1 O -X 10 10 600 -750 200 L 50 50 1 1 O -X RST 11 -550 -400 200 R 50 50 1 1 I -X CLK 12 -550 350 200 R 50 50 1 1 I -ENDDRAW -ENDDEF -# -# eSim_74LS04 -# -DEF eSim_74LS04 X 0 40 Y Y 1 F N -F0 "X" 0 100 60 H V C CNN -F1 "eSim_74LS04" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S 350 500 -350 -500 0 1 0 N -X ~ 1 -550 450 200 R 50 50 1 1 P -X ~ 2 -550 300 200 R 50 50 1 1 P I -X ~ 3 -550 150 200 R 50 50 1 1 P -X ~ 4 -550 0 200 R 50 50 1 1 P I -X ~ 5 -550 -150 200 R 50 50 1 1 P -X ~ 6 -550 -300 200 R 50 50 1 1 P I -X GND 7 -550 -450 200 R 50 50 1 1 P -X ~ 8 550 -450 200 L 50 50 1 1 P I -X ~ 9 550 -300 200 L 50 50 1 1 P -X ~ 10 550 -150 200 L 50 50 1 1 P I -X ~ 11 550 0 200 L 50 50 1 1 P -X ~ 12 550 150 200 L 50 50 1 1 P I -X ~ 13 550 300 200 L 50 50 1 1 P -X VCC 14 550 450 200 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# IC_4023 -# -DEF IC_4023 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4023" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X C3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X A3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4028 -# -DEF IC_4028 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4028" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X Q4 1 -500 350 200 R 50 50 1 1 O -X Q2 2 -500 250 200 R 50 50 1 1 O -X Q0 3 -500 150 200 R 50 50 1 1 O -X Q7 4 -500 50 200 R 50 50 1 1 O -X Q9 5 -500 -50 200 R 50 50 1 1 O -X Q5 6 -500 -150 200 R 50 50 1 1 O -X Q6 7 -500 -250 200 R 50 50 1 1 O -X Vss 8 -500 -350 200 R 50 50 1 1 I -X Q8 9 500 -350 200 L 50 50 1 1 O -X A0 10 500 -250 200 L 50 50 1 1 I -X A3 11 500 -150 200 L 50 50 1 1 I -X A2 12 500 -50 200 L 50 50 1 1 I -X A1 13 500 50 200 L 50 50 1 1 I -X Q1 14 500 150 200 L 50 50 1 1 O -X Q3 15 500 250 200 L 50 50 1 1 O -X Vdd 16 500 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_4073 -# -DEF IC_4073 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4073" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X A3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X C3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_74153 -# -DEF IC_74153 X 0 40 Y Y 1 F N -F0 "X" 100 50 60 H V C CNN -F1 "IC_74153" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 100 -200 60 0 0 0 4:1 Normal 0 C C -T 0 100 -100 60 0 0 0 DUAL Normal 0 C C -T 0 100 -300 60 0 0 0 MUX Normal 0 C C -S -200 500 350 -550 0 1 0 N -X a0 1 -400 350 200 R 50 50 1 1 I -X a1 2 -400 250 200 R 50 50 1 1 I -X a2 3 -400 150 200 R 50 50 1 1 I -X a3 4 -400 50 200 R 50 50 1 1 I -X EA 5 0 700 200 D 50 50 1 1 I I -X b0 6 -400 -150 200 R 50 50 1 1 I -X b1 7 -400 -250 200 R 50 50 1 1 I -X b2 8 -400 -350 200 R 50 50 1 1 I -X b3 9 -400 -450 200 R 50 50 1 1 I -X EB 10 200 700 200 D 50 50 1 1 I I -X s1 11 50 -750 200 U 50 50 1 1 I -X s0 12 150 -750 200 U 50 50 1 1 I -X ya 13 550 250 200 L 50 50 1 1 O -X yb 14 550 -300 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_74154 -# -DEF IC_74154 X 0 40 Y Y 1 F N -F0 "X" 0 -200 60 H V C CNN -F1 "IC_74154" 50 -50 60 H V C CNN -F2 "" 0 50 60 H V C CNN -F3 "" 0 50 60 H V C CNN -DRAW -T 0 0 400 60 0 0 0 4:16~ Normal 0 C C -T 0 0 250 60 0 0 0 decoder Normal 0 C C -S -350 700 400 -700 0 0 0 N -X ~Y0 1 -550 550 200 R 50 50 1 1 O I -X ~Y1 2 -550 450 200 R 50 50 1 1 O I -X ~Y2 3 -550 350 200 R 50 50 1 1 O I -X ~Y3 4 -550 250 200 R 50 50 1 1 O I -X ~Y4 5 -550 150 200 R 50 50 1 1 O I -X ~Y5 6 -550 50 200 R 50 50 1 1 O I -X ~Y6 7 -550 -50 200 R 50 50 1 1 O I -X ~Y7 8 -550 -150 200 R 50 50 1 1 O I -X ~Y8 9 -550 -250 200 R 50 50 1 1 O I -X ~Y9 10 -550 -350 200 R 50 50 1 1 O I -X A3 20 600 150 200 L 50 50 1 1 I -X ~Y10 11 -550 -450 200 R 50 50 1 1 O I -X A2 21 600 250 200 L 50 50 1 1 I -X GND 12 -550 -550 200 R 50 50 1 1 I -X A1 22 600 350 200 L 50 50 1 1 I -X ~Y11 13 600 -550 200 L 50 50 1 1 O I -X A0 23 600 450 200 L 50 50 1 1 I -X ~Y12 14 600 -450 200 L 50 50 1 1 O I -X Vcc 24 600 550 200 L 50 50 1 1 I -X ~Y13 15 600 -350 200 L 50 50 1 1 O I -X ~Y14 16 600 -250 200 L 50 50 1 1 O I -X ~Y15 17 600 -150 200 L 50 50 1 1 O I -X ~E0 18 600 -50 200 L 50 50 1 1 I I -X ~E1 19 600 50 200 L 50 50 1 1 I I -ENDDRAW -ENDDEF -# -# IC_74157 -# -DEF IC_74157 X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "IC_74157" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 50 -300 60 0 0 0 2:1 Normal 0 C C -T 0 50 -400 60 0 0 0 MUX Normal 0 C C -T 0 50 -200 60 0 0 0 QUAD Normal 0 C C -S -350 550 400 -650 0 1 0 N -X a0 1 -550 450 200 R 50 50 1 1 I -X a1 2 -550 300 200 R 50 50 1 1 I -X b0 3 -550 200 200 R 50 50 1 1 I -X b1 4 -550 100 200 R 50 50 1 1 I -X c0 5 -550 0 200 R 50 50 1 1 I -X c1 6 -550 -100 200 R 50 50 1 1 I -X d0 7 -550 -200 200 R 50 50 1 1 I -X d1 8 -550 -300 200 R 50 50 1 1 I -X EN 9 -550 -550 200 R 50 50 1 1 I I -X S 10 -550 -450 200 R 50 50 1 1 I -X Yd 11 600 0 200 L 50 50 1 1 O -X Ya 12 600 300 200 L 50 50 1 1 O -X Yb 13 600 200 200 L 50 50 1 1 O -X Yc 14 600 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_7485 -# -DEF IC_7485 X 0 40 Y Y 1 F N -F0 "X" -50 -100 60 H V C CNN -F1 "IC_7485" -50 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C -S -350 450 400 -400 0 1 0 N -X AB(in) 3 600 -300 200 L 50 50 1 1 I -X A3 4 -550 100 200 R 50 50 1 1 I -X B3 5 -550 -350 200 R 50 50 1 1 I -X A2 6 -550 200 200 R 50 50 1 1 I -X B2 7 -550 -250 200 R 50 50 1 1 I -X A1 8 -550 300 200 R 50 50 1 1 I -X B1 9 -550 -150 200 R 50 50 1 1 I -X A0 10 -550 400 200 R 50 50 1 1 I -X B0 11 -550 -50 200 R 50 50 1 1 I -X A>B(out) 12 600 350 200 L 50 50 1 1 O -X A=B(out) 13 600 250 200 L 50 50 1 1 O -X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A fig: Symbol of tline -**NOTE: We have to put one space between Z0=50 and Td=3ns** +**NOTE: We have to put one space between Z0=50 and Td=3ns**
This can be done in the cir.out file after creating the circuits and converting kiCad to NgSpice. @@ -30,5 +30,5 @@ across all frequencies. As waves move towards the load end of the lossy transmis line, distortion is caused by a change in speed. The symbol for Single Lossy Transmission Lines(SLTL) is shown below- -![ymod](https://user-images.githubusercontent.com/43288153/184139539-ed4eac77-934a-423c-8f7b-2cba4daf42d1.png) +![ymod](https://user-images.githubusercontent.com/43288153/184139539-ed4eac77-934a-423c-8f7b-2cba4daf42d1.png)
fig: Symbol of SLTL -- cgit From 5a62af12c43837f49b04d7ca1b1d0fb058cbc383 Mon Sep 17 00:00:00 2001 From: Dilip Boidya Date: Thu, 11 Aug 2022 18:39:01 +0530 Subject: Readme file for Transmission Lines --- library/deviceModelLibrary/Transmission Lines/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'library') diff --git a/library/deviceModelLibrary/Transmission Lines/README.md b/library/deviceModelLibrary/Transmission Lines/README.md index 960a3dd3..3cd6aef4 100644 --- a/library/deviceModelLibrary/Transmission Lines/README.md +++ b/library/deviceModelLibrary/Transmission Lines/README.md @@ -19,7 +19,7 @@ ceived at the load end. There is no power dissipation in the line itself. **NOTE: We have to put one space between Z0=50 and Td=3ns**
- This can be done in the cir.out file after creating the circuits and converting kiCad + This can be done in the cir.out file after creating the circuit(s) and converting kiCad to NgSpice. ## Single Lossy Transmission Line (SLTL) -- cgit From 6e218518adabcc62063e503bb224a48f056e2122 Mon Sep 17 00:00:00 2001 From: Dilip Boidya Date: Thu, 11 Aug 2022 19:40:25 +0530 Subject: Readme file for LEDs --- library/deviceModelLibrary/LEDs/README.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'library') diff --git a/library/deviceModelLibrary/LEDs/README.md b/library/deviceModelLibrary/LEDs/README.md index dabb7269..11973ed1 100644 --- a/library/deviceModelLibrary/LEDs/README.md +++ b/library/deviceModelLibrary/LEDs/README.md @@ -10,9 +10,7 @@ that the forward voltage of the LEDs are higher than the normal diode. Bv=5 Ibv=10e-6 Fc=0.5 Isr=0.0 Nr=2.0 Kf=0.0 Af=1.0 Ffe=1.0 Xti=3.0 Eg=1.11 Tbv=0.0 Trs=0.0 ) ``` -NOTE: The name of the above LED is set as eSim_Red_LED the same name of the -LED must be given to the subcircuit while creating the symbol for LED. While the -D is the designator for the diode. +**NOTE: The name of the above LED is set as eSim_Red_LED the same name of the LED must be given to the subcircuit while creating the symbol for LED. While the D is the designator for the diode.** # Blue LED -- cgit From d61c9f8c60b68daf369211491c5260629af7c06f Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:18:05 +0530 Subject: AD620 is an Instrumentation Amplifier IC. --- library/SubcircuitLibrary/AD_620/AD_620-cache.lib | 83 +++ library/SubcircuitLibrary/AD_620/AD_620.cir | 23 + library/SubcircuitLibrary/AD_620/AD_620.cir.out | 25 + library/SubcircuitLibrary/AD_620/AD_620.pro | 71 +++ library/SubcircuitLibrary/AD_620/AD_620.sch | 377 +++++++++++ library/SubcircuitLibrary/AD_620/AD_620.sub | 19 + .../AD_620/AD_620_Previous_Values.xml | 1 + library/SubcircuitLibrary/AD_620/NPN.lib | 4 + library/SubcircuitLibrary/AD_620/PNP.lib | 4 + library/SubcircuitLibrary/AD_620/README.md | 34 + library/SubcircuitLibrary/AD_620/analysis | 1 + library/SubcircuitLibrary/AD_620/lm_741-cache.lib | 119 ++++ library/SubcircuitLibrary/AD_620/lm_741.cir | 43 ++ library/SubcircuitLibrary/AD_620/lm_741.cir.out | 46 ++ library/SubcircuitLibrary/AD_620/lm_741.pro | 44 ++ library/SubcircuitLibrary/AD_620/lm_741.sch | 697 +++++++++++++++++++++ library/SubcircuitLibrary/AD_620/lm_741.sub | 40 ++ .../AD_620/lm_741_Previous_Values.xml | 1 + library/SubcircuitLibrary/AD_620/npn_1.lib | 29 + library/SubcircuitLibrary/AD_620/pnp_1.lib | 29 + 20 files changed, 1690 insertions(+) create mode 100644 library/SubcircuitLibrary/AD_620/AD_620-cache.lib create mode 100644 library/SubcircuitLibrary/AD_620/AD_620.cir create mode 100644 library/SubcircuitLibrary/AD_620/AD_620.cir.out create mode 100644 library/SubcircuitLibrary/AD_620/AD_620.pro create mode 100644 library/SubcircuitLibrary/AD_620/AD_620.sch create mode 100644 library/SubcircuitLibrary/AD_620/AD_620.sub create mode 100644 library/SubcircuitLibrary/AD_620/AD_620_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/AD_620/NPN.lib create mode 100644 library/SubcircuitLibrary/AD_620/PNP.lib create mode 100644 library/SubcircuitLibrary/AD_620/README.md create mode 100644 library/SubcircuitLibrary/AD_620/analysis create mode 100644 library/SubcircuitLibrary/AD_620/lm_741-cache.lib create mode 100644 library/SubcircuitLibrary/AD_620/lm_741.cir create mode 100644 library/SubcircuitLibrary/AD_620/lm_741.cir.out create mode 100644 library/SubcircuitLibrary/AD_620/lm_741.pro create mode 100644 library/SubcircuitLibrary/AD_620/lm_741.sch create mode 100644 library/SubcircuitLibrary/AD_620/lm_741.sub create mode 100644 library/SubcircuitLibrary/AD_620/lm_741_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/AD_620/npn_1.lib create mode 100644 library/SubcircuitLibrary/AD_620/pnp_1.lib (limited to 'library') diff --git a/library/SubcircuitLibrary/AD_620/AD_620-cache.lib b/library/SubcircuitLibrary/AD_620/AD_620-cache.lib new file mode 100644 index 00000000..d1bbdfdd --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/AD_620/AD_620.cir b/library/SubcircuitLibrary/AD_620/AD_620.cir new file mode 100644 index 00000000..068c956d --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620.cir @@ -0,0 +1,23 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\AD_620\AD_620.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/22 10:13:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_R31-Pad2_ Net-_U1-Pad3_ Net-_R6-Pad2_ ? Net-_R11-Pad1_ Net-_R5-Pad2_ ? lm_741 +X3 ? Net-_R11-Pad2_ Net-_R12-Pad2_ Net-_R6-Pad2_ ? Net-_R21-Pad2_ Net-_R5-Pad2_ ? lm_741 +X2 ? Net-_R32-Pad1_ Net-_U1-Pad2_ Net-_R6-Pad2_ ? Net-_R12-Pad1_ Net-_R5-Pad2_ ? lm_741 +R11 Net-_R11-Pad1_ Net-_R11-Pad2_ 10k +R12 Net-_R12-Pad1_ Net-_R12-Pad2_ 10k +R21 Net-_R11-Pad2_ Net-_R21-Pad2_ 11.11k +R22 Net-_R12-Pad2_ Net-_R22-Pad2_ 11.11k +R31 Net-_R11-Pad1_ Net-_R31-Pad2_ 24.7k +R32 Net-_R32-Pad1_ Net-_R12-Pad1_ 24.7k +R5 /vcc Net-_R5-Pad2_ 1 +R6 Net-_R6-Pad1_ Net-_R6-Pad2_ 1 +R4 Net-_R4-Pad1_ Net-_R32-Pad1_ 40 +U1 Net-_R31-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R6-Pad1_ Net-_R22-Pad2_ Net-_R21-Pad2_ /vcc Net-_R4-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/AD_620/AD_620.cir.out b/library/SubcircuitLibrary/AD_620/AD_620.cir.out new file mode 100644 index 00000000..a96f610c --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620.cir.out @@ -0,0 +1,25 @@ +* c:\fossee\esim\library\subcircuitlibrary\ad_620\ad_620.cir + +.include lm_741.sub +x1 ? net-_r31-pad2_ net-_u1-pad3_ net-_r6-pad2_ ? net-_r11-pad1_ net-_r5-pad2_ ? lm_741 +x3 ? net-_r11-pad2_ net-_r12-pad2_ net-_r6-pad2_ ? net-_r21-pad2_ net-_r5-pad2_ ? lm_741 +x2 ? net-_r32-pad1_ net-_u1-pad2_ net-_r6-pad2_ ? net-_r12-pad1_ net-_r5-pad2_ ? lm_741 +r11 net-_r11-pad1_ net-_r11-pad2_ 10k +r12 net-_r12-pad1_ net-_r12-pad2_ 10k +r21 net-_r11-pad2_ net-_r21-pad2_ 11.11k +r22 net-_r12-pad2_ net-_r22-pad2_ 11.11k +r31 net-_r11-pad1_ net-_r31-pad2_ 24.7k +r32 net-_r32-pad1_ net-_r12-pad1_ 24.7k +r5 /vcc net-_r5-pad2_ 1 +r6 net-_r6-pad1_ net-_r6-pad2_ 1 +r4 net-_r4-pad1_ net-_r32-pad1_ 40 +* u1 net-_r31-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r6-pad1_ net-_r22-pad2_ net-_r21-pad2_ /vcc net-_r4-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/AD_620/AD_620.pro b/library/SubcircuitLibrary/AD_620/AD_620.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/AD_620/AD_620.sch b/library/SubcircuitLibrary/AD_620/AD_620.sch new file mode 100644 index 00000000..11154276 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620.sch @@ -0,0 +1,377 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:AD_620-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 62A60F4C +P 5600 3650 +F 0 "X1" H 5400 3650 60 0000 C CNN +F 1 "lm_741" H 5500 3400 60 0000 C CNN +F 2 "" H 5600 3650 60 0000 C CNN +F 3 "" H 5600 3650 60 0000 C CNN + 1 5600 3650 + 1 0 0 1 +$EndComp +$Comp +L lm_741 X3 +U 1 1 62A60F4D +P 8250 4800 +F 0 "X3" H 8050 4800 60 0000 C CNN +F 1 "lm_741" H 8150 4550 60 0000 C CNN +F 2 "" H 8250 4800 60 0000 C CNN +F 3 "" H 8250 4800 60 0000 C CNN + 1 8250 4800 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 62A60F4E +P 5600 5700 +F 0 "X2" H 5400 5700 60 0000 C CNN +F 1 "lm_741" H 5500 5450 60 0000 C CNN +F 2 "" H 5600 5700 60 0000 C CNN +F 3 "" H 5600 5700 60 0000 C CNN + 1 5600 5700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 62A60F4F +P 7100 4700 +F 0 "R11" H 7150 4830 50 0000 C CNN +F 1 "10k" H 7150 4650 50 0000 C CNN +F 2 "" H 7150 4680 30 0000 C CNN +F 3 "" V 7150 4750 30 0000 C CNN + 1 7100 4700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 62A60F50 +P 7100 4950 +F 0 "R12" H 7150 5080 50 0000 C CNN +F 1 "10k" H 7150 4900 50 0000 C CNN +F 2 "" H 7150 4930 30 0000 C CNN +F 3 "" V 7150 5000 30 0000 C CNN + 1 7100 4950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 62A60F51 +P 8350 4050 +F 0 "R21" H 8400 4180 50 0000 C CNN +F 1 "11.11k" H 8400 4000 50 0000 C CNN +F 2 "" H 8400 4030 30 0000 C CNN +F 3 "" V 8400 4100 30 0000 C CNN + 1 8350 4050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 62A60F52 +P 7600 5750 +F 0 "R22" H 7650 5880 50 0000 C CNN +F 1 "11.11k" H 7650 5700 50 0000 C CNN +F 2 "" H 7650 5730 30 0000 C CNN +F 3 "" V 7650 5800 30 0000 C CNN + 1 7600 5750 + 0 1 1 0 +$EndComp +$Comp +L resistor R31 +U 1 1 62A60F53 +P 6250 4150 +F 0 "R31" H 6300 4280 50 0000 C CNN +F 1 "24.7k" H 6300 4100 50 0000 C CNN +F 2 "" H 6300 4130 30 0000 C CNN +F 3 "" V 6300 4200 30 0000 C CNN + 1 6250 4150 + 0 1 1 0 +$EndComp +$Comp +L resistor R32 +U 1 1 62A60F55 +P 6250 5300 +F 0 "R32" H 6300 5430 50 0000 C CNN +F 1 "24.7k" H 6300 5250 50 0000 C CNN +F 2 "" H 6300 5280 30 0000 C CNN +F 3 "" V 6300 5350 30 0000 C CNN + 1 6250 5300 + 0 1 1 0 +$EndComp +Text Label 7300 3400 0 60 ~ 0 +vcc +$Comp +L resistor R5 +U 1 1 62A60F69 +P 7250 3800 +F 0 "R5" H 7300 3930 50 0000 C CNN +F 1 "1" H 7300 3750 50 0000 C CNN +F 2 "" H 7300 3780 30 0000 C CNN +F 3 "" V 7300 3850 30 0000 C CNN + 1 7250 3800 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 62A60F6A +P 6800 2750 +F 0 "R6" H 6850 2880 50 0000 C CNN +F 1 "1" H 6850 2700 50 0000 C CNN +F 2 "" H 6850 2730 30 0000 C CNN +F 3 "" V 6850 2800 30 0000 C CNN + 1 6800 2750 + -1 0 0 1 +$EndComp +$Comp +L resistor R4 +U 1 1 62A60F6B +P 6250 4900 +F 0 "R4" H 6300 5030 50 0000 C CNN +F 1 "40" H 6300 4850 50 0000 C CNN +F 2 "" H 6300 4880 30 0000 C CNN +F 3 "" V 6300 4950 30 0000 C CNN + 1 6250 4900 + 0 1 1 0 +$EndComp +Wire Wire Line + 6150 3650 6150 4050 +Wire Wire Line + 6150 4050 6800 4050 +Wire Wire Line + 6800 4050 6800 4650 +Wire Wire Line + 6800 4650 7000 4650 +Connection ~ 6300 4050 +Wire Wire Line + 7300 4650 7700 4650 +Wire Wire Line + 7300 4900 7700 4900 +Wire Wire Line + 7650 5650 7650 4900 +Connection ~ 7650 4900 +Wire Wire Line + 8250 4000 7600 4000 +Wire Wire Line + 7600 4000 7600 4650 +Connection ~ 7600 4650 +Wire Wire Line + 8800 4800 9400 4800 +Wire Wire Line + 8550 4000 9050 4000 +Wire Wire Line + 9050 4000 9050 4800 +Connection ~ 9050 4800 +Wire Wire Line + 5050 3550 3800 3550 +Wire Wire Line + 5450 4100 5450 5250 +Wire Wire Line + 5450 4350 8100 4350 +Wire Wire Line + 4800 3200 5450 3200 +Wire Wire Line + 4800 3200 4800 6150 +Wire Wire Line + 4800 6150 7200 6150 +Wire Wire Line + 8100 5250 7200 5250 +Wire Wire Line + 7200 5250 7200 6150 +Connection ~ 5450 6150 +Wire Wire Line + 7650 5950 7650 6250 +Wire Wire Line + 4900 3200 4900 2800 +Wire Wire Line + 4900 2800 6600 2800 +Connection ~ 4900 3200 +Wire Wire Line + 7750 3200 7300 3200 +Wire Wire Line + 7300 3200 7300 3700 +Wire Wire Line + 7300 4000 7300 4350 +Wire Wire Line + 6300 4350 6300 4500 +Wire Wire Line + 6300 4700 6300 4800 +Wire Wire Line + 6300 5100 6300 5200 +Wire Wire Line + 6300 5500 6300 5700 +Wire Wire Line + 6150 5700 6800 5700 +Wire Wire Line + 6800 5700 6800 4900 +Wire Wire Line + 6800 4900 7000 4900 +Connection ~ 6300 5700 +Wire Wire Line + 5050 3800 5050 4400 +Wire Wire Line + 5050 4400 6300 4400 +Wire Wire Line + 5050 5550 5050 5200 +Wire Wire Line + 5050 5200 6300 5200 +Connection ~ 5450 4350 +Connection ~ 7300 4350 +Wire Wire Line + 5050 5800 3800 5800 +Wire Wire Line + 6900 2800 7350 2800 +Wire Wire Line + 6300 4500 3850 4500 +Connection ~ 6300 4400 +Wire Wire Line + 6300 4700 3850 4700 +Wire Wire Line + 7650 6250 8850 6250 +$Comp +L PORT U1 +U 1 1 62A61C9F +P 3600 4500 +F 0 "U1" H 3650 4600 30 0000 C CNN +F 1 "PORT" H 3600 4500 30 0000 C CNN +F 2 "" H 3600 4500 60 0000 C CNN +F 3 "" H 3600 4500 60 0000 C CNN + 1 3600 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62A61D59 +P 3550 5800 +F 0 "U1" H 3600 5900 30 0000 C CNN +F 1 "PORT" H 3550 5800 30 0000 C CNN +F 2 "" H 3550 5800 60 0000 C CNN +F 3 "" H 3550 5800 60 0000 C CNN + 2 3550 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62A61E36 +P 3550 3550 +F 0 "U1" H 3600 3650 30 0000 C CNN +F 1 "PORT" H 3550 3550 30 0000 C CNN +F 2 "" H 3550 3550 60 0000 C CNN +F 3 "" H 3550 3550 60 0000 C CNN + 3 3550 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62A61EFF +P 7600 2800 +F 0 "U1" H 7650 2900 30 0000 C CNN +F 1 "PORT" H 7600 2800 30 0000 C CNN +F 2 "" H 7600 2800 60 0000 C CNN +F 3 "" H 7600 2800 60 0000 C CNN + 4 7600 2800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62A61FDE +P 9100 6250 +F 0 "U1" H 9150 6350 30 0000 C CNN +F 1 "PORT" H 9100 6250 30 0000 C CNN +F 2 "" H 9100 6250 60 0000 C CNN +F 3 "" H 9100 6250 60 0000 C CNN + 5 9100 6250 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62A62529 +P 9650 4800 +F 0 "U1" H 9700 4900 30 0000 C CNN +F 1 "PORT" H 9650 4800 30 0000 C CNN +F 2 "" H 9650 4800 60 0000 C CNN +F 3 "" H 9650 4800 60 0000 C CNN + 6 9650 4800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62A625D2 +P 8000 3200 +F 0 "U1" H 8050 3300 30 0000 C CNN +F 1 "PORT" H 8000 3200 30 0000 C CNN +F 2 "" H 8000 3200 60 0000 C CNN +F 3 "" H 8000 3200 60 0000 C CNN + 7 8000 3200 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62A62687 +P 3600 4700 +F 0 "U1" H 3650 4800 30 0000 C CNN +F 1 "PORT" H 3600 4700 30 0000 C CNN +F 2 "" H 3600 4700 60 0000 C CNN +F 3 "" H 3600 4700 60 0000 C CNN + 8 3600 4700 + 1 0 0 -1 +$EndComp +NoConn ~ 5550 4050 +NoConn ~ 5650 4000 +NoConn ~ 5650 5350 +NoConn ~ 5550 5300 +NoConn ~ 8300 4450 +NoConn ~ 8200 4400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/AD_620/AD_620.sub b/library/SubcircuitLibrary/AD_620/AD_620.sub new file mode 100644 index 00000000..d4ba9832 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620.sub @@ -0,0 +1,19 @@ +* Subcircuit AD_620 +.subckt AD_620 net-_r31-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r6-pad1_ net-_r22-pad2_ net-_r21-pad2_ /vcc net-_r4-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\ad_620\ad_620.cir +.include lm_741.sub +x1 ? net-_r31-pad2_ net-_u1-pad3_ net-_r6-pad2_ ? net-_r11-pad1_ net-_r5-pad2_ ? lm_741 +x3 ? net-_r11-pad2_ net-_r12-pad2_ net-_r6-pad2_ ? net-_r21-pad2_ net-_r5-pad2_ ? lm_741 +x2 ? net-_r32-pad1_ net-_u1-pad2_ net-_r6-pad2_ ? net-_r12-pad1_ net-_r5-pad2_ ? lm_741 +r11 net-_r11-pad1_ net-_r11-pad2_ 10k +r12 net-_r12-pad1_ net-_r12-pad2_ 10k +r21 net-_r11-pad2_ net-_r21-pad2_ 11.11k +r22 net-_r12-pad2_ net-_r22-pad2_ 11.11k +r31 net-_r11-pad1_ net-_r31-pad2_ 24.7k +r32 net-_r32-pad1_ net-_r12-pad1_ 24.7k +r5 /vcc net-_r5-pad2_ 1 +r6 net-_r6-pad1_ net-_r6-pad2_ 1 +r4 net-_r4-pad1_ net-_r32-pad1_ 40 +* Control Statements + +.ends AD_620 \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/AD_620_Previous_Values.xml b/library/SubcircuitLibrary/AD_620/AD_620_Previous_Values.xml new file mode 100644 index 00000000..f5f997ef --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/AD_620_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/NPN.lib b/library/SubcircuitLibrary/AD_620/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/AD_620/PNP.lib b/library/SubcircuitLibrary/AD_620/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/AD_620/README.md b/library/SubcircuitLibrary/AD_620/README.md new file mode 100644 index 00000000..605204e3 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/README.md @@ -0,0 +1,34 @@ + +# AD620 Amplifier + +AD620 is 8-pin IC. It is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of. 1 to 10,000. + + +## Usage/Examples + +Blood Pressure Monitor + +Medical ECG + +Weigh Scales + +Data Acquisition Equipment + +Process Controls in Industry + +Battery operated and portable Devices + +## Documentation + +To know the details of AD620 IC please go through with the documentation : [AD620_datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ad620.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. Here this amplifier IC works fine for lower gains. But for getting higher gains like 500, 1000 there may be mismacthed with external resistance value. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/analysis b/library/SubcircuitLibrary/AD_620/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/lm_741-cache.lib b/library/SubcircuitLibrary/AD_620/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/AD_620/lm_741.cir b/library/SubcircuitLibrary/AD_620/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/AD_620/lm_741.cir.out b/library/SubcircuitLibrary/AD_620/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/AD_620/lm_741.pro b/library/SubcircuitLibrary/AD_620/lm_741.pro new file mode 100644 index 00000000..b56de1b0 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/AD_620/lm_741.sch b/library/SubcircuitLibrary/AD_620/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 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U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/AD_620/lm_741.sub b/library/SubcircuitLibrary/AD_620/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/AD_620/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/npn_1.lib b/library/SubcircuitLibrary/AD_620/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD_620/pnp_1.lib b/library/SubcircuitLibrary/AD_620/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/AD_620/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file -- cgit From a01cfbc349112ae78a463897b885c6d2e541bf19 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:29:45 +0530 Subject: LM7809 is a Volatge Regulator IC. --- .../SubcircuitLibrary/LM_7809/LM_7809-cache.lib | 138 ++++ library/SubcircuitLibrary/LM_7809/LM_7809.cir | 51 ++ library/SubcircuitLibrary/LM_7809/LM_7809.cir.out | 60 ++ library/SubcircuitLibrary/LM_7809/LM_7809.pro | 71 ++ library/SubcircuitLibrary/LM_7809/LM_7809.sch | 743 +++++++++++++++++++++ library/SubcircuitLibrary/LM_7809/LM_7809.sub | 54 ++ .../LM_7809/LM_7809_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM_7809/NPN.lib | 4 + library/SubcircuitLibrary/LM_7809/PNP.lib | 4 + library/SubcircuitLibrary/LM_7809/README.md | 35 + library/SubcircuitLibrary/LM_7809/analysis | 1 + library/SubcircuitLibrary/LM_7809/desktop.ini | 4 + 12 files changed, 1166 insertions(+) create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809-cache.lib create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809.cir create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809.cir.out create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809.pro create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809.sch create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809.sub create mode 100644 library/SubcircuitLibrary/LM_7809/LM_7809_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM_7809/NPN.lib create mode 100644 library/SubcircuitLibrary/LM_7809/PNP.lib create mode 100644 library/SubcircuitLibrary/LM_7809/README.md create mode 100644 library/SubcircuitLibrary/LM_7809/analysis create mode 100644 library/SubcircuitLibrary/LM_7809/desktop.ini (limited to 'library') diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809-cache.lib b/library/SubcircuitLibrary/LM_7809/LM_7809-cache.lib new file mode 100644 index 00000000..27408fec --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809.cir b/library/SubcircuitLibrary/LM_7809/LM_7809.cir new file mode 100644 index 00000000..ac173e2b --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM_7809\LM_7809.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/14/22 00:48:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q14-Pad3_ eSim_NPN +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +Q14 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q14-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q10-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q8 Net-_Q12-Pad2_ Net-_Q10-Pad1_ Net-_Q5-Pad1_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q12-Pad2_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q9 Net-_Q12-Pad1_ Net-_Q9-Pad2_ Net-_Q14-Pad3_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q12-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +Q13 Net-_Q12-Pad1_ Net-_Q13-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q7 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q7-Pad3_ eSim_PNP +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q15 Net-_Q14-Pad3_ Net-_C1-Pad1_ Net-_Q12-Pad1_ eSim_PNP +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1K +R10 Net-_Q10-Pad3_ Net-_Q2-Pad3_ 6K +R11 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20K +R7 Net-_Q3-Pad2_ Net-_Q14-Pad3_ 6K +R9 Net-_Q6-Pad3_ Net-_Q14-Pad3_ 1K +R12 Net-_Q11-Pad3_ Net-_Q14-Pad3_ 6K +R18 Net-_Q17-Pad3_ Net-_Q10-Pad1_ 0.3 +R19 Net-_Q10-Pad1_ Net-_Q10-Pad2_ 385 +R20 Net-_Q10-Pad2_ Net-_Q14-Pad3_ 293 +R16 Net-_Q16-Pad3_ Net-_Q10-Pad1_ 200 +R17 Net-_Q17-Pad3_ Net-_Q13-Pad2_ 240 +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100K +R8 Net-_Q16-Pad1_ Net-_Q7-Pad3_ 100 +R13 Net-_Q16-Pad1_ Net-_Q12-Pad3_ 50 +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10K +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3K +R4 Net-_Q2-Pad2_ Net-_Q9-Pad2_ 2.7K +R5 Net-_Q9-Pad2_ Net-_Q14-Pad3_ 500 +R14 Net-_Q12-Pad1_ Net-_C1-Pad1_ 6K +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30pF +U3 Net-_Q12-Pad1_ Net-_R15-Pad2_ zener +U2 Net-_Q14-Pad3_ Net-_Q1-Pad2_ zener +U1 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q14-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809.cir.out b/library/SubcircuitLibrary/LM_7809/LM_7809.cir.out new file mode 100644 index 00000000..0f5b6f84 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809.cir.out @@ -0,0 +1,60 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm_7809\lm_7809.cir + +.include NPN.lib +.include PNP.lib +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q14-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +q14 net-_c1-pad1_ net-_q11-pad3_ net-_q14-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q10-pad3_ net-_q2-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q8 net-_q12-pad2_ net-_q10-pad1_ net-_q5-pad1_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q9 net-_q12-pad1_ net-_q9-pad2_ net-_q14-pad3_ Q2N2222 +q16 net-_q16-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +q13 net-_q12-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q7-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q15 net-_q14-pad3_ net-_c1-pad1_ net-_q12-pad1_ Q2N2907A +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +r10 net-_q10-pad3_ net-_q2-pad3_ 6k +r11 net-_q2-pad3_ net-_c1-pad2_ 20k +r7 net-_q3-pad2_ net-_q14-pad3_ 6k +r9 net-_q6-pad3_ net-_q14-pad3_ 1k +r12 net-_q11-pad3_ net-_q14-pad3_ 6k +r18 net-_q17-pad3_ net-_q10-pad1_ 0.3 +r19 net-_q10-pad1_ net-_q10-pad2_ 385 +r20 net-_q10-pad2_ net-_q14-pad3_ 293 +r16 net-_q16-pad3_ net-_q10-pad1_ 200 +r17 net-_q17-pad3_ net-_q13-pad2_ 240 +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r8 net-_q16-pad1_ net-_q7-pad3_ 100 +r13 net-_q16-pad1_ net-_q12-pad3_ 50 +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q9-pad2_ 2.7k +r5 net-_q9-pad2_ net-_q14-pad3_ 500 +r14 net-_q12-pad1_ net-_c1-pad1_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +* u3 net-_q12-pad1_ net-_r15-pad2_ zener +* u2 net-_q14-pad3_ net-_q1-pad2_ zener +* u1 net-_q16-pad1_ net-_q10-pad1_ net-_q14-pad3_ port +a1 net-_q12-pad1_ net-_r15-pad2_ u3 +a2 net-_q14-pad3_ net-_q1-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809.pro b/library/SubcircuitLibrary/LM_7809/LM_7809.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809.sch b/library/SubcircuitLibrary/LM_7809/LM_7809.sch new file mode 100644 index 00000000..9cd1c1e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809.sch @@ -0,0 +1,743 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM_7809-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q3 +U 1 1 627E1EA8 +P 4050 5650 +F 0 "Q3" H 3950 5700 50 0000 R CNN +F 1 "eSim_NPN" H 4000 5800 50 0000 R CNN +F 2 "" H 4250 5750 29 0000 C CNN +F 3 "" H 4050 5650 60 0000 C CNN + 1 4050 5650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 627E1EA9 +P 4850 5650 +F 0 "Q6" H 4750 5700 50 0000 R CNN +F 1 "eSim_NPN" H 4800 5800 50 0000 R CNN +F 2 "" H 5050 5750 29 0000 C CNN +F 3 "" H 4850 5650 60 0000 C CNN + 1 4850 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 627E1EAA +P 4350 5050 +F 0 "Q4" H 4250 5100 50 0000 R CNN +F 1 "eSim_NPN" H 4300 5200 50 0000 R CNN +F 2 "" H 4550 5150 29 0000 C CNN +F 3 "" H 4350 5050 60 0000 C CNN + 1 4350 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 627E1EAB +P 6100 5850 +F 0 "Q14" H 6000 5900 50 0000 R CNN +F 1 "eSim_NPN" H 6050 6000 50 0000 R CNN +F 2 "" H 6300 5950 29 0000 C CNN +F 3 "" H 6100 5850 60 0000 C CNN + 1 6100 5850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 627E1EAC +P 5500 5450 +F 0 "Q11" H 5400 5500 50 0000 R CNN +F 1 "eSim_NPN" H 5450 5600 50 0000 R CNN +F 2 "" H 5700 5550 29 0000 C CNN +F 3 "" H 5500 5450 60 0000 C CNN + 1 5500 5450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 627E1EAD +P 4550 4250 +F 0 "Q5" H 4450 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4500 4400 50 0000 R CNN +F 2 "" H 4750 4350 29 0000 C CNN +F 3 "" H 4550 4250 60 0000 C CNN + 1 4550 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 627E1EAE +P 5250 3850 +F 0 "Q10" H 5150 3900 50 0000 R CNN +F 1 "eSim_NPN" H 5200 4000 50 0000 R CNN +F 2 "" H 5450 3950 29 0000 C CNN +F 3 "" H 5250 3850 60 0000 C CNN + 1 5250 3850 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 627E1EAF +P 4900 3500 +F 0 "Q8" H 4800 3550 50 0000 R CNN +F 1 "eSim_NPN" H 4850 3650 50 0000 R CNN +F 2 "" H 5100 3600 29 0000 C CNN +F 3 "" H 4900 3500 60 0000 C CNN + 1 4900 3500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 627E1EB0 +P 3600 2550 +F 0 "Q1" H 3500 2600 50 0000 R CNN +F 1 "eSim_NPN" H 3550 2700 50 0000 R CNN +F 2 "" H 3800 2650 29 0000 C CNN +F 3 "" H 3600 2550 60 0000 C CNN + 1 3600 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 627E1EB1 +P 4050 3750 +F 0 "Q2" H 3950 3800 50 0000 R CNN +F 1 "eSim_NPN" H 4000 3900 50 0000 R CNN +F 2 "" H 4250 3850 29 0000 C CNN +F 3 "" H 4050 3750 60 0000 C CNN + 1 4050 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 627E1EB2 +P 5050 2800 +F 0 "Q9" H 4950 2850 50 0000 R CNN +F 1 "eSim_NPN" H 5000 2950 50 0000 R CNN +F 2 "" H 5250 2900 29 0000 C CNN +F 3 "" H 5050 2800 60 0000 C CNN + 1 5050 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 627E1EB3 +P 6600 2000 +F 0 "Q16" H 6500 2050 50 0000 R CNN +F 1 "eSim_NPN" H 6550 2150 50 0000 R CNN +F 2 "" H 6800 2100 29 0000 C CNN +F 3 "" H 6600 2000 60 0000 C CNN + 1 6600 2000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 627E1EB4 +P 7250 2800 +F 0 "Q17" H 7150 2850 50 0000 R CNN +F 1 "eSim_NPN" H 7200 2950 50 0000 R CNN +F 2 "" H 7450 2900 29 0000 C CNN +F 3 "" H 7250 2800 60 0000 C CNN + 1 7250 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 627E1EB5 +P 6000 3050 +F 0 "Q13" H 5900 3100 50 0000 R CNN +F 1 "eSim_NPN" H 5950 3200 50 0000 R CNN +F 2 "" H 6200 3150 29 0000 C CNN +F 3 "" H 6000 3050 60 0000 C CNN + 1 6000 3050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 627E1EB6 +P 4900 1500 +F 0 "Q7" H 4800 1550 50 0000 R CNN +F 1 "eSim_PNP" H 4850 1650 50 0000 R CNN +F 2 "" H 5100 1600 29 0000 C CNN +F 3 "" H 4900 1500 60 0000 C CNN + 1 4900 1500 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 627E1EB7 +P 5700 1500 +F 0 "Q12" H 5600 1550 50 0000 R CNN +F 1 "eSim_PNP" H 5650 1650 50 0000 R CNN +F 2 "" H 5900 1600 29 0000 C CNN +F 3 "" H 5700 1500 60 0000 C CNN + 1 5700 1500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 627E1EB8 +P 6400 4500 +F 0 "Q15" H 6300 4550 50 0000 R CNN +F 1 "eSim_PNP" H 6350 4650 50 0000 R CNN +F 2 "" H 6600 4600 29 0000 C CNN +F 3 "" H 6400 4500 60 0000 C CNN + 1 6400 4500 + 1 0 0 1 +$EndComp +$Comp +L resistor R6 +U 1 1 627E1EB9 +P 4100 4600 +F 0 "R6" H 4150 4730 50 0000 C CNN +F 1 "1K" H 4150 4550 50 0000 C CNN +F 2 "" H 4150 4580 30 0000 C CNN +F 3 "" V 4150 4650 30 0000 C CNN + 1 4100 4600 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 627E1EBA +P 5100 4250 +F 0 "R10" H 5150 4400 50 0000 C CNN +F 1 "6K" H 5150 4200 50 0000 C CNN +F 2 "" H 5150 4230 30 0000 C CNN +F 3 "" V 5150 4300 30 0000 C CNN + 1 5100 4250 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 627E1EBB +P 5100 4700 +F 0 "R11" H 5150 4850 50 0000 C CNN +F 1 "20K" H 5150 4650 50 0000 C CNN +F 2 "" H 5150 4680 30 0000 C CNN +F 3 "" V 5150 4750 30 0000 C CNN + 1 5100 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 627E1EBC +P 4400 6050 +F 0 "R7" H 4450 6200 50 0000 C CNN +F 1 "6K" H 4450 6000 50 0000 C CNN +F 2 "" H 4450 6030 30 0000 C CNN +F 3 "" V 4450 6100 30 0000 C CNN + 1 4400 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 627E1EBD +P 4900 6050 +F 0 "R9" H 4950 6200 50 0000 C CNN +F 1 "1K" H 4950 6000 50 0000 C CNN +F 2 "" H 4950 6030 30 0000 C CNN +F 3 "" V 4950 6100 30 0000 C CNN + 1 4900 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 627E1EBE +P 5550 6050 +F 0 "R12" H 5600 6200 50 0000 C CNN +F 1 "6K" H 5600 6000 50 0000 C CNN +F 2 "" H 5600 6030 30 0000 C CNN +F 3 "" V 5600 6100 30 0000 C CNN + 1 5550 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 627E1EBF +P 7300 3250 +F 0 "R18" H 7350 3400 50 0000 C CNN +F 1 "0.3" H 7350 3200 50 0000 C CNN +F 2 "" H 7350 3230 30 0000 C CNN +F 3 "" V 7350 3300 30 0000 C CNN + 1 7300 3250 + 0 1 1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 627E1EC0 +P 7300 4200 +F 0 "R19" H 7350 4350 50 0000 C CNN +F 1 "385" H 7350 4150 50 0000 C CNN +F 2 "" H 7350 4180 30 0000 C CNN +F 3 "" V 7350 4250 30 0000 C CNN + 1 7300 4200 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 627E1EC1 +P 7300 5550 +F 0 "R20" H 7350 5700 50 0000 C CNN +F 1 "293" H 7350 5500 50 0000 C CNN +F 2 "" H 7350 5530 30 0000 C CNN +F 3 "" V 7350 5600 30 0000 C CNN + 1 7300 5550 + 0 1 1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 627E1EC2 +P 6650 3250 +F 0 "R16" H 6700 3400 50 0000 C CNN +F 1 "200" H 6700 3200 50 0000 C CNN +F 2 "" H 6700 3230 30 0000 C CNN +F 3 "" V 6700 3300 30 0000 C CNN + 1 6650 3250 + 0 1 1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 627E1EC3 +P 6950 3000 +F 0 "R17" H 7000 3150 50 0000 C CNN +F 1 "240" H 7000 2950 50 0000 C CNN +F 2 "" H 7000 2980 30 0000 C CNN +F 3 "" V 7000 3050 30 0000 C CNN + 1 6950 3000 + -1 0 0 1 +$EndComp +$Comp +L resistor R1 +U 1 1 627E1EC4 +P 3050 750 +F 0 "R1" H 3100 900 50 0000 C CNN +F 1 "100K" H 3100 700 50 0000 C CNN +F 2 "" H 3100 730 30 0000 C CNN +F 3 "" V 3100 800 30 0000 C CNN + 1 3050 750 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 627E1EC5 +P 4750 750 +F 0 "R8" H 4800 900 50 0000 C CNN +F 1 "100" H 4800 700 50 0000 C CNN +F 2 "" H 4800 730 30 0000 C CNN +F 3 "" V 4800 800 30 0000 C CNN + 1 4750 750 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 627E1EC6 +P 5750 750 +F 0 "R13" H 5800 900 50 0000 C CNN +F 1 "50" H 5800 700 50 0000 C CNN +F 2 "" H 5800 730 30 0000 C CNN +F 3 "" V 5800 800 30 0000 C CNN + 1 5750 750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 627E1EC7 +P 3650 750 +F 0 "R2" H 3700 900 50 0000 C CNN +F 1 "500" H 3700 700 50 0000 C CNN +F 2 "" H 3700 730 30 0000 C CNN +F 3 "" V 3700 800 30 0000 C CNN + 1 3650 750 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 627E1EC8 +P 6150 750 +F 0 "R15" H 6200 900 50 0000 C CNN +F 1 "10K" H 6200 700 50 0000 C CNN +F 2 "" H 6200 730 30 0000 C CNN +F 3 "" V 6200 800 30 0000 C CNN + 1 6150 750 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 627E1EC9 +P 3650 3150 +F 0 "R3" H 3700 3280 50 0000 C CNN +F 1 "3.3K" H 3700 3100 50 0000 C CNN +F 2 "" H 3700 3130 30 0000 C CNN +F 3 "" V 3700 3200 30 0000 C CNN + 1 3650 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 627E1ECA +P 3650 4100 +F 0 "R4" H 3700 4230 50 0000 C CNN +F 1 "2.7K" H 3700 4050 50 0000 C CNN +F 2 "" H 3700 4080 30 0000 C CNN +F 3 "" V 3700 4150 30 0000 C CNN + 1 3650 4100 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 627E1ECB +P 3650 5250 +F 0 "R5" H 3700 5380 50 0000 C CNN +F 1 "500" H 3700 5200 50 0000 C CNN +F 2 "" H 3700 5230 30 0000 C CNN +F 3 "" V 3700 5300 30 0000 C CNN + 1 3650 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 627E1ECC +P 5750 4200 +F 0 "R14" H 5800 4350 50 0000 C CNN +F 1 "6K" H 5800 4150 50 0000 C CNN +F 2 "" H 5800 4180 30 0000 C CNN +F 3 "" V 5800 4250 30 0000 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 627E1ECD +P 5300 5100 +F 0 "C1" H 5325 5200 50 0000 L CNN +F 1 "30pF" H 5325 5000 50 0000 L CNN +F 2 "" H 5338 4950 30 0000 C CNN +F 3 "" H 5300 5100 60 0000 C CNN + 1 5300 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 5100 3500 8800 3500 +Wire Wire Line + 2400 650 7350 650 +Connection ~ 3700 650 +Connection ~ 4800 650 +Connection ~ 5800 650 +Connection ~ 6200 650 +Wire Wire Line + 3100 950 3100 4900 +Wire Wire Line + 7350 6450 3100 6450 +Wire Wire Line + 7350 5750 7350 6450 +Wire Wire Line + 7350 4400 7350 5450 +Wire Wire Line + 7350 3000 7350 3150 +Wire Wire Line + 7350 3450 7350 4100 +Connection ~ 7350 3500 +Wire Wire Line + 6700 3450 6700 3500 +Connection ~ 6700 3500 +Wire Wire Line + 3400 2550 3100 2550 +Connection ~ 3100 2550 +Wire Wire Line + 3700 950 3700 2350 +Wire Wire Line + 3700 2750 3700 3050 +Wire Wire Line + 3700 3350 3700 4000 +Wire Wire Line + 3700 4300 3700 5150 +Wire Wire Line + 3700 5450 3700 6450 +Connection ~ 3700 6450 +Wire Wire Line + 4950 6250 4950 6450 +Connection ~ 4950 6450 +Wire Wire Line + 5600 6250 5600 6450 +Connection ~ 5600 6450 +Wire Wire Line + 4450 6250 4450 6450 +Connection ~ 4450 6450 +Wire Wire Line + 5150 4050 5150 4150 +Wire Wire Line + 5150 4450 5150 4600 +Wire Wire Line + 5150 4900 5150 4950 +Wire Wire Line + 5150 4950 4950 4950 +Wire Wire Line + 4950 4950 4950 5450 +Wire Wire Line + 4950 5850 4950 5950 +Wire Wire Line + 4250 5650 4650 5650 +Wire Wire Line + 4450 4450 4450 4850 +Wire Wire Line + 4450 5250 4450 5950 +Connection ~ 4450 5650 +Wire Wire Line + 4800 950 4800 1300 +Wire Wire Line + 4800 1700 4800 3300 +Wire Wire Line + 4800 3700 4800 3850 +Wire Wire Line + 4800 3850 4450 3850 +Wire Wire Line + 4450 3850 4450 4050 +Wire Wire Line + 4800 3250 4150 3250 +Wire Wire Line + 4150 3250 4150 3550 +Connection ~ 4800 3250 +Wire Wire Line + 4150 3950 4150 4500 +Wire Wire Line + 3850 3750 3700 3750 +Connection ~ 3700 3750 +Wire Wire Line + 4150 4800 4150 4850 +Wire Wire Line + 4150 4850 3950 4850 +Wire Wire Line + 3950 4850 3950 5450 +Wire Wire Line + 3950 5850 3950 6450 +Connection ~ 3950 6450 +Wire Wire Line + 4150 5050 3950 5050 +Connection ~ 3950 5050 +Wire Wire Line + 4150 4450 5150 4450 +Connection ~ 4150 4450 +Connection ~ 4450 4450 +Wire Wire Line + 5450 3850 7150 3850 +Wire Wire Line + 7150 3850 7150 4850 +Wire Wire Line + 7150 4850 7350 4850 +Connection ~ 7350 4850 +Wire Wire Line + 5800 1700 5800 4100 +Wire Wire Line + 4950 5100 5150 5100 +Connection ~ 4950 5100 +Wire Wire Line + 5800 4400 5800 5250 +Wire Wire Line + 5800 5250 5600 5250 +Wire Wire Line + 5600 5650 5600 5950 +Wire Wire Line + 4950 5450 5300 5450 +Wire Wire Line + 5450 5100 6200 5100 +Connection ~ 5800 5100 +Wire Wire Line + 6200 5100 6200 5650 +Wire Wire Line + 5900 5850 5600 5850 +Connection ~ 5600 5850 +Wire Wire Line + 6200 6050 6200 6450 +Connection ~ 6200 6450 +Wire Wire Line + 6700 650 6700 1800 +Connection ~ 6700 650 +Wire Wire Line + 6700 2200 6700 3150 +Wire Wire Line + 7050 3050 7350 3050 +Connection ~ 7350 3050 +Wire Wire Line + 5900 3250 5900 3500 +Connection ~ 5900 3500 +Wire Wire Line + 6200 3050 6750 3050 +Wire Wire Line + 6200 950 6200 1150 +Wire Wire Line + 6700 2800 7050 2800 +Connection ~ 6700 2800 +Wire Wire Line + 7350 650 7350 2600 +Wire Wire Line + 5100 1500 5500 1500 +Wire Wire Line + 5800 950 5800 1300 +Wire Wire Line + 5300 1500 5300 1800 +Wire Wire Line + 5300 1800 4800 1800 +Connection ~ 4800 1800 +Connection ~ 5300 1500 +Wire Wire Line + 4850 2800 3850 2800 +Wire Wire Line + 3850 2800 3850 4500 +Wire Wire Line + 3850 4500 3700 4500 +Connection ~ 3700 4500 +Wire Wire Line + 5150 3000 5150 3200 +Wire Wire Line + 5150 3200 3800 3200 +Wire Wire Line + 3800 3200 3800 6450 +Connection ~ 3800 6450 +Wire Wire Line + 6500 4700 6500 6450 +Connection ~ 6500 6450 +Wire Wire Line + 6200 4500 5800 4500 +Connection ~ 5800 4500 +Wire Wire Line + 6500 4300 6500 4000 +Wire Wire Line + 6500 4000 5800 4000 +Connection ~ 5800 4000 +Wire Wire Line + 5150 2600 5150 2000 +Wire Wire Line + 5150 2000 6400 2000 +Connection ~ 5800 2000 +Wire Wire Line + 5900 2850 5900 2000 +Connection ~ 5900 2000 +Wire Wire Line + 5150 3650 5150 3500 +Connection ~ 5150 3500 +Wire Wire Line + 4750 4250 4950 4250 +Wire Wire Line + 4950 4250 4950 4100 +Wire Wire Line + 4950 4100 5150 4100 +Connection ~ 5150 4100 +$Comp +L zener U3 +U 1 1 627E1ED2 +P 6200 1450 +F 0 "U3" H 6150 1350 60 0000 C CNN +F 1 "zener" H 6200 1550 60 0000 C CNN +F 2 "" H 6250 1450 60 0000 C CNN +F 3 "" H 6250 1450 60 0000 C CNN + 1 6200 1450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 1650 6200 2000 +Connection ~ 6200 2000 +$Comp +L zener U2 +U 1 1 627E1ED3 +P 3100 5200 +F 0 "U2" H 3050 5100 60 0000 C CNN +F 1 "zener" H 3100 5300 60 0000 C CNN +F 2 "" H 3150 5200 60 0000 C CNN +F 3 "" H 3150 5200 60 0000 C CNN + 1 3100 5200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3100 6450 3100 5400 +Connection ~ 3100 650 +$Comp +L PORT U1 +U 1 1 627EEACD +P 2150 650 +F 0 "U1" H 2200 750 30 0000 C CNN +F 1 "PORT" H 2150 650 30 0000 C CNN +F 2 "" H 2150 650 60 0000 C CNN +F 3 "" H 2150 650 60 0000 C CNN + 1 2150 650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 627EFDCA +P 9050 3500 +F 0 "U1" H 9100 3600 30 0000 C CNN +F 1 "PORT" H 9050 3500 30 0000 C CNN +F 2 "" H 9050 3500 60 0000 C CNN +F 3 "" H 9050 3500 60 0000 C CNN + 2 9050 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 627F2063 +P 5300 6800 +F 0 "U1" H 5350 6900 30 0000 C CNN +F 1 "PORT" H 5300 6800 30 0000 C CNN +F 2 "" H 5300 6800 60 0000 C CNN +F 3 "" H 5300 6800 60 0000 C CNN + 3 5300 6800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5300 6550 5300 6450 +Connection ~ 5300 6450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809.sub b/library/SubcircuitLibrary/LM_7809/LM_7809.sub new file mode 100644 index 00000000..3af8c373 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809.sub @@ -0,0 +1,54 @@ +* Subcircuit LM_7809 +.subckt LM_7809 net-_q16-pad1_ net-_q10-pad1_ net-_q14-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\lm_7809\lm_7809.cir +.include NPN.lib +.include PNP.lib +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q14-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +q14 net-_c1-pad1_ net-_q11-pad3_ net-_q14-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q10-pad3_ net-_q2-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q8 net-_q12-pad2_ net-_q10-pad1_ net-_q5-pad1_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q9 net-_q12-pad1_ net-_q9-pad2_ net-_q14-pad3_ Q2N2222 +q16 net-_q16-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +q13 net-_q12-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q7-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q15 net-_q14-pad3_ net-_c1-pad1_ net-_q12-pad1_ Q2N2907A +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +r10 net-_q10-pad3_ net-_q2-pad3_ 6k +r11 net-_q2-pad3_ net-_c1-pad2_ 20k +r7 net-_q3-pad2_ net-_q14-pad3_ 6k +r9 net-_q6-pad3_ net-_q14-pad3_ 1k +r12 net-_q11-pad3_ net-_q14-pad3_ 6k +r18 net-_q17-pad3_ net-_q10-pad1_ 0.3 +r19 net-_q10-pad1_ net-_q10-pad2_ 385 +r20 net-_q10-pad2_ net-_q14-pad3_ 293 +r16 net-_q16-pad3_ net-_q10-pad1_ 200 +r17 net-_q17-pad3_ net-_q13-pad2_ 240 +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r8 net-_q16-pad1_ net-_q7-pad3_ 100 +r13 net-_q16-pad1_ net-_q12-pad3_ 50 +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q9-pad2_ 2.7k +r5 net-_q9-pad2_ net-_q14-pad3_ 500 +r14 net-_q12-pad1_ net-_c1-pad1_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +* u3 net-_q12-pad1_ net-_r15-pad2_ zener +* u2 net-_q14-pad3_ net-_q1-pad2_ zener +a1 net-_q12-pad1_ net-_r15-pad2_ u3 +a2 net-_q14-pad3_ net-_q1-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM_7809 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM_7809/LM_7809_Previous_Values.xml b/library/SubcircuitLibrary/LM_7809/LM_7809_Previous_Values.xml new file mode 100644 index 00000000..8aa8f5b8 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/LM_7809_Previous_Values.xml @@ -0,0 +1 @@ +zener5.62.0e-21.0e-121.0FALSEzener5.62.0e-21.0e-121.0FALSEzener5.62.0e-21.0e-121.0FALSEzener5.62.0e-21.0e-121.0FALSEC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM_7809/NPN.lib b/library/SubcircuitLibrary/LM_7809/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM_7809/PNP.lib b/library/SubcircuitLibrary/LM_7809/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM_7809/README.md b/library/SubcircuitLibrary/LM_7809/README.md new file mode 100644 index 00000000..96898d44 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/README.md @@ -0,0 +1,35 @@ + +# LM7809 Voltage Regulator + +LM7809 is a voltage regulator IC which belongs to 78xx series. It produces 9 volt constant DC output with the higher input voltages. It is used in various electronics devices or gadgets to maintain a constant DC power supply. + + +## Usage/Examples + +Voltage Step Down + +Power Supplies + +Motor Drivers + +Battery Chargers + +Solar Supplies + +Microcontroller power supplies + + +## Documentation + +To know the details of LM7809 IC please go through with the documentation [LM7809_datasheet](https://pdf.datasheet.live/7cb7272b/fairchildsemi.com/LM7809.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 diff --git a/library/SubcircuitLibrary/LM_7809/analysis b/library/SubcircuitLibrary/LM_7809/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM_7809/desktop.ini b/library/SubcircuitLibrary/LM_7809/desktop.ini new file mode 100644 index 00000000..d957fd18 --- /dev/null +++ b/library/SubcircuitLibrary/LM_7809/desktop.ini @@ -0,0 +1,4 @@ +[ViewState] +Mode= +Vid= +FolderType=Generic -- cgit From 4d5f13e717b7814e3bb4f54adfeb762c0fc8c8d6 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:35:23 +0530 Subject: LM386 is an Amplifier IC. --- library/SubcircuitLibrary/LM386/D.lib | 2 + library/SubcircuitLibrary/LM386/LM386-cache.lib | 126 ++++++ library/SubcircuitLibrary/LM386/LM386.cir | 31 ++ library/SubcircuitLibrary/LM386/LM386.cir.out | 35 ++ library/SubcircuitLibrary/LM386/LM386.pro | 71 +++ library/SubcircuitLibrary/LM386/LM386.sch | 476 +++++++++++++++++++++ library/SubcircuitLibrary/LM386/LM386.sub | 29 ++ .../LM386/LM386_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM386/NPN.lib | 4 + library/SubcircuitLibrary/LM386/PNP.lib | 4 + library/SubcircuitLibrary/LM386/README.md | 47 ++ library/SubcircuitLibrary/LM386/analysis | 1 + 12 files changed, 827 insertions(+) create mode 100644 library/SubcircuitLibrary/LM386/D.lib create mode 100644 library/SubcircuitLibrary/LM386/LM386-cache.lib create mode 100644 library/SubcircuitLibrary/LM386/LM386.cir create mode 100644 library/SubcircuitLibrary/LM386/LM386.cir.out create mode 100644 library/SubcircuitLibrary/LM386/LM386.pro create mode 100644 library/SubcircuitLibrary/LM386/LM386.sch create mode 100644 library/SubcircuitLibrary/LM386/LM386.sub create mode 100644 library/SubcircuitLibrary/LM386/LM386_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM386/NPN.lib create mode 100644 library/SubcircuitLibrary/LM386/PNP.lib create mode 100644 library/SubcircuitLibrary/LM386/README.md create mode 100644 library/SubcircuitLibrary/LM386/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/LM386/D.lib b/library/SubcircuitLibrary/LM386/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM386/LM386-cache.lib b/library/SubcircuitLibrary/LM386/LM386-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM386/LM386.cir b/library/SubcircuitLibrary/LM386/LM386.cir new file mode 100644 index 00000000..d08cae25 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM386\LM386.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/22 20:52:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad3_ eSim_PNP +Q5 Net-_Q4-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q6 Net-_Q1-Pad1_ Net-_Q6-Pad2_ Net-_Q5-Pad2_ eSim_PNP +Q8 Net-_Q10-Pad2_ Net-_D2-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q1-Pad1_ eSim_NPN +Q7 Net-_D2-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q9 Net-_Q9-Pad1_ Net-_D1-Pad1_ Net-_Q10-Pad1_ eSim_NPN +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_Q2-Pad3_ Net-_R5-Pad2_ 150 +R6 Net-_R5-Pad2_ Net-_Q5-Pad3_ 1.35k +R4 Net-_R3-Pad2_ Net-_Q2-Pad3_ 15k +R3 Net-_Q9-Pad1_ Net-_R3-Pad2_ 15k +R7 Net-_Q5-Pad3_ Net-_Q10-Pad1_ 17k +R2 Net-_Q6-Pad2_ Net-_Q1-Pad1_ 50k +R1 Net-_Q1-Pad2_ Net-_Q1-Pad1_ 50k +R8 Net-_Q9-Pad1_ Net-_D1-Pad1_ 1.5k +U1 Net-_Q5-Pad3_ Net-_Q1-Pad2_ Net-_Q6-Pad2_ Net-_Q1-Pad1_ Net-_Q10-Pad1_ Net-_Q9-Pad1_ Net-_R3-Pad2_ Net-_R5-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM386/LM386.cir.out b/library/SubcircuitLibrary/LM386/LM386.cir.out new file mode 100644 index 00000000..2c5505af --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386.cir.out @@ -0,0 +1,35 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm386\lm386.cir + +.include D.lib +.include PNP.lib +.include NPN.lib +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A +q5 net-_q4-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q6 net-_q1-pad1_ net-_q6-pad2_ net-_q5-pad2_ Q2N2907A +q8 net-_q10-pad2_ net-_d2-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q1-pad1_ Q2N2222 +q7 net-_d2-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q9 net-_q9-pad1_ net-_d1-pad1_ net-_q10-pad1_ Q2N2222 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_q2-pad3_ net-_r5-pad2_ 150 +r6 net-_r5-pad2_ net-_q5-pad3_ 1.35k +r4 net-_r3-pad2_ net-_q2-pad3_ 15k +r3 net-_q9-pad1_ net-_r3-pad2_ 15k +r7 net-_q5-pad3_ net-_q10-pad1_ 17k +r2 net-_q6-pad2_ net-_q1-pad1_ 50k +r1 net-_q1-pad2_ net-_q1-pad1_ 50k +r8 net-_q9-pad1_ net-_d1-pad1_ 1.5k +* u1 net-_q5-pad3_ net-_q1-pad2_ net-_q6-pad2_ net-_q1-pad1_ net-_q10-pad1_ net-_q9-pad1_ net-_r3-pad2_ net-_r5-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM386/LM386.pro b/library/SubcircuitLibrary/LM386/LM386.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/LM386/LM386.sch b/library/SubcircuitLibrary/LM386/LM386.sch new file mode 100644 index 00000000..65d81e0b --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386.sch @@ -0,0 +1,476 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM386-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q3 +U 1 1 628CA42B +P 4800 5150 +F 0 "Q3" H 4700 5200 50 0000 R CNN +F 1 "eSim_NPN" H 4750 5300 50 0000 R CNN +F 2 "" H 5000 5250 29 0000 C CNN +F 3 "" H 4800 5150 60 0000 C CNN + 1 4800 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 628CA42C +P 5900 5150 +F 0 "Q4" H 5800 5200 50 0000 R CNN +F 1 "eSim_NPN" H 5850 5300 50 0000 R CNN +F 2 "" H 6100 5250 29 0000 C CNN +F 3 "" H 5900 5150 60 0000 C CNN + 1 5900 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 628CA42D +P 4600 4050 +F 0 "Q2" H 4500 4100 50 0000 R CNN +F 1 "eSim_PNP" H 4550 4200 50 0000 R CNN +F 2 "" H 4800 4150 29 0000 C CNN +F 3 "" H 4600 4050 60 0000 C CNN + 1 4600 4050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 628CA42E +P 6100 4050 +F 0 "Q5" H 6000 4100 50 0000 R CNN +F 1 "eSim_PNP" H 6050 4200 50 0000 R CNN +F 2 "" H 6300 4150 29 0000 C CNN +F 3 "" H 6100 4050 60 0000 C CNN + 1 6100 4050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 628CA42F +P 3900 4500 +F 0 "Q1" H 3800 4550 50 0000 R CNN +F 1 "eSim_PNP" H 3850 4650 50 0000 R CNN +F 2 "" H 4100 4600 29 0000 C CNN +F 3 "" H 3900 4500 60 0000 C CNN + 1 3900 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 628CA430 +P 6650 4550 +F 0 "Q6" H 6550 4600 50 0000 R CNN +F 1 "eSim_PNP" H 6600 4700 50 0000 R CNN +F 2 "" H 6850 4650 29 0000 C CNN +F 3 "" H 6650 4550 60 0000 C CNN + 1 6650 4550 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 628CA431 +P 8000 4300 +F 0 "Q8" H 7900 4350 50 0000 R CNN +F 1 "eSim_PNP" H 7950 4450 50 0000 R CNN +F 2 "" H 8200 4400 29 0000 C CNN +F 3 "" H 8000 4300 60 0000 C CNN + 1 8000 4300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 628CA432 +P 8450 5150 +F 0 "Q10" H 8350 5200 50 0000 R CNN +F 1 "eSim_NPN" H 8400 5300 50 0000 R CNN +F 2 "" H 8650 5250 29 0000 C CNN +F 3 "" H 8450 5150 60 0000 C CNN + 1 8450 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 628CA433 +P 7300 5150 +F 0 "Q7" H 7200 5200 50 0000 R CNN +F 1 "eSim_NPN" H 7250 5300 50 0000 R CNN +F 2 "" H 7500 5250 29 0000 C CNN +F 3 "" H 7300 5150 60 0000 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 628CA434 +P 8450 3300 +F 0 "Q9" H 8350 3350 50 0000 R CNN +F 1 "eSim_NPN" H 8400 3450 50 0000 R CNN +F 2 "" H 8650 3400 29 0000 C CNN +F 3 "" H 8450 3300 60 0000 C CNN + 1 8450 3300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 628CA435 +P 7400 4000 +F 0 "D2" H 7400 4100 50 0000 C CNN +F 1 "eSim_Diode" H 7400 3900 50 0000 C CNN +F 2 "" H 7400 4000 60 0000 C CNN +F 3 "" H 7400 4000 60 0000 C CNN + 1 7400 4000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 628CA436 +P 7400 3250 +F 0 "D1" H 7400 3350 50 0000 C CNN +F 1 "eSim_Diode" H 7400 3150 50 0000 C CNN +F 2 "" H 7400 3250 60 0000 C CNN +F 3 "" H 7400 3250 60 0000 C CNN + 1 7400 3250 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 628CA437 +P 5000 3650 +F 0 "R5" H 5050 3780 50 0000 C CNN +F 1 "150" H 5050 3600 50 0000 C CNN +F 2 "" H 5050 3630 30 0000 C CNN +F 3 "" V 5050 3700 30 0000 C CNN + 1 5000 3650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 628CA438 +P 5700 3650 +F 0 "R6" H 5750 3780 50 0000 C CNN +F 1 "1.35k" H 5750 3600 50 0000 C CNN +F 2 "" H 5750 3630 30 0000 C CNN +F 3 "" V 5750 3700 30 0000 C CNN + 1 5700 3650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 628CA439 +P 4650 3000 +F 0 "R4" H 4700 3130 50 0000 C CNN +F 1 "15k" H 4700 2950 50 0000 C CNN +F 2 "" H 4700 2980 30 0000 C CNN +F 3 "" V 4700 3050 30 0000 C CNN + 1 4650 3000 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 628CA43A +P 4650 2450 +F 0 "R3" H 4700 2580 50 0000 C CNN +F 1 "15k" H 4700 2400 50 0000 C CNN +F 2 "" H 4700 2430 30 0000 C CNN +F 3 "" V 4700 2500 30 0000 C CNN + 1 4650 2450 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 628CA43B +P 6650 3650 +F 0 "R7" H 6700 3780 50 0000 C CNN +F 1 "17k" H 6700 3600 50 0000 C CNN +F 2 "" H 6700 3630 30 0000 C CNN +F 3 "" V 6700 3700 30 0000 C CNN + 1 6650 3650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 628CA43C +P 6850 5050 +F 0 "R2" H 6900 5180 50 0000 C CNN +F 1 "50k" H 6900 5000 50 0000 C CNN +F 2 "" H 6900 5030 30 0000 C CNN +F 3 "" V 6900 5100 30 0000 C CNN + 1 6850 5050 + 0 1 1 0 +$EndComp +Wire Wire Line + 3700 5350 9800 5350 +Connection ~ 4700 5350 +Connection ~ 6000 5350 +Wire Wire Line + 4400 4050 4000 4050 +Wire Wire Line + 4000 4050 4000 4300 +Wire Wire Line + 4700 3200 4700 3850 +Wire Wire Line + 4700 2650 4700 2900 +Wire Wire Line + 5200 3600 5600 3600 +Wire Wire Line + 4900 3600 4700 3600 +Connection ~ 4700 3600 +Wire Wire Line + 4700 4250 4700 4950 +Wire Wire Line + 6000 4250 6000 4950 +Wire Wire Line + 5900 3600 6550 3600 +Wire Wire Line + 6850 3600 10400 3600 +Wire Wire Line + 8550 3500 8550 4950 +Connection ~ 8550 3600 +Wire Wire Line + 7400 3400 7400 3850 +Wire Wire Line + 7400 4150 7400 4950 +Connection ~ 7400 5350 +Wire Wire Line + 7800 4300 7400 4300 +Connection ~ 7400 4300 +Wire Wire Line + 8100 4500 8100 5150 +Wire Wire Line + 8100 5150 8250 5150 +Wire Wire Line + 8100 4100 8100 3900 +Wire Wire Line + 8100 3900 8550 3900 +Connection ~ 8550 3900 +Wire Wire Line + 6000 3150 6000 3850 +Connection ~ 6000 3600 +Wire Wire Line + 6300 4050 6550 4050 +Wire Wire Line + 6550 4050 6550 4350 +Wire Wire Line + 5000 5150 5700 5150 +Wire Wire Line + 4700 4600 5400 4600 +Wire Wire Line + 5400 4600 5400 5150 +Connection ~ 5400 5150 +Connection ~ 4700 4600 +Wire Wire Line + 4000 4700 4000 5350 +Connection ~ 4000 5350 +Wire Wire Line + 6550 4750 6550 5350 +Connection ~ 6550 5350 +Wire Wire Line + 6850 4550 6900 4550 +Wire Wire Line + 6900 3900 6900 4950 +Wire Wire Line + 6900 5250 6900 5350 +Connection ~ 6900 5350 +Wire Wire Line + 6000 4750 7100 4750 +Wire Wire Line + 7100 4750 7100 5150 +Connection ~ 6000 4750 +Wire Wire Line + 4700 2350 8950 2350 +Wire Wire Line + 8550 2350 8550 3100 +Wire Wire Line + 7400 2800 7400 3100 +Wire Wire Line + 8250 3300 7750 3300 +Wire Wire Line + 7750 3300 7750 2850 +Wire Wire Line + 7750 2850 7400 2850 +Connection ~ 8550 2350 +Connection ~ 8550 5350 +Wire Wire Line + 3200 4050 3200 3900 +Wire Wire Line + 3200 3900 6900 3900 +Connection ~ 6900 4550 +Wire Wire Line + 3700 4500 3700 4800 +$Comp +L resistor R1 +U 1 1 628CA447 +P 3650 4900 +F 0 "R1" H 3700 5030 50 0000 C CNN +F 1 "50k" H 3700 4850 50 0000 C CNN +F 2 "" H 3700 4880 30 0000 C CNN +F 3 "" V 3700 4950 30 0000 C CNN + 1 3650 4900 + 0 1 1 0 +$EndComp +Wire Wire Line + 3700 5100 3700 5350 +$Comp +L resistor R8 +U 1 1 628CA448 +P 7350 2600 +F 0 "R8" H 7400 2730 50 0000 C CNN +F 1 "1.5k" H 7400 2550 50 0000 C CNN +F 2 "" H 7400 2580 30 0000 C CNN +F 3 "" V 7400 2650 30 0000 C CNN + 1 7350 2600 + 0 1 1 0 +$EndComp +Wire Wire Line + 7400 2500 7400 2350 +Connection ~ 7400 2350 +Connection ~ 7400 2850 +$Comp +L PORT U1 +U 1 1 628CA6F2 +P 6250 3150 +F 0 "U1" H 6300 3250 30 0000 C CNN +F 1 "PORT" H 6250 3150 30 0000 C CNN +F 2 "" H 6250 3150 60 0000 C CNN +F 3 "" H 6250 3150 60 0000 C CNN + 1 6250 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 628CA797 +P 3050 4500 +F 0 "U1" H 3100 4600 30 0000 C CNN +F 1 "PORT" H 3050 4500 30 0000 C CNN +F 2 "" H 3050 4500 60 0000 C CNN +F 3 "" H 3050 4500 60 0000 C CNN + 2 3050 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 628CAA82 +P 2950 4050 +F 0 "U1" H 3000 4150 30 0000 C CNN +F 1 "PORT" H 2950 4050 30 0000 C CNN +F 2 "" H 2950 4050 60 0000 C CNN +F 3 "" H 2950 4050 60 0000 C CNN + 3 2950 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 628CB3C2 +P 10050 5350 +F 0 "U1" H 10100 5450 30 0000 C CNN +F 1 "PORT" H 10050 5350 30 0000 C CNN +F 2 "" H 10050 5350 60 0000 C CNN +F 3 "" H 10050 5350 60 0000 C CNN + 4 10050 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 628CB505 +P 10650 3600 +F 0 "U1" H 10700 3700 30 0000 C CNN +F 1 "PORT" H 10650 3600 30 0000 C CNN +F 2 "" H 10650 3600 60 0000 C CNN +F 3 "" H 10650 3600 60 0000 C CNN + 5 10650 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 628CBD1A +P 9200 2350 +F 0 "U1" H 9250 2450 30 0000 C CNN +F 1 "PORT" H 9200 2350 30 0000 C CNN +F 2 "" H 9200 2350 60 0000 C CNN +F 3 "" H 9200 2350 60 0000 C CNN + 6 9200 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 628CC4F2 +P 4200 2800 +F 0 "U1" H 4250 2900 30 0000 C CNN +F 1 "PORT" H 4200 2800 30 0000 C CNN +F 2 "" H 4200 2800 60 0000 C CNN +F 3 "" H 4200 2800 60 0000 C CNN + 7 4200 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 628CC571 +P 5100 3150 +F 0 "U1" H 5150 3250 30 0000 C CNN +F 1 "PORT" H 5100 3150 30 0000 C CNN +F 2 "" H 5100 3150 60 0000 C CNN +F 3 "" H 5100 3150 60 0000 C CNN + 8 5100 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 2800 4700 2800 +Connection ~ 4700 2800 +Wire Wire Line + 5350 3150 5350 3600 +Connection ~ 5350 3600 +Wire Wire Line + 3300 4500 3700 4500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM386/LM386.sub b/library/SubcircuitLibrary/LM386/LM386.sub new file mode 100644 index 00000000..a683b68b --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386.sub @@ -0,0 +1,29 @@ +* Subcircuit LM386 +.subckt LM386 net-_q5-pad3_ net-_q1-pad2_ net-_q6-pad2_ net-_q1-pad1_ net-_q10-pad1_ net-_q9-pad1_ net-_r3-pad2_ net-_r5-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\lm386\lm386.cir +.include D.lib +.include PNP.lib +.include NPN.lib +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad3_ net-_q2-pad3_ Q2N2907A +q5 net-_q4-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q6 net-_q1-pad1_ net-_q6-pad2_ net-_q5-pad2_ Q2N2907A +q8 net-_q10-pad2_ net-_d2-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q1-pad1_ Q2N2222 +q7 net-_d2-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q9 net-_q9-pad1_ net-_d1-pad1_ net-_q10-pad1_ Q2N2222 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_q2-pad3_ net-_r5-pad2_ 150 +r6 net-_r5-pad2_ net-_q5-pad3_ 1.35k +r4 net-_r3-pad2_ net-_q2-pad3_ 15k +r3 net-_q9-pad1_ net-_r3-pad2_ 15k +r7 net-_q5-pad3_ net-_q10-pad1_ 17k +r2 net-_q6-pad2_ net-_q1-pad1_ 50k +r1 net-_q1-pad2_ net-_q1-pad1_ 50k +r8 net-_q9-pad1_ net-_d1-pad1_ 1.5k +* Control Statements + +.ends LM386 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386/LM386_Previous_Values.xml b/library/SubcircuitLibrary/LM386/LM386_Previous_Values.xml new file mode 100644 index 00000000..09dc0357 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/LM386_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386/NPN.lib b/library/SubcircuitLibrary/LM386/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM386/PNP.lib b/library/SubcircuitLibrary/LM386/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM386/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM386/README.md b/library/SubcircuitLibrary/LM386/README.md new file mode 100644 index 00000000..55a6f475 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/README.md @@ -0,0 +1,47 @@ + +# LM386 Amplifier + +LM386 is power amplifier IC designed for use in low voltage consumer applications. It is used in various field of electronics applications like Radio amplifier, TV sound systems, power converter etc. The gain of the IC can be varied from 20 to 200 using external circuit or components. + + +## Usage/Examples + +Wien bridge oscillator + +Power converters + +Ultrasonic drivers + +Small servo drivers + +Intercoms + +Line drivers + +TV sound systems + +Portable tape player amplifiers + +AM to FM radio amplifiers + +Audio boosters + +Used in speakers of laptop & portable + +Used for voice record from microphone, battery operated speakers. + + +## Documentation + +To know the details of LM386 IC please go through with the documentation : [LM386_datasheet](https://www.ti.com/lit/ds/symlink/lm386.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. But remember there may be minor error for very high gain. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM386/analysis b/library/SubcircuitLibrary/LM386/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM386/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From e89df49ea9ec469ad4a0a8745da1ffc5ba47bcf7 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:45:06 +0530 Subject: CD4000 is 3 input NOR gate with a NOT gate IC. --- .../SubcircuitLibrary/CD_4000/CD_4000-cache.lib | 100 +++++ library/SubcircuitLibrary/CD_4000/CD_4000.cir | 25 ++ library/SubcircuitLibrary/CD_4000/CD_4000.cir.out | 28 ++ library/SubcircuitLibrary/CD_4000/CD_4000.pro | 71 +++ library/SubcircuitLibrary/CD_4000/CD_4000.sch | 497 +++++++++++++++++++++ library/SubcircuitLibrary/CD_4000/CD_4000.sub | 22 + .../CD_4000/CD_4000_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4000/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4000/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4000/README.md | 25 ++ library/SubcircuitLibrary/CD_4000/analysis | 1 + 11 files changed, 794 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000.cir create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000.cir.out create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000.pro create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000.sch create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000.sub create mode 100644 library/SubcircuitLibrary/CD_4000/CD_4000_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4000/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4000/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4000/README.md create mode 100644 library/SubcircuitLibrary/CD_4000/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000-cache.lib b/library/SubcircuitLibrary/CD_4000/CD_4000-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000.cir b/library/SubcircuitLibrary/CD_4000/CD_4000.cir new file mode 100644 index 00000000..22ed56b8 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4000\CD_4000.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/22 11:19:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M4-Pad1_ Net-_M2-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P +M5 Net-_M1-Pad1_ Net-_M5-Pad2_ Net-_M4-Pad1_ Net-_M4-Pad1_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M1-Pad1_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M10-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M12-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M13 Net-_M10-Pad1_ Net-_M13-Pad2_ Net-_M12-Pad1_ Net-_M12-Pad1_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M14 Net-_M10-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M8 Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M7 Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M5-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M7-Pad2_ Net-_M7-Pad1_ Net-_M10-Pad1_ Net-_M11-Pad2_ Net-_M10-Pad2_ Net-_M13-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000.cir.out b/library/SubcircuitLibrary/CD_4000/CD_4000.cir.out new file mode 100644 index 00000000..b6add1a8 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000.cir.out @@ -0,0 +1,28 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4000\cd_4000.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m2-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m5-pad2_ net-_m4-pad1_ net-_m4-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m10-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m10-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad1_ net-_m13-pad2_ net-_m12-pad1_ net-_m12-pad1_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad1_ net-_m1-pad3_ net-_m7-pad2_ net-_m7-pad1_ net-_m10-pad1_ net-_m11-pad2_ net-_m10-pad2_ net-_m13-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000.pro b/library/SubcircuitLibrary/CD_4000/CD_4000.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000.sch b/library/SubcircuitLibrary/CD_4000/CD_4000.sch new file mode 100644 index 00000000..2f277edb --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000.sch @@ -0,0 +1,497 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4000-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M3 +U 1 1 62C26ADA +P 4900 2950 +F 0 "M3" H 4850 3000 50 0000 R CNN +F 1 "eSim_MOS_P" H 4950 3100 50 0000 R CNN +F 2 "" H 5150 3050 29 0000 C CNN +F 3 "" H 4950 2950 60 0000 C CNN + 1 4900 2950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62C26B01 +P 4350 4250 +F 0 "M1" H 4350 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4450 4200 50 0000 R CNN +F 2 "" H 4650 3950 29 0000 C CNN +F 3 "" H 4450 4050 60 0000 C CNN + 1 4350 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 62C26B60 +P 4900 3400 +F 0 "M4" H 4850 3450 50 0000 R CNN +F 1 "eSim_MOS_P" H 4950 3550 50 0000 R CNN +F 2 "" H 5150 3500 29 0000 C CNN +F 3 "" H 4950 3400 60 0000 C CNN + 1 4900 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 62C26B91 +P 4900 3850 +F 0 "M5" H 4850 3900 50 0000 R CNN +F 1 "eSim_MOS_P" H 4950 4000 50 0000 R CNN +F 2 "" H 5150 3950 29 0000 C CNN +F 3 "" H 4950 3850 60 0000 C CNN + 1 4900 3850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62C26BF1 +P 4850 4250 +F 0 "M2" H 4850 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4950 4200 50 0000 R CNN +F 2 "" H 5150 3950 29 0000 C CNN +F 3 "" H 4950 4050 60 0000 C CNN + 1 4850 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 62C26C28 +P 5650 4250 +F 0 "M6" H 5650 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 5750 4200 50 0000 R CNN +F 2 "" H 5950 3950 29 0000 C CNN +F 3 "" H 5750 4050 60 0000 C CNN + 1 5650 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 62C2708C +P 7750 2950 +F 0 "M11" H 7700 3000 50 0000 R CNN +F 1 "eSim_MOS_P" H 7800 3100 50 0000 R CNN +F 2 "" H 8000 3050 29 0000 C CNN +F 3 "" H 7800 2950 60 0000 C CNN + 1 7750 2950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 62C27092 +P 7200 4250 +F 0 "M9" H 7200 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 7300 4200 50 0000 R CNN +F 2 "" H 7500 3950 29 0000 C CNN +F 3 "" H 7300 4050 60 0000 C CNN + 1 7200 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 62C27098 +P 7750 3400 +F 0 "M12" H 7700 3450 50 0000 R CNN +F 1 "eSim_MOS_P" H 7800 3550 50 0000 R CNN +F 2 "" H 8000 3500 29 0000 C CNN +F 3 "" H 7800 3400 60 0000 C CNN + 1 7750 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 62C2709E +P 7750 3850 +F 0 "M13" H 7700 3900 50 0000 R CNN +F 1 "eSim_MOS_P" H 7800 4000 50 0000 R CNN +F 2 "" H 8000 3950 29 0000 C CNN +F 3 "" H 7800 3850 60 0000 C CNN + 1 7750 3850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 62C270A4 +P 7700 4250 +F 0 "M10" H 7700 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 7800 4200 50 0000 R CNN +F 2 "" H 8000 3950 29 0000 C CNN +F 3 "" H 7800 4050 60 0000 C CNN + 1 7700 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M14 +U 1 1 62C270AA +P 8500 4250 +F 0 "M14" H 8500 4100 50 0000 R CNN +F 1 "eSim_MOS_N" H 8600 4200 50 0000 R CNN +F 2 "" H 8800 3950 29 0000 C CNN +F 3 "" H 8600 4050 60 0000 C CNN + 1 8500 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 62C284DF +P 5950 1650 +F 0 "M8" H 5900 1700 50 0000 R CNN +F 1 "eSim_MOS_P" H 6000 1800 50 0000 R CNN +F 2 "" H 6200 1750 29 0000 C CNN +F 3 "" H 6000 1650 60 0000 C CNN + 1 5950 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 62C2851C +P 5900 2000 +F 0 "M7" H 5900 1850 50 0000 R CNN +F 1 "eSim_MOS_N" H 6000 1950 50 0000 R CNN +F 2 "" H 6200 1700 29 0000 C CNN +F 3 "" H 6000 1800 60 0000 C CNN + 1 5900 2000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 3150 5050 3200 +Wire Wire Line + 5050 3600 5050 3650 +Wire Wire Line + 5050 4050 5050 4250 +Wire Wire Line + 4550 4250 5450 4250 +Connection ~ 5050 4250 +Wire Wire Line + 4550 4650 5450 4650 +Connection ~ 5050 4650 +Wire Wire Line + 5150 4600 5150 4650 +Connection ~ 5150 4650 +Wire Wire Line + 4650 4600 4650 4650 +Connection ~ 4650 4650 +Wire Wire Line + 5350 4600 5350 4650 +Connection ~ 5350 4650 +Wire Wire Line + 5150 3250 5150 3200 +Wire Wire Line + 5150 3200 5050 3200 +Wire Wire Line + 5150 3700 5150 3650 +Wire Wire Line + 5150 3650 5050 3650 +Wire Wire Line + 5150 2750 5150 2800 +Wire Wire Line + 5050 2750 5150 2750 +Wire Wire Line + 3900 2950 4750 2950 +Wire Wire Line + 4250 2950 4250 4450 +Wire Wire Line + 3900 3400 4750 3400 +Wire Wire Line + 4700 3400 4700 4450 +Wire Wire Line + 4700 4450 4750 4450 +Wire Wire Line + 4750 3850 4750 4100 +Wire Wire Line + 4750 4100 5750 4100 +Wire Wire Line + 5750 4100 5750 4450 +Connection ~ 4250 2950 +Connection ~ 4700 3400 +Wire Wire Line + 4750 3850 3900 3850 +Wire Wire Line + 5050 4150 6250 4150 +Connection ~ 5050 4150 +Wire Wire Line + 7900 3150 7900 3200 +Wire Wire Line + 7900 3600 7900 3650 +Wire Wire Line + 7900 4050 7900 4250 +Wire Wire Line + 7400 4250 8300 4250 +Connection ~ 7900 4250 +Wire Wire Line + 7400 4650 8300 4650 +Connection ~ 7900 4650 +Wire Wire Line + 8000 4600 8000 4650 +Connection ~ 8000 4650 +Wire Wire Line + 7500 4600 7500 4650 +Connection ~ 7500 4650 +Wire Wire Line + 8200 4600 8200 4650 +Connection ~ 8200 4650 +Wire Wire Line + 8000 3250 8000 3200 +Wire Wire Line + 8000 3200 7900 3200 +Wire Wire Line + 8000 3700 8000 3650 +Wire Wire Line + 8000 3650 7900 3650 +Wire Wire Line + 8000 2750 8000 2800 +Wire Wire Line + 7900 2750 8000 2750 +Wire Wire Line + 6750 2950 7600 2950 +Wire Wire Line + 7100 2950 7100 4450 +Wire Wire Line + 6750 3400 7600 3400 +Wire Wire Line + 7550 3400 7550 4450 +Wire Wire Line + 7550 4450 7600 4450 +Wire Wire Line + 7600 3850 7600 4100 +Wire Wire Line + 7600 4100 8600 4100 +Wire Wire Line + 8600 4100 8600 4450 +Connection ~ 7100 2950 +Connection ~ 7550 3400 +Wire Wire Line + 7600 3850 6750 3850 +Wire Wire Line + 7900 4150 9000 4150 +Connection ~ 7900 4150 +Wire Wire Line + 5100 1350 5100 2750 +Wire Wire Line + 5100 2700 7950 2700 +Wire Wire Line + 7950 2700 7950 2750 +Connection ~ 7950 2750 +Connection ~ 5100 2750 +Wire Wire Line + 5050 4650 5050 4750 +Wire Wire Line + 5050 4750 7900 4750 +Wire Wire Line + 7900 4750 7900 4650 +Wire Wire Line + 5800 1650 5800 2200 +Wire Wire Line + 6100 1850 6100 2000 +Wire Wire Line + 6100 1450 6200 1450 +Wire Wire Line + 6200 1450 6200 1500 +Wire Wire Line + 6200 2350 6200 2400 +Wire Wire Line + 6200 2400 6100 2400 +Wire Wire Line + 6100 1900 6950 1900 +Connection ~ 6100 1900 +Wire Wire Line + 3900 1900 5800 1900 +Connection ~ 5800 1900 +Wire Wire Line + 6150 1350 6150 1450 +Wire Wire Line + 3900 1350 6150 1350 +Connection ~ 5100 2700 +Connection ~ 6150 1450 +Wire Wire Line + 6100 2400 6100 4900 +Connection ~ 6100 4750 +Wire Wire Line + 6100 4900 3900 4900 +Connection ~ 5100 1350 +$Comp +L PORT U1 +U 3 1 62C2A217 +P 3650 2950 +F 0 "U1" H 3700 3050 30 0000 C CNN +F 1 "PORT" H 3650 2950 30 0000 C CNN +F 2 "" H 3650 2950 60 0000 C CNN +F 3 "" H 3650 2950 60 0000 C CNN + 3 3650 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62C2A2A8 +P 3650 3400 +F 0 "U1" H 3700 3500 30 0000 C CNN +F 1 "PORT" H 3650 3400 30 0000 C CNN +F 2 "" H 3650 3400 60 0000 C CNN +F 3 "" H 3650 3400 60 0000 C CNN + 4 3650 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62C2A395 +P 3650 3850 +F 0 "U1" H 3700 3950 30 0000 C CNN +F 1 "PORT" H 3650 3850 30 0000 C CNN +F 2 "" H 3650 3850 60 0000 C CNN +F 3 "" H 3650 3850 60 0000 C CNN + 5 3650 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62C2A452 +P 6500 4150 +F 0 "U1" H 6550 4250 30 0000 C CNN +F 1 "PORT" H 6500 4150 30 0000 C CNN +F 2 "" H 6500 4150 60 0000 C CNN +F 3 "" H 6500 4150 60 0000 C CNN + 6 6500 4150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62C2A512 +P 3650 4900 +F 0 "U1" H 3700 5000 30 0000 C CNN +F 1 "PORT" H 3650 4900 30 0000 C CNN +F 2 "" H 3650 4900 60 0000 C CNN +F 3 "" H 3650 4900 60 0000 C CNN + 7 3650 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62C2A676 +P 3650 1900 +F 0 "U1" H 3700 2000 30 0000 C CNN +F 1 "PORT" H 3650 1900 30 0000 C CNN +F 2 "" H 3650 1900 60 0000 C CNN +F 3 "" H 3650 1900 60 0000 C CNN + 8 3650 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62C2A78A +P 7200 1900 +F 0 "U1" H 7250 2000 30 0000 C CNN +F 1 "PORT" H 7200 1900 30 0000 C CNN +F 2 "" H 7200 1900 60 0000 C CNN +F 3 "" H 7200 1900 60 0000 C CNN + 9 7200 1900 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62C2A8A5 +P 9250 4150 +F 0 "U1" H 9300 4250 30 0000 C CNN +F 1 "PORT" H 9250 4150 30 0000 C CNN +F 2 "" H 9250 4150 60 0000 C CNN +F 3 "" H 9250 4150 60 0000 C CNN + 10 9250 4150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62C2A947 +P 6500 2950 +F 0 "U1" H 6550 3050 30 0000 C CNN +F 1 "PORT" H 6500 2950 30 0000 C CNN +F 2 "" H 6500 2950 60 0000 C CNN +F 3 "" H 6500 2950 60 0000 C CNN + 11 6500 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62C2A9D8 +P 6500 3400 +F 0 "U1" H 6550 3500 30 0000 C CNN +F 1 "PORT" H 6500 3400 30 0000 C CNN +F 2 "" H 6500 3400 60 0000 C CNN +F 3 "" H 6500 3400 60 0000 C CNN + 12 6500 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62C2AA7D +P 6500 3850 +F 0 "U1" H 6550 3950 30 0000 C CNN +F 1 "PORT" H 6500 3850 30 0000 C CNN +F 2 "" H 6500 3850 60 0000 C CNN +F 3 "" H 6500 3850 60 0000 C CNN + 13 6500 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62C2AC1F +P 3650 1350 +F 0 "U1" H 3700 1450 30 0000 C CNN +F 1 "PORT" H 3650 1350 30 0000 C CNN +F 2 "" H 3650 1350 60 0000 C CNN +F 3 "" H 3650 1350 60 0000 C CNN + 14 3650 1350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000.sub b/library/SubcircuitLibrary/CD_4000/CD_4000.sub new file mode 100644 index 00000000..15439f70 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000.sub @@ -0,0 +1,22 @@ +* Subcircuit CD_4000 +.subckt CD_4000 net-_m1-pad2_ net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad1_ net-_m1-pad3_ net-_m7-pad2_ net-_m7-pad1_ net-_m10-pad1_ net-_m11-pad2_ net-_m10-pad2_ net-_m13-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4000\cd_4000.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m2-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m5-pad2_ net-_m4-pad1_ net-_m4-pad1_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m10-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m10-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad1_ net-_m13-pad2_ net-_m12-pad1_ net-_m12-pad1_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4000 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4000/CD_4000_Previous_Values.xml b/library/SubcircuitLibrary/CD_4000/CD_4000_Previous_Values.xml new file mode 100644 index 00000000..d8fed1b2 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/CD_4000_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4000/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4000/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4000/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4000/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4000/README.md b/library/SubcircuitLibrary/CD_4000/README.md new file mode 100644 index 00000000..f75cfe00 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/README.md @@ -0,0 +1,25 @@ + +# CD4000 IC + +It is dual 3-input NOR Gate IC. CD4000 IC is designed with 180nm CMOS technology in eSim consisting two NOR Gates and one NOT Gate. When all the inputs are LOW, then only output is HIGH, else LOW for NOR gate and NOT gate inverts the input as output. +## Usage/Examples + +Multiplexer + +Crystal oscillator + +Phase Locked Loop (PLL) +## Documentation + +To know the details of CD4000 IC please go through with the documentation : [CD4000_datasheet](http://eeshop.unl.edu/pdf/CD4000.pdf) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4000/analysis b/library/SubcircuitLibrary/CD_4000/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4000/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 0c8e849d3dc0fed85a8acf2193a6d5e6bd13cc5c Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:47:18 +0530 Subject: CD4008 is 4 bit Full Adder IC. --- .../SubcircuitLibrary/CD_4008/Adder_2bit-cache.lib | 100 + library/SubcircuitLibrary/CD_4008/Adder_2bit.cir | 95 + .../SubcircuitLibrary/CD_4008/Adder_2bit.cir.out | 98 + library/SubcircuitLibrary/CD_4008/Adder_2bit.pro | 71 + library/SubcircuitLibrary/CD_4008/Adder_2bit.sch | 2101 ++++++++++++++++++++ library/SubcircuitLibrary/CD_4008/Adder_2bit.sub | 92 + .../CD_4008/Adder_2bit_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD_4008/CD_4008-cache.lib | 66 + library/SubcircuitLibrary/CD_4008/CD_4008.cir | 13 + library/SubcircuitLibrary/CD_4008/CD_4008.cir.out | 15 + library/SubcircuitLibrary/CD_4008/CD_4008.pro | 71 + library/SubcircuitLibrary/CD_4008/CD_4008.sch | 353 ++++ library/SubcircuitLibrary/CD_4008/CD_4008.sub | 9 + .../CD_4008/CD_4008_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4008/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4008/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4008/README.md | 27 + library/SubcircuitLibrary/CD_4008/analysis | 1 + 18 files changed, 3138 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit.cir create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit.cir.out create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit.pro create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit.sch create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit.sub create mode 100644 library/SubcircuitLibrary/CD_4008/Adder_2bit_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008.cir create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008.cir.out create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008.pro create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008.sch create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008.sub create mode 100644 library/SubcircuitLibrary/CD_4008/CD_4008_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4008/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4008/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4008/README.md create mode 100644 library/SubcircuitLibrary/CD_4008/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit-cache.lib b/library/SubcircuitLibrary/CD_4008/Adder_2bit-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir b/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir new file mode 100644 index 00000000..08ebd25f --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir @@ -0,0 +1,95 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Adder_2bit\Adder_2bit.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/22 13:42:53 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M18 Net-_M18-Pad1_ Net-_M1-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M28 Net-_M18-Pad1_ Net-_M14-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M19 Net-_M19-Pad1_ Net-_M19-Pad2_ Net-_M18-Pad1_ Net-_M18-Pad1_ eSim_MOS_P +M29 Net-_M19-Pad1_ Net-_M10-Pad2_ Net-_M18-Pad1_ Net-_M18-Pad1_ eSim_MOS_P +M67 Net-_M64-Pad1_ Net-_M13-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M64 Net-_M64-Pad1_ Net-_M13-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M42 Net-_M19-Pad1_ Net-_M17-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M20 Net-_M20-Pad1_ Net-_M1-Pad2_ Net-_M19-Pad1_ Net-_M19-Pad1_ eSim_MOS_P +M30 Net-_M20-Pad1_ Net-_M10-Pad2_ Net-_M19-Pad1_ Net-_M19-Pad1_ eSim_MOS_P +M21 Net-_M13-Pad1_ Net-_M19-Pad2_ Net-_M20-Pad1_ Net-_M20-Pad1_ eSim_MOS_P +M31 Net-_M13-Pad1_ Net-_M14-Pad2_ Net-_M20-Pad1_ Net-_M20-Pad1_ eSim_MOS_P +M43 Net-_M13-Pad1_ Net-_M11-Pad2_ Net-_M19-Pad1_ Net-_M19-Pad1_ eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M1-Pad2_ Net-_M13-Pad3_ Net-_M13-Pad3_ eSim_MOS_N +M14 Net-_M13-Pad3_ Net-_M14-Pad2_ Net-_M14-Pad3_ Net-_M14-Pad3_ eSim_MOS_N +M24 Net-_M13-Pad1_ Net-_M19-Pad2_ Net-_M24-Pad3_ Net-_M24-Pad3_ eSim_MOS_N +M25 Net-_M24-Pad3_ Net-_M10-Pad2_ Net-_M14-Pad3_ Net-_M14-Pad3_ eSim_MOS_N +M17 Net-_M14-Pad3_ Net-_M17-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M35 Net-_M13-Pad1_ Net-_M1-Pad2_ Net-_M35-Pad3_ Net-_M35-Pad3_ eSim_MOS_N +M36 Net-_M35-Pad3_ Net-_M10-Pad2_ Net-_M36-Pad3_ Net-_M36-Pad3_ eSim_MOS_N +M49 Net-_M13-Pad1_ Net-_M19-Pad2_ Net-_M49-Pad3_ Net-_M49-Pad3_ eSim_MOS_N +M50 Net-_M49-Pad3_ Net-_M14-Pad2_ Net-_M36-Pad3_ Net-_M36-Pad3_ eSim_MOS_N +M41 Net-_M36-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M7 Net-_M19-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M6 Net-_M19-Pad2_ Net-_M1-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M61 Net-_M14-Pad2_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M63 Net-_M14-Pad2_ Net-_M10-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M58 Net-_M17-Pad2_ Net-_M11-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M59 Net-_M17-Pad2_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M3 Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M4 Net-_M11-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_P +M5 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M12 Net-_M1-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M2 Net-_M1-Pad3_ Net-_M10-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M8 Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_N +M9 Net-_M8-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M15 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N +M16 Net-_M15-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M23 Net-_M22-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M22 Net-_M22-Pad1_ Net-_M1-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M54 Net-_M54-Pad1_ Net-_M26-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M68 Net-_M54-Pad1_ Net-_M48-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M55 Net-_M55-Pad1_ Net-_M37-Pad1_ Net-_M54-Pad1_ Net-_M54-Pad1_ eSim_MOS_P +M69 Net-_M55-Pad1_ Net-_M27-Pad2_ Net-_M54-Pad1_ Net-_M54-Pad1_ eSim_MOS_P +M84 Net-_M83-Pad1_ Net-_M47-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M83 Net-_M83-Pad1_ Net-_M47-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M75 Net-_M55-Pad1_ Net-_M53-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M56 Net-_M56-Pad1_ Net-_M26-Pad2_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M70 Net-_M56-Pad1_ Net-_M27-Pad2_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M57 Net-_M47-Pad1_ Net-_M37-Pad1_ Net-_M56-Pad1_ Net-_M56-Pad1_ eSim_MOS_P +M71 Net-_M47-Pad1_ Net-_M48-Pad2_ Net-_M56-Pad1_ Net-_M56-Pad1_ eSim_MOS_P +M76 Net-_M47-Pad1_ Net-_M22-Pad1_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M47 Net-_M47-Pad1_ Net-_M26-Pad2_ Net-_M47-Pad3_ Net-_M47-Pad3_ eSim_MOS_N +M48 Net-_M47-Pad3_ Net-_M48-Pad2_ Net-_M48-Pad3_ Net-_M48-Pad3_ eSim_MOS_N +M65 Net-_M47-Pad1_ Net-_M37-Pad1_ Net-_M65-Pad3_ Net-_M65-Pad3_ eSim_MOS_N +M66 Net-_M65-Pad3_ Net-_M27-Pad2_ Net-_M48-Pad3_ Net-_M48-Pad3_ eSim_MOS_N +M53 Net-_M48-Pad3_ Net-_M53-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M72 Net-_M47-Pad1_ Net-_M26-Pad2_ Net-_M72-Pad3_ Net-_M72-Pad3_ eSim_MOS_N +M73 Net-_M72-Pad3_ Net-_M27-Pad2_ Net-_M73-Pad3_ Net-_M73-Pad3_ eSim_MOS_N +M77 Net-_M47-Pad1_ Net-_M37-Pad1_ Net-_M77-Pad3_ Net-_M77-Pad3_ eSim_MOS_N +M78 Net-_M77-Pad3_ Net-_M48-Pad2_ Net-_M73-Pad3_ Net-_M73-Pad3_ eSim_MOS_N +M74 Net-_M73-Pad3_ Net-_M22-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M38 Net-_M37-Pad1_ Net-_M26-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M37 Net-_M37-Pad1_ Net-_M26-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M81 Net-_M48-Pad2_ Net-_M27-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M82 Net-_M48-Pad2_ Net-_M27-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M79 Net-_M53-Pad2_ Net-_M22-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M80 Net-_M53-Pad2_ Net-_M22-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M32 Net-_M32-Pad1_ Net-_M26-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M44 Net-_M32-Pad1_ Net-_M27-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M33 Net-_M33-Pad1_ Net-_M27-Pad2_ Net-_M32-Pad1_ Net-_M32-Pad1_ eSim_MOS_P +M45 Net-_M33-Pad1_ Net-_M22-Pad1_ Net-_M32-Pad1_ Net-_M32-Pad1_ eSim_MOS_P +M34 Net-_M26-Pad1_ Net-_M26-Pad2_ Net-_M33-Pad1_ Net-_M33-Pad1_ eSim_MOS_P +M46 Net-_M26-Pad1_ Net-_M22-Pad1_ Net-_M33-Pad1_ Net-_M33-Pad1_ eSim_MOS_P +M26 Net-_M26-Pad1_ Net-_M26-Pad2_ Net-_M26-Pad3_ Net-_M26-Pad3_ eSim_MOS_N +M27 Net-_M26-Pad3_ Net-_M27-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M39 Net-_M26-Pad1_ Net-_M27-Pad2_ Net-_M39-Pad3_ Net-_M39-Pad3_ eSim_MOS_N +M40 Net-_M39-Pad3_ Net-_M22-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M51 Net-_M26-Pad1_ Net-_M26-Pad2_ Net-_M51-Pad3_ Net-_M51-Pad3_ eSim_MOS_N +M52 Net-_M51-Pad3_ Net-_M22-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M62 Net-_M60-Pad1_ Net-_M26-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M60 Net-_M60-Pad1_ Net-_M26-Pad1_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +U1 Net-_M27-Pad2_ Net-_M26-Pad2_ Net-_M10-Pad2_ Net-_M1-Pad2_ Net-_M16-Pad3_ Net-_M11-Pad2_ Net-_M64-Pad1_ Net-_M83-Pad1_ Net-_M10-Pad3_ Net-_M60-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir.out b/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir.out new file mode 100644 index 00000000..4779b944 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit.cir.out @@ -0,0 +1,98 @@ +* c:\fossee\esim\library\subcircuitlibrary\adder_2bit\adder_2bit.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m18 net-_m18-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m28 net-_m18-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m19 net-_m19-pad1_ net-_m19-pad2_ net-_m18-pad1_ net-_m18-pad1_ CMOSP W=100u L=100u M=1 +m29 net-_m19-pad1_ net-_m10-pad2_ net-_m18-pad1_ net-_m18-pad1_ CMOSP W=100u L=100u M=1 +m67 net-_m64-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m64 net-_m64-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m42 net-_m19-pad1_ net-_m17-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m20 net-_m20-pad1_ net-_m1-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m30 net-_m20-pad1_ net-_m10-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m21 net-_m13-pad1_ net-_m19-pad2_ net-_m20-pad1_ net-_m20-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m13-pad1_ net-_m14-pad2_ net-_m20-pad1_ net-_m20-pad1_ CMOSP W=100u L=100u M=1 +m43 net-_m13-pad1_ net-_m11-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m1-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m14-pad3_ net-_m14-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m13-pad1_ net-_m19-pad2_ net-_m24-pad3_ net-_m24-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m24-pad3_ net-_m10-pad2_ net-_m14-pad3_ net-_m14-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m14-pad3_ net-_m17-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m35 net-_m13-pad1_ net-_m1-pad2_ net-_m35-pad3_ net-_m35-pad3_ CMOSN W=100u L=100u M=1 +m36 net-_m35-pad3_ net-_m10-pad2_ net-_m36-pad3_ net-_m36-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m13-pad1_ net-_m19-pad2_ net-_m49-pad3_ net-_m49-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m49-pad3_ net-_m14-pad2_ net-_m36-pad3_ net-_m36-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m36-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m19-pad2_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m19-pad2_ net-_m1-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m61 net-_m14-pad2_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m63 net-_m14-pad2_ net-_m10-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m17-pad2_ net-_m11-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m59 net-_m17-pad2_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m10-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m12 net-_m1-pad1_ net-_m11-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m1-pad3_ net-_m10-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m1-pad1_ net-_m10-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m1-pad1_ net-_m1-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m22-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m1-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m54 net-_m54-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m68 net-_m54-pad1_ net-_m48-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m55 net-_m55-pad1_ net-_m37-pad1_ net-_m54-pad1_ net-_m54-pad1_ CMOSP W=100u L=100u M=1 +m69 net-_m55-pad1_ net-_m27-pad2_ net-_m54-pad1_ net-_m54-pad1_ CMOSP W=100u L=100u M=1 +m84 net-_m83-pad1_ net-_m47-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m83 net-_m83-pad1_ net-_m47-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m75 net-_m55-pad1_ net-_m53-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m56 net-_m56-pad1_ net-_m26-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m70 net-_m56-pad1_ net-_m27-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 net-_m47-pad1_ net-_m37-pad1_ net-_m56-pad1_ net-_m56-pad1_ CMOSP W=100u L=100u M=1 +m71 net-_m47-pad1_ net-_m48-pad2_ net-_m56-pad1_ net-_m56-pad1_ CMOSP W=100u L=100u M=1 +m76 net-_m47-pad1_ net-_m22-pad1_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m47 net-_m47-pad1_ net-_m26-pad2_ net-_m47-pad3_ net-_m47-pad3_ CMOSN W=100u L=100u M=1 +m48 net-_m47-pad3_ net-_m48-pad2_ net-_m48-pad3_ net-_m48-pad3_ CMOSN W=100u L=100u M=1 +m65 net-_m47-pad1_ net-_m37-pad1_ net-_m65-pad3_ net-_m65-pad3_ CMOSN W=100u L=100u M=1 +m66 net-_m65-pad3_ net-_m27-pad2_ net-_m48-pad3_ net-_m48-pad3_ CMOSN W=100u L=100u M=1 +m53 net-_m48-pad3_ net-_m53-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m72 net-_m47-pad1_ net-_m26-pad2_ net-_m72-pad3_ net-_m72-pad3_ CMOSN W=100u L=100u M=1 +m73 net-_m72-pad3_ net-_m27-pad2_ net-_m73-pad3_ net-_m73-pad3_ CMOSN W=100u L=100u M=1 +m77 net-_m47-pad1_ net-_m37-pad1_ net-_m77-pad3_ net-_m77-pad3_ CMOSN W=100u L=100u M=1 +m78 net-_m77-pad3_ net-_m48-pad2_ net-_m73-pad3_ net-_m73-pad3_ CMOSN W=100u L=100u M=1 +m74 net-_m73-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m38 net-_m37-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m37 net-_m37-pad1_ net-_m26-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m81 net-_m48-pad2_ net-_m27-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m82 net-_m48-pad2_ net-_m27-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m79 net-_m53-pad2_ net-_m22-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m80 net-_m53-pad2_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m32 net-_m32-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m44 net-_m32-pad1_ net-_m27-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m27-pad2_ net-_m32-pad1_ net-_m32-pad1_ CMOSP W=100u L=100u M=1 +m45 net-_m33-pad1_ net-_m22-pad1_ net-_m32-pad1_ net-_m32-pad1_ CMOSP W=100u L=100u M=1 +m34 net-_m26-pad1_ net-_m26-pad2_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m46 net-_m26-pad1_ net-_m22-pad1_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m26 net-_m26-pad1_ net-_m26-pad2_ net-_m26-pad3_ net-_m26-pad3_ CMOSN W=100u L=100u M=1 +m27 net-_m26-pad3_ net-_m27-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m26-pad1_ net-_m27-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m51 net-_m26-pad1_ net-_m26-pad2_ net-_m51-pad3_ net-_m51-pad3_ CMOSN W=100u L=100u M=1 +m52 net-_m51-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m62 net-_m60-pad1_ net-_m26-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m60 net-_m60-pad1_ net-_m26-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m27-pad2_ net-_m26-pad2_ net-_m10-pad2_ net-_m1-pad2_ net-_m16-pad3_ net-_m11-pad2_ net-_m64-pad1_ net-_m83-pad1_ net-_m10-pad3_ net-_m60-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit.pro b/library/SubcircuitLibrary/CD_4008/Adder_2bit.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit.sch b/library/SubcircuitLibrary/CD_4008/Adder_2bit.sch new file mode 100644 index 00000000..4f7e97e3 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit.sch @@ -0,0 +1,2101 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4008_Adder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M18 +U 1 1 62986DF2 +P -8800 -3350 +F 0 "M18" H -8850 -3300 50 0000 R CNN +F 1 "eSim_MOS_P" H -8750 -3200 50 0000 R CNN +F 2 "" H -8550 -3250 29 0000 C CNN +F 3 "" H -8750 -3350 60 0000 C CNN + 1 -8800 -3350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M28 +U 1 1 62986DF3 +P -8100 -3350 +F 0 "M28" H -8150 -3300 50 0000 R CNN +F 1 "eSim_MOS_P" H -8050 -3200 50 0000 R CNN +F 2 "" H -7850 -3250 29 0000 C CNN +F 3 "" H -8050 -3350 60 0000 C CNN + 1 -8100 -3350 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M19 +U 1 1 62986DF4 +P -8800 -2850 +F 0 "M19" H -8850 -2800 50 0000 R CNN +F 1 "eSim_MOS_P" H -8750 -2700 50 0000 R CNN +F 2 "" H -8550 -2750 29 0000 C CNN +F 3 "" H -8750 -2850 60 0000 C CNN + 1 -8800 -2850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M29 +U 1 1 62986DF5 +P -8100 -2850 +F 0 "M29" H -8150 -2800 50 0000 R CNN +F 1 "eSim_MOS_P" H -8050 -2700 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-5000 -3100 30 0000 C CNN +F 2 "" H -5000 -3100 60 0000 C CNN +F 3 "" H -5000 -3100 60 0000 C CNN + 6 -5000 -3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 62998792 +P -5000 -2200 +F 0 "U1" H -4950 -2100 30 0000 C CNN +F 1 "PORT" H -5000 -2200 30 0000 C CNN +F 2 "" H -5000 -2200 60 0000 C CNN +F 3 "" H -5000 -2200 60 0000 C CNN + 9 -5000 -2200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6299963D +P -5200 -1550 +F 0 "U1" H -5150 -1450 30 0000 C CNN +F 1 "PORT" H -5200 -1550 30 0000 C CNN +F 2 "" H -5200 -1550 60 0000 C CNN +F 3 "" H -5200 -1550 60 0000 C CNN + 10 -5200 -1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6299FB00 +P -8650 5200 +F 0 "U1" H -8600 5300 30 0000 C CNN +F 1 "PORT" H -8650 5200 30 0000 C CNN +F 2 "" H -8650 5200 60 0000 C CNN +F 3 "" H -8650 5200 60 0000 C CNN + 5 -8650 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 629A0EB3 +P -2800 5200 +F 0 "U1" H -2750 5300 30 0000 C CNN +F 1 "PORT" H -2800 5200 30 0000 C CNN +F 2 "" H -2800 5200 60 0000 C CNN +F 3 "" H -2800 5200 60 0000 C CNN + 4 -2800 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 629A4397 +P -3000 6750 +F 0 "U1" H -2950 6850 30 0000 C CNN +F 1 "PORT" H -3000 6750 30 0000 C CNN +F 2 "" H -3000 6750 60 0000 C CNN +F 3 "" H -3000 6750 60 0000 C CNN + 11 -3000 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 629A56CE +P -2550 10050 +F 0 "U1" H -2500 10150 30 0000 C CNN +F 1 "PORT" H -2550 10050 30 0000 C CNN +F 2 "" H -2550 10050 60 0000 C CNN +F 3 "" H -2550 10050 60 0000 C CNN + 17 -2550 10050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 629A86A4 +P -4900 11450 +F 0 "U1" H -4850 11550 30 0000 C CNN +F 1 "PORT" H -4900 11450 30 0000 C CNN +F 2 "" H -4900 11450 60 0000 C CNN +F 3 "" H -4900 11450 60 0000 C CNN + 8 -4900 11450 + -1 0 0 1 +$EndComp +Wire Wire Line + -5200 11450 -5150 11450 +Connection ~ -5200 10950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit.sub b/library/SubcircuitLibrary/CD_4008/Adder_2bit.sub new file mode 100644 index 00000000..f94f0c02 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit.sub @@ -0,0 +1,92 @@ +* Subcircuit Adder_2bit +.subckt Adder_2bit net-_m27-pad2_ net-_m26-pad2_ net-_m10-pad2_ net-_m1-pad2_ net-_m16-pad3_ net-_m11-pad2_ net-_m64-pad1_ net-_m83-pad1_ net-_m10-pad3_ net-_m60-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\adder_2bit\adder_2bit.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m18 net-_m18-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m28 net-_m18-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m19 net-_m19-pad1_ net-_m19-pad2_ net-_m18-pad1_ net-_m18-pad1_ CMOSP W=100u L=100u M=1 +m29 net-_m19-pad1_ net-_m10-pad2_ net-_m18-pad1_ net-_m18-pad1_ CMOSP W=100u L=100u M=1 +m67 net-_m64-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m64 net-_m64-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m42 net-_m19-pad1_ net-_m17-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m20 net-_m20-pad1_ net-_m1-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m30 net-_m20-pad1_ net-_m10-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m21 net-_m13-pad1_ net-_m19-pad2_ net-_m20-pad1_ net-_m20-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m13-pad1_ net-_m14-pad2_ net-_m20-pad1_ net-_m20-pad1_ CMOSP W=100u L=100u M=1 +m43 net-_m13-pad1_ net-_m11-pad2_ net-_m19-pad1_ net-_m19-pad1_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m1-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m14-pad3_ net-_m14-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m13-pad1_ net-_m19-pad2_ net-_m24-pad3_ net-_m24-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m24-pad3_ net-_m10-pad2_ net-_m14-pad3_ net-_m14-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m14-pad3_ net-_m17-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m35 net-_m13-pad1_ net-_m1-pad2_ net-_m35-pad3_ net-_m35-pad3_ CMOSN W=100u L=100u M=1 +m36 net-_m35-pad3_ net-_m10-pad2_ net-_m36-pad3_ net-_m36-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m13-pad1_ net-_m19-pad2_ net-_m49-pad3_ net-_m49-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m49-pad3_ net-_m14-pad2_ net-_m36-pad3_ net-_m36-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m36-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m19-pad2_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m19-pad2_ net-_m1-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m61 net-_m14-pad2_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m63 net-_m14-pad2_ net-_m10-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m17-pad2_ net-_m11-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m59 net-_m17-pad2_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m10-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m12 net-_m1-pad1_ net-_m11-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m1-pad3_ net-_m10-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m1-pad1_ net-_m10-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m1-pad1_ net-_m1-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m22-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m1-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m54 net-_m54-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m68 net-_m54-pad1_ net-_m48-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m55 net-_m55-pad1_ net-_m37-pad1_ net-_m54-pad1_ net-_m54-pad1_ CMOSP W=100u L=100u M=1 +m69 net-_m55-pad1_ net-_m27-pad2_ net-_m54-pad1_ net-_m54-pad1_ CMOSP W=100u L=100u M=1 +m84 net-_m83-pad1_ net-_m47-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m83 net-_m83-pad1_ net-_m47-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m75 net-_m55-pad1_ net-_m53-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m56 net-_m56-pad1_ net-_m26-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m70 net-_m56-pad1_ net-_m27-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 net-_m47-pad1_ net-_m37-pad1_ net-_m56-pad1_ net-_m56-pad1_ CMOSP W=100u L=100u M=1 +m71 net-_m47-pad1_ net-_m48-pad2_ net-_m56-pad1_ net-_m56-pad1_ CMOSP W=100u L=100u M=1 +m76 net-_m47-pad1_ net-_m22-pad1_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m47 net-_m47-pad1_ net-_m26-pad2_ net-_m47-pad3_ net-_m47-pad3_ CMOSN W=100u L=100u M=1 +m48 net-_m47-pad3_ net-_m48-pad2_ net-_m48-pad3_ net-_m48-pad3_ CMOSN W=100u L=100u M=1 +m65 net-_m47-pad1_ net-_m37-pad1_ net-_m65-pad3_ net-_m65-pad3_ CMOSN W=100u L=100u M=1 +m66 net-_m65-pad3_ net-_m27-pad2_ net-_m48-pad3_ net-_m48-pad3_ CMOSN W=100u L=100u M=1 +m53 net-_m48-pad3_ net-_m53-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m72 net-_m47-pad1_ net-_m26-pad2_ net-_m72-pad3_ net-_m72-pad3_ CMOSN W=100u L=100u M=1 +m73 net-_m72-pad3_ net-_m27-pad2_ net-_m73-pad3_ net-_m73-pad3_ CMOSN W=100u L=100u M=1 +m77 net-_m47-pad1_ net-_m37-pad1_ net-_m77-pad3_ net-_m77-pad3_ CMOSN W=100u L=100u M=1 +m78 net-_m77-pad3_ net-_m48-pad2_ net-_m73-pad3_ net-_m73-pad3_ CMOSN W=100u L=100u M=1 +m74 net-_m73-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m38 net-_m37-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m37 net-_m37-pad1_ net-_m26-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m81 net-_m48-pad2_ net-_m27-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m82 net-_m48-pad2_ net-_m27-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m79 net-_m53-pad2_ net-_m22-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m80 net-_m53-pad2_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m32 net-_m32-pad1_ net-_m26-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m44 net-_m32-pad1_ net-_m27-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m27-pad2_ net-_m32-pad1_ net-_m32-pad1_ CMOSP W=100u L=100u M=1 +m45 net-_m33-pad1_ net-_m22-pad1_ net-_m32-pad1_ net-_m32-pad1_ CMOSP W=100u L=100u M=1 +m34 net-_m26-pad1_ net-_m26-pad2_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m46 net-_m26-pad1_ net-_m22-pad1_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m26 net-_m26-pad1_ net-_m26-pad2_ net-_m26-pad3_ net-_m26-pad3_ CMOSN W=100u L=100u M=1 +m27 net-_m26-pad3_ net-_m27-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m26-pad1_ net-_m27-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m51 net-_m26-pad1_ net-_m26-pad2_ net-_m51-pad3_ net-_m51-pad3_ CMOSN W=100u L=100u M=1 +m52 net-_m51-pad3_ net-_m22-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m62 net-_m60-pad1_ net-_m26-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m60 net-_m60-pad1_ net-_m26-pad1_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends Adder_2bit \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4008/Adder_2bit_Previous_Values.xml b/library/SubcircuitLibrary/CD_4008/Adder_2bit_Previous_Values.xml new file mode 100644 index 00000000..f015d34c --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/Adder_2bit_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008-cache.lib b/library/SubcircuitLibrary/CD_4008/CD_4008-cache.lib new file mode 100644 index 00000000..fe35cb8f --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008-cache.lib @@ -0,0 +1,66 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Adder_2Bit +# +DEF Adder_2Bit X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Adder_2Bit" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 650 450 -550 0 1 0 N +X B1 4 -650 150 200 R 50 50 1 1 I +X A1 5 -650 0 200 R 50 50 1 1 I +X B0 6 -650 -150 200 R 50 50 1 1 I +X A0 7 -650 -300 200 R 50 50 1 1 I +X GND 8 -650 -450 200 R 50 50 1 1 I +X Cin 9 650 -450 200 L 50 50 1 1 O +X S0 10 650 -300 200 L 50 50 1 1 O +X S1 11 650 -150 200 L 50 50 1 1 O +X VDD 16 650 550 200 L 50 50 1 1 I +X Co 17 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.cir b/library/SubcircuitLibrary/CD_4008/CD_4008.cir new file mode 100644 index 00000000..6909def4 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4008\CD_4008.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/22 20:13:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad16_ Net-_X1-Pad17_ Adder_2Bit +X2 Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad8_ Net-_X1-Pad17_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad16_ Net-_U1-Pad14_ Adder_2Bit +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.cir.out b/library/SubcircuitLibrary/CD_4008/CD_4008.cir.out new file mode 100644 index 00000000..3d2544ee --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008.cir.out @@ -0,0 +1,15 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4008\cd_4008.cir + +.include Adder_2bit.sub +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad16_ net-_x1-pad17_ Adder_2bit +x2 net-_u1-pad15_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad8_ net-_x1-pad17_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad16_ net-_u1-pad14_ Adder_2bit +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.pro b/library/SubcircuitLibrary/CD_4008/CD_4008.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.sch b/library/SubcircuitLibrary/CD_4008/CD_4008.sch new file mode 100644 index 00000000..e10152f2 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008.sch @@ -0,0 +1,353 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD4008_ADDER_4bit-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Adder_2Bit X1 +U 1 1 6298C667 +P 4950 4150 +F 0 "X1" H 4950 4150 60 0000 C CNN +F 1 "Adder_2Bit" H 4950 4250 60 0000 C CNN +F 2 "" H 4950 4150 60 0001 C CNN +F 3 "" H 4950 4150 60 0001 C CNN + 1 4950 4150 + 1 0 0 -1 +$EndComp +$Comp +L Adder_2Bit X2 +U 1 1 6298C668 +P 6600 4150 +F 0 "X2" H 6600 4150 60 0000 C CNN +F 1 "Adder_2Bit" H 6600 4250 60 0000 C CNN +F 2 "" H 6600 4150 60 0001 C CNN +F 3 "" H 6600 4150 60 0001 C CNN + 1 6600 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 4000 5750 4000 +Wire Wire Line + 5750 4000 5750 4800 +Wire Wire Line + 5750 4800 7250 4800 +Wire Wire Line + 7250 4800 7250 4600 +Wire Wire Line + 7250 2850 7250 3600 +Wire Wire Line + 7250 3400 5600 3400 +Wire Wire Line + 5600 3400 5600 3600 +Wire Wire Line + 5950 4850 5950 4600 +Wire Wire Line + 4300 4850 5950 4850 +Wire Wire Line + 4300 4850 4300 4600 +Wire Wire Line + 2700 2000 4300 2000 +Wire Wire Line + 4300 2000 4300 4000 +Wire Wire Line + 2700 2450 3850 2450 +Wire Wire Line + 3850 2450 3850 4150 +Wire Wire Line + 3850 4150 4300 4150 +Wire Wire Line + 2700 2950 3600 2950 +Wire Wire Line + 3600 2950 3600 4300 +Wire Wire Line + 3600 4300 4300 4300 +Wire Wire Line + 2700 3500 3400 3500 +Wire Wire Line + 3400 3500 3400 4450 +Wire Wire Line + 3400 4450 4300 4450 +Wire Wire Line + 5650 2850 5650 4300 +Wire Wire Line + 5650 4300 5600 4300 +Wire Wire Line + 5750 3100 5700 3100 +Wire Wire Line + 5700 3100 5700 4450 +Wire Wire Line + 5700 4450 5600 4450 +Wire Wire Line + 2700 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 3700 +Wire Wire Line + 3200 3700 5950 3700 +Wire Wire Line + 5950 3700 5950 4000 +Wire Wire Line + 2700 4500 3300 4500 +Wire Wire Line + 3300 4500 3300 3800 +Wire Wire Line + 3300 3800 5900 3800 +Wire Wire Line + 5900 3800 5900 4150 +Wire Wire Line + 5900 4150 5950 4150 +Wire Wire Line + 2700 5000 5800 5000 +Wire Wire Line + 5800 5000 5800 4300 +Wire Wire Line + 5800 4300 5950 4300 +Wire Wire Line + 2700 5550 5900 5550 +Wire Wire Line + 5900 5550 5900 4450 +Wire Wire Line + 5900 4450 5950 4450 +Wire Wire Line + 7250 4300 7500 4300 +Wire Wire Line + 7250 4450 7500 4450 +Wire Wire Line + 7500 4450 7500 4550 +Wire Wire Line + 7250 4000 7550 4000 +Wire Wire Line + 6400 4900 5600 4900 +Wire Wire Line + 5600 4900 5600 4600 +Wire Wire Line + 7250 2850 7300 2850 +Connection ~ 7250 3400 +Connection ~ 5200 4850 +Wire Wire Line + 5200 5800 5200 4850 +$Comp +L PORT U1 +U 1 1 6298E683 +P 2450 4500 +F 0 "U1" H 2500 4600 30 0000 C CNN +F 1 "PORT" H 2450 4500 30 0000 C CNN +F 2 "" H 2450 4500 60 0000 C CNN +F 3 "" H 2450 4500 60 0000 C CNN + 1 2450 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6298E6C8 +P 2450 5000 +F 0 "U1" H 2500 5100 30 0000 C CNN +F 1 "PORT" H 2450 5000 30 0000 C CNN +F 2 "" H 2450 5000 60 0000 C CNN +F 3 "" H 2450 5000 60 0000 C CNN + 2 2450 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6298E74C +P 2450 5550 +F 0 "U1" H 2500 5650 30 0000 C CNN +F 1 "PORT" H 2450 5550 30 0000 C CNN +F 2 "" H 2450 5550 60 0000 C CNN +F 3 "" H 2450 5550 60 0000 C CNN + 3 2450 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6298EDFF +P 2450 4050 +F 0 "U1" H 2500 4150 30 0000 C CNN +F 1 "PORT" H 2450 4050 30 0000 C CNN +F 2 "" H 2450 4050 60 0000 C CNN +F 3 "" H 2450 4050 60 0000 C CNN + 15 2450 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6298F2EA +P 2450 3500 +F 0 "U1" H 2500 3600 30 0000 C CNN +F 1 "PORT" H 2450 3500 30 0000 C CNN +F 2 "" H 2450 3500 60 0000 C CNN +F 3 "" H 2450 3500 60 0000 C CNN + 7 2450 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6298F38C +P 2450 2950 +F 0 "U1" H 2500 3050 30 0000 C CNN +F 1 "PORT" H 2450 2950 30 0000 C CNN +F 2 "" H 2450 2950 60 0000 C CNN +F 3 "" H 2450 2950 60 0000 C CNN + 6 2450 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6298F3CD +P 2450 2450 +F 0 "U1" H 2500 2550 30 0000 C CNN +F 1 "PORT" H 2450 2450 30 0000 C CNN +F 2 "" H 2450 2450 60 0000 C CNN +F 3 "" H 2450 2450 60 0000 C CNN + 5 2450 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6298F420 +P 2450 2000 +F 0 "U1" H 2500 2100 30 0000 C CNN +F 1 "PORT" H 2450 2000 30 0000 C CNN +F 2 "" H 2450 2000 60 0000 C CNN +F 3 "" H 2450 2000 60 0000 C CNN + 4 2450 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6298FEA6 +P 4950 5800 +F 0 "U1" H 5000 5900 30 0000 C CNN +F 1 "PORT" H 4950 5800 30 0000 C CNN +F 2 "" H 4950 5800 60 0000 C CNN +F 3 "" H 4950 5800 60 0000 C CNN + 8 4950 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62990870 +P 6650 4900 +F 0 "U1" H 6700 5000 30 0000 C CNN +F 1 "PORT" H 6650 4900 30 0000 C CNN +F 2 "" H 6650 4900 60 0000 C CNN +F 3 "" H 6650 4900 60 0000 C CNN + 9 6650 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 62990AD2 +P 6000 3100 +F 0 "U1" H 6050 3200 30 0000 C CNN +F 1 "PORT" H 6000 3100 30 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 10 6000 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 62990B25 +P 5900 2850 +F 0 "U1" H 5950 2950 30 0000 C CNN +F 1 "PORT" H 5900 2850 30 0000 C CNN +F 2 "" H 5900 2850 60 0000 C CNN +F 3 "" H 5900 2850 60 0000 C CNN + 11 5900 2850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62990C76 +P 7750 4550 +F 0 "U1" H 7800 4650 30 0000 C CNN +F 1 "PORT" H 7750 4550 30 0000 C CNN +F 2 "" H 7750 4550 60 0000 C CNN +F 3 "" H 7750 4550 60 0000 C CNN + 12 7750 4550 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62990CD3 +P 7750 4300 +F 0 "U1" H 7800 4400 30 0000 C CNN +F 1 "PORT" H 7750 4300 30 0000 C CNN +F 2 "" H 7750 4300 60 0000 C CNN +F 3 "" H 7750 4300 60 0000 C CNN + 13 7750 4300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62990D95 +P 7800 4000 +F 0 "U1" H 7850 4100 30 0000 C CNN +F 1 "PORT" H 7800 4000 30 0000 C CNN +F 2 "" H 7800 4000 60 0000 C CNN +F 3 "" H 7800 4000 60 0000 C CNN + 14 7800 4000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62990E29 +P 7550 2850 +F 0 "U1" H 7600 2950 30 0000 C CNN +F 1 "PORT" H 7550 2850 30 0000 C CNN +F 2 "" H 7550 2850 60 0000 C CNN +F 3 "" H 7550 2850 60 0000 C CNN + 16 7550 2850 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008.sub b/library/SubcircuitLibrary/CD_4008/CD_4008.sub new file mode 100644 index 00000000..8f8b1fc1 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008.sub @@ -0,0 +1,9 @@ +* Subcircuit CD_4008 +.subckt CD_4008 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4008\cd_4008.cir +.include Adder_2bit.sub +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad16_ net-_x1-pad17_ Adder_2bit +x2 net-_u1-pad15_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad8_ net-_x1-pad17_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad16_ net-_u1-pad14_ Adder_2bit +* Control Statements + +.ends CD_4008 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4008/CD_4008_Previous_Values.xml b/library/SubcircuitLibrary/CD_4008/CD_4008_Previous_Values.xml new file mode 100644 index 00000000..ed759a67 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/CD_4008_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\SubcircuitLibrary\Adder_2bitC:\FOSSEE\eSim\library\SubcircuitLibrary\Adder_2bit \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4008/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4008/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4008/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4008/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4008/README.md b/library/SubcircuitLibrary/CD_4008/README.md new file mode 100644 index 00000000..e07f1d56 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/README.md @@ -0,0 +1,27 @@ + +# CD4008 IC + +CD4008 is 4 bit full adder with parallel carry out IC. It is designed with 180nm CMOS technology in eSim. It is 16 pin IC. +## Usage/Examples + +High Speed Arithmetic operations + +Miniature calculators + +Counters + +Simple logic control designs +## Documentation + +To know the details of CD4008 IC please go through with the documentation : [CD4008_datasheet](https://www.alldatasheet.com/datasheet-pdf/pdf/66388/INTERSIL/CD4008.html) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4008/analysis b/library/SubcircuitLibrary/CD_4008/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4008/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 83cebb7f7be5a626376b4305d2548819da8e63c4 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:49:24 +0530 Subject: CD4011 is NAND gate IC. --- .../SubcircuitLibrary/CD_4011/CD_4011-cache.lib | 100 ++++ library/SubcircuitLibrary/CD_4011/CD_4011.cir | 27 + library/SubcircuitLibrary/CD_4011/CD_4011.cir.out | 30 + library/SubcircuitLibrary/CD_4011/CD_4011.pro | 71 +++ library/SubcircuitLibrary/CD_4011/CD_4011.sch | 663 +++++++++++++++++++++ library/SubcircuitLibrary/CD_4011/CD_4011.sub | 24 + .../CD_4011/CD_4011_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4011/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4011/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4011/README.md | 32 + library/SubcircuitLibrary/CD_4011/analysis | 1 + 11 files changed, 973 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011.cir create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011.cir.out create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011.pro create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011.sch create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011.sub create mode 100644 library/SubcircuitLibrary/CD_4011/CD_4011_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4011/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4011/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4011/README.md create mode 100644 library/SubcircuitLibrary/CD_4011/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011-cache.lib b/library/SubcircuitLibrary/CD_4011/CD_4011-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011.cir b/library/SubcircuitLibrary/CD_4011/CD_4011.cir new file mode 100644 index 00000000..ec450aea --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011.cir @@ -0,0 +1,27 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4011\CD_4011.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/22 10:04:49 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M5 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_N +M8 Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M6 Net-_M5-Pad3_ Net-_M6-Pad2_ Net-_M12-Pad3_ Net-_M12-Pad3_ eSim_MOS_N +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M13 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M13-Pad3_ Net-_M13-Pad3_ eSim_MOS_N +M16 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M14 Net-_M13-Pad3_ Net-_M14-Pad2_ Net-_M12-Pad3_ Net-_M12-Pad3_ eSim_MOS_N +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M7 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M12-Pad3_ Net-_M12-Pad3_ eSim_MOS_N +M9 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_N +M15 Net-_M11-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M12 Net-_M11-Pad3_ Net-_M12-Pad2_ Net-_M12-Pad3_ Net-_M12-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M12-Pad2_ Net-_M12-Pad3_ Net-_M10-Pad2_ Net-_M14-Pad2_ Net-_M10-Pad1_ Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011.cir.out b/library/SubcircuitLibrary/CD_4011/CD_4011.cir.out new file mode 100644 index 00000000..b2c1ec12 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011.cir.out @@ -0,0 +1,30 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4011\cd_4011.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m6-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad1_ net-_m10-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m11-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m11-pad3_ net-_m12-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad3_ net-_m10-pad2_ net-_m14-pad2_ net-_m10-pad1_ net-_m2-pad1_ net-_m2-pad2_ net-_m6-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011.pro b/library/SubcircuitLibrary/CD_4011/CD_4011.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011.sch b/library/SubcircuitLibrary/CD_4011/CD_4011.sch new file mode 100644 index 00000000..a274458b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011.sch @@ -0,0 +1,663 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4011-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 628F017A +P 3750 4150 +F 0 "M2" H 3700 4200 50 0000 R CNN +F 1 "eSim_MOS_P" H 3800 4300 50 0000 R CNN +F 2 "" H 4000 4250 29 0000 C CNN +F 3 "" H 3800 4150 60 0000 C CNN + 1 3750 4150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 628F017B +P 3950 4650 +F 0 "M5" H 3950 4500 50 0000 R CNN +F 1 "eSim_MOS_N" H 4050 4600 50 0000 R CNN +F 2 "" H 4250 4350 29 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 1 3950 4650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 628F017C +P 4550 4150 +F 0 "M8" H 4500 4200 50 0000 R CNN +F 1 "eSim_MOS_P" H 4600 4300 50 0000 R CNN +F 2 "" H 4800 4250 29 0000 C CNN +F 3 "" H 4600 4150 60 0000 C CNN + 1 4550 4150 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 628F017D +P 3950 5250 +F 0 "M6" H 3950 5100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4050 5200 50 0000 R CNN +F 2 "" H 4250 4950 29 0000 C CNN +F 3 "" H 4050 5050 60 0000 C CNN + 1 3950 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M10 +U 1 1 628F017E +P 6100 4150 +F 0 "M10" H 6050 4200 50 0000 R CNN +F 1 "eSim_MOS_P" H 6150 4300 50 0000 R CNN +F 2 "" H 6350 4250 29 0000 C CNN +F 3 "" H 6150 4150 60 0000 C CNN + 1 6100 4150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 628F017F +P 6300 4650 +F 0 "M13" H 6300 4500 50 0000 R CNN +F 1 "eSim_MOS_N" H 6400 4600 50 0000 R CNN +F 2 "" H 6600 4350 29 0000 C CNN +F 3 "" H 6400 4450 60 0000 C CNN + 1 6300 4650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 628F0180 +P 6900 4150 +F 0 "M16" H 6850 4200 50 0000 R CNN +F 1 "eSim_MOS_P" H 6950 4300 50 0000 R CNN +F 2 "" H 7150 4250 29 0000 C CNN +F 3 "" H 6950 4150 60 0000 C CNN + 1 6900 4150 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M14 +U 1 1 628F0181 +P 6300 5250 +F 0 "M14" H 6300 5100 50 0000 R CNN +F 1 "eSim_MOS_N" H 6400 5200 50 0000 R CNN +F 2 "" H 6600 4950 29 0000 C CNN +F 3 "" H 6400 5050 60 0000 C CNN + 1 6300 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M1 +U 1 1 628F0182 +P 3750 2050 +F 0 "M1" H 3700 2100 50 0000 R CNN +F 1 "eSim_MOS_P" H 3800 2200 50 0000 R CNN +F 2 "" H 4000 2150 29 0000 C CNN +F 3 "" H 3800 2050 60 0000 C CNN + 1 3750 2050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 628F0183 +P 3950 2550 +F 0 "M3" H 3950 2400 50 0000 R CNN +F 1 "eSim_MOS_N" H 4050 2500 50 0000 R CNN +F 2 "" H 4250 2250 29 0000 C CNN +F 3 "" H 4050 2350 60 0000 C CNN + 1 3950 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 628F0184 +P 4550 2050 +F 0 "M7" H 4500 2100 50 0000 R CNN +F 1 "eSim_MOS_P" H 4600 2200 50 0000 R CNN +F 2 "" H 4800 2150 29 0000 C CNN +F 3 "" H 4600 2050 60 0000 C CNN + 1 4550 2050 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 628F0185 +P 3950 3150 +F 0 "M4" H 3950 3000 50 0000 R CNN +F 1 "eSim_MOS_N" H 4050 3100 50 0000 R CNN +F 2 "" H 4250 2850 29 0000 C CNN +F 3 "" H 4050 2950 60 0000 C CNN + 1 3950 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M9 +U 1 1 628F0186 +P 6100 2050 +F 0 "M9" H 6050 2100 50 0000 R CNN +F 1 "eSim_MOS_P" H 6150 2200 50 0000 R CNN +F 2 "" H 6350 2150 29 0000 C CNN +F 3 "" H 6150 2050 60 0000 C CNN + 1 6100 2050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M11 +U 1 1 628F0187 +P 6300 2550 +F 0 "M11" H 6300 2400 50 0000 R CNN +F 1 "eSim_MOS_N" H 6400 2500 50 0000 R CNN +F 2 "" H 6600 2250 29 0000 C CNN +F 3 "" H 6400 2350 60 0000 C CNN + 1 6300 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M15 +U 1 1 628F0188 +P 6900 2050 +F 0 "M15" H 6850 2100 50 0000 R CNN +F 1 "eSim_MOS_P" H 6950 2200 50 0000 R CNN +F 2 "" H 7150 2150 29 0000 C CNN +F 3 "" H 6950 2050 60 0000 C CNN + 1 6900 2050 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 628F0189 +P 6300 3150 +F 0 "M12" H 6300 3000 50 0000 R CNN +F 1 "eSim_MOS_N" H 6400 3100 50 0000 R CNN +F 2 "" H 6600 2850 29 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6300 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 3950 3900 3850 +Wire Wire Line + 3900 3850 4400 3850 +Wire Wire Line + 4400 3850 4400 3950 +Wire Wire Line + 3900 4350 3900 4400 +Wire Wire Line + 3900 4400 4400 4400 +Wire Wire Line + 4400 4400 4400 4350 +Wire Wire Line + 4000 4000 4000 3850 +Connection ~ 4000 3850 +Wire Wire Line + 4300 4000 4300 3850 +Connection ~ 4300 3850 +Wire Wire Line + 4150 4400 4150 4650 +Connection ~ 4150 4400 +Wire Wire Line + 4150 5050 4150 5250 +Wire Wire Line + 4250 5000 4250 5150 +Wire Wire Line + 4250 5150 4150 5150 +Connection ~ 4150 5150 +Wire Wire Line + 4150 5650 4150 5700 +Wire Wire Line + 4150 5700 4250 5700 +Wire Wire Line + 4250 5700 4250 5600 +Wire Wire Line + 4150 4550 4700 4550 +Connection ~ 4150 4550 +Wire Wire Line + 3600 4150 3500 4150 +Wire Wire Line + 3500 4150 3500 4850 +Wire Wire Line + 3500 4850 3850 4850 +Wire Wire Line + 3850 5450 3800 5450 +Wire Wire Line + 3800 5450 3800 4450 +Wire Wire Line + 3800 4450 4700 4450 +Wire Wire Line + 4700 4450 4700 4150 +Wire Wire Line + 3500 4450 3150 4450 +Connection ~ 3500 4450 +Wire Wire Line + 3800 5050 3150 5050 +Connection ~ 3800 5050 +Wire Wire Line + 6250 3950 6250 3850 +Wire Wire Line + 6250 3850 6750 3850 +Wire Wire Line + 6750 3850 6750 3950 +Wire Wire Line + 6250 4350 6250 4400 +Wire Wire Line + 6250 4400 6750 4400 +Wire Wire Line + 6750 4400 6750 4350 +Wire Wire Line + 6350 4000 6350 3850 +Connection ~ 6350 3850 +Wire Wire Line + 6650 4000 6650 3850 +Connection ~ 6650 3850 +Wire Wire Line + 6500 4400 6500 4650 +Connection ~ 6500 4400 +Wire Wire Line + 6500 5050 6500 5250 +Wire Wire Line + 6600 5000 6600 5150 +Wire Wire Line + 6600 5150 6500 5150 +Connection ~ 6500 5150 +Wire Wire Line + 6500 5650 6500 5700 +Wire Wire Line + 6500 5700 6600 5700 +Wire Wire Line + 6600 5700 6600 5600 +Wire Wire Line + 6500 4550 7050 4550 +Connection ~ 6500 4550 +Wire Wire Line + 5950 4150 5850 4150 +Wire Wire Line + 5850 4150 5850 4850 +Wire Wire Line + 5850 4850 6200 4850 +Wire Wire Line + 6200 5450 6150 5450 +Wire Wire Line + 6150 5450 6150 4450 +Wire Wire Line + 6150 4450 7050 4450 +Wire Wire Line + 7050 4450 7050 4150 +Wire Wire Line + 5850 4450 5500 4450 +Connection ~ 5850 4450 +Wire Wire Line + 6150 5050 5500 5050 +Connection ~ 6150 5050 +Wire Wire Line + 3900 1850 3900 1750 +Wire Wire Line + 3900 1750 4400 1750 +Wire Wire Line + 4400 1750 4400 1850 +Wire Wire Line + 3900 2250 3900 2300 +Wire Wire Line + 3900 2300 4400 2300 +Wire Wire Line + 4400 2300 4400 2250 +Wire Wire Line + 4000 1900 4000 1750 +Connection ~ 4000 1750 +Wire Wire Line + 4300 1900 4300 1750 +Connection ~ 4300 1750 +Wire Wire Line + 4150 2300 4150 2550 +Connection ~ 4150 2300 +Wire Wire Line + 4150 2950 4150 3150 +Wire Wire Line + 4250 2900 4250 3050 +Wire Wire Line + 4250 3050 4150 3050 +Connection ~ 4150 3050 +Wire Wire Line + 4150 3550 4150 3600 +Wire Wire Line + 4150 3600 4250 3600 +Wire Wire Line + 4250 3600 4250 3500 +Wire Wire Line + 4150 2450 4700 2450 +Connection ~ 4150 2450 +Wire Wire Line + 3600 2050 3500 2050 +Wire Wire Line + 3500 2050 3500 2750 +Wire Wire Line + 3500 2750 3850 2750 +Wire Wire Line + 3850 3350 3800 3350 +Wire Wire Line + 3800 3350 3800 2350 +Wire Wire Line + 3800 2350 4700 2350 +Wire Wire Line + 4700 2350 4700 2050 +Wire Wire Line + 3500 2350 3150 2350 +Connection ~ 3500 2350 +Wire Wire Line + 3800 2950 3150 2950 +Connection ~ 3800 2950 +Wire Wire Line + 6250 1850 6250 1750 +Wire Wire Line + 6250 1750 6750 1750 +Wire Wire Line + 6750 1750 6750 1850 +Wire Wire Line + 6250 2250 6250 2300 +Wire Wire Line + 6250 2300 6750 2300 +Wire Wire Line + 6750 2300 6750 2250 +Wire Wire Line + 6350 1900 6350 1750 +Connection ~ 6350 1750 +Wire Wire Line + 6650 1900 6650 1750 +Connection ~ 6650 1750 +Wire Wire Line + 6500 2300 6500 2550 +Connection ~ 6500 2300 +Wire Wire Line + 6500 2950 6500 3150 +Wire Wire Line + 6600 2900 6600 3050 +Wire Wire Line + 6600 3050 6500 3050 +Connection ~ 6500 3050 +Wire Wire Line + 6500 3550 6500 3600 +Wire Wire Line + 6500 3600 6600 3600 +Wire Wire Line + 6600 3600 6600 3500 +Wire Wire Line + 6500 2450 7050 2450 +Connection ~ 6500 2450 +Wire Wire Line + 5950 2050 5850 2050 +Wire Wire Line + 5850 2050 5850 2750 +Wire Wire Line + 5850 2750 6200 2750 +Wire Wire Line + 6200 3350 6150 3350 +Wire Wire Line + 6150 3350 6150 2350 +Wire Wire Line + 6150 2350 7050 2350 +Wire Wire Line + 7050 2350 7050 2050 +Wire Wire Line + 5850 2350 5500 2350 +Connection ~ 5850 2350 +Wire Wire Line + 6150 2950 5500 2950 +Connection ~ 6150 2950 +Wire Wire Line + 4200 3600 4200 3650 +Wire Wire Line + 4200 3650 6550 3650 +Wire Wire Line + 6550 3650 6550 3600 +Connection ~ 6550 3600 +Connection ~ 4200 3600 +Wire Wire Line + 4200 3850 4200 3800 +Wire Wire Line + 4200 3800 6550 3800 +Wire Wire Line + 6550 3800 6550 3850 +Connection ~ 6550 3850 +Connection ~ 4200 3850 +Wire Wire Line + 4200 5700 4200 5750 +Wire Wire Line + 4200 5750 6550 5750 +Wire Wire Line + 6550 5750 6550 5700 +Connection ~ 6550 5700 +Connection ~ 4200 5700 +Wire Wire Line + 4200 1750 4200 1700 +Wire Wire Line + 4200 1700 6500 1700 +Wire Wire Line + 6500 1700 6500 1750 +Connection ~ 6500 1750 +Connection ~ 4200 1750 +Wire Wire Line + 5100 1700 5100 3800 +Connection ~ 5100 3800 +Connection ~ 5100 1700 +Wire Wire Line + 5200 3650 5200 5750 +Connection ~ 5200 5750 +Connection ~ 5200 3650 +Wire Wire Line + 5550 1700 5550 1500 +Wire Wire Line + 5550 1500 4950 1500 +Connection ~ 5550 1700 +Wire Wire Line + 5500 5750 5500 6050 +Wire Wire Line + 5500 6050 4950 6050 +Connection ~ 5500 5750 +$Comp +L PORT U1 +U 1 1 628F08C6 +P 2900 2350 +F 0 "U1" H 2950 2450 30 0000 C CNN +F 1 "PORT" H 2900 2350 30 0000 C CNN +F 2 "" H 2900 2350 60 0000 C CNN +F 3 "" H 2900 2350 60 0000 C CNN + 1 2900 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 628F094D +P 2900 2950 +F 0 "U1" H 2950 3050 30 0000 C CNN +F 1 "PORT" H 2900 2950 30 0000 C CNN +F 2 "" H 2900 2950 60 0000 C CNN +F 3 "" H 2900 2950 60 0000 C CNN + 2 2900 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 628F09C0 +P 4950 2450 +F 0 "U1" H 5000 2550 30 0000 C CNN +F 1 "PORT" H 4950 2450 30 0000 C CNN +F 2 "" H 4950 2450 60 0000 C CNN +F 3 "" H 4950 2450 60 0000 C CNN + 3 4950 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 628F0A6B +P 7300 2450 +F 0 "U1" H 7350 2550 30 0000 C CNN +F 1 "PORT" H 7300 2450 30 0000 C CNN +F 2 "" H 7300 2450 60 0000 C CNN +F 3 "" H 7300 2450 60 0000 C CNN + 4 7300 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 628F0C06 +P 5250 2350 +F 0 "U1" H 5300 2450 30 0000 C CNN +F 1 "PORT" H 5250 2350 30 0000 C CNN +F 2 "" H 5250 2350 60 0000 C CNN +F 3 "" H 5250 2350 60 0000 C CNN + 5 5250 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 628F0C9B +P 5250 2950 +F 0 "U1" H 5300 3050 30 0000 C CNN +F 1 "PORT" H 5250 2950 30 0000 C CNN +F 2 "" H 5250 2950 60 0000 C CNN +F 3 "" H 5250 2950 60 0000 C CNN + 6 5250 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 628F0D16 +P 4700 6050 +F 0 "U1" H 4750 6150 30 0000 C CNN +F 1 "PORT" H 4700 6050 30 0000 C CNN +F 2 "" H 4700 6050 60 0000 C CNN +F 3 "" H 4700 6050 60 0000 C CNN + 7 4700 6050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 628F0DF3 +P 5250 4450 +F 0 "U1" H 5300 4550 30 0000 C CNN +F 1 "PORT" H 5250 4450 30 0000 C CNN +F 2 "" H 5250 4450 60 0000 C CNN +F 3 "" H 5250 4450 60 0000 C CNN + 8 5250 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 628F0E8C +P 5250 5050 +F 0 "U1" H 5300 5150 30 0000 C CNN +F 1 "PORT" H 5250 5050 30 0000 C CNN +F 2 "" H 5250 5050 60 0000 C CNN +F 3 "" H 5250 5050 60 0000 C CNN + 9 5250 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 628F0F4D +P 7300 4550 +F 0 "U1" H 7350 4650 30 0000 C CNN +F 1 "PORT" H 7300 4550 30 0000 C CNN +F 2 "" H 7300 4550 60 0000 C CNN +F 3 "" H 7300 4550 60 0000 C CNN + 10 7300 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 628F0FE8 +P 4950 4550 +F 0 "U1" H 5000 4650 30 0000 C CNN +F 1 "PORT" H 4950 4550 30 0000 C CNN +F 2 "" H 4950 4550 60 0000 C CNN +F 3 "" H 4950 4550 60 0000 C CNN + 11 4950 4550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 628F10E8 +P 2900 4450 +F 0 "U1" H 2950 4550 30 0000 C CNN +F 1 "PORT" H 2900 4450 30 0000 C CNN +F 2 "" H 2900 4450 60 0000 C CNN +F 3 "" H 2900 4450 60 0000 C CNN + 12 2900 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 628F114F +P 2900 5050 +F 0 "U1" H 2950 5150 30 0000 C CNN +F 1 "PORT" H 2900 5050 30 0000 C CNN +F 2 "" H 2900 5050 60 0000 C CNN +F 3 "" H 2900 5050 60 0000 C CNN + 13 2900 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 628F11AC +P 4700 1500 +F 0 "U1" H 4750 1600 30 0000 C CNN +F 1 "PORT" H 4700 1500 30 0000 C CNN +F 2 "" H 4700 1500 60 0000 C CNN +F 3 "" H 4700 1500 60 0000 C CNN + 14 4700 1500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011.sub b/library/SubcircuitLibrary/CD_4011/CD_4011.sub new file mode 100644 index 00000000..b2753141 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011.sub @@ -0,0 +1,24 @@ +* Subcircuit CD_4011 +.subckt CD_4011 net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad3_ net-_m10-pad2_ net-_m14-pad2_ net-_m10-pad1_ net-_m2-pad1_ net-_m2-pad2_ net-_m6-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4011\cd_4011.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m6-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad1_ net-_m10-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m11-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m11-pad3_ net-_m12-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4011 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4011/CD_4011_Previous_Values.xml b/library/SubcircuitLibrary/CD_4011/CD_4011_Previous_Values.xml new file mode 100644 index 00000000..e953367c --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/CD_4011_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4011/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4011/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4011/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4011/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4011/README.md b/library/SubcircuitLibrary/CD_4011/README.md new file mode 100644 index 00000000..7e8f7317 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/README.md @@ -0,0 +1,32 @@ + +# CD4011 IC + +It is 2-input NAND Gate IC. CD4011 IC is designed with 180nm CMOS technology in eSim consisting four NAND Gates. When both the inputs are HIGH then only output is LOW, otherwise HIGH. It is also called inverted AND Gate, a type of Universal Gate. + + +## Usage/Examples + +Employed in portable Audio Docks + +Used in AV Receivers + +Used in MP3 Players or Recorders + +Applied in Home Theater + +Incorporated in Blu-Ray Players + +## Documentation + +To know the details of CD4011 IC please go through with the documentation : [CD4011_datasheet](https://www.ti.com/lit/gpn/cd4011b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4011/analysis b/library/SubcircuitLibrary/CD_4011/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4011/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 84bf88d2e5d1cf90a0e500bacd918c050aae5d74 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:51:28 +0530 Subject: CD4023 is 3 input NAND gate IC. --- .../SubcircuitLibrary/CD_4023/CD_4023-cache.lib | 100 ++++ library/SubcircuitLibrary/CD_4023/CD_4023.cir | 29 + library/SubcircuitLibrary/CD_4023/CD_4023.cir.out | 32 ++ library/SubcircuitLibrary/CD_4023/CD_4023.pro | 71 +++ library/SubcircuitLibrary/CD_4023/CD_4023.sch | 606 +++++++++++++++++++++ library/SubcircuitLibrary/CD_4023/CD_4023.sub | 26 + .../CD_4023/CD_4023_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4023/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4023/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4023/README.md | 26 + library/SubcircuitLibrary/CD_4023/analysis | 1 + 11 files changed, 916 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023.cir create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023.cir.out create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023.pro create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023.sch create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023.sub create mode 100644 library/SubcircuitLibrary/CD_4023/CD_4023_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4023/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4023/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4023/README.md create mode 100644 library/SubcircuitLibrary/CD_4023/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023-cache.lib b/library/SubcircuitLibrary/CD_4023/CD_4023-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023.cir b/library/SubcircuitLibrary/CD_4023/CD_4023.cir new file mode 100644 index 00000000..5f80efd8 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023.cir @@ -0,0 +1,29 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4023\CD_4023.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/22 15:14:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M6 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M5 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_N +M8 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M13 Net-_M12-Pad3_ Net-_M13-Pad2_ Net-_M13-Pad3_ Net-_M13-Pad3_ eSim_MOS_N +M18 Net-_M12-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M16 Net-_M12-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M12-Pad3_ Net-_M12-Pad3_ eSim_MOS_N +M14 Net-_M13-Pad3_ Net-_M14-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_N +M7 Net-_M15-Pad1_ Net-_M7-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M17 Net-_M15-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M15 Net-_M15-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M9 Net-_M15-Pad1_ Net-_M7-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M11 Net-_M10-Pad3_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M12-Pad2_ Net-_M13-Pad2_ Net-_M14-Pad2_ Net-_M12-Pad1_ Net-_M11-Pad3_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M15-Pad1_ Net-_M7-Pad2_ Net-_M10-Pad2_ Net-_M11-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023.cir.out b/library/SubcircuitLibrary/CD_4023/CD_4023.cir.out new file mode 100644 index 00000000..86a72392 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4023\cd_4023.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m12-pad3_ net-_m13-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m12-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m15-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m15-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m15-pad1_ net-_m7-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m11 net-_m10-pad3_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m3-pad2_ net-_m12-pad2_ net-_m13-pad2_ net-_m14-pad2_ net-_m12-pad1_ net-_m11-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m15-pad1_ net-_m7-pad2_ net-_m10-pad2_ net-_m11-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023.pro b/library/SubcircuitLibrary/CD_4023/CD_4023.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023.sch b/library/SubcircuitLibrary/CD_4023/CD_4023.sch new file mode 100644 index 00000000..011d0fb3 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023.sch @@ -0,0 +1,606 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4023-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M1 +U 1 1 628F45D1 +P 3150 4000 +F 0 "M1" H 3100 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 3200 4150 50 0000 R CNN +F 2 "" H 3400 4100 29 0000 C CNN +F 3 "" H 3200 4000 60 0000 C CNN + 1 3150 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 628F45D2 +P 3600 4850 +F 0 "M3" H 3600 4700 50 0000 R CNN +F 1 "eSim_MOS_N" H 3700 4800 50 0000 R CNN +F 2 "" H 3900 4550 29 0000 C CNN +F 3 "" H 3700 4650 60 0000 C CNN + 1 3600 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 628F45D3 +P 4350 4000 +F 0 "M6" H 4300 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 4400 4150 50 0000 R CNN +F 2 "" H 4600 4100 29 0000 C CNN +F 3 "" H 4400 4000 60 0000 C CNN + 1 4350 4000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 628F45D4 +P 3650 4000 +F 0 "M5" H 3600 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 3700 4150 50 0000 R CNN +F 2 "" H 3900 4100 29 0000 C CNN +F 3 "" H 3700 4000 60 0000 C CNN + 1 3650 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 628F45D5 +P 3600 4400 +F 0 "M2" H 3600 4250 50 0000 R CNN +F 1 "eSim_MOS_N" H 3700 4350 50 0000 R CNN +F 2 "" H 3900 4100 29 0000 C CNN +F 3 "" H 3700 4200 60 0000 C CNN + 1 3600 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 628F45D6 +P 3600 5300 +F 0 "M4" H 3600 5150 50 0000 R CNN +F 1 "eSim_MOS_N" H 3700 5250 50 0000 R CNN +F 2 "" H 3900 5000 29 0000 C CNN +F 3 "" H 3700 5100 60 0000 C CNN + 1 3600 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 4200 3300 4250 +Wire Wire Line + 3300 4250 4200 4250 +Wire Wire Line + 3800 4200 3800 4400 +Wire Wire Line + 4200 4250 4200 4200 +Connection ~ 3800 4250 +Wire Wire Line + 3800 4800 3800 4850 +Wire Wire Line + 3800 5250 3800 5300 +Wire Wire Line + 3900 4750 3900 4800 +Wire Wire Line + 3900 4800 3800 4800 +Wire Wire Line + 3900 5200 3900 5250 +Wire Wire Line + 3900 5250 3800 5250 +Wire Wire Line + 3900 5650 3900 5700 +Wire Wire Line + 3800 5700 6050 5700 +Wire Wire Line + 3300 3800 6350 3800 +Wire Wire Line + 3400 3800 3400 3850 +Wire Wire Line + 3900 3800 3900 3850 +Wire Wire Line + 4100 3800 4100 3850 +Wire Wire Line + 3800 4350 4550 4350 +Connection ~ 3800 4350 +Wire Wire Line + 3000 4000 3000 4600 +Wire Wire Line + 2850 4600 3500 4600 +Wire Wire Line + 3500 4000 3500 5050 +Wire Wire Line + 4500 4000 4500 4300 +Wire Wire Line + 4500 4300 3450 4300 +Wire Wire Line + 3450 4300 3450 5500 +Wire Wire Line + 3450 5500 3500 5500 +Connection ~ 3000 4600 +Wire Wire Line + 3450 5000 2850 5000 +Connection ~ 3450 5000 +Wire Wire Line + 3500 4800 2850 4800 +Connection ~ 3500 4800 +Connection ~ 3800 3800 +Connection ~ 3400 3800 +Connection ~ 4100 3800 +Connection ~ 3900 3800 +$Comp +L eSim_MOS_P M8 +U 1 1 628F45D7 +P 5300 4000 +F 0 "M8" H 5250 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 5350 4150 50 0000 R CNN +F 2 "" H 5550 4100 29 0000 C CNN +F 3 "" H 5350 4000 60 0000 C CNN + 1 5300 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 628F45D8 +P 5750 4850 +F 0 "M13" H 5750 4700 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 4800 50 0000 R CNN +F 2 "" H 6050 4550 29 0000 C CNN +F 3 "" H 5850 4650 60 0000 C CNN + 1 5750 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M18 +U 1 1 628F45D9 +P 6500 4000 +F 0 "M18" H 6450 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 6550 4150 50 0000 R CNN +F 2 "" H 6750 4100 29 0000 C CNN +F 3 "" H 6550 4000 60 0000 C CNN + 1 6500 4000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 628F45DA +P 5800 4000 +F 0 "M16" H 5750 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 5850 4150 50 0000 R CNN +F 2 "" H 6050 4100 29 0000 C CNN +F 3 "" H 5850 4000 60 0000 C CNN + 1 5800 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 628F45DB +P 5750 4400 +F 0 "M12" H 5750 4250 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 4350 50 0000 R CNN +F 2 "" H 6050 4100 29 0000 C CNN +F 3 "" H 5850 4200 60 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M14 +U 1 1 628F45DC +P 5750 5300 +F 0 "M14" H 5750 5150 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 5250 50 0000 R CNN +F 2 "" H 6050 5000 29 0000 C CNN +F 3 "" H 5850 5100 60 0000 C CNN + 1 5750 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 4200 5450 4250 +Wire Wire Line + 5450 4250 6350 4250 +Wire Wire Line + 5950 4200 5950 4400 +Wire Wire Line + 6350 4250 6350 4200 +Connection ~ 5950 4250 +Wire Wire Line + 5950 4800 5950 4850 +Wire Wire Line + 5950 5250 5950 5300 +Wire Wire Line + 6050 4750 6050 4800 +Wire Wire Line + 6050 4800 5950 4800 +Wire Wire Line + 6050 5200 6050 5250 +Wire Wire Line + 6050 5250 5950 5250 +Wire Wire Line + 6050 5700 6050 5650 +Wire Wire Line + 5550 3800 5550 3850 +Wire Wire Line + 6050 3800 6050 3850 +Wire Wire Line + 6250 3800 6250 3850 +Wire Wire Line + 5950 4350 6700 4350 +Connection ~ 5950 4350 +Wire Wire Line + 5150 4000 5150 4600 +Wire Wire Line + 5000 4600 5650 4600 +Wire Wire Line + 5650 4000 5650 5050 +Wire Wire Line + 6650 4000 6650 4300 +Wire Wire Line + 6650 4300 5600 4300 +Wire Wire Line + 5600 4300 5600 5500 +Wire Wire Line + 5600 5500 5650 5500 +Connection ~ 5150 4600 +Wire Wire Line + 5600 5000 5000 5000 +Connection ~ 5600 5000 +Wire Wire Line + 5650 4800 5000 4800 +Connection ~ 5650 4800 +Connection ~ 5950 3800 +Connection ~ 5550 3800 +Connection ~ 6250 3800 +Connection ~ 6050 3800 +$Comp +L eSim_MOS_P M7 +U 1 1 628F45E3 +P 5300 1850 +F 0 "M7" H 5250 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 5350 2000 50 0000 R CNN +F 2 "" H 5550 1950 29 0000 C CNN +F 3 "" H 5350 1850 60 0000 C CNN + 1 5300 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 628F45E4 +P 5750 2700 +F 0 "M10" H 5750 2550 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 2650 50 0000 R CNN +F 2 "" H 6050 2400 29 0000 C CNN +F 3 "" H 5850 2500 60 0000 C CNN + 1 5750 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M17 +U 1 1 628F45E5 +P 6500 1850 +F 0 "M17" H 6450 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 6550 2000 50 0000 R CNN +F 2 "" H 6750 1950 29 0000 C CNN +F 3 "" H 6550 1850 60 0000 C CNN + 1 6500 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M15 +U 1 1 628F45E6 +P 5800 1850 +F 0 "M15" H 5750 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 5850 2000 50 0000 R CNN +F 2 "" H 6050 1950 29 0000 C CNN +F 3 "" H 5850 1850 60 0000 C CNN + 1 5800 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 628F45E7 +P 5750 2250 +F 0 "M9" H 5750 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 2200 50 0000 R CNN +F 2 "" H 6050 1950 29 0000 C CNN +F 3 "" H 5850 2050 60 0000 C CNN + 1 5750 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M11 +U 1 1 628F45E8 +P 5750 3150 +F 0 "M11" H 5750 3000 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 3100 50 0000 R CNN +F 2 "" H 6050 2850 29 0000 C CNN +F 3 "" H 5850 2950 60 0000 C CNN + 1 5750 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 2050 5450 2100 +Wire Wire Line + 5450 2100 6350 2100 +Wire Wire Line + 5950 2050 5950 2250 +Wire Wire Line + 6350 2100 6350 2050 +Connection ~ 5950 2100 +Wire Wire Line + 5950 2650 5950 2700 +Wire Wire Line + 5950 3100 5950 3150 +Wire Wire Line + 6050 2600 6050 2650 +Wire Wire Line + 6050 2650 5950 2650 +Wire Wire Line + 6050 3050 6050 3100 +Wire Wire Line + 6050 3100 5950 3100 +Wire Wire Line + 6050 3550 6050 3500 +Wire Wire Line + 5550 1650 5550 1700 +Wire Wire Line + 6050 1650 6050 1700 +Wire Wire Line + 6250 1650 6250 1700 +Wire Wire Line + 5950 2200 6700 2200 +Connection ~ 5950 2200 +Wire Wire Line + 5150 1850 5150 2450 +Wire Wire Line + 5000 2450 5650 2450 +Wire Wire Line + 5650 1850 5650 2900 +Wire Wire Line + 6650 1850 6650 2150 +Wire Wire Line + 6650 2150 5600 2150 +Wire Wire Line + 5600 2150 5600 3350 +Wire Wire Line + 5600 3350 5650 3350 +Connection ~ 5150 2450 +Wire Wire Line + 5600 2850 5000 2850 +Connection ~ 5600 2850 +Wire Wire Line + 5650 2650 5000 2650 +Connection ~ 5650 2650 +Connection ~ 5950 1650 +Connection ~ 5550 1650 +Connection ~ 6250 1650 +Connection ~ 6050 1650 +Connection ~ 5950 3550 +Connection ~ 5450 1650 +Connection ~ 5450 3800 +Connection ~ 4200 3800 +Connection ~ 5950 5700 +Connection ~ 3900 5700 +Connection ~ 4650 5700 +Wire Wire Line + 4850 1450 4850 3800 +Connection ~ 4850 3800 +Wire Wire Line + 5000 5700 5000 5950 +Wire Wire Line + 5000 5950 4450 5950 +Connection ~ 5000 5700 +$Comp +L PORT U1 +U 1 1 628F6990 +P 2600 4600 +F 0 "U1" H 2650 4700 30 0000 C CNN +F 1 "PORT" H 2600 4600 30 0000 C CNN +F 2 "" H 2600 4600 60 0000 C CNN +F 3 "" H 2600 4600 60 0000 C CNN + 1 2600 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 628F6A4B +P 2600 4800 +F 0 "U1" H 2650 4900 30 0000 C CNN +F 1 "PORT" H 2600 4800 30 0000 C CNN +F 2 "" H 2600 4800 60 0000 C CNN +F 3 "" H 2600 4800 60 0000 C CNN + 2 2600 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 628F6AB4 +P 4750 4600 +F 0 "U1" H 4800 4700 30 0000 C CNN +F 1 "PORT" H 4750 4600 30 0000 C CNN +F 2 "" H 4750 4600 60 0000 C CNN +F 3 "" H 4750 4600 60 0000 C CNN + 3 4750 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 628F6B19 +P 4750 4800 +F 0 "U1" H 4800 4900 30 0000 C CNN +F 1 "PORT" H 4750 4800 30 0000 C CNN +F 2 "" H 4750 4800 60 0000 C CNN +F 3 "" H 4750 4800 60 0000 C CNN + 4 4750 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 628F6B78 +P 4750 5000 +F 0 "U1" H 4800 5100 30 0000 C CNN +F 1 "PORT" H 4750 5000 30 0000 C CNN +F 2 "" H 4750 5000 60 0000 C CNN +F 3 "" H 4750 5000 60 0000 C CNN + 5 4750 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 628F6C2E +P 6950 4350 +F 0 "U1" H 7000 4450 30 0000 C CNN +F 1 "PORT" H 6950 4350 30 0000 C CNN +F 2 "" H 6950 4350 60 0000 C CNN +F 3 "" H 6950 4350 60 0000 C CNN + 6 6950 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 628F6CC7 +P 4200 5950 +F 0 "U1" H 4250 6050 30 0000 C CNN +F 1 "PORT" H 4200 5950 30 0000 C CNN +F 2 "" H 4200 5950 60 0000 C CNN +F 3 "" H 4200 5950 60 0000 C CNN + 7 4200 5950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 628F6D56 +P 2600 5000 +F 0 "U1" H 2650 5100 30 0000 C CNN +F 1 "PORT" H 2600 5000 30 0000 C CNN +F 2 "" H 2600 5000 60 0000 C CNN +F 3 "" H 2600 5000 60 0000 C CNN + 8 2600 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 628F6E60 +P 4800 4350 +F 0 "U1" H 4850 4450 30 0000 C CNN +F 1 "PORT" H 4800 4350 30 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 9 4800 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 628F6F5C +P 6950 2200 +F 0 "U1" H 7000 2300 30 0000 C CNN +F 1 "PORT" H 6950 2200 30 0000 C CNN +F 2 "" H 6950 2200 60 0000 C CNN +F 3 "" H 6950 2200 60 0000 C CNN + 10 6950 2200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 628F71A3 +P 4750 2450 +F 0 "U1" H 4800 2550 30 0000 C CNN +F 1 "PORT" H 4750 2450 30 0000 C CNN +F 2 "" H 4750 2450 60 0000 C CNN +F 3 "" H 4750 2450 60 0000 C CNN + 11 4750 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 628F7210 +P 4750 2650 +F 0 "U1" H 4800 2750 30 0000 C CNN +F 1 "PORT" H 4750 2650 30 0000 C CNN +F 2 "" H 4750 2650 60 0000 C CNN +F 3 "" H 4750 2650 60 0000 C CNN + 12 4750 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 628F7283 +P 4750 2850 +F 0 "U1" H 4800 2950 30 0000 C CNN +F 1 "PORT" H 4750 2850 30 0000 C CNN +F 2 "" H 4750 2850 60 0000 C CNN +F 3 "" H 4750 2850 60 0000 C CNN + 13 4750 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 628F7300 +P 4550 1450 +F 0 "U1" H 4600 1550 30 0000 C CNN +F 1 "PORT" H 4550 1450 30 0000 C CNN +F 2 "" H 4550 1450 60 0000 C CNN +F 3 "" H 4550 1450 60 0000 C CNN + 14 4550 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 1650 6350 1650 +Wire Wire Line + 4650 3550 6050 3550 +Wire Wire Line + 4650 3550 4650 5700 +Wire Wire Line + 4800 1450 4850 1450 +Connection ~ 4850 1650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023.sub b/library/SubcircuitLibrary/CD_4023/CD_4023.sub new file mode 100644 index 00000000..1a637c95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023.sub @@ -0,0 +1,26 @@ +* Subcircuit CD_4023 +.subckt CD_4023 net-_m1-pad2_ net-_m3-pad2_ net-_m12-pad2_ net-_m13-pad2_ net-_m14-pad2_ net-_m12-pad1_ net-_m11-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m15-pad1_ net-_m7-pad2_ net-_m10-pad2_ net-_m11-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4023\cd_4023.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m12-pad3_ net-_m13-pad2_ net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m12-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad3_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m15-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m15-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m15-pad1_ net-_m7-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m11 net-_m10-pad3_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4023 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4023/CD_4023_Previous_Values.xml b/library/SubcircuitLibrary/CD_4023/CD_4023_Previous_Values.xml new file mode 100644 index 00000000..52cd8138 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/CD_4023_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4023/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4023/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4023/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4023/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4023/README.md b/library/SubcircuitLibrary/CD_4023/README.md new file mode 100644 index 00000000..fe51165e --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/README.md @@ -0,0 +1,26 @@ + +# CD4023 IC + +It is 3-input NAND Gate IC. CD4023 IC is designed with 180nm CMOS technology in eSim consisting three NAND Gates. When both the inputs are HIGH then only output is LOW, otherwise HIGH. It is also called inverted AND Gate, a type of Universal logic Gate. + + +## Usage/Examples + +Burglar alarm + +Freezer warning buzzer + +## Documentation + +To know the details of CD4023 IC please go through with the documentation : [CD4023_datasheet](https://www.ti.com/lit/gpn/cd4023b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4023/analysis b/library/SubcircuitLibrary/CD_4023/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4023/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From e3d6e33a22a75efba2edbce316324836015190e7 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:52:52 +0530 Subject: CD4070 is XNOR gate IC. --- .../SubcircuitLibrary/CD_4070/CD_4070-cache.lib | 100 ++ library/SubcircuitLibrary/CD_4070/CD_4070.cir | 67 + library/SubcircuitLibrary/CD_4070/CD_4070.cir.out | 70 + library/SubcircuitLibrary/CD_4070/CD_4070.pro | 71 + library/SubcircuitLibrary/CD_4070/CD_4070.sch | 1532 ++++++++++++++++++++ library/SubcircuitLibrary/CD_4070/CD_4070.sub | 64 + .../CD_4070/CD_4070_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4070/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4070/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4070/README.md | 26 + library/SubcircuitLibrary/CD_4070/analysis | 1 + 11 files changed, 1956 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070.cir create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070.cir.out create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070.pro create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070.sch create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070.sub create mode 100644 library/SubcircuitLibrary/CD_4070/CD_4070_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4070/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4070/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4070/README.md create mode 100644 library/SubcircuitLibrary/CD_4070/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070-cache.lib b/library/SubcircuitLibrary/CD_4070/CD_4070-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070.cir b/library/SubcircuitLibrary/CD_4070/CD_4070.cir new file mode 100644 index 00000000..8fa1881b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070.cir @@ -0,0 +1,67 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4070\CD_4070.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/22 16:05:10 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M21 Net-_M13-Pad2_ Net-_M14-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M25 Net-_M13-Pad2_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M9 Net-_M10-Pad3_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M13 Net-_M10-Pad3_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M14 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad3_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M17 Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M17-Pad3_ Net-_M17-Pad3_ eSim_MOS_N +M18 Net-_M17-Pad3_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M50 Net-_M34-Pad2_ Net-_M42-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M54 Net-_M34-Pad2_ Net-_M42-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M37 Net-_M37-Pad1_ Net-_M29-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M41 Net-_M37-Pad1_ Net-_M34-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M38 Net-_M33-Pad1_ Net-_M29-Pad1_ Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M42 Net-_M33-Pad1_ Net-_M42-Pad2_ Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M31 Net-_M29-Pad1_ Net-_M29-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M29 Net-_M29-Pad1_ Net-_M29-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M33 Net-_M33-Pad1_ Net-_M29-Pad2_ Net-_M33-Pad3_ Net-_M33-Pad3_ eSim_MOS_N +M34 Net-_M33-Pad3_ Net-_M34-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M45 Net-_M33-Pad1_ Net-_M29-Pad1_ Net-_M45-Pad3_ Net-_M45-Pad3_ eSim_MOS_N +M46 Net-_M45-Pad3_ Net-_M42-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M23 Net-_M15-Pad2_ Net-_M16-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M27 Net-_M15-Pad2_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M15 Net-_M11-Pad1_ Net-_M15-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M16 Net-_M12-Pad1_ Net-_M16-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M4 Net-_M12-Pad2_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M12-Pad2_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M12-Pad1_ Net-_M11-Pad2_ Net-_M7-Pad3_ Net-_M7-Pad3_ eSim_MOS_N +M8 Net-_M7-Pad3_ Net-_M15-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M19 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M19-Pad3_ Net-_M19-Pad3_ eSim_MOS_N +M20 Net-_M19-Pad3_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M52 Net-_M36-Pad2_ Net-_M44-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M56 Net-_M36-Pad2_ Net-_M44-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M39 Net-_M39-Pad1_ Net-_M30-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M43 Net-_M39-Pad1_ Net-_M36-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M40 Net-_M35-Pad1_ Net-_M30-Pad1_ Net-_M39-Pad1_ Net-_M39-Pad1_ eSim_MOS_P +M44 Net-_M35-Pad1_ Net-_M44-Pad2_ Net-_M39-Pad1_ Net-_M39-Pad1_ eSim_MOS_P +M32 Net-_M30-Pad1_ Net-_M30-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M30 Net-_M30-Pad1_ Net-_M30-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M35 Net-_M35-Pad1_ Net-_M30-Pad2_ Net-_M35-Pad3_ Net-_M35-Pad3_ eSim_MOS_N +M36 Net-_M35-Pad3_ Net-_M36-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M47 Net-_M35-Pad1_ Net-_M30-Pad1_ Net-_M47-Pad3_ Net-_M47-Pad3_ eSim_MOS_N +M48 Net-_M47-Pad3_ Net-_M44-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M26 Net-_M22-Pad1_ Net-_M10-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M22 Net-_M22-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M28 Net-_M24-Pad1_ Net-_M12-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M24 Net-_M24-Pad1_ Net-_M12-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M53 Net-_M49-Pad1_ Net-_M35-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M49 Net-_M49-Pad1_ Net-_M35-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M55 Net-_M51-Pad1_ Net-_M33-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M51 Net-_M51-Pad1_ Net-_M33-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M11-Pad2_ Net-_M16-Pad2_ Net-_M24-Pad1_ Net-_M49-Pad1_ Net-_M30-Pad2_ Net-_M44-Pad2_ Net-_M1-Pad3_ Net-_M29-Pad2_ Net-_M42-Pad2_ Net-_M51-Pad1_ Net-_M22-Pad1_ Net-_M1-Pad2_ Net-_M14-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070.cir.out b/library/SubcircuitLibrary/CD_4070/CD_4070.cir.out new file mode 100644 index 00000000..8dd74c9b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070.cir.out @@ -0,0 +1,70 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4070\cd_4070.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m21 net-_m13-pad2_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m25 net-_m13-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m10-pad3_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m10-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m10-pad1_ net-_m1-pad1_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m34-pad2_ net-_m42-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m54 net-_m34-pad2_ net-_m42-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ net-_m29-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m41 net-_m37-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m38 net-_m33-pad1_ net-_m29-pad1_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m42 net-_m33-pad1_ net-_m42-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m29-pad1_ net-_m29-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m29 net-_m29-pad1_ net-_m29-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m29-pad2_ net-_m33-pad3_ net-_m33-pad3_ CMOSN W=100u L=100u M=1 +m34 net-_m33-pad3_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m33-pad1_ net-_m29-pad1_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ net-_m42-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m15-pad2_ net-_m16-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m27 net-_m15-pad2_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m16-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m12-pad2_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m12-pad2_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m12-pad1_ net-_m11-pad2_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m15-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m12-pad1_ net-_m12-pad2_ net-_m19-pad3_ net-_m19-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m19-pad3_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m52 net-_m36-pad2_ net-_m44-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m56 net-_m36-pad2_ net-_m44-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m39-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m43 net-_m39-pad1_ net-_m36-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m40 net-_m35-pad1_ net-_m30-pad1_ net-_m39-pad1_ net-_m39-pad1_ CMOSP W=100u L=100u M=1 +m44 net-_m35-pad1_ net-_m44-pad2_ net-_m39-pad1_ net-_m39-pad1_ CMOSP W=100u L=100u M=1 +m32 net-_m30-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m30 net-_m30-pad1_ net-_m30-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m30-pad2_ net-_m35-pad3_ net-_m35-pad3_ CMOSN W=100u L=100u M=1 +m36 net-_m35-pad3_ net-_m36-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m47 net-_m35-pad1_ net-_m30-pad1_ net-_m47-pad3_ net-_m47-pad3_ CMOSN W=100u L=100u M=1 +m48 net-_m47-pad3_ net-_m44-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m22-pad1_ net-_m10-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m10-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m28 net-_m24-pad1_ net-_m12-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m24-pad1_ net-_m12-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m53 net-_m49-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m49 net-_m49-pad1_ net-_m35-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m55 net-_m51-pad1_ net-_m33-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m51 net-_m51-pad1_ net-_m33-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m11-pad2_ net-_m16-pad2_ net-_m24-pad1_ net-_m49-pad1_ net-_m30-pad2_ net-_m44-pad2_ net-_m1-pad3_ net-_m29-pad2_ net-_m42-pad2_ net-_m51-pad1_ net-_m22-pad1_ net-_m1-pad2_ net-_m14-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070.pro b/library/SubcircuitLibrary/CD_4070/CD_4070.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070.sch b/library/SubcircuitLibrary/CD_4070/CD_4070.sch new file mode 100644 index 00000000..3cb5f222 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070.sch @@ -0,0 +1,1532 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4070-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M21 +U 1 1 629348CB +P 4750 1500 +F 0 "M21" H 4700 1550 50 0000 R CNN +F 1 "eSim_MOS_P" H 4800 1650 50 0000 R CNN +F 2 "" H 5000 1600 29 0000 C CNN +F 3 "" H 4800 1500 60 0000 C CNN + 1 4750 1500 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M25 +U 1 1 629348CC +P 4800 1900 +F 0 "M25" H 4800 1750 50 0000 R CNN +F 1 "eSim_MOS_N" H 4900 1850 50 0000 R CNN +F 2 "" H 5100 1600 29 0000 C CNN +F 3 "" H 4900 1700 60 0000 C CNN + 1 4800 1900 + -1 0 0 -1 +$EndComp +$Comp +L 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Wire Line + 10100 3800 9100 3800 +Wire Wire Line + 9100 3800 9100 4750 +Wire Wire Line + 9100 4750 8950 4750 +Connection ~ 10100 4450 +Wire Wire Line + 7800 6000 7800 5850 +Wire Wire Line + 7800 5850 9250 5850 +Wire Wire Line + 9250 5850 9250 4450 +Connection ~ 9250 4450 +Wire Wire Line + 6550 5500 7800 5500 +Wire Wire Line + 8950 5500 8950 5250 +Wire Wire Line + 8950 5250 7350 5250 +Wire Wire Line + 7350 5250 7350 4500 +Connection ~ 7350 4500 +Wire Wire Line + 10100 6000 8950 6000 +Wire Wire Line + 8350 5100 9450 5100 +Connection ~ 8350 5100 +Wire Wire Line + 7150 5000 7150 6250 +Connection ~ 8100 6250 +Connection ~ 7150 5000 +Wire Wire Line + 9550 6250 9550 5000 +Connection ~ 8650 6250 +Connection ~ 9550 5000 +Connection ~ 8100 4000 +Connection ~ 7200 4000 +Connection ~ 9500 4000 +Connection ~ 8650 4000 +Wire Wire Line + 5750 1000 5750 800 +Wire Wire Line + 5750 800 6050 800 +Connection ~ 5750 1000 +Connection ~ 7150 3550 +Connection ~ 4550 3550 +Connection ~ 7150 6250 +Connection ~ 4550 6250 +Wire Wire Line + 3400 4000 3400 3700 +Wire Wire Line + 3400 3700 8400 3700 +Wire Wire Line + 8400 3700 8400 4000 +Connection ~ 8400 4000 +Connection ~ 3400 4000 +Wire Wire Line + 5550 1000 5550 3700 +Connection ~ 5550 3700 +Connection ~ 5550 1000 +Wire Wire Line + 5850 3550 5850 6550 +Connection ~ 5850 6250 +Connection ~ 5850 3550 +Wire Wire Line + 5850 6550 5450 6550 +Wire Wire Line + 4950 2650 4950 2850 +Wire Wire Line + 4650 2450 4650 3050 +Wire Wire Line + 4950 3250 5050 3250 +Wire Wire Line + 5050 3250 5050 3200 +Wire Wire Line + 4950 2250 5050 2250 +Wire Wire Line + 5050 2250 5050 2300 +$Comp +L eSim_MOS_P M28 +U 1 1 6293690C +P 4800 5150 +F 0 "M28" H 4750 5200 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 5300 50 0000 R CNN +F 2 "" H 5050 5250 29 0000 C CNN +F 3 "" H 4850 5150 60 0000 C CNN + 1 4800 5150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M24 +U 1 1 62936912 +P 4750 5550 +F 0 "M24" H 4750 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 4850 5500 50 0000 R CNN +F 2 "" H 5050 5250 29 0000 C CNN +F 3 "" H 4850 5350 60 0000 C CNN + 1 4750 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 5350 4950 5550 +Wire Wire Line + 4650 5150 4650 5750 +Wire Wire Line + 4950 5950 5050 5950 +Wire Wire Line + 5050 5950 5050 5900 +Wire Wire Line + 4950 4950 5050 4950 +Wire Wire Line + 5050 4950 5050 5000 +$Comp +L eSim_MOS_P M53 +U 1 1 62936A1C +P 9750 5150 +F 0 "M53" H 9700 5200 50 0000 R CNN +F 1 "eSim_MOS_P" H 9800 5300 50 0000 R CNN +F 2 "" H 10000 5250 29 0000 C CNN +F 3 "" H 9800 5150 60 0000 C CNN + 1 9750 5150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M49 +U 1 1 62936A22 +P 9700 5550 +F 0 "M49" H 9700 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 9800 5500 50 0000 R CNN +F 2 "" H 10000 5250 29 0000 C CNN +F 3 "" H 9800 5350 60 0000 C CNN + 1 9700 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9900 5350 9900 5550 +Wire Wire Line + 9600 5150 9600 5750 +Wire Wire Line + 9900 5950 10000 5950 +Wire Wire Line + 10000 5950 10000 5900 +Wire Wire Line + 9900 4950 10000 4950 +Wire Wire Line + 10000 4950 10000 5000 +Wire Wire Line + 4400 2400 4400 2750 +Wire Wire Line + 4400 2750 4650 2750 +Connection ~ 4650 2750 +Wire Wire Line + 4950 2750 5300 2750 +Connection ~ 4950 2750 +$Comp +L eSim_MOS_P M55 +U 1 1 6293892C +P 9800 2450 +F 0 "M55" H 9750 2500 50 0000 R CNN +F 1 "eSim_MOS_P" H 9850 2600 50 0000 R CNN +F 2 "" H 10050 2550 29 0000 C CNN +F 3 "" H 9850 2450 60 0000 C CNN + 1 9800 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M51 +U 1 1 62938932 +P 9750 2850 +F 0 "M51" H 9750 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 9850 2800 50 0000 R CNN +F 2 "" H 10050 2550 29 0000 C CNN +F 3 "" H 9850 2650 60 0000 C CNN + 1 9750 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9950 2650 9950 2850 +Wire Wire Line + 9650 2450 9650 3050 +Wire Wire Line + 9950 3250 10050 3250 +Wire Wire Line + 10050 3250 10050 3200 +Wire Wire Line + 9950 2250 10050 2250 +Wire Wire Line + 10050 2250 10050 2300 +Wire Wire Line + 9450 2400 9450 2750 +Wire Wire Line + 9450 2750 9650 2750 +Connection ~ 9650 2750 +Wire Wire Line + 9950 2750 10400 2750 +Connection ~ 9950 2750 +Wire Wire Line + 10000 1300 10000 2250 +Connection ~ 9600 1300 +Connection ~ 10000 2250 +Wire Wire Line + 10000 3550 10000 3250 +Connection ~ 9550 3550 +Connection ~ 10000 3250 +Wire Wire Line + 5000 3250 5000 3550 +Connection ~ 5000 3550 +Connection ~ 5000 3250 +Wire Wire Line + 5000 1300 5000 2250 +Connection ~ 4600 1300 +Connection ~ 5000 2250 +Wire Wire Line + 4400 5100 4400 5450 +Wire Wire Line + 4400 5450 4650 5450 +Connection ~ 4650 5450 +Wire Wire Line + 4950 5450 5350 5450 +Connection ~ 4950 5450 +Wire Wire Line + 5000 4000 5000 4950 +Connection ~ 4600 4000 +Connection ~ 5000 4950 +Wire Wire Line + 5000 5950 5000 6250 +Connection ~ 5000 6250 +Connection ~ 5000 5950 +Wire Wire Line + 9450 5100 9450 5450 +Wire Wire Line + 9450 5450 9600 5450 +Connection ~ 9600 5450 +Wire Wire Line + 9900 5450 10400 5450 +Connection ~ 9900 5450 +Wire Wire Line + 9950 6250 9950 5950 +Connection ~ 9550 6250 +Connection ~ 9950 5950 +Wire Wire Line + 9950 4000 9950 4950 +Connection ~ 9600 4000 +Connection ~ 9950 4950 +$Comp +L PORT U1 +U 1 1 62940A44 +P 1050 4500 +F 0 "U1" H 1100 4600 30 0000 C CNN +F 1 "PORT" H 1050 4500 30 0000 C CNN +F 2 "" H 1050 4500 60 0000 C CNN +F 3 "" H 1050 4500 60 0000 C CNN + 1 1050 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 629421B0 +P 5700 4450 +F 0 "U1" H 5750 4550 30 0000 C CNN +F 1 "PORT" H 5700 4450 30 0000 C CNN +F 2 "" H 5700 4450 60 0000 C CNN +F 3 "" H 5700 4450 60 0000 C CNN + 2 5700 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 62942261 +P 5600 5450 +F 0 "U1" H 5650 5550 30 0000 C CNN +F 1 "PORT" H 5600 5450 30 0000 C CNN +F 2 "" H 5600 5450 60 0000 C CNN +F 3 "" H 5600 5450 60 0000 C CNN + 3 5600 5450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62942E1E +P 10650 5450 +F 0 "U1" H 10700 5550 30 0000 C CNN +F 1 "PORT" H 10650 5450 30 0000 C CNN +F 2 "" H 10650 5450 60 0000 C CNN +F 3 "" H 10650 5450 60 0000 C CNN + 4 10650 5450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62942ECD +P 6050 4500 +F 0 "U1" H 6100 4600 30 0000 C CNN +F 1 "PORT" H 6050 4500 30 0000 C CNN +F 2 "" H 6050 4500 60 0000 C CNN +F 3 "" H 6050 4500 60 0000 C CNN + 5 6050 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62942FC0 +P 10700 4450 +F 0 "U1" H 10750 4550 30 0000 C CNN +F 1 "PORT" H 10700 4450 30 0000 C CNN +F 2 "" H 10700 4450 60 0000 C CNN +F 3 "" H 10700 4450 60 0000 C CNN + 6 10700 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 62943409 +P 5200 6550 +F 0 "U1" H 5250 6650 30 0000 C CNN +F 1 "PORT" H 5200 6550 30 0000 C CNN +F 2 "" H 5200 6550 60 0000 C CNN +F 3 "" H 5200 6550 60 0000 C CNN + 7 5200 6550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6294598A +P 6050 1800 +F 0 "U1" H 6100 1900 30 0000 C CNN +F 1 "PORT" H 6050 1800 30 0000 C CNN +F 2 "" H 6050 1800 60 0000 C CNN +F 3 "" H 6050 1800 60 0000 C CNN + 8 6050 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62945A89 +P 10700 1750 +F 0 "U1" H 10750 1850 30 0000 C CNN +F 1 "PORT" H 10700 1750 30 0000 C CNN +F 2 "" H 10700 1750 60 0000 C CNN +F 3 "" H 10700 1750 60 0000 C CNN + 9 10700 1750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 62945B96 +P 10650 2750 +F 0 "U1" H 10700 2850 30 0000 C CNN +F 1 "PORT" H 10650 2750 30 0000 C CNN +F 2 "" H 10650 2750 60 0000 C CNN +F 3 "" H 10650 2750 60 0000 C CNN + 10 10650 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 62946EA2 +P 5550 2750 +F 0 "U1" H 5600 2850 30 0000 C CNN +F 1 "PORT" H 5550 2750 30 0000 C CNN +F 2 "" H 5550 2750 60 0000 C CNN +F 3 "" H 5550 2750 60 0000 C CNN + 11 5550 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 62946F6D +P 1050 1800 +F 0 "U1" H 1100 1900 30 0000 C CNN +F 1 "PORT" H 1050 1800 30 0000 C CNN +F 2 "" H 1050 1800 60 0000 C CNN +F 3 "" H 1050 1800 60 0000 C CNN + 12 1050 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 629481D4 +P 5700 1750 +F 0 "U1" H 5750 1850 30 0000 C CNN +F 1 "PORT" H 5700 1750 30 0000 C CNN +F 2 "" H 5700 1750 60 0000 C CNN +F 3 "" H 5700 1750 60 0000 C CNN + 13 5700 1750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6294829B +P 6300 800 +F 0 "U1" H 6350 900 30 0000 C CNN +F 1 "PORT" H 6300 800 30 0000 C CNN +F 2 "" H 6300 800 60 0000 C CNN +F 3 "" H 6300 800 60 0000 C CNN + 14 6300 800 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070.sub b/library/SubcircuitLibrary/CD_4070/CD_4070.sub new file mode 100644 index 00000000..87dfeb51 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070.sub @@ -0,0 +1,64 @@ +* Subcircuit CD_4070 +.subckt CD_4070 net-_m11-pad2_ net-_m16-pad2_ net-_m24-pad1_ net-_m49-pad1_ net-_m30-pad2_ net-_m44-pad2_ net-_m1-pad3_ net-_m29-pad2_ net-_m42-pad2_ net-_m51-pad1_ net-_m22-pad1_ net-_m1-pad2_ net-_m14-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4070\cd_4070.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m21 net-_m13-pad2_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m25 net-_m13-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m10-pad3_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m10-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m10-pad1_ net-_m1-pad1_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m34-pad2_ net-_m42-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m54 net-_m34-pad2_ net-_m42-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ net-_m29-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m41 net-_m37-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m38 net-_m33-pad1_ net-_m29-pad1_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m42 net-_m33-pad1_ net-_m42-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m29-pad1_ net-_m29-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m29 net-_m29-pad1_ net-_m29-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m29-pad2_ net-_m33-pad3_ net-_m33-pad3_ CMOSN W=100u L=100u M=1 +m34 net-_m33-pad3_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m33-pad1_ net-_m29-pad1_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ net-_m42-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m15-pad2_ net-_m16-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m27 net-_m15-pad2_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m16-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m12-pad2_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m12-pad2_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m12-pad1_ net-_m11-pad2_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m15-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m12-pad1_ net-_m12-pad2_ net-_m19-pad3_ net-_m19-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m19-pad3_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m52 net-_m36-pad2_ net-_m44-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m56 net-_m36-pad2_ net-_m44-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m39-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m43 net-_m39-pad1_ net-_m36-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m40 net-_m35-pad1_ net-_m30-pad1_ net-_m39-pad1_ net-_m39-pad1_ CMOSP W=100u L=100u M=1 +m44 net-_m35-pad1_ net-_m44-pad2_ net-_m39-pad1_ net-_m39-pad1_ CMOSP W=100u L=100u M=1 +m32 net-_m30-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m30 net-_m30-pad1_ net-_m30-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m30-pad2_ net-_m35-pad3_ net-_m35-pad3_ CMOSN W=100u L=100u M=1 +m36 net-_m35-pad3_ net-_m36-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m47 net-_m35-pad1_ net-_m30-pad1_ net-_m47-pad3_ net-_m47-pad3_ CMOSN W=100u L=100u M=1 +m48 net-_m47-pad3_ net-_m44-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m22-pad1_ net-_m10-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m10-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m28 net-_m24-pad1_ net-_m12-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m24-pad1_ net-_m12-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m53 net-_m49-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m49 net-_m49-pad1_ net-_m35-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m55 net-_m51-pad1_ net-_m33-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m51 net-_m51-pad1_ net-_m33-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4070 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4070/CD_4070_Previous_Values.xml b/library/SubcircuitLibrary/CD_4070/CD_4070_Previous_Values.xml new file mode 100644 index 00000000..ae1f75df --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/CD_4070_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4070/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4070/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4070/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4070/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4070/README.md b/library/SubcircuitLibrary/CD_4070/README.md new file mode 100644 index 00000000..f27fd979 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/README.md @@ -0,0 +1,26 @@ + +# CD4070 IC + +It is 2-input XOR Gate IC. CD4070 IC is designed with 180nm CMOS technology in eSim consisting four XOR Gates. It plays the role of odd 1’s detector. When both inputs are same, then output is LOW. It is also known as Special logic Gate. + +## Usage/Examples + +Logical Comparators + +Adders, Subtractors + +Parity Generators and Checkers +## Documentation + +To know the details of CD4070 IC please go through with the documentation : [CD4070_datasheet](https://www.ti.com/lit/gpn/cd4070b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4070/analysis b/library/SubcircuitLibrary/CD_4070/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4070/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 6996111988e740ae0283746398cacce78d4be6e7 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:55:29 +0530 Subject: CD4071 is OR gate IC. --- .../SubcircuitLibrary/CD_4071/CD_4071-cache.lib | 100 +++ library/SubcircuitLibrary/CD_4071/CD_4071.cir | 35 + library/SubcircuitLibrary/CD_4071/CD_4071.cir.out | 38 + library/SubcircuitLibrary/CD_4071/CD_4071.pro | 71 ++ library/SubcircuitLibrary/CD_4071/CD_4071.sch | 845 +++++++++++++++++++++ library/SubcircuitLibrary/CD_4071/CD_4071.sub | 32 + .../CD_4071/CD_4071_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4071/README.md | 30 + library/SubcircuitLibrary/CD_4071/analysis | 1 + 11 files changed, 1177 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071.cir create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071.cir.out create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071.pro create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071.sch create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071.sub create mode 100644 library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4071/README.md create mode 100644 library/SubcircuitLibrary/CD_4071/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib b/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.cir b/library/SubcircuitLibrary/CD_4071/CD_4071.cir new file mode 100644 index 00000000..03d0d508 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4071\CD_4071.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/20/22 11:07:38 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P +M7 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M15 Net-_M15-Pad1_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M16 Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M15-Pad1_ Net-_M15-Pad1_ eSim_MOS_P +M19 Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M23 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M21 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M5-Pad1_ Net-_M5-Pad1_ eSim_MOS_P +M8 Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M17 Net-_M17-Pad1_ Net-_M14-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M14 Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M18 Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M17-Pad1_ Net-_M17-Pad1_ eSim_MOS_P +M20 Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M24 Net-_M22-Pad1_ Net-_M14-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M22 Net-_M22-Pad1_ Net-_M14-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M10-Pad1_ Net-_M22-Pad1_ Net-_M14-Pad2_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M13-Pad2_ Net-_M16-Pad2_ Net-_M21-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out b/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out new file mode 100644 index 00000000..27410a17 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.cir.out @@ -0,0 +1,38 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4071\cd_4071.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m13-pad1_ net-_m16-pad2_ net-_m15-pad1_ net-_m15-pad1_ CMOSP W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m21-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m10-pad2_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m14-pad1_ net-_m18-pad2_ net-_m17-pad1_ net-_m17-pad1_ CMOSP W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m22-pad1_ net-_m14-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m22-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m1-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.pro b/library/SubcircuitLibrary/CD_4071/CD_4071.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.sch b/library/SubcircuitLibrary/CD_4071/CD_4071.sch new file mode 100644 index 00000000..1aca01d6 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.sch @@ -0,0 +1,845 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4071-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M3 +U 1 1 628727AE +P 3100 1750 +F 0 "M3" H 3050 1800 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 1900 50 0000 R CNN +F 2 "" H 3350 1850 29 0000 C CNN +F 3 "" H 3150 1750 60 0000 C CNN + 1 3100 1750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 628727AF +P 2700 2800 +F 0 "M1" H 2700 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 2800 2750 50 0000 R CNN +F 2 "" H 3000 2500 29 0000 C CNN +F 3 "" H 2800 2600 60 0000 C CNN + 1 2700 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 628727B0 +P 3100 2300 +F 0 "M4" H 3050 2350 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 2450 50 0000 R CNN +F 2 "" H 3350 2400 29 0000 C CNN +F 3 "" H 3150 2300 60 0000 C CNN + 1 3100 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 628727B1 +P 3850 2800 +F 0 "M7" H 3850 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 3950 2750 50 0000 R CNN +F 2 "" H 4150 2500 29 0000 C CNN +F 3 "" H 3950 2600 60 0000 C CNN + 1 3850 2800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 628727B2 +P 4800 2350 +F 0 "M11" H 4750 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 2500 50 0000 R CNN +F 2 "" H 5050 2450 29 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 1 4800 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 628727B3 +P 4750 2800 +F 0 "M9" H 4750 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 4850 2750 50 0000 R CNN +F 2 "" H 5050 2500 29 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4750 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3250 1950 3250 2100 +Wire Wire Line + 2900 3200 2900 3300 +Wire Wire Line + 2900 3300 3650 3300 +Wire Wire Line + 3650 3300 3650 3200 +Wire Wire Line + 2900 2800 2900 2750 +Wire Wire Line + 2900 2750 3650 2750 +Wire Wire Line + 3650 2750 3650 2800 +Wire Wire Line + 3250 2500 3250 2750 +Connection ~ 3250 2750 +Wire Wire Line + 3000 3150 3000 3300 +Connection ~ 3000 3300 +Wire Wire Line + 3550 3150 3550 3300 +Connection ~ 3550 3300 +Wire Wire Line + 4950 2550 4950 2800 +Wire Wire Line + 4650 2350 4600 2350 +Wire Wire Line + 4600 2350 4600 3000 +Wire Wire Line + 4600 3000 4650 3000 +Wire Wire Line + 4950 2150 5050 2150 +Wire Wire Line + 5050 2150 5050 2200 +Wire Wire Line + 4950 3200 5050 3200 +Wire Wire Line + 5050 3200 5050 3150 +Wire Wire Line + 3250 1550 3350 1550 +Wire Wire Line + 3350 1550 3350 1600 +Wire Wire Line + 3350 2150 3350 2050 +Wire Wire Line + 3350 2050 3250 2050 +Connection ~ 3250 2050 +Wire Wire Line + 3250 2600 4600 2600 +Connection ~ 4600 2600 +Connection ~ 3250 2600 +Wire Wire Line + 2950 1750 2500 1750 +Wire Wire Line + 2500 1750 2500 3000 +Wire Wire Line + 2500 3000 2600 3000 +Wire Wire Line + 2950 2300 2950 2500 +Wire Wire Line + 2200 2500 3950 2500 +Wire Wire Line + 3950 2500 3950 3000 +Wire Wire Line + 2500 2350 2200 2350 +Connection ~ 2500 2350 +Connection ~ 2950 2500 +Wire Wire Line + 3300 1550 3300 1500 +Wire Wire Line + 3300 1500 5000 1500 +Wire Wire Line + 5000 1500 5000 2150 +Connection ~ 5000 2150 +Connection ~ 3300 1550 +Wire Wire Line + 3250 3300 3250 3350 +Wire Wire Line + 3250 3350 8450 3350 +Wire Wire Line + 5000 3350 5000 3200 +Connection ~ 5000 3200 +Connection ~ 3250 3300 +Wire Wire Line + 4950 2650 5250 2650 +Connection ~ 4950 2650 +$Comp +L eSim_MOS_P M15 +U 1 1 628727B4 +P 6550 1750 +F 0 "M15" H 6500 1800 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 1900 50 0000 R CNN +F 2 "" H 6800 1850 29 0000 C CNN +F 3 "" H 6600 1750 60 0000 C CNN + 1 6550 1750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 628727B5 +P 6150 2800 +F 0 "M13" H 6150 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 6250 2750 50 0000 R CNN +F 2 "" H 6450 2500 29 0000 C CNN +F 3 "" H 6250 2600 60 0000 C CNN + 1 6150 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 628727B6 +P 6550 2300 +F 0 "M16" H 6500 2350 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 2450 50 0000 R CNN +F 2 "" H 6800 2400 29 0000 C CNN +F 3 "" H 6600 2300 60 0000 C CNN + 1 6550 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M19 +U 1 1 628727B7 +P 7300 2800 +F 0 "M19" H 7300 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 7400 2750 50 0000 R CNN +F 2 "" H 7600 2500 29 0000 C CNN +F 3 "" H 7400 2600 60 0000 C CNN + 1 7300 2800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M23 +U 1 1 628727B8 +P 8250 2350 +F 0 "M23" H 8200 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 8300 2500 50 0000 R CNN +F 2 "" H 8500 2450 29 0000 C CNN +F 3 "" H 8300 2350 60 0000 C CNN + 1 8250 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 628727B9 +P 8200 2800 +F 0 "M21" H 8200 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 8300 2750 50 0000 R CNN +F 2 "" H 8500 2500 29 0000 C CNN +F 3 "" H 8300 2600 60 0000 C CNN + 1 8200 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 1950 6700 2100 +Wire Wire Line + 6350 3200 6350 3300 +Wire Wire Line + 6350 3300 7100 3300 +Wire Wire Line + 7100 3300 7100 3200 +Wire Wire Line + 6350 2800 6350 2750 +Wire Wire Line + 6350 2750 7100 2750 +Wire Wire Line + 7100 2750 7100 2800 +Wire Wire Line + 6700 2500 6700 2750 +Connection ~ 6700 2750 +Wire Wire Line + 6450 3150 6450 3300 +Connection ~ 6450 3300 +Wire Wire Line + 7000 3150 7000 3300 +Connection ~ 7000 3300 +Wire Wire Line + 8400 2550 8400 2800 +Wire Wire Line + 8100 2350 8050 2350 +Wire Wire Line + 8050 2350 8050 3000 +Wire Wire Line + 8050 3000 8100 3000 +Wire Wire Line + 8400 2150 8500 2150 +Wire Wire Line + 8500 2150 8500 2200 +Wire Wire Line + 8400 3200 8500 3200 +Wire Wire Line + 8500 3200 8500 3150 +Wire Wire Line + 6700 1550 6800 1550 +Wire Wire Line + 6800 1550 6800 1600 +Wire Wire Line + 6800 2150 6800 2050 +Wire Wire Line + 6800 2050 6700 2050 +Connection ~ 6700 2050 +Wire Wire Line + 6700 2600 8050 2600 +Connection ~ 8050 2600 +Connection ~ 6700 2600 +Wire Wire Line + 6400 1750 5950 1750 +Wire Wire Line + 5950 1750 5950 3000 +Wire Wire Line + 5950 3000 6050 3000 +Wire Wire Line + 6400 2300 6400 2500 +Wire Wire Line + 5650 2500 7400 2500 +Wire Wire Line + 7400 2500 7400 3000 +Wire Wire Line + 5950 2350 5650 2350 +Connection ~ 5950 2350 +Connection ~ 6400 2500 +Wire Wire Line + 6750 1550 6750 1500 +Wire Wire Line + 6750 1500 8450 1500 +Wire Wire Line + 8450 1500 8450 2150 +Connection ~ 8450 2150 +Connection ~ 6750 1550 +Wire Wire Line + 6700 3350 6700 3300 +Wire Wire Line + 8450 3350 8450 3200 +Connection ~ 8450 3200 +Connection ~ 6700 3300 +Wire Wire Line + 8400 2650 8700 2650 +Connection ~ 8400 2650 +$Comp +L eSim_MOS_P M5 +U 1 1 628727BA +P 3100 3950 +F 0 "M5" H 3050 4000 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 4100 50 0000 R CNN +F 2 "" H 3350 4050 29 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 1 3100 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 628727BB +P 2700 5000 +F 0 "M2" H 2700 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 2800 4950 50 0000 R CNN +F 2 "" H 3000 4700 29 0000 C CNN +F 3 "" H 2800 4800 60 0000 C CNN + 1 2700 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 628727BC +P 3100 4500 +F 0 "M6" H 3050 4550 50 0000 R CNN +F 1 "eSim_MOS_P" H 3150 4650 50 0000 R CNN +F 2 "" H 3350 4600 29 0000 C CNN +F 3 "" H 3150 4500 60 0000 C CNN + 1 3100 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 628727BD +P 3850 5000 +F 0 "M8" H 3850 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 3950 4950 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4800 60 0000 C CNN + 1 3850 5000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 628727BE +P 4800 4550 +F 0 "M12" H 4750 4600 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 4700 50 0000 R CNN +F 2 "" H 5050 4650 29 0000 C CNN +F 3 "" H 4850 4550 60 0000 C CNN + 1 4800 4550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 628727BF +P 4750 5000 +F 0 "M10" H 4750 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 4850 4950 50 0000 R CNN +F 2 "" H 5050 4700 29 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4750 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3250 4150 3250 4300 +Wire Wire Line + 2900 5400 2900 5500 +Wire Wire Line + 2900 5500 3650 5500 +Wire Wire Line + 3650 5500 3650 5400 +Wire Wire Line + 2900 5000 2900 4950 +Wire Wire Line + 2900 4950 3650 4950 +Wire Wire Line + 3650 4950 3650 5000 +Wire Wire Line + 3250 4700 3250 4950 +Connection ~ 3250 4950 +Wire Wire Line + 3000 5350 3000 5500 +Connection ~ 3000 5500 +Wire Wire Line + 3550 5350 3550 5500 +Connection ~ 3550 5500 +Wire Wire Line + 4950 4750 4950 5000 +Wire Wire Line + 4650 4550 4600 4550 +Wire Wire Line + 4600 4550 4600 5200 +Wire Wire Line + 4600 5200 4650 5200 +Wire Wire Line + 4950 4350 5050 4350 +Wire Wire Line + 5050 4350 5050 4400 +Wire Wire Line + 4950 5400 5050 5400 +Wire Wire Line + 5050 5400 5050 5350 +Wire Wire Line + 3250 3750 3350 3750 +Wire Wire Line + 3350 3750 3350 3800 +Wire Wire Line + 3350 4350 3350 4250 +Wire Wire Line + 3350 4250 3250 4250 +Connection ~ 3250 4250 +Wire Wire Line + 3250 4800 4600 4800 +Connection ~ 4600 4800 +Connection ~ 3250 4800 +Wire Wire Line + 2950 3950 2500 3950 +Wire Wire Line + 2500 3950 2500 5200 +Wire Wire Line + 2500 5200 2600 5200 +Wire Wire Line + 2950 4500 2950 4700 +Wire Wire Line + 2200 4700 3950 4700 +Wire Wire Line + 3950 4700 3950 5200 +Wire Wire Line + 2500 4550 2200 4550 +Connection ~ 2500 4550 +Connection ~ 2950 4700 +Wire Wire Line + 3300 3750 3300 3700 +Wire Wire Line + 3300 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 4350 +Connection ~ 5000 4350 +Connection ~ 3300 3750 +Wire Wire Line + 3250 5500 3250 5550 +Wire Wire Line + 3250 5550 8450 5550 +Wire Wire Line + 5000 5550 5000 5400 +Connection ~ 5000 5400 +Connection ~ 3250 5500 +Wire Wire Line + 4950 4850 5250 4850 +Connection ~ 4950 4850 +$Comp +L eSim_MOS_P M17 +U 1 1 628727C0 +P 6550 3950 +F 0 "M17" H 6500 4000 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 4100 50 0000 R CNN +F 2 "" H 6800 4050 29 0000 C CNN +F 3 "" H 6600 3950 60 0000 C CNN + 1 6550 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M14 +U 1 1 628727C1 +P 6150 5000 +F 0 "M14" H 6150 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 6250 4950 50 0000 R CNN +F 2 "" H 6450 4700 29 0000 C CNN +F 3 "" H 6250 4800 60 0000 C CNN + 1 6150 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M18 +U 1 1 628727C2 +P 6550 4500 +F 0 "M18" H 6500 4550 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 4650 50 0000 R CNN +F 2 "" H 6800 4600 29 0000 C CNN +F 3 "" H 6600 4500 60 0000 C CNN + 1 6550 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M20 +U 1 1 628727C3 +P 7300 5000 +F 0 "M20" H 7300 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 7400 4950 50 0000 R CNN +F 2 "" H 7600 4700 29 0000 C CNN +F 3 "" H 7400 4800 60 0000 C CNN + 1 7300 5000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M24 +U 1 1 628727C4 +P 8250 4550 +F 0 "M24" H 8200 4600 50 0000 R CNN +F 1 "eSim_MOS_P" H 8300 4700 50 0000 R CNN +F 2 "" H 8500 4650 29 0000 C CNN +F 3 "" H 8300 4550 60 0000 C CNN + 1 8250 4550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M22 +U 1 1 628727C5 +P 8200 5000 +F 0 "M22" H 8200 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 8300 4950 50 0000 R CNN +F 2 "" H 8500 4700 29 0000 C CNN +F 3 "" H 8300 4800 60 0000 C CNN + 1 8200 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 4150 6700 4300 +Wire Wire Line + 6350 5400 6350 5500 +Wire Wire Line + 6350 5500 7100 5500 +Wire Wire Line + 7100 5500 7100 5400 +Wire Wire Line + 6350 5000 6350 4950 +Wire Wire Line + 6350 4950 7100 4950 +Wire Wire Line + 7100 4950 7100 5000 +Wire Wire Line + 6700 4700 6700 4950 +Connection ~ 6700 4950 +Wire Wire Line + 6450 5350 6450 5500 +Connection ~ 6450 5500 +Wire Wire Line + 7000 5350 7000 5500 +Connection ~ 7000 5500 +Wire Wire Line + 8400 4750 8400 5000 +Wire Wire Line + 8100 4550 8050 4550 +Wire Wire Line + 8050 4550 8050 5200 +Wire Wire Line + 8050 5200 8100 5200 +Wire Wire Line + 8400 4350 8500 4350 +Wire Wire Line + 8500 4350 8500 4400 +Wire Wire Line + 8400 5400 8500 5400 +Wire Wire Line + 8500 5400 8500 5350 +Wire Wire Line + 6700 3750 6800 3750 +Wire Wire Line + 6800 3750 6800 3800 +Wire Wire Line + 6800 4350 6800 4250 +Wire Wire Line + 6800 4250 6700 4250 +Connection ~ 6700 4250 +Wire Wire Line + 6700 4800 8050 4800 +Connection ~ 8050 4800 +Connection ~ 6700 4800 +Wire Wire Line + 6400 3950 5950 3950 +Wire Wire Line + 5950 3950 5950 5200 +Wire Wire Line + 5950 5200 6050 5200 +Wire Wire Line + 6400 4500 6400 4700 +Wire Wire Line + 5650 4700 7400 4700 +Wire Wire Line + 7400 4700 7400 5200 +Wire Wire Line + 5950 4550 5650 4550 +Connection ~ 5950 4550 +Connection ~ 6400 4700 +Wire Wire Line + 6750 3750 6750 3700 +Wire Wire Line + 6750 3700 8450 3700 +Wire Wire Line + 8450 3700 8450 4350 +Connection ~ 8450 4350 +Connection ~ 6750 3750 +Wire Wire Line + 6700 5550 6700 5500 +Wire Wire Line + 8450 5550 8450 5400 +Connection ~ 8450 5400 +Connection ~ 6700 5500 +Wire Wire Line + 8400 4850 8700 4850 +Connection ~ 8400 4850 +Wire Wire Line + 4150 1500 4150 1400 +Wire Wire Line + 4150 1400 7450 1400 +Wire Wire Line + 7450 1400 7450 1500 +Connection ~ 7450 1500 +Connection ~ 4150 1500 +Wire Wire Line + 4750 3700 4750 3650 +Wire Wire Line + 4750 3650 7250 3650 +Wire Wire Line + 7250 3650 7250 3700 +Connection ~ 7250 3700 +Connection ~ 4750 3700 +Connection ~ 6700 3350 +Connection ~ 5000 3350 +Connection ~ 6700 5550 +Connection ~ 5000 5550 +Wire Wire Line + 5450 1400 5450 3650 +Connection ~ 5450 3650 +Connection ~ 5450 1400 +Wire Wire Line + 5550 3350 5550 5750 +Connection ~ 5550 5550 +Connection ~ 5550 3350 +$Comp +L PORT U1 +U 1 1 6287296A +P 1950 4550 +F 0 "U1" H 2000 4650 30 0000 C CNN +F 1 "PORT" H 1950 4550 30 0000 C CNN +F 2 "" H 1950 4550 60 0000 C CNN +F 3 "" H 1950 4550 60 0000 C CNN + 1 1950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62872A2C +P 1950 4700 +F 0 "U1" H 2000 4800 30 0000 C CNN +F 1 "PORT" H 1950 4700 30 0000 C CNN +F 2 "" H 1950 4700 60 0000 C CNN +F 3 "" H 1950 4700 60 0000 C CNN + 2 1950 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62872A8F +P 5500 4850 +F 0 "U1" H 5550 4950 30 0000 C CNN +F 1 "PORT" H 5500 4850 30 0000 C CNN +F 2 "" H 5500 4850 60 0000 C CNN +F 3 "" H 5500 4850 60 0000 C CNN + 3 5500 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62872B0A +P 8950 4850 +F 0 "U1" H 9000 4950 30 0000 C CNN +F 1 "PORT" H 8950 4850 30 0000 C CNN +F 2 "" H 8950 4850 60 0000 C CNN +F 3 "" H 8950 4850 60 0000 C CNN + 4 8950 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62872C19 +P 5400 4550 +F 0 "U1" H 5450 4650 30 0000 C CNN +F 1 "PORT" H 5400 4550 30 0000 C CNN +F 2 "" H 5400 4550 60 0000 C CNN +F 3 "" H 5400 4550 60 0000 C CNN + 5 5400 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62872CBA +P 5400 4700 +F 0 "U1" H 5450 4800 30 0000 C CNN +F 1 "PORT" H 5400 4700 30 0000 C CNN +F 2 "" H 5400 4700 60 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 6 5400 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62872D4F +P 5300 5750 +F 0 "U1" H 5350 5850 30 0000 C CNN +F 1 "PORT" H 5300 5750 30 0000 C CNN +F 2 "" H 5300 5750 60 0000 C CNN +F 3 "" H 5300 5750 60 0000 C CNN + 7 5300 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62872F3E +P 5400 2350 +F 0 "U1" H 5450 2450 30 0000 C CNN +F 1 "PORT" H 5400 2350 30 0000 C CNN +F 2 "" H 5400 2350 60 0000 C CNN +F 3 "" H 5400 2350 60 0000 C CNN + 8 5400 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62872FF3 +P 5400 2500 +F 0 "U1" H 5450 2600 30 0000 C CNN +F 1 "PORT" H 5400 2500 30 0000 C CNN +F 2 "" H 5400 2500 60 0000 C CNN +F 3 "" H 5400 2500 60 0000 C CNN + 9 5400 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 628730B4 +P 8950 2650 +F 0 "U1" H 9000 2750 30 0000 C CNN +F 1 "PORT" H 8950 2650 30 0000 C CNN +F 2 "" H 8950 2650 60 0000 C CNN +F 3 "" H 8950 2650 60 0000 C CNN + 10 8950 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6287314B +P 5500 2650 +F 0 "U1" H 5550 2750 30 0000 C CNN +F 1 "PORT" H 5500 2650 30 0000 C CNN +F 2 "" H 5500 2650 60 0000 C CNN +F 3 "" H 5500 2650 60 0000 C CNN + 11 5500 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6287321E +P 1950 2350 +F 0 "U1" H 2000 2450 30 0000 C CNN +F 1 "PORT" H 1950 2350 30 0000 C CNN +F 2 "" H 1950 2350 60 0000 C CNN +F 3 "" H 1950 2350 60 0000 C CNN + 12 1950 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 628732C3 +P 1950 2500 +F 0 "U1" H 2000 2600 30 0000 C CNN +F 1 "PORT" H 1950 2500 30 0000 C CNN +F 2 "" H 1950 2500 60 0000 C CNN +F 3 "" H 1950 2500 60 0000 C CNN + 13 1950 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 628739BA +P 3900 1400 +F 0 "U1" H 3950 1500 30 0000 C CNN +F 1 "PORT" H 3900 1400 30 0000 C CNN +F 2 "" H 3900 1400 60 0000 C CNN +F 3 "" H 3900 1400 60 0000 C CNN + 14 3900 1400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071.sub b/library/SubcircuitLibrary/CD_4071/CD_4071.sub new file mode 100644 index 00000000..973024dd --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071.sub @@ -0,0 +1,32 @@ +* Subcircuit CD_4071 +.subckt CD_4071 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m22-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m1-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4071\cd_4071.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m15 net-_m15-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m13-pad1_ net-_m16-pad2_ net-_m15-pad1_ net-_m15-pad1_ CMOSP W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m21-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m10-pad2_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m17-pad1_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m14-pad1_ net-_m18-pad2_ net-_m17-pad1_ net-_m17-pad1_ CMOSP W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m24 net-_m22-pad1_ net-_m14-pad1_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m22-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4071 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml b/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml new file mode 100644 index 00000000..942286c7 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/CD_4071_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4071/README.md b/library/SubcircuitLibrary/CD_4071/README.md new file mode 100644 index 00000000..9f99fe20 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/README.md @@ -0,0 +1,30 @@ + +# CD4071 IC + +It is 2-input OR Gate IC. CD4071 IC is designed with 180nm CMOS technology in eSim consisting four OR Gates. When both the inputs are LOW then only output is LOW, otherwise HIGH. + + +## Usage/Examples + +In designing basic logic circuits or Alarm circuits for example alarm for a car door system can be designed using this IC. + +Encoders + +Decoders + +We can design Multiplexers of any size and also De-multiplexers. + +## Documentation + +To know the details of CD4071 IC please go through with the documentation : [CD4071_datasheet](https://www.ti.com/lit/gpn/cd4071b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4071/analysis b/library/SubcircuitLibrary/CD_4071/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4071/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 8144a629b934a21f3df7bb71215311e9b5b5e8cb Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:58:19 +0530 Subject: CD4077 is XNOR gate IC. --- .../SubcircuitLibrary/CD_4077/CD_4077-cache.lib | 100 ++ library/SubcircuitLibrary/CD_4077/CD_4077.cir | 59 + library/SubcircuitLibrary/CD_4077/CD_4077.cir.out | 62 + library/SubcircuitLibrary/CD_4077/CD_4077.pro | 71 + library/SubcircuitLibrary/CD_4077/CD_4077.sch | 1376 ++++++++++++++++++++ library/SubcircuitLibrary/CD_4077/CD_4077.sub | 56 + .../CD_4077/CD_4077_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4077/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4077/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4077/README.md | 28 + library/SubcircuitLibrary/CD_4077/analysis | 1 + 11 files changed, 1778 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077.cir create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077.cir.out create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077.pro create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077.sch create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077.sub create mode 100644 library/SubcircuitLibrary/CD_4077/CD_4077_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4077/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4077/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4077/README.md create mode 100644 library/SubcircuitLibrary/CD_4077/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077-cache.lib b/library/SubcircuitLibrary/CD_4077/CD_4077-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077.cir b/library/SubcircuitLibrary/CD_4077/CD_4077.cir new file mode 100644 index 00000000..349ff880 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077.cir @@ -0,0 +1,59 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4077\CD_4077.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/19/22 23:08:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M15 Net-_M11-Pad1_ Net-_M15-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M16 Net-_M12-Pad1_ Net-_M16-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M7 Net-_M12-Pad1_ Net-_M11-Pad2_ Net-_M7-Pad3_ Net-_M7-Pad3_ eSim_MOS_N +M19 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M19-Pad3_ Net-_M19-Pad3_ eSim_MOS_N +M8 Net-_M7-Pad3_ Net-_M15-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M20 Net-_M19-Pad3_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M12-Pad2_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M12-Pad2_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M22 Net-_M15-Pad2_ Net-_M16-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M24 Net-_M15-Pad2_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M39 Net-_M35-Pad1_ Net-_M32-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M35 Net-_M35-Pad1_ Net-_M26-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M36 Net-_M31-Pad1_ Net-_M26-Pad1_ Net-_M35-Pad1_ Net-_M35-Pad1_ eSim_MOS_P +M40 Net-_M31-Pad1_ Net-_M40-Pad2_ Net-_M35-Pad1_ Net-_M35-Pad1_ eSim_MOS_P +M31 Net-_M31-Pad1_ Net-_M26-Pad2_ Net-_M31-Pad3_ Net-_M31-Pad3_ eSim_MOS_N +M43 Net-_M31-Pad1_ Net-_M26-Pad1_ Net-_M43-Pad3_ Net-_M43-Pad3_ eSim_MOS_N +M32 Net-_M31-Pad3_ Net-_M32-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M44 Net-_M43-Pad3_ Net-_M40-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M28 Net-_M26-Pad1_ Net-_M26-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M26 Net-_M26-Pad1_ Net-_M26-Pad2_ Net-_M26-Pad3_ Net-_M26-Pad3_ eSim_MOS_N +M46 Net-_M32-Pad2_ Net-_M40-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M48 Net-_M32-Pad2_ Net-_M40-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M13 Net-_M10-Pad3_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M10-Pad3_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M14 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_P +M5 Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_N +M17 Net-_M10-Pad1_ Net-_M1-Pad1_ Net-_M17-Pad3_ Net-_M17-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad3_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M18 Net-_M17-Pad3_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M21 Net-_M13-Pad2_ Net-_M14-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M23 Net-_M13-Pad2_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M37 Net-_M33-Pad1_ Net-_M30-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M33 Net-_M33-Pad1_ Net-_M25-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M34 Net-_M29-Pad1_ Net-_M25-Pad1_ Net-_M33-Pad1_ Net-_M33-Pad1_ eSim_MOS_P +M38 Net-_M29-Pad1_ Net-_M38-Pad2_ Net-_M33-Pad1_ Net-_M33-Pad1_ eSim_MOS_P +M29 Net-_M29-Pad1_ Net-_M25-Pad2_ Net-_M29-Pad3_ Net-_M29-Pad3_ eSim_MOS_N +M41 Net-_M29-Pad1_ Net-_M25-Pad1_ Net-_M41-Pad3_ Net-_M41-Pad3_ eSim_MOS_N +M30 Net-_M29-Pad3_ Net-_M30-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M42 Net-_M41-Pad3_ Net-_M38-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M27 Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M25 Net-_M25-Pad1_ Net-_M25-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M45 Net-_M30-Pad2_ Net-_M38-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M47 Net-_M30-Pad2_ Net-_M38-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M14-Pad2_ Net-_M10-Pad1_ Net-_M29-Pad1_ Net-_M25-Pad2_ Net-_M38-Pad2_ Net-_M1-Pad3_ Net-_M26-Pad2_ Net-_M40-Pad2_ Net-_M31-Pad1_ Net-_M12-Pad1_ Net-_M11-Pad2_ Net-_M16-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077.cir.out b/library/SubcircuitLibrary/CD_4077/CD_4077.cir.out new file mode 100644 index 00000000..07aa4263 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077.cir.out @@ -0,0 +1,62 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4077\cd_4077.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m16-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m12-pad1_ net-_m11-pad2_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m12-pad1_ net-_m12-pad2_ net-_m19-pad3_ net-_m19-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m15-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m19-pad3_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m12-pad2_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m12-pad2_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m15-pad2_ net-_m16-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m15-pad2_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m35-pad1_ net-_m32-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m26-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m36 net-_m31-pad1_ net-_m26-pad1_ net-_m35-pad1_ net-_m35-pad1_ CMOSP W=100u L=100u M=1 +m40 net-_m31-pad1_ net-_m40-pad2_ net-_m35-pad1_ net-_m35-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m31-pad1_ net-_m26-pad2_ net-_m31-pad3_ net-_m31-pad3_ CMOSN W=100u L=100u M=1 +m43 net-_m31-pad1_ net-_m26-pad1_ net-_m43-pad3_ net-_m43-pad3_ CMOSN W=100u L=100u M=1 +m32 net-_m31-pad3_ net-_m32-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m44 net-_m43-pad3_ net-_m40-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m28 net-_m26-pad1_ net-_m26-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m26 net-_m26-pad1_ net-_m26-pad2_ net-_m26-pad3_ net-_m26-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m32-pad2_ net-_m40-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m48 net-_m32-pad2_ net-_m40-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m10-pad3_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m10-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m10-pad1_ net-_m1-pad1_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m13-pad2_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m23 net-_m13-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m33-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m25-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m34 net-_m29-pad1_ net-_m25-pad1_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m38 net-_m29-pad1_ net-_m38-pad2_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m29 net-_m29-pad1_ net-_m25-pad2_ net-_m29-pad3_ net-_m29-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m29-pad1_ net-_m25-pad1_ net-_m41-pad3_ net-_m41-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m29-pad3_ net-_m30-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m42 net-_m41-pad3_ net-_m38-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m27 net-_m25-pad1_ net-_m25-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m25 net-_m25-pad1_ net-_m25-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m30-pad2_ net-_m38-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m47 net-_m30-pad2_ net-_m38-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m14-pad2_ net-_m10-pad1_ net-_m29-pad1_ net-_m25-pad2_ net-_m38-pad2_ net-_m1-pad3_ net-_m26-pad2_ net-_m40-pad2_ net-_m31-pad1_ net-_m12-pad1_ net-_m11-pad2_ net-_m16-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077.pro b/library/SubcircuitLibrary/CD_4077/CD_4077.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077.sch b/library/SubcircuitLibrary/CD_4077/CD_4077.sch new file mode 100644 index 00000000..393fedbc --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077.sch @@ -0,0 +1,1376 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4077-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M15 +U 1 1 62867BD2 +P 4300 1250 +F 0 "M15" H 4250 1300 50 0000 R CNN +F 1 "eSim_MOS_P" H 4350 1400 50 0000 R CNN +F 2 "" H 4550 1350 29 0000 C CNN +F 3 "" H 4350 1250 60 0000 C CNN + 1 4300 1250 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 62867BD3 +P 3500 1250 +F 0 "M11" H 3450 1300 50 0000 R CNN +F 1 "eSim_MOS_P" H 3550 1400 50 0000 R CNN +F 2 "" H 3750 1350 29 0000 C CNN +F 3 "" H 3550 1250 60 0000 C CNN + 1 3500 1250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 62867BD4 +P 3500 1800 +F 0 "M12" H 3450 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 3550 1950 50 0000 R CNN +F 2 "" H 3750 1900 29 0000 C CNN +F 3 "" H 3550 1800 60 0000 C CNN + 1 3500 1800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M16 +U 1 1 62867BD5 +P 4300 1800 +F 0 "M16" H 4250 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 4350 1950 50 0000 R CNN +F 2 "" H 4550 1900 29 0000 C CNN +F 3 "" H 4350 1800 60 0000 C CNN + 1 4300 1800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 62867BD6 +P 3450 2250 +F 0 "M7" H 3450 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 3550 2200 50 0000 R CNN +F 2 "" H 3750 1950 29 0000 C CNN +F 3 "" H 3550 2050 60 0000 C CNN + 1 3450 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M19 +U 1 1 62867BD7 +P 4350 2250 +F 0 "M19" H 4350 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4450 2200 50 0000 R CNN +F 2 "" H 4650 1950 29 0000 C CNN +F 3 "" H 4450 2050 60 0000 C CNN + 1 4350 2250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 62867BD8 +P 3450 2750 +F 0 "M8" H 3450 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 3550 2700 50 0000 R CNN +F 2 "" H 3750 2450 29 0000 C CNN +F 3 "" H 3550 2550 60 0000 C CNN + 1 3450 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M20 +U 1 1 62867BD9 +P 4350 2750 +F 0 "M20" H 4350 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 4450 2700 50 0000 R CNN +F 2 "" H 4650 2450 29 0000 C CNN +F 3 "" H 4450 2550 60 0000 C CNN + 1 4350 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 62867BDA +P 2750 1200 +F 0 "M4" H 2700 1250 50 0000 R CNN +F 1 "eSim_MOS_P" H 2800 1350 50 0000 R CNN +F 2 "" H 3000 1300 29 0000 C CNN +F 3 "" H 2800 1200 60 0000 C CNN + 1 2750 1200 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62867BDB +P 2700 1550 +F 0 "M2" H 2700 1400 50 0000 R CNN +F 1 "eSim_MOS_N" H 2800 1500 50 0000 R CNN +F 2 "" H 3000 1250 29 0000 C CNN +F 3 "" H 2800 1350 60 0000 C CNN + 1 2700 1550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M22 +U 1 1 62867BDC +P 5300 1200 +F 0 "M22" H 5250 1250 50 0000 R CNN +F 1 "eSim_MOS_P" H 5350 1350 50 0000 R CNN +F 2 "" H 5550 1300 29 0000 C CNN +F 3 "" H 5350 1200 60 0000 C CNN + 1 5300 1200 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M24 +U 1 1 62867BDD +P 5350 1550 +F 0 "M24" H 5350 1400 50 0000 R CNN +F 1 "eSim_MOS_N" H 5450 1500 50 0000 R CNN +F 2 "" H 5650 1250 29 0000 C CNN +F 3 "" H 5450 1350 60 0000 C CNN + 1 5350 1550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M39 +U 1 1 62867BDE +P 8250 1250 +F 0 "M39" H 8200 1300 50 0000 R CNN +F 1 "eSim_MOS_P" H 8300 1400 50 0000 R CNN +F 2 "" H 8500 1350 29 0000 C CNN +F 3 "" H 8300 1250 60 0000 C CNN + 1 8250 1250 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M35 +U 1 1 62867BDF +P 7450 1250 +F 0 "M35" H 7400 1300 50 0000 R CNN +F 1 "eSim_MOS_P" H 7500 1400 50 0000 R CNN +F 2 "" H 7700 1350 29 0000 C CNN +F 3 "" H 7500 1250 60 0000 C CNN + 1 7450 1250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M36 +U 1 1 62867BE0 +P 7450 1800 +F 0 "M36" H 7400 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 7500 1950 50 0000 R CNN +F 2 "" H 7700 1900 29 0000 C CNN +F 3 "" H 7500 1800 60 0000 C CNN + 1 7450 1800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M40 +U 1 1 62867BE1 +P 8250 1800 +F 0 "M40" H 8200 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 8300 1950 50 0000 R CNN +F 2 "" H 8500 1900 29 0000 C CNN +F 3 "" H 8300 1800 60 0000 C CNN + 1 8250 1800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M31 +U 1 1 62867BE2 +P 7400 2250 +F 0 "M31" H 7400 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 7500 2200 50 0000 R CNN +F 2 "" H 7700 1950 29 0000 C CNN +F 3 "" H 7500 2050 60 0000 C CNN + 1 7400 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M43 +U 1 1 62867BE3 +P 8300 2250 +F 0 "M43" H 8300 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 8400 2200 50 0000 R CNN +F 2 "" H 8600 1950 29 0000 C CNN +F 3 "" H 8400 2050 60 0000 C CNN + 1 8300 2250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M32 +U 1 1 62867BE4 +P 7400 2750 +F 0 "M32" H 7400 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 7500 2700 50 0000 R CNN +F 2 "" H 7700 2450 29 0000 C CNN +F 3 "" H 7500 2550 60 0000 C CNN + 1 7400 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M44 +U 1 1 62867BE5 +P 8300 2750 +F 0 "M44" H 8300 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 8400 2700 50 0000 R CNN +F 2 "" H 8600 2450 29 0000 C CNN +F 3 "" H 8400 2550 60 0000 C CNN + 1 8300 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M28 +U 1 1 62867BE6 +P 6700 1200 +F 0 "M28" H 6650 1250 50 0000 R CNN +F 1 "eSim_MOS_P" H 6750 1350 50 0000 R CNN +F 2 "" H 6950 1300 29 0000 C CNN +F 3 "" H 6750 1200 60 0000 C CNN + 1 6700 1200 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M26 +U 1 1 62867BE7 +P 6650 1550 +F 0 "M26" H 6650 1400 50 0000 R CNN +F 1 "eSim_MOS_N" H 6750 1500 50 0000 R CNN +F 2 "" H 6950 1250 29 0000 C CNN +F 3 "" H 6750 1350 60 0000 C CNN + 1 6650 1550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M46 +U 1 1 62867BE8 +P 9250 1200 +F 0 "M46" H 9200 1250 50 0000 R CNN +F 1 "eSim_MOS_P" H 9300 1350 50 0000 R CNN +F 2 "" H 9500 1300 29 0000 C CNN +F 3 "" H 9300 1200 60 0000 C CNN + 1 9250 1200 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M48 +U 1 1 62867BE9 +P 9300 1550 +F 0 "M48" H 9300 1400 50 0000 R CNN +F 1 "eSim_MOS_N" H 9400 1500 50 0000 R CNN +F 2 "" H 9600 1250 29 0000 C CNN +F 3 "" H 9400 1350 60 0000 C CNN + 1 9300 1550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 62867BEA +P 4250 4050 +F 0 "M13" H 4200 4100 50 0000 R CNN +F 1 "eSim_MOS_P" H 4300 4200 50 0000 R CNN +F 2 "" H 4500 4150 29 0000 C CNN +F 3 "" H 4300 4050 60 0000 C CNN + 1 4250 4050 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M9 +U 1 1 62867BEB +P 3450 4050 +F 0 "M9" H 3400 4100 50 0000 R CNN +F 1 "eSim_MOS_P" H 3500 4200 50 0000 R CNN +F 2 "" H 3700 4150 29 0000 C CNN +F 3 "" H 3500 4050 60 0000 C CNN + 1 3450 4050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M10 +U 1 1 62867BEC +P 3450 4600 +F 0 "M10" H 3400 4650 50 0000 R CNN +F 1 "eSim_MOS_P" H 3500 4750 50 0000 R CNN +F 2 "" H 3700 4700 29 0000 C CNN +F 3 "" H 3500 4600 60 0000 C CNN + 1 3450 4600 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 62867BED +P 4250 4600 +F 0 "M14" H 4200 4650 50 0000 R CNN +F 1 "eSim_MOS_P" H 4300 4750 50 0000 R CNN +F 2 "" H 4500 4700 29 0000 C CNN +F 3 "" H 4300 4600 60 0000 C CNN + 1 4250 4600 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 62867BEE +P 3400 5050 +F 0 "M5" H 3400 4900 50 0000 R CNN +F 1 "eSim_MOS_N" H 3500 5000 50 0000 R CNN +F 2 "" H 3700 4750 29 0000 C CNN +F 3 "" H 3500 4850 60 0000 C CNN + 1 3400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M17 +U 1 1 62867BEF +P 4300 5050 +F 0 "M17" H 4300 4900 50 0000 R CNN +F 1 "eSim_MOS_N" H 4400 5000 50 0000 R CNN +F 2 "" H 4600 4750 29 0000 C CNN +F 3 "" H 4400 4850 60 0000 C CNN + 1 4300 5050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 62867BF0 +P 3400 5550 +F 0 "M6" H 3400 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 3500 5500 50 0000 R CNN +F 2 "" H 3700 5250 29 0000 C CNN +F 3 "" H 3500 5350 60 0000 C CNN + 1 3400 5550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M18 +U 1 1 62867BF1 +P 4300 5550 +F 0 "M18" H 4300 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 4400 5500 50 0000 R CNN +F 2 "" H 4600 5250 29 0000 C CNN +F 3 "" H 4400 5350 60 0000 C CNN + 1 4300 5550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 62867BF2 +P 2700 4000 +F 0 "M3" H 2650 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 2750 4150 50 0000 R CNN +F 2 "" H 2950 4100 29 0000 C CNN +F 3 "" H 2750 4000 60 0000 C CNN + 1 2700 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62867BF3 +P 2650 4350 +F 0 "M1" H 2650 4200 50 0000 R CNN +F 1 "eSim_MOS_N" H 2750 4300 50 0000 R CNN +F 2 "" H 2950 4050 29 0000 C CNN +F 3 "" H 2750 4150 60 0000 C CNN + 1 2650 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M21 +U 1 1 62867BF4 +P 5250 4000 +F 0 "M21" H 5200 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 4150 50 0000 R CNN +F 2 "" H 5500 4100 29 0000 C CNN +F 3 "" H 5300 4000 60 0000 C CNN + 1 5250 4000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M23 +U 1 1 62867BF5 +P 5300 4350 +F 0 "M23" H 5300 4200 50 0000 R CNN +F 1 "eSim_MOS_N" H 5400 4300 50 0000 R CNN +F 2 "" H 5600 4050 29 0000 C CNN +F 3 "" H 5400 4150 60 0000 C CNN + 1 5300 4350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M37 +U 1 1 62867BF6 +P 8200 4050 +F 0 "M37" H 8150 4100 50 0000 R CNN +F 1 "eSim_MOS_P" H 8250 4200 50 0000 R CNN +F 2 "" H 8450 4150 29 0000 C CNN +F 3 "" H 8250 4050 60 0000 C CNN + 1 8200 4050 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M33 +U 1 1 62867BF7 +P 7400 4050 +F 0 "M33" H 7350 4100 50 0000 R CNN +F 1 "eSim_MOS_P" H 7450 4200 50 0000 R CNN +F 2 "" H 7650 4150 29 0000 C CNN +F 3 "" H 7450 4050 60 0000 C CNN + 1 7400 4050 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M34 +U 1 1 62867BF8 +P 7400 4600 +F 0 "M34" H 7350 4650 50 0000 R CNN +F 1 "eSim_MOS_P" H 7450 4750 50 0000 R CNN +F 2 "" H 7650 4700 29 0000 C CNN +F 3 "" H 7450 4600 60 0000 C CNN + 1 7400 4600 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M38 +U 1 1 62867BF9 +P 8200 4600 +F 0 "M38" H 8150 4650 50 0000 R CNN +F 1 "eSim_MOS_P" H 8250 4750 50 0000 R CNN +F 2 "" H 8450 4700 29 0000 C CNN +F 3 "" H 8250 4600 60 0000 C CNN + 1 8200 4600 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M29 +U 1 1 62867BFA +P 7350 5050 +F 0 "M29" H 7350 4900 50 0000 R CNN +F 1 "eSim_MOS_N" H 7450 5000 50 0000 R CNN +F 2 "" H 7650 4750 29 0000 C CNN +F 3 "" H 7450 4850 60 0000 C CNN + 1 7350 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M41 +U 1 1 62867BFB +P 8250 5050 +F 0 "M41" H 8250 4900 50 0000 R CNN +F 1 "eSim_MOS_N" H 8350 5000 50 0000 R CNN +F 2 "" H 8550 4750 29 0000 C CNN +F 3 "" H 8350 4850 60 0000 C CNN + 1 8250 5050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M30 +U 1 1 62867BFC +P 7350 5550 +F 0 "M30" H 7350 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 7450 5500 50 0000 R CNN +F 2 "" H 7650 5250 29 0000 C CNN +F 3 "" H 7450 5350 60 0000 C CNN + 1 7350 5550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M42 +U 1 1 62867BFD +P 8250 5550 +F 0 "M42" H 8250 5400 50 0000 R CNN +F 1 "eSim_MOS_N" H 8350 5500 50 0000 R CNN +F 2 "" H 8550 5250 29 0000 C CNN +F 3 "" H 8350 5350 60 0000 C CNN + 1 8250 5550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M27 +U 1 1 62867BFE +P 6650 4000 +F 0 "M27" H 6600 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 6700 4150 50 0000 R CNN +F 2 "" H 6900 4100 29 0000 C CNN +F 3 "" H 6700 4000 60 0000 C CNN + 1 6650 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M25 +U 1 1 62867BFF +P 6600 4350 +F 0 "M25" H 6600 4200 50 0000 R CNN +F 1 "eSim_MOS_N" H 6700 4300 50 0000 R CNN +F 2 "" H 6900 4050 29 0000 C CNN +F 3 "" H 6700 4150 60 0000 C CNN + 1 6600 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M45 +U 1 1 62867C00 +P 9200 4000 +F 0 "M45" H 9150 4050 50 0000 R CNN +F 1 "eSim_MOS_P" H 9250 4150 50 0000 R CNN +F 2 "" H 9450 4100 29 0000 C CNN +F 3 "" H 9250 4000 60 0000 C CNN + 1 9200 4000 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M47 +U 1 1 62867C01 +P 9250 4350 +F 0 "M47" H 9250 4200 50 0000 R CNN +F 1 "eSim_MOS_N" H 9350 4300 50 0000 R CNN +F 2 "" H 9550 4050 29 0000 C CNN +F 3 "" H 9350 4150 60 0000 C CNN + 1 9250 4350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3650 1000 3650 1050 +Wire Wire Line + 2900 1000 5150 1000 +Wire Wire Line + 4150 1000 4150 1050 +Wire Wire Line + 3650 1450 3650 1600 +Wire Wire Line + 4150 1450 4150 1600 +Wire Wire Line + 3650 1500 4150 1500 +Connection ~ 4150 1500 +Connection ~ 3650 1500 +Wire Wire Line + 3650 2000 4150 2000 +Wire Wire Line + 3650 2250 4150 2250 +Wire Wire Line + 2950 3150 9050 3150 +Wire Wire Line + 3900 2000 3900 2250 +Connection ~ 3900 2250 +Connection ~ 3900 2000 +Wire Wire Line + 3650 2650 3650 2750 +Wire Wire Line + 4150 2650 4150 2750 +Wire Wire Line + 3750 1100 3750 1000 +Connection ~ 3750 1000 +Wire Wire Line + 4050 1100 4050 1000 +Connection ~ 4050 1000 +Wire Wire Line + 3750 1650 3750 1550 +Wire Wire Line + 3750 1550 3650 1550 +Connection ~ 3650 1550 +Wire Wire Line + 4050 1650 4050 1550 +Wire Wire Line + 4050 1550 4150 1550 +Connection ~ 4150 1550 +Wire Wire Line + 3750 2600 3750 2700 +Wire Wire Line + 3750 2700 3650 2700 +Connection ~ 3650 2700 +Wire Wire Line + 4050 2600 4050 2700 +Wire Wire Line + 4050 2700 4150 2700 +Connection ~ 4150 2700 +Wire Wire Line + 3750 3100 3750 3150 +Connection ~ 3750 3150 +Wire Wire Line + 4050 3100 4050 3150 +Connection ~ 4050 3150 +Wire Wire Line + 2600 1200 2600 1750 +Wire Wire Line + 3000 1000 3000 1050 +Wire Wire Line + 2900 1950 3000 1950 +Wire Wire Line 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Line + 9650 4850 8700 4850 +Wire Wire Line + 8700 4600 8700 5750 +Wire Wire Line + 8700 4600 8350 4600 +Connection ~ 9350 4250 +Wire Wire Line + 6250 5250 7250 5250 +Connection ~ 6250 4300 +Wire Wire Line + 8850 4900 6950 4900 +Wire Wire Line + 6950 4900 6950 5750 +Wire Wire Line + 6950 5750 7250 5750 +Connection ~ 8850 4250 +Wire Wire Line + 8700 5750 8350 5750 +Connection ~ 8700 4850 +Wire Wire Line + 7150 5000 8350 5000 +Wire Wire Line + 8350 5000 8350 5250 +Connection ~ 7150 4600 +Wire Wire Line + 7800 4950 8550 4950 +Wire Wire Line + 8550 4950 8550 5300 +Wire Wire Line + 8550 5300 9450 5300 +Connection ~ 7800 4950 +Wire Wire Line + 6850 4750 6850 5950 +Connection ~ 7550 5950 +Connection ~ 6850 4750 +Wire Wire Line + 9000 5950 9000 4750 +Connection ~ 8050 5950 +Connection ~ 9000 4750 +Wire Wire Line + 5150 1000 5150 750 +Wire Wire Line + 5000 750 6850 750 +Wire Wire Line + 6850 750 6850 1000 +Wire Wire Line + 5100 3800 5100 3500 +Wire Wire Line + 5100 3500 6800 3500 +Wire Wire Line + 6800 3500 6800 3800 +Connection ~ 6950 3150 +Connection ~ 5100 3150 +Connection ~ 6850 5950 +Connection ~ 5050 5950 +Wire Wire Line + 5800 3150 5800 6200 +Connection ~ 5800 5950 +Connection ~ 5800 3150 +Wire Wire Line + 6000 750 6000 3500 +Connection ~ 6000 3500 +Connection ~ 6000 750 +Wire Wire Line + 5700 4700 5850 4700 +Connection ~ 5700 4700 +Connection ~ 9650 4250 +Connection ~ 9700 1450 +Connection ~ 5750 2050 +$Comp +L PORT U1 +U 1 1 628776E2 +P 1650 4300 +F 0 "U1" H 1700 4400 30 0000 C CNN +F 1 "PORT" H 1650 4300 30 0000 C CNN +F 2 "" H 1650 4300 60 0000 C CNN +F 3 "" H 1650 4300 60 0000 C CNN + 1 1650 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62877816 +P 6100 4700 +F 0 "U1" H 6150 4800 30 0000 C CNN +F 1 "PORT" H 6100 4700 30 0000 C CNN +F 2 "" H 6100 4700 60 0000 C CNN +F 3 "" H 6100 4700 60 0000 C CNN + 2 6100 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 628778B1 +P 5750 5300 +F 0 "U1" H 5800 5400 30 0000 C CNN +F 1 "PORT" H 5750 5300 30 0000 C CNN +F 2 "" H 5750 5300 60 0000 C CNN +F 3 "" H 5750 5300 60 0000 C CNN + 3 5750 5300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 628780D0 +P 9700 5300 +F 0 "U1" H 9750 5400 30 0000 C CNN +F 1 "PORT" H 9700 5300 30 0000 C CNN +F 2 "" H 9700 5300 60 0000 C CNN +F 3 "" H 9700 5300 60 0000 C CNN + 4 9700 5300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62878167 +P 6000 4300 +F 0 "U1" H 6050 4400 30 0000 C CNN +F 1 "PORT" H 6000 4300 30 0000 C CNN +F 2 "" H 6000 4300 60 0000 C CNN +F 3 "" H 6000 4300 60 0000 C CNN + 5 6000 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 628781F8 +P 10050 4250 +F 0 "U1" H 10100 4350 30 0000 C CNN +F 1 "PORT" H 10050 4250 30 0000 C CNN +F 2 "" H 10050 4250 60 0000 C CNN +F 3 "" H 10050 4250 60 0000 C CNN + 6 10050 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 62878287 +P 5550 6200 +F 0 "U1" H 5600 6300 30 0000 C CNN +F 1 "PORT" H 5550 6200 30 0000 C CNN +F 2 "" H 5550 6200 60 0000 C CNN +F 3 "" H 5550 6200 60 0000 C CNN + 7 5550 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6287B799 +P 6050 1500 +F 0 "U1" H 6100 1600 30 0000 C CNN +F 1 "PORT" H 6050 1500 30 0000 C CNN +F 2 "" H 6050 1500 60 0000 C CNN +F 3 "" H 6050 1500 60 0000 C CNN + 8 6050 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6287B940 +P 10100 1450 +F 0 "U1" H 10150 1550 30 0000 C CNN +F 1 "PORT" H 10100 1450 30 0000 C CNN +F 2 "" H 10100 1450 60 0000 C CNN +F 3 "" H 10100 1450 60 0000 C CNN + 9 10100 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6287B9DD +P 9750 2500 +F 0 "U1" H 9800 2600 30 0000 C CNN +F 1 "PORT" H 9750 2500 30 0000 C CNN +F 2 "" H 9750 2500 60 0000 C CNN +F 3 "" H 9750 2500 60 0000 C CNN + 10 9750 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6287CC98 +P 5800 2500 +F 0 "U1" H 5850 2600 30 0000 C CNN +F 1 "PORT" H 5800 2500 30 0000 C CNN +F 2 "" H 5800 2500 60 0000 C CNN +F 3 "" H 5800 2500 60 0000 C CNN + 11 5800 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 6287CD45 +P 1650 1500 +F 0 "U1" H 1700 1600 30 0000 C CNN +F 1 "PORT" H 1650 1500 30 0000 C CNN +F 2 "" H 1650 1500 60 0000 C CNN +F 3 "" H 1650 1500 60 0000 C CNN + 12 1650 1500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6287D802 +P 6000 2050 +F 0 "U1" H 6050 2150 30 0000 C CNN +F 1 "PORT" H 6000 2050 30 0000 C CNN +F 2 "" H 6000 2050 60 0000 C CNN +F 3 "" H 6000 2050 60 0000 C CNN + 13 6000 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6287D8A7 +P 4750 750 +F 0 "U1" H 4800 850 30 0000 C CNN +F 1 "PORT" H 4750 750 30 0000 C CNN +F 2 "" H 4750 750 60 0000 C CNN +F 3 "" H 4750 750 60 0000 C CNN + 14 4750 750 + 1 0 0 -1 +$EndComp +Connection ~ 5150 750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077.sub b/library/SubcircuitLibrary/CD_4077/CD_4077.sub new file mode 100644 index 00000000..aa351499 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077.sub @@ -0,0 +1,56 @@ +* Subcircuit CD_4077 +.subckt CD_4077 net-_m1-pad2_ net-_m14-pad2_ net-_m10-pad1_ net-_m29-pad1_ net-_m25-pad2_ net-_m38-pad2_ net-_m1-pad3_ net-_m26-pad2_ net-_m40-pad2_ net-_m31-pad1_ net-_m12-pad1_ net-_m11-pad2_ net-_m16-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4077\cd_4077.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m15 net-_m11-pad1_ net-_m15-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m12-pad1_ net-_m16-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m12-pad1_ net-_m11-pad2_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m12-pad1_ net-_m12-pad2_ net-_m19-pad3_ net-_m19-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ net-_m15-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m19-pad3_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m12-pad2_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m12-pad2_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m15-pad2_ net-_m16-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m15-pad2_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m39 net-_m35-pad1_ net-_m32-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m35 net-_m35-pad1_ net-_m26-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m36 net-_m31-pad1_ net-_m26-pad1_ net-_m35-pad1_ net-_m35-pad1_ CMOSP W=100u L=100u M=1 +m40 net-_m31-pad1_ net-_m40-pad2_ net-_m35-pad1_ net-_m35-pad1_ CMOSP W=100u L=100u M=1 +m31 net-_m31-pad1_ net-_m26-pad2_ net-_m31-pad3_ net-_m31-pad3_ CMOSN W=100u L=100u M=1 +m43 net-_m31-pad1_ net-_m26-pad1_ net-_m43-pad3_ net-_m43-pad3_ CMOSN W=100u L=100u M=1 +m32 net-_m31-pad3_ net-_m32-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m44 net-_m43-pad3_ net-_m40-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m28 net-_m26-pad1_ net-_m26-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m26 net-_m26-pad1_ net-_m26-pad2_ net-_m26-pad3_ net-_m26-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m32-pad2_ net-_m40-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m48 net-_m32-pad2_ net-_m40-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m10-pad3_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m10-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m10-pad1_ net-_m1-pad1_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m13-pad2_ net-_m14-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m23 net-_m13-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m33-pad1_ net-_m30-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m33 net-_m33-pad1_ net-_m25-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m34 net-_m29-pad1_ net-_m25-pad1_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m38 net-_m29-pad1_ net-_m38-pad2_ net-_m33-pad1_ net-_m33-pad1_ CMOSP W=100u L=100u M=1 +m29 net-_m29-pad1_ net-_m25-pad2_ net-_m29-pad3_ net-_m29-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m29-pad1_ net-_m25-pad1_ net-_m41-pad3_ net-_m41-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m29-pad3_ net-_m30-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m42 net-_m41-pad3_ net-_m38-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m27 net-_m25-pad1_ net-_m25-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m25 net-_m25-pad1_ net-_m25-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m30-pad2_ net-_m38-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m47 net-_m30-pad2_ net-_m38-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4077 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4077/CD_4077_Previous_Values.xml b/library/SubcircuitLibrary/CD_4077/CD_4077_Previous_Values.xml new file mode 100644 index 00000000..fa4a68a2 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/CD_4077_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4077/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4077/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4077/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4077/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4077/README.md b/library/SubcircuitLibrary/CD_4077/README.md new file mode 100644 index 00000000..2d40325c --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/README.md @@ -0,0 +1,28 @@ + +# CD4077 IC + +It is 2-input XNOR Gate IC. CD4077 IC is designed with 180nm CMOS technology in eSim consisting four XNOR Gates. It plays the role of even 1’s detector. When both inputs are same, then output is HIGH, else LOW. It is also known as Special logic Gate. + +## Usage/Examples + +Logical Comparators + +Adders, Subtractors + +Parity Generators and Checkers + +Touch sensor circuit +## Documentation + +To know the details of CD4077 IC please go through with the documentation : [CD4077_datasheet](https://www.ti.com/lit/gpn/cd4077b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4077/analysis b/library/SubcircuitLibrary/CD_4077/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4077/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 17da1ca53183d152c61ec720a975b87ddbdb4d06 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 22:59:43 +0530 Subject: CD4081 is AND gate IC. --- .../SubcircuitLibrary/CD_4081/CD_4081-cache.lib | 100 +++ library/SubcircuitLibrary/CD_4081/CD_4081.cir | 35 + library/SubcircuitLibrary/CD_4081/CD_4081.cir.out | 38 ++ library/SubcircuitLibrary/CD_4081/CD_4081.pro | 71 ++ library/SubcircuitLibrary/CD_4081/CD_4081.sch | 745 +++++++++++++++++++++ library/SubcircuitLibrary/CD_4081/CD_4081.sub | 32 + .../CD_4081/CD_4081_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD_4081/README.md | 34 + library/SubcircuitLibrary/CD_4081/analysis | 1 + 11 files changed, 1081 insertions(+) create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081.cir create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081.cir.out create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081.pro create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081.sch create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081.sub create mode 100644 library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD_4081/README.md create mode 100644 library/SubcircuitLibrary/CD_4081/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib b/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.cir b/library/SubcircuitLibrary/CD_4081/CD_4081.cir new file mode 100644 index 00000000..03101ff9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD_4081\CD_4081.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/30/22 21:25:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M8 Net-_M10-Pad2_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M12 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M5 Net-_M10-Pad2_ Net-_M2-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad3_ Net-_M6-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M23 Net-_M23-Pad1_ Net-_M14-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M20 Net-_M14-Pad1_ Net-_M18-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M14 Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M24 Net-_M23-Pad1_ Net-_M14-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M17 Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M17-Pad3_ Net-_M17-Pad3_ eSim_MOS_N +M18 Net-_M17-Pad3_ Net-_M18-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M9 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M7 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M11 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M21 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M19 Net-_M13-Pad1_ Net-_M16-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M22 Net-_M21-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M15 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N +M16 Net-_M15-Pad3_ Net-_M16-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +U1 Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M10-Pad1_ Net-_M23-Pad1_ Net-_M14-Pad2_ Net-_M18-Pad2_ Net-_M10-Pad3_ Net-_M13-Pad2_ Net-_M16-Pad2_ Net-_M21-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out b/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out new file mode 100644 index 00000000..b4c78312 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081.cir.out @@ -0,0 +1,38 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd_4081\cd_4081.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m10-pad2_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m6-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m23-pad1_ net-_m14-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m23-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m17 net-_m14-pad1_ net-_m14-pad2_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m18-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m16-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m23-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m10-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.pro b/library/SubcircuitLibrary/CD_4081/CD_4081.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.sch b/library/SubcircuitLibrary/CD_4081/CD_4081.sch new file mode 100644 index 00000000..7a89dcc8 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081.sch @@ -0,0 +1,745 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4081-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_N M10 +U 1 1 6294E1FE +P 4000 4900 +F 0 "M10" H 4000 4750 50 0000 R CNN +F 1 "eSim_MOS_N" H 4100 4850 50 0000 R CNN +F 2 "" H 4300 4600 29 0000 C CNN +F 3 "" H 4100 4700 60 0000 C CNN + 1 4000 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 6294E1FF +P 3450 4450 +F 0 "M8" H 3400 4500 50 0000 R CNN +F 1 "eSim_MOS_P" H 3500 4600 50 0000 R CNN +F 2 "" H 3700 4550 29 0000 C CNN +F 3 "" H 3500 4450 60 0000 C CNN + 1 3450 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 6294E200 +P 2700 4450 +F 0 "M2" H 2650 4500 50 0000 R CNN +F 1 "eSim_MOS_P" H 2750 4600 50 0000 R CNN +F 2 "" H 2950 4550 29 0000 C CNN +F 3 "" H 2750 4450 60 0000 C CNN + 1 2700 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 6294E201 +P 4050 4550 +F 0 "M12" H 4000 4600 50 0000 R CNN +F 1 "eSim_MOS_P" H 4100 4700 50 0000 R CNN +F 2 "" H 4300 4650 29 0000 C CNN +F 3 "" H 4100 4550 60 0000 C CNN + 1 4050 4550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M5 +U 1 1 6294E202 +P 2850 4900 +F 0 "M5" H 2850 4750 50 0000 R CNN +F 1 "eSim_MOS_N" H 2950 4850 50 0000 R CNN +F 2 "" H 3150 4600 29 0000 C CNN +F 3 "" H 2950 4700 60 0000 C CNN + 1 2850 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 6294E203 +P 2850 5400 +F 0 "M6" H 2850 5250 50 0000 R CNN +F 1 "eSim_MOS_N" H 2950 5350 50 0000 R CNN +F 2 "" H 3150 5100 29 0000 C CNN +F 3 "" H 2950 5200 60 0000 C CNN + 1 2850 5400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M23 +U 1 1 6294E204 +P 7100 4900 +F 0 "M23" H 7100 4750 50 0000 R CNN +F 1 "eSim_MOS_N" H 7200 4850 50 0000 R CNN +F 2 "" H 7400 4600 29 0000 C CNN +F 3 "" H 7200 4700 60 0000 C CNN + 1 7100 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M20 +U 1 1 6294E205 +P 6550 4450 +F 0 "M20" H 6500 4500 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 4600 50 0000 R CNN +F 2 "" H 6800 4550 29 0000 C CNN +F 3 "" H 6600 4450 60 0000 C CNN + 1 6550 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 6294E206 +P 5800 4450 +F 0 "M14" H 5750 4500 50 0000 R CNN +F 1 "eSim_MOS_P" H 5850 4600 50 0000 R CNN +F 2 "" H 6050 4550 29 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 1 5800 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M24 +U 1 1 6294E207 +P 7150 4550 +F 0 "M24" H 7100 4600 50 0000 R CNN +F 1 "eSim_MOS_P" H 7200 4700 50 0000 R CNN +F 2 "" H 7400 4650 29 0000 C CNN +F 3 "" H 7200 4550 60 0000 C CNN + 1 7150 4550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M17 +U 1 1 6294E208 +P 5950 4900 +F 0 "M17" H 5950 4750 50 0000 R CNN +F 1 "eSim_MOS_N" H 6050 4850 50 0000 R CNN +F 2 "" H 6250 4600 29 0000 C CNN +F 3 "" H 6050 4700 60 0000 C CNN + 1 5950 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M18 +U 1 1 6294E209 +P 5950 5400 +F 0 "M18" H 5950 5250 50 0000 R CNN +F 1 "eSim_MOS_N" H 6050 5350 50 0000 R CNN +F 2 "" H 6250 5100 29 0000 C CNN +F 3 "" H 6050 5200 60 0000 C CNN + 1 5950 5400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 6294E20A +P 4000 2800 +F 0 "M9" H 4000 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 4100 2750 50 0000 R CNN +F 2 "" H 4300 2500 29 0000 C CNN +F 3 "" H 4100 2600 60 0000 C CNN + 1 4000 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 6294E20B +P 3450 2350 +F 0 "M7" H 3400 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 3500 2500 50 0000 R CNN +F 2 "" H 3700 2450 29 0000 C CNN +F 3 "" H 3500 2350 60 0000 C CNN + 1 3450 2350 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M1 +U 1 1 6294E20C +P 2700 2350 +F 0 "M1" H 2650 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 2750 2500 50 0000 R CNN +F 2 "" H 2950 2450 29 0000 C CNN +F 3 "" H 2750 2350 60 0000 C CNN + 1 2700 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 6294E20D +P 4050 2450 +F 0 "M11" H 4000 2500 50 0000 R CNN +F 1 "eSim_MOS_P" H 4100 2600 50 0000 R CNN +F 2 "" H 4300 2550 29 0000 C CNN +F 3 "" H 4100 2450 60 0000 C CNN + 1 4050 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 6294E20E +P 2850 2800 +F 0 "M3" H 2850 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 2950 2750 50 0000 R CNN +F 2 "" H 3150 2500 29 0000 C CNN +F 3 "" H 2950 2600 60 0000 C CNN + 1 2850 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 6294E20F +P 2850 3300 +F 0 "M4" H 2850 3150 50 0000 R CNN +F 1 "eSim_MOS_N" H 2950 3250 50 0000 R CNN +F 2 "" H 3150 3000 29 0000 C CNN +F 3 "" H 2950 3100 60 0000 C CNN + 1 2850 3300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 6294E210 +P 7050 2800 +F 0 "M21" H 7050 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 7150 2750 50 0000 R CNN +F 2 "" H 7350 2500 29 0000 C CNN +F 3 "" H 7150 2600 60 0000 C CNN + 1 7050 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M19 +U 1 1 6294E211 +P 6500 2350 +F 0 "M19" H 6450 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 6550 2500 50 0000 R CNN +F 2 "" H 6750 2450 29 0000 C CNN +F 3 "" H 6550 2350 60 0000 C CNN + 1 6500 2350 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 6294E212 +P 5750 2350 +F 0 "M13" H 5700 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 5800 2500 50 0000 R CNN +F 2 "" H 6000 2450 29 0000 C CNN +F 3 "" H 5800 2350 60 0000 C CNN + 1 5750 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M22 +U 1 1 6294E213 +P 7100 2450 +F 0 "M22" H 7050 2500 50 0000 R CNN +F 1 "eSim_MOS_P" H 7150 2600 50 0000 R CNN +F 2 "" H 7350 2550 29 0000 C CNN +F 3 "" H 7150 2450 60 0000 C CNN + 1 7100 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M15 +U 1 1 6294E214 +P 5900 2800 +F 0 "M15" H 5900 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 6000 2750 50 0000 R CNN +F 2 "" H 6200 2500 29 0000 C CNN +F 3 "" H 6000 2600 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M16 +U 1 1 6294E215 +P 5900 3300 +F 0 "M16" H 5900 3150 50 0000 R CNN +F 1 "eSim_MOS_N" H 6000 3250 50 0000 R CNN +F 2 "" H 6200 3000 29 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 5900 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 4250 7350 4250 +Wire Wire Line + 2850 4650 3300 4650 +Wire Wire Line + 3050 4650 3050 4900 +Connection ~ 3050 4650 +Wire Wire Line + 3050 5300 3050 5400 +Wire Wire Line + 3150 5750 3150 5800 +Wire Wire Line + 3050 5800 7350 5800 +Wire Wire Line + 3150 5250 3150 5300 +Wire Wire Line + 3150 5300 3050 5300 +Wire Wire Line + 3200 4300 3200 4250 +Connection ~ 3200 4250 +Wire Wire Line + 2950 4300 2950 4250 +Connection ~ 2950 4250 +Wire Wire Line + 4200 4350 4300 4350 +Wire Wire Line + 4300 4350 4300 4400 +Wire Wire Line + 4200 5300 4300 5300 +Wire Wire Line + 4300 5300 4300 5250 +Wire Wire Line + 4200 4750 4200 4900 +Wire Wire Line + 3900 4550 3900 5100 +Wire Wire Line + 3050 4800 3900 4800 +Connection ~ 3050 4800 +Connection ~ 3900 4800 +Wire Wire Line + 2550 4450 2550 5100 +Wire Wire Line + 2550 5100 2750 5100 +Wire Wire Line + 3600 4450 3600 5400 +Wire Wire Line + 3600 5400 2750 5400 +Wire Wire Line + 2750 5400 2750 5600 +Wire Wire Line + 2550 4750 2200 4750 +Connection ~ 2550 4750 +Wire Wire Line + 2750 5500 2200 5500 +Connection ~ 2750 5500 +Wire Wire Line + 4200 4800 4500 4800 +Connection ~ 4200 4800 +Wire Wire Line + 5950 4650 6400 4650 +Wire Wire Line + 6150 4650 6150 4900 +Connection ~ 6150 4650 +Wire Wire Line + 6150 5300 6150 5400 +Wire Wire Line + 6250 5800 6250 5750 +Wire Wire Line + 6250 5250 6250 5300 +Wire Wire Line + 6250 5300 6150 5300 +Wire Wire Line + 6300 4300 6300 4250 +Connection ~ 6300 4250 +Wire Wire Line + 6050 4300 6050 4250 +Connection ~ 6050 4250 +Wire Wire Line + 7300 4350 7400 4350 +Wire Wire Line + 7400 4350 7400 4400 +Wire Wire Line + 7300 5300 7400 5300 +Wire Wire Line + 7400 5300 7400 5250 +Wire Wire Line + 7300 4750 7300 4900 +Wire Wire Line + 7000 4550 7000 5100 +Wire Wire Line + 6150 4800 7000 4800 +Connection ~ 6150 4800 +Connection ~ 7000 4800 +Wire Wire Line + 5650 4450 5650 5100 +Wire Wire Line + 5650 5100 5850 5100 +Wire Wire Line + 6700 4450 6700 5400 +Wire Wire Line + 6700 5400 5850 5400 +Wire Wire Line + 5850 5400 5850 5600 +Wire Wire Line + 5650 4750 5300 4750 +Connection ~ 5650 4750 +Wire Wire Line + 5850 5500 5300 5500 +Connection ~ 5850 5500 +Wire Wire Line + 7300 4800 7600 4800 +Connection ~ 7300 4800 +Wire Wire Line + 2850 2150 7300 2150 +Wire Wire Line + 2850 2550 3300 2550 +Wire Wire Line + 3050 2550 3050 2800 +Connection ~ 3050 2550 +Wire Wire Line + 3050 3200 3050 3300 +Wire Wire Line + 3150 3650 3150 3700 +Wire Wire Line + 3050 3700 7300 3700 +Wire Wire Line + 3150 3150 3150 3200 +Wire Wire Line + 3150 3200 3050 3200 +Wire Wire Line + 3200 2200 3200 2150 +Connection ~ 3200 2150 +Wire Wire Line + 2950 2200 2950 2150 +Connection ~ 2950 2150 +Wire Wire Line + 4200 2250 4300 2250 +Wire Wire Line + 4300 2250 4300 2300 +Wire Wire Line + 4200 3200 4300 3200 +Wire Wire Line + 4300 3200 4300 3150 +Wire Wire Line + 4200 2650 4200 2800 +Wire Wire Line + 3900 2450 3900 3000 +Wire Wire Line + 3050 2700 3900 2700 +Connection ~ 3050 2700 +Connection ~ 3900 2700 +Wire Wire Line + 2550 2350 2550 3000 +Wire Wire Line + 2550 3000 2750 3000 +Wire Wire Line + 3600 2350 3600 3300 +Wire Wire Line + 3600 3300 2750 3300 +Wire Wire Line + 2750 3300 2750 3500 +Wire Wire Line + 2550 2650 2200 2650 +Connection ~ 2550 2650 +Wire Wire Line + 2750 3400 2200 3400 +Connection ~ 2750 3400 +Wire Wire Line + 4200 2700 4500 2700 +Connection ~ 4200 2700 +Wire Wire Line + 5900 2550 6350 2550 +Wire Wire Line + 6100 2550 6100 2800 +Connection ~ 6100 2550 +Wire Wire Line + 6100 3200 6100 3300 +Wire Wire Line + 6200 3700 6200 3650 +Wire Wire Line + 6200 3150 6200 3200 +Wire Wire Line + 6200 3200 6100 3200 +Wire Wire Line + 6250 2200 6250 2150 +Connection ~ 6250 2150 +Wire Wire Line + 6000 2200 6000 2150 +Connection ~ 6000 2150 +Wire Wire Line + 7250 2250 7350 2250 +Wire Wire Line + 7350 2250 7350 2300 +Wire Wire Line + 7250 3200 7350 3200 +Wire Wire Line + 7350 3200 7350 3150 +Wire Wire Line + 7250 2650 7250 2800 +Wire Wire Line + 6950 2450 6950 3000 +Wire Wire Line + 6100 2700 6950 2700 +Connection ~ 6100 2700 +Connection ~ 6950 2700 +Wire Wire Line + 5600 2350 5600 3000 +Wire Wire Line + 5600 3000 5800 3000 +Wire Wire Line + 6650 2350 6650 3300 +Wire Wire Line + 6650 3300 5800 3300 +Wire Wire Line + 5800 3300 5800 3500 +Wire Wire Line + 5600 2650 5250 2650 +Connection ~ 5600 2650 +Wire Wire Line + 5800 3400 5250 3400 +Connection ~ 5800 3400 +Wire Wire Line + 7250 2700 7550 2700 +Connection ~ 7250 2700 +Connection ~ 5950 4250 +Connection ~ 3300 4250 +Connection ~ 5900 2150 +Connection ~ 3300 2150 +Connection ~ 6100 3700 +Connection ~ 3150 3700 +Connection ~ 6150 5800 +Connection ~ 3150 5800 +Wire Wire Line + 4950 3700 4950 6050 +Connection ~ 4950 5800 +Connection ~ 4950 3700 +Wire Wire Line + 4800 1850 4800 4250 +Connection ~ 4800 4250 +Connection ~ 4800 2150 +Wire Wire Line + 7300 2150 7300 2250 +Connection ~ 6350 2150 +Connection ~ 7300 2250 +Wire Wire Line + 7300 3700 7300 3200 +Connection ~ 6200 3700 +Connection ~ 7300 3200 +Wire Wire Line + 4250 3200 4250 3700 +Connection ~ 4250 3700 +Connection ~ 4250 3200 +Wire Wire Line + 4250 2250 4250 2150 +Connection ~ 4250 2150 +Connection ~ 4250 2250 +Wire Wire Line + 4250 4350 4250 4250 +Connection ~ 4250 4250 +Connection ~ 4250 4350 +Wire Wire Line + 4250 5300 4250 5800 +Connection ~ 4250 5800 +Connection ~ 4250 5300 +Wire Wire Line + 7350 4250 7350 4350 +Connection ~ 6400 4250 +Connection ~ 7350 4350 +Wire Wire Line + 7350 5800 7350 5300 +Connection ~ 6250 5800 +Connection ~ 7350 5300 +$Comp +L PORT U1 +U 1 1 629516D8 +P 1950 4750 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 1950 4750 30 0000 C CNN +F 2 "" H 1950 4750 60 0000 C CNN +F 3 "" H 1950 4750 60 0000 C CNN + 1 1950 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62951745 +P 1950 5500 +F 0 "U1" H 2000 5600 30 0000 C CNN +F 1 "PORT" H 1950 5500 30 0000 C CNN +F 2 "" H 1950 5500 60 0000 C CNN +F 3 "" H 1950 5500 60 0000 C CNN + 2 1950 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 629517B4 +P 4750 4800 +F 0 "U1" H 4800 4900 30 0000 C CNN +F 1 "PORT" H 4750 4800 30 0000 C CNN +F 2 "" H 4750 4800 60 0000 C CNN +F 3 "" H 4750 4800 60 0000 C CNN + 3 4750 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62951900 +P 7850 4800 +F 0 "U1" H 7900 4900 30 0000 C CNN +F 1 "PORT" H 7850 4800 30 0000 C CNN +F 2 "" H 7850 4800 60 0000 C CNN +F 3 "" H 7850 4800 60 0000 C CNN + 4 7850 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62951991 +P 5050 4750 +F 0 "U1" H 5100 4850 30 0000 C CNN +F 1 "PORT" H 5050 4750 30 0000 C CNN +F 2 "" H 5050 4750 60 0000 C CNN +F 3 "" H 5050 4750 60 0000 C CNN + 5 5050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 629519FC +P 5050 5500 +F 0 "U1" H 5100 5600 30 0000 C CNN +F 1 "PORT" H 5050 5500 30 0000 C CNN +F 2 "" H 5050 5500 60 0000 C CNN +F 3 "" H 5050 5500 60 0000 C CNN + 6 5050 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6295226B +P 4700 6050 +F 0 "U1" H 4750 6150 30 0000 C CNN +F 1 "PORT" H 4700 6050 30 0000 C CNN +F 2 "" H 4700 6050 60 0000 C CNN +F 3 "" H 4700 6050 60 0000 C CNN + 7 4700 6050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62952B28 +P 5000 2650 +F 0 "U1" H 5050 2750 30 0000 C CNN +F 1 "PORT" H 5000 2650 30 0000 C CNN +F 2 "" H 5000 2650 60 0000 C CNN +F 3 "" H 5000 2650 60 0000 C CNN + 8 5000 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62952BC3 +P 5000 3400 +F 0 "U1" H 5050 3500 30 0000 C CNN +F 1 "PORT" H 5000 3400 30 0000 C CNN +F 2 "" H 5000 3400 60 0000 C CNN +F 3 "" H 5000 3400 60 0000 C CNN + 9 5000 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62952C34 +P 7800 2700 +F 0 "U1" H 7850 2800 30 0000 C CNN +F 1 "PORT" H 7800 2700 30 0000 C CNN +F 2 "" H 7800 2700 60 0000 C CNN +F 3 "" H 7800 2700 60 0000 C CNN + 10 7800 2700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 62952CD1 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 11 4750 2700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 62952D8E +P 1950 2650 +F 0 "U1" H 2000 2750 30 0000 C CNN +F 1 "PORT" H 1950 2650 30 0000 C CNN +F 2 "" H 1950 2650 60 0000 C CNN +F 3 "" H 1950 2650 60 0000 C CNN + 12 1950 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62952E35 +P 1950 3400 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 1950 3400 30 0000 C CNN +F 2 "" H 1950 3400 60 0000 C CNN +F 3 "" H 1950 3400 60 0000 C CNN + 13 1950 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62953458 +P 4550 1850 +F 0 "U1" H 4600 1950 30 0000 C CNN +F 1 "PORT" H 4550 1850 30 0000 C CNN +F 2 "" H 4550 1850 60 0000 C CNN +F 3 "" H 4550 1850 60 0000 C CNN + 14 4550 1850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081.sub b/library/SubcircuitLibrary/CD_4081/CD_4081.sub new file mode 100644 index 00000000..f5050506 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081.sub @@ -0,0 +1,32 @@ +* Subcircuit CD_4081 +.subckt CD_4081 net-_m2-pad2_ net-_m6-pad2_ net-_m10-pad1_ net-_m23-pad1_ net-_m14-pad2_ net-_m18-pad2_ net-_m10-pad3_ net-_m13-pad2_ net-_m16-pad2_ net-_m21-pad1_ net-_m11-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd_4081\cd_4081.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m8 net-_m10-pad2_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m10-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m10-pad2_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ net-_m6-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m23 net-_m23-pad1_ net-_m14-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 net-_m14-pad1_ net-_m18-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m24 net-_m23-pad1_ net-_m14-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m17 net-_m14-pad1_ net-_m14-pad2_ net-_m17-pad3_ net-_m17-pad3_ CMOSN W=100u L=100u M=1 +m18 net-_m17-pad3_ net-_m18-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m1-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m4-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m21-pad1_ net-_m13-pad1_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m19 net-_m13-pad1_ net-_m16-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m22 net-_m21-pad1_ net-_m13-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m15 net-_m13-pad1_ net-_m13-pad2_ net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m16-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD_4081 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml b/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml new file mode 100644 index 00000000..5166d2ba --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/CD_4081_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib b/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib b/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD_4081/README.md b/library/SubcircuitLibrary/CD_4081/README.md new file mode 100644 index 00000000..5e6b11c7 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/README.md @@ -0,0 +1,34 @@ + +# CD4081 IC + +It is 2-input AND Gate IC. CD4081 IC is designed with 180nm CMOS technology in eSim consisting four AND Gates. When both the inputs are HIGH then only output is HIGH, otherwise LOW. + + +## Usage/Examples + +Logic buffers, inverters, and decoders + +Implementing logic circuits + +Signal conditioning + +Enable gate + +Inhibit gate + +Measurement of frequency + +## Documentation + +To know the details of CD4081 IC please go through with the documentation : [CD4081_datasheet](https://www.ti.com/lit/gpn/cd4081b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD_4081/analysis b/library/SubcircuitLibrary/CD_4081/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD_4081/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 5df674106b28e222330d6b1b0207e9903aec2bfe Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:01:56 +0530 Subject: CD4001 is NOR gate IC. --- library/SubcircuitLibrary/CD4001/CD4001-cache.lib | 100 ++++ library/SubcircuitLibrary/CD4001/CD4001.cir | 27 + library/SubcircuitLibrary/CD4001/CD4001.cir.out | 30 + library/SubcircuitLibrary/CD4001/CD4001.pro | 71 +++ library/SubcircuitLibrary/CD4001/CD4001.sch | 616 +++++++++++++++++++++ library/SubcircuitLibrary/CD4001/CD4001.sub | 24 + .../CD4001/CD4001_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD4001/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD4001/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD4001/README.md | 26 + library/SubcircuitLibrary/CD4001/analysis | 1 + 11 files changed, 920 insertions(+) create mode 100644 library/SubcircuitLibrary/CD4001/CD4001-cache.lib create mode 100644 library/SubcircuitLibrary/CD4001/CD4001.cir create mode 100644 library/SubcircuitLibrary/CD4001/CD4001.cir.out create mode 100644 library/SubcircuitLibrary/CD4001/CD4001.pro create mode 100644 library/SubcircuitLibrary/CD4001/CD4001.sch create mode 100644 library/SubcircuitLibrary/CD4001/CD4001.sub create mode 100644 library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4001/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4001/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4001/README.md create mode 100644 library/SubcircuitLibrary/CD4001/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD4001/CD4001-cache.lib b/library/SubcircuitLibrary/CD4001/CD4001-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4001/CD4001.cir b/library/SubcircuitLibrary/CD4001/CD4001.cir new file mode 100644 index 00000000..17bf85e4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001.cir @@ -0,0 +1,27 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4001\CD4001.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/22 15:17:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M5 Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M5-Pad1_ Net-_M5-Pad1_ eSim_MOS_P +M8 Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M13 Net-_M13-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M14 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M16 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P +M7 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M12-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P +M15 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M2-Pad1_ Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M11-Pad2_ Net-_M12-Pad2_ Net-_M12-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4001/CD4001.cir.out b/library/SubcircuitLibrary/CD4001/CD4001.cir.out new file mode 100644 index 00000000..169eff19 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001.cir.out @@ -0,0 +1,30 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4001\cd4001.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m12-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m15 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m2-pad2_ net-_m6-pad2_ net-_m2-pad1_ net-_m10-pad1_ net-_m10-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad1_ net-_m1-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4001/CD4001.pro b/library/SubcircuitLibrary/CD4001/CD4001.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4001/CD4001.sch b/library/SubcircuitLibrary/CD4001/CD4001.sch new file mode 100644 index 00000000..9fc9cff3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001.sch @@ -0,0 +1,616 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD4001-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M5 +U 1 1 628DC1F6 +P 4950 3750 +F 0 "M5" H 4900 3800 50 0000 R CNN +F 1 "eSim_MOS_P" H 5000 3900 50 0000 R CNN +F 2 "" H 5200 3850 29 0000 C CNN +F 3 "" H 5000 3750 60 0000 C CNN + 1 4950 3750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 628DC1F7 +P 4550 4750 +F 0 "M2" H 4550 4600 50 0000 R CNN +F 1 "eSim_MOS_N" H 4650 4700 50 0000 R CNN +F 2 "" H 4850 4450 29 0000 C CNN +F 3 "" H 4650 4550 60 0000 C CNN + 1 4550 4750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 628DC1F8 +P 4950 4250 +F 0 "M6" H 4900 4300 50 0000 R CNN +F 1 "eSim_MOS_P" H 5000 4400 50 0000 R CNN +F 2 "" H 5200 4350 29 0000 C CNN +F 3 "" H 5000 4250 60 0000 C CNN + 1 4950 4250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 628DC1F9 +P 5550 4750 +F 0 "M8" H 5550 4600 50 0000 R CNN +F 1 "eSim_MOS_N" H 5650 4700 50 0000 R CNN +F 2 "" H 5850 4450 29 0000 C CNN +F 3 "" H 5650 4550 60 0000 C CNN + 1 5550 4750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 628DC1FA +P 7200 3750 +F 0 "M13" H 7150 3800 50 0000 R CNN +F 1 "eSim_MOS_P" H 7250 3900 50 0000 R CNN +F 2 "" H 7450 3850 29 0000 C CNN +F 3 "" H 7250 3750 60 0000 C CNN + 1 7200 3750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 628DC1FB +P 6800 4750 +F 0 "M10" H 6800 4600 50 0000 R CNN +F 1 "eSim_MOS_N" H 6900 4700 50 0000 R CNN +F 2 "" H 7100 4450 29 0000 C CNN +F 3 "" H 6900 4550 60 0000 C CNN + 1 6800 4750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 628DC1FC +P 7200 4250 +F 0 "M14" H 7150 4300 50 0000 R CNN +F 1 "eSim_MOS_P" H 7250 4400 50 0000 R CNN +F 2 "" H 7450 4350 29 0000 C CNN +F 3 "" H 7250 4250 60 0000 C CNN + 1 7200 4250 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M16 +U 1 1 628DC1FD +P 7800 4750 +F 0 "M16" H 7800 4600 50 0000 R CNN +F 1 "eSim_MOS_N" H 7900 4700 50 0000 R CNN +F 2 "" H 8100 4450 29 0000 C CNN +F 3 "" H 7900 4550 60 0000 C CNN + 1 7800 4750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 628DC1FE +P 4900 1850 +F 0 "M3" H 4850 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 4950 2000 50 0000 R CNN +F 2 "" H 5150 1950 29 0000 C CNN +F 3 "" H 4950 1850 60 0000 C CNN + 1 4900 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 628DC1FF +P 4500 2850 +F 0 "M1" H 4500 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 4600 2800 50 0000 R CNN +F 2 "" H 4800 2550 29 0000 C CNN +F 3 "" H 4600 2650 60 0000 C CNN + 1 4500 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 628DC200 +P 4900 2350 +F 0 "M4" H 4850 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 4950 2500 50 0000 R CNN +F 2 "" H 5150 2450 29 0000 C CNN +F 3 "" H 4950 2350 60 0000 C CNN + 1 4900 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M7 +U 1 1 628DC201 +P 5500 2850 +F 0 "M7" H 5500 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 5600 2800 50 0000 R CNN +F 2 "" H 5800 2550 29 0000 C CNN +F 3 "" H 5600 2650 60 0000 C CNN + 1 5500 2850 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 628DC202 +P 7200 1850 +F 0 "M11" H 7150 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 7250 2000 50 0000 R CNN +F 2 "" H 7450 1950 29 0000 C CNN +F 3 "" H 7250 1850 60 0000 C CNN + 1 7200 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 628DC203 +P 6800 2850 +F 0 "M9" H 6800 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 6900 2800 50 0000 R CNN +F 2 "" H 7100 2550 29 0000 C CNN +F 3 "" H 6900 2650 60 0000 C CNN + 1 6800 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 628DC204 +P 7200 2350 +F 0 "M12" H 7150 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 7250 2500 50 0000 R CNN +F 2 "" H 7450 2450 29 0000 C CNN +F 3 "" H 7250 2350 60 0000 C CNN + 1 7200 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M15 +U 1 1 628DC205 +P 7800 2850 +F 0 "M15" H 7800 2700 50 0000 R CNN +F 1 "eSim_MOS_N" H 7900 2800 50 0000 R CNN +F 2 "" H 8100 2550 29 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 1 7800 2850 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3950 5100 4050 +Wire Wire Line + 4750 4750 4750 4650 +Wire Wire Line + 4750 4650 5350 4650 +Wire Wire Line + 5350 4650 5350 4750 +Wire Wire Line + 4750 5150 4750 5200 +Wire Wire Line + 4750 5200 7600 5200 +Wire Wire Line + 5350 5200 5350 5150 +Wire Wire Line + 5250 5100 5250 5200 +Connection ~ 5250 5200 +Wire Wire Line + 4850 5100 4850 5200 +Connection ~ 4850 5200 +Wire Wire Line + 5100 4450 5100 4650 +Connection ~ 5100 4650 +Wire Wire Line + 5200 4100 5200 4000 +Wire Wire Line + 5200 4000 5100 4000 +Connection ~ 5100 4000 +Wire Wire Line + 5200 3600 5200 3550 +Wire Wire Line + 5100 3550 7450 3550 +Wire Wire Line + 4800 3750 4400 3750 +Wire Wire Line + 4400 3750 4400 4950 +Wire Wire Line + 4400 4950 4450 4950 +Wire Wire Line + 4800 4250 4700 4250 +Wire Wire Line + 4700 4250 4700 4800 +Wire Wire Line + 4700 4800 5650 4800 +Wire Wire Line + 5650 4800 5650 4950 +Wire Wire Line + 5100 4500 5600 4500 +Connection ~ 5100 4500 +Wire Wire Line + 4400 4250 4150 4250 +Connection ~ 4400 4250 +Wire Wire Line + 4700 4450 4150 4450 +Connection ~ 4700 4450 +Wire Wire Line + 7350 3950 7350 4050 +Wire Wire Line + 7000 4750 7000 4650 +Wire Wire Line + 7000 4650 7600 4650 +Wire Wire Line + 7600 4650 7600 4750 +Wire Wire Line + 7000 5200 7000 5150 +Wire Wire Line + 7600 5200 7600 5150 +Wire Wire Line + 7500 5100 7500 5200 +Connection ~ 7500 5200 +Wire Wire Line + 7100 5100 7100 5200 +Connection ~ 7100 5200 +Wire Wire Line + 7350 4450 7350 4650 +Connection ~ 7350 4650 +Wire Wire Line + 7450 4100 7450 4000 +Wire Wire Line + 7450 4000 7350 4000 +Connection ~ 7350 4000 +Wire Wire Line + 7450 3550 7450 3600 +Wire Wire Line + 7050 3750 6650 3750 +Wire Wire Line + 6650 3750 6650 4950 +Wire Wire Line + 6650 4950 6700 4950 +Wire Wire Line + 7050 4250 6950 4250 +Wire Wire Line + 6950 4250 6950 4800 +Wire Wire Line + 6950 4800 7900 4800 +Wire Wire Line + 7900 4800 7900 4950 +Wire Wire Line + 7350 4500 7850 4500 +Connection ~ 7350 4500 +Wire Wire Line + 6650 4250 6400 4250 +Connection ~ 6650 4250 +Wire Wire Line + 6950 4450 6400 4450 +Connection ~ 6950 4450 +Wire Wire Line + 5050 2050 5050 2150 +Wire Wire Line + 4700 2850 4700 2750 +Wire Wire Line + 4700 2750 5300 2750 +Wire Wire Line + 5300 2750 5300 2850 +Wire Wire Line + 4700 3250 4700 3300 +Wire Wire Line + 4700 3300 7600 3300 +Wire Wire Line + 5300 3300 5300 3250 +Wire Wire Line + 5200 3200 5200 3300 +Connection ~ 5200 3300 +Wire Wire Line + 4800 3200 4800 3300 +Connection ~ 4800 3300 +Wire Wire Line + 5050 2550 5050 2750 +Connection ~ 5050 2750 +Wire Wire Line + 5150 2200 5150 2100 +Wire Wire Line + 5150 2100 5050 2100 +Connection ~ 5050 2100 +Wire Wire Line + 5150 1700 5150 1650 +Wire Wire Line + 5050 1650 7450 1650 +Wire Wire Line + 4750 1850 4350 1850 +Wire Wire Line + 4350 1850 4350 3050 +Wire Wire Line + 4350 3050 4400 3050 +Wire Wire Line + 4750 2350 4650 2350 +Wire Wire Line + 4650 2350 4650 2900 +Wire Wire Line + 4650 2900 5600 2900 +Wire Wire Line + 5600 2900 5600 3050 +Wire Wire Line + 5050 2600 5550 2600 +Connection ~ 5050 2600 +Wire Wire Line + 4350 2350 4100 2350 +Connection ~ 4350 2350 +Wire Wire Line + 4650 2550 4100 2550 +Connection ~ 4650 2550 +Wire Wire Line + 7350 2050 7350 2150 +Wire Wire Line + 7000 2850 7000 2750 +Wire Wire Line + 7000 2750 7600 2750 +Wire Wire Line + 7600 2750 7600 2850 +Wire Wire Line + 7000 3300 7000 3250 +Wire Wire Line + 7600 3300 7600 3250 +Wire Wire Line + 7500 3200 7500 3300 +Connection ~ 7500 3300 +Wire Wire Line + 7100 3200 7100 3300 +Connection ~ 7100 3300 +Wire Wire Line + 7350 2550 7350 2750 +Connection ~ 7350 2750 +Wire Wire Line + 7450 2200 7450 2100 +Wire Wire Line + 7450 2100 7350 2100 +Connection ~ 7350 2100 +Wire Wire Line + 7450 1650 7450 1700 +Wire Wire Line + 7050 1850 6650 1850 +Wire Wire Line + 6650 1850 6650 3050 +Wire Wire Line + 6650 3050 6700 3050 +Wire Wire Line + 7050 2350 6950 2350 +Wire Wire Line + 6950 2350 6950 2900 +Wire Wire Line + 6950 2900 7900 2900 +Wire Wire Line + 7900 2900 7900 3050 +Wire Wire Line + 7350 2600 7850 2600 +Connection ~ 7350 2600 +Wire Wire Line + 6650 2350 6400 2350 +Connection ~ 6650 2350 +Wire Wire Line + 6950 2550 6400 2550 +Connection ~ 6950 2550 +Connection ~ 7350 3550 +Connection ~ 5200 3550 +Connection ~ 7350 1650 +Connection ~ 5150 1650 +Connection ~ 7000 3300 +Connection ~ 5300 3300 +Connection ~ 7000 5200 +Connection ~ 5350 5200 +Wire Wire Line + 5800 3300 5800 5200 +Connection ~ 5800 5200 +Connection ~ 5800 3300 +Connection ~ 6050 1650 +Wire Wire Line + 6300 5400 6300 5200 +Connection ~ 6300 5200 +$Comp +L PORT U1 +U 1 1 628E3C82 +P 3900 4250 +F 0 "U1" H 3950 4350 30 0000 C CNN +F 1 "PORT" H 3900 4250 30 0000 C CNN +F 2 "" H 3900 4250 60 0000 C CNN +F 3 "" H 3900 4250 60 0000 C CNN + 1 3900 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 628E3D0D +P 3900 4450 +F 0 "U1" H 3950 4550 30 0000 C CNN +F 1 "PORT" H 3900 4450 30 0000 C CNN +F 2 "" H 3900 4450 60 0000 C CNN +F 3 "" H 3900 4450 60 0000 C CNN + 2 3900 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 628E3D80 +P 5850 4500 +F 0 "U1" H 5900 4600 30 0000 C CNN +F 1 "PORT" H 5850 4500 30 0000 C CNN +F 2 "" H 5850 4500 60 0000 C CNN +F 3 "" H 5850 4500 60 0000 C CNN + 3 5850 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 628E3DE3 +P 8100 4500 +F 0 "U1" H 8150 4600 30 0000 C CNN +F 1 "PORT" H 8100 4500 30 0000 C CNN +F 2 "" H 8100 4500 60 0000 C CNN +F 3 "" H 8100 4500 60 0000 C CNN + 4 8100 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 628E3EA4 +P 6150 4250 +F 0 "U1" H 6200 4350 30 0000 C CNN +F 1 "PORT" H 6150 4250 30 0000 C CNN +F 2 "" H 6150 4250 60 0000 C CNN +F 3 "" H 6150 4250 60 0000 C CNN + 5 6150 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 628E3F07 +P 6150 4450 +F 0 "U1" H 6200 4550 30 0000 C CNN +F 1 "PORT" H 6150 4450 30 0000 C CNN +F 2 "" H 6150 4450 60 0000 C CNN +F 3 "" H 6150 4450 60 0000 C CNN + 6 6150 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 628E4017 +P 6050 5400 +F 0 "U1" H 6100 5500 30 0000 C CNN +F 1 "PORT" H 6050 5400 30 0000 C CNN +F 2 "" H 6050 5400 60 0000 C CNN +F 3 "" H 6050 5400 60 0000 C CNN + 7 6050 5400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 628E4565 +P 6150 2350 +F 0 "U1" H 6200 2450 30 0000 C CNN +F 1 "PORT" H 6150 2350 30 0000 C CNN +F 2 "" H 6150 2350 60 0000 C CNN +F 3 "" H 6150 2350 60 0000 C CNN + 8 6150 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 628E45D8 +P 6150 2550 +F 0 "U1" H 6200 2650 30 0000 C CNN +F 1 "PORT" H 6150 2550 30 0000 C CNN +F 2 "" H 6150 2550 60 0000 C CNN +F 3 "" H 6150 2550 60 0000 C CNN + 9 6150 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 628E463D +P 8100 2600 +F 0 "U1" H 8150 2700 30 0000 C CNN +F 1 "PORT" H 8100 2600 30 0000 C CNN +F 2 "" H 8100 2600 60 0000 C CNN +F 3 "" H 8100 2600 60 0000 C CNN + 10 8100 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 628E473E +P 5800 2600 +F 0 "U1" H 5850 2700 30 0000 C CNN +F 1 "PORT" H 5800 2600 30 0000 C CNN +F 2 "" H 5800 2600 60 0000 C CNN +F 3 "" H 5800 2600 60 0000 C CNN + 11 5800 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 628E47DD +P 3850 2350 +F 0 "U1" H 3900 2450 30 0000 C CNN +F 1 "PORT" H 3850 2350 30 0000 C CNN +F 2 "" H 3850 2350 60 0000 C CNN +F 3 "" H 3850 2350 60 0000 C CNN + 12 3850 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 628E484A +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 13 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 628E4934 +P 5800 1350 +F 0 "U1" H 5850 1450 30 0000 C CNN +F 1 "PORT" H 5800 1350 30 0000 C CNN +F 2 "" H 5800 1350 60 0000 C CNN +F 3 "" H 5800 1350 60 0000 C CNN + 14 5800 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 1350 6050 3550 +Connection ~ 6050 3550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4001/CD4001.sub b/library/SubcircuitLibrary/CD4001/CD4001.sub new file mode 100644 index 00000000..9371c24e --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001.sub @@ -0,0 +1,24 @@ +* Subcircuit CD4001 +.subckt CD4001 net-_m2-pad2_ net-_m6-pad2_ net-_m2-pad1_ net-_m10-pad1_ net-_m10-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad1_ net-_m1-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4001\cd4001.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1 +m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m10-pad1_ net-_m14-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1 +m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m12-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1 +m15 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD4001 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml b/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml new file mode 100644 index 00000000..f4515cf9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4001/README.md b/library/SubcircuitLibrary/CD4001/README.md new file mode 100644 index 00000000..db436fdf --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/README.md @@ -0,0 +1,26 @@ + +# CD4001 IC + +It is 2-input NOR Gate IC. CD4001 IC is designed with 180nm CMOS technology in eSim consisting four NOR Gates. When both the inputs are LOW then only output is HIGH, otherwise LOW. It is also called inverted OR Gate, a type of Universal Gate. + + +## Usage/Examples + +The IC can be used for Noise Removing. + +Also used in devices such as PCs and notebooks. + +## Documentation + +To know the details of CD4001 IC please go through with the documentation : [CD4001_datasheet](https://www.ti.com/lit/gpn/cd4001b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4001/analysis b/library/SubcircuitLibrary/CD4001/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4001/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From b4bbdccebce86b996ef66ac98e7e321e4df44152 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:03:43 +0530 Subject: CD4028 is Binary to Decimal converter IC. --- .../SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib | 100 +++ library/SubcircuitLibrary/CD4028_B/AND_Gate.cir | 17 + .../SubcircuitLibrary/CD4028_B/AND_Gate.cir.out | 20 + library/SubcircuitLibrary/CD4028_B/AND_Gate.pro | 71 ++ library/SubcircuitLibrary/CD4028_B/AND_Gate.sch | 250 ++++++ library/SubcircuitLibrary/CD4028_B/AND_Gate.sub | 14 + .../CD4028_B/AND_Gate_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib | 136 +++ library/SubcircuitLibrary/CD4028_B/CD4028_B.cir | 36 + .../SubcircuitLibrary/CD4028_B/CD4028_B.cir.out | 41 + library/SubcircuitLibrary/CD4028_B/CD4028_B.pro | 71 ++ library/SubcircuitLibrary/CD4028_B/CD4028_B.sch | 942 +++++++++++++++++++++ library/SubcircuitLibrary/CD4028_B/CD4028_B.sub | 35 + .../CD4028_B/CD4028_B_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib | 13 + .../SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib | 100 +++ library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir | 15 + .../SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out | 18 + library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro | 71 ++ library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch | 211 +++++ library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub | 12 + .../CD4028_B/NOR_Gate_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD4028_B/README.md | 27 + library/SubcircuitLibrary/CD4028_B/analysis | 1 + 25 files changed, 2215 insertions(+) create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate.cir create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate.pro create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate.sch create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate.sub create mode 100644 library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B.cir create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B.pro create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B.sch create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B.sub create mode 100644 library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub create mode 100644 library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4028_B/README.md create mode 100644 library/SubcircuitLibrary/CD4028_B/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib b/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir new file mode 100644 index 00000000..17b9331f --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate\AND_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 14:03:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +U1 Net-_M5-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out new file mode 100644 index 00000000..bea80ad4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\and_gate\and_gate.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +* u1 net-_m5-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m3-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro b/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch new file mode 100644 index 00000000..5f7950b3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch @@ -0,0 +1,250 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:AND_Gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M1 +U 1 1 62B6B95F +P 4550 1800 +F 0 "M1" H 4500 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 4600 1950 50 0000 R CNN +F 2 "" H 4800 1900 29 0000 C CNN +F 3 "" H 4600 1800 60 0000 C CNN + 1 4550 1800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62B6B9AC +P 4700 2250 +F 0 "M2" H 4700 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4800 2200 50 0000 R CNN +F 2 "" H 5000 1950 29 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4700 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 62B6B9ED +P 5250 1800 +F 0 "M4" H 5200 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 1950 50 0000 R CNN +F 2 "" H 5500 1900 29 0000 C CNN +F 3 "" H 5300 1800 60 0000 C CNN + 1 5250 1800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 62B6BA57 +P 4700 2750 +F 0 "M3" H 4700 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 4800 2700 50 0000 R CNN +F 2 "" H 5000 2450 29 0000 C CNN +F 3 "" H 4800 2550 60 0000 C CNN + 1 4700 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1600 6000 1600 +Wire Wire Line + 5000 1650 5000 1600 +Connection ~ 5000 1600 +Wire Wire Line + 4800 1650 4800 1600 +Connection ~ 4800 1600 +Wire Wire Line + 4700 2000 5100 2000 +Wire Wire Line + 4900 2250 4900 2000 +Connection ~ 4900 2000 +Wire Wire Line + 4900 2650 4900 2750 +Wire Wire Line + 5000 2600 5000 2700 +Wire Wire Line + 5000 2700 4900 2700 +Connection ~ 4900 2700 +Wire Wire Line + 5000 3400 5000 3100 +Wire Wire Line + 4900 3150 6000 3150 +Wire Wire Line + 4900 2150 5650 2150 +Connection ~ 4900 2150 +$Comp +L eSim_MOS_N M5 +U 1 1 62B6BB39 +P 5750 2250 +F 0 "M5" H 5750 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 2200 50 0000 R CNN +F 2 "" H 6050 1950 29 0000 C CNN +F 3 "" H 5850 2050 60 0000 C CNN + 1 5750 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62B6BB82 +P 5800 1900 +F 0 "M6" H 5750 1950 50 0000 R CNN +F 1 "eSim_MOS_P" H 5850 2050 50 0000 R CNN +F 2 "" H 6050 2000 29 0000 C CNN +F 3 "" H 5850 1900 60 0000 C CNN + 1 5800 1900 + 1 0 0 1 +$EndComp +Wire Wire Line + 5950 1700 6050 1700 +Wire Wire Line + 6050 1700 6050 1750 +Wire Wire Line + 6050 2600 6050 2650 +Wire Wire Line + 6050 2650 5950 2650 +Wire Wire Line + 5950 2100 5950 2250 +Wire Wire Line + 5650 1900 5650 2450 +Connection ~ 5650 2150 +Wire Wire Line + 5950 2150 6300 2150 +Connection ~ 5950 2150 +Wire Wire Line + 6000 1600 6000 1700 +Connection ~ 5100 1600 +Connection ~ 6000 1700 +Wire Wire Line + 6000 3150 6000 2650 +Connection ~ 5000 3150 +Connection ~ 6000 2650 +Wire Wire Line + 4400 1800 4400 2450 +Wire Wire Line + 4400 2450 4600 2450 +Wire Wire Line + 5400 1800 5400 2800 +Wire Wire Line + 5400 2800 4600 2800 +Wire Wire Line + 4600 2800 4600 2950 +Wire Wire Line + 4400 2100 3950 2100 +Connection ~ 4400 2100 +Wire Wire Line + 4600 2850 3950 2850 +Connection ~ 4600 2850 +$Comp +L PORT U1 +U 3 1 62B6BDF0 +P 3700 2850 +F 0 "U1" H 3750 2950 30 0000 C CNN +F 1 "PORT" H 3700 2850 30 0000 C CNN +F 2 "" H 3700 2850 60 0000 C CNN +F 3 "" H 3700 2850 60 0000 C CNN + 3 3700 2850 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B6BE6B +P 6550 2150 +F 0 "U1" H 6600 2250 30 0000 C CNN +F 1 "PORT" H 6550 2150 30 0000 C CNN +F 2 "" H 6550 2150 60 0000 C CNN +F 3 "" H 6550 2150 60 0000 C CNN + 1 6550 2150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62B6BEC8 +P 3700 2100 +F 0 "U1" H 3750 2200 30 0000 C CNN +F 1 "PORT" H 3700 2100 30 0000 C CNN +F 2 "" H 3700 2100 60 0000 C CNN +F 3 "" H 3700 2100 60 0000 C CNN + 2 3700 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B6BF63 +P 3750 1300 +F 0 "U1" H 3800 1400 30 0000 C CNN +F 1 "PORT" H 3750 1300 30 0000 C CNN +F 2 "" H 3750 1300 60 0000 C CNN +F 3 "" H 3750 1300 60 0000 C CNN + 4 3750 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62B6BF90 +P 3800 3400 +F 0 "U1" H 3850 3500 30 0000 C CNN +F 1 "PORT" H 3800 3400 30 0000 C CNN +F 2 "" H 3800 3400 60 0000 C CNN +F 3 "" H 3800 3400 60 0000 C CNN + 5 3800 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 1300 4900 1300 +Wire Wire Line + 4900 1300 4900 1600 +Connection ~ 4900 1600 +Wire Wire Line + 4050 3400 5000 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub new file mode 100644 index 00000000..ad6e1a1e --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub @@ -0,0 +1,14 @@ +* Subcircuit AND_Gate +.subckt AND_Gate net-_m5-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m3-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\and_gate\and_gate.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +* Control Statements + +.ends AND_Gate \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml new file mode 100644 index 00000000..eabe321b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib b/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib new file mode 100644 index 00000000..972525a2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# AND_gate +# +DEF AND_gate X 0 40 Y Y 1 F N +F0 "X" 150 50 60 H V C CNN +F1 "AND_gate" 150 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 300 -25 202 603 -603 0 1 0 N 400 150 400 -200 +P 4 0 1 0 400 150 -300 150 -300 -200 400 -200 N +X OUT 1 700 -50 200 L 50 50 1 1 O +X A 2 -500 100 200 R 50 50 1 1 I +X B 3 -500 -100 200 R 50 50 1 1 I +X VDD 4 -50 350 200 D 50 50 1 1 I +X GND 5 -150 -400 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# NOR +# +DEF NOR X 0 40 Y Y 1 F N +F0 "X" 100 100 60 H V C CNN +F1 "NOR" 150 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 50 0 1 0 N +P 6 0 1 0 -250 150 250 150 350 0 250 -150 -250 -150 -250 150 N +X OUT 1 650 0 200 L 50 50 1 1 O +X A 2 -450 100 200 R 50 50 1 1 I +X B 3 -450 -100 200 R 50 50 1 1 I +X VDD 4 -100 350 200 D 50 50 1 1 I +X GND 5 0 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir new file mode 100644 index 00000000..530338ba --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4028_B\CD4028_B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 16:06:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X5 Net-_X12-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X6 Net-_X13-Pad2_ Net-_M4-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X7 Net-_X10-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X2 Net-_X11-Pad2_ Net-_M4-Pad1_ Net-_M1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X1 Net-_X1-Pad1_ Net-_M2-Pad2_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X3 Net-_X12-Pad3_ Net-_M2-Pad1_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X4 Net-_X16-Pad3_ Net-_M2-Pad2_ Net-_M3-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X8 Net-_U1-Pad3_ Net-_X12-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X9 Net-_U1-Pad14_ Net-_X13-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X10 Net-_U1-Pad2_ Net-_X10-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X11 Net-_U1-Pad15_ Net-_X11-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X12 Net-_U1-Pad1_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X13 Net-_U1-Pad6_ Net-_X13-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X14 Net-_U1-Pad7_ Net-_X10-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X15 Net-_U1-Pad4_ Net-_X11-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X16 Net-_U1-Pad9_ Net-_X12-Pad2_ Net-_X16-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X17 Net-_U1-Pad5_ Net-_X13-Pad2_ Net-_X16-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +M8 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_M1-Pad3_ Net-_U1-Pad9_ Net-_M4-Pad2_ Net-_M3-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_M5-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out new file mode 100644 index 00000000..69859b03 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out @@ -0,0 +1,41 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4028_b\cd4028_b.cir + +.include AND_Gate.sub +.include NOR_Gate.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x5 net-_x12-pad2_ net-_m4-pad2_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x6 net-_x13-pad2_ net-_m4-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x7 net-_x10-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x2 net-_x11-pad2_ net-_m4-pad1_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x1 net-_x1-pad1_ net-_m2-pad2_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x3 net-_x12-pad3_ net-_m2-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x4 net-_x16-pad3_ net-_m2-pad2_ net-_m3-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x8 net-_u1-pad3_ net-_x12-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x9 net-_u1-pad14_ net-_x13-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x10 net-_u1-pad2_ net-_x10-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x11 net-_u1-pad15_ net-_x11-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x12 net-_u1-pad1_ net-_x12-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x13 net-_u1-pad6_ net-_x13-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x14 net-_u1-pad7_ net-_x10-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x15 net-_u1-pad4_ net-_x11-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x16 net-_u1-pad9_ net-_x12-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x17 net-_u1-pad5_ net-_x13-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_m4-pad2_ net-_m3-pad2_ net-_m2-pad2_ net-_m1-pad2_ net-_u1-pad14_ net-_u1-pad15_ net-_m5-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro b/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch new file mode 100644 index 00000000..bf06b0df --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch @@ -0,0 +1,942 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD4028_B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L NOR X5 +U 1 1 62B82191 +P 2900 1500 +F 0 "X5" H 3000 1600 60 0000 C CNN +F 1 "NOR" H 3050 1450 60 0000 C CNN +F 2 "" H 2900 1500 60 0001 C CNN +F 3 "" H 2900 1500 60 0001 C CNN + 1 2900 1500 + 1 0 0 -1 +$EndComp +$Comp +L NOR X6 +U 1 1 62B821F6 +P 2900 2400 +F 0 "X6" H 3000 2500 60 0000 C CNN +F 1 "NOR" H 3050 2350 60 0000 C CNN +F 2 "" H 2900 2400 60 0001 C CNN +F 3 "" H 2900 2400 60 0001 C CNN + 1 2900 2400 + 1 0 0 -1 +$EndComp +$Comp +L NOR X7 +U 1 1 62B82225 +P 2900 3250 +F 0 "X7" H 3000 3350 60 0000 C CNN +F 1 "NOR" H 3050 3200 60 0000 C CNN +F 2 "" H 2900 3250 60 0001 C CNN +F 3 "" H 2900 3250 60 0001 C CNN + 1 2900 3250 + 1 0 0 -1 +$EndComp +$Comp +L NOR X2 +U 1 1 62B8225C +P 2850 4050 +F 0 "X2" H 2950 4150 60 0000 C CNN +F 1 "NOR" H 3000 4000 60 0000 C CNN +F 2 "" H 2850 4050 60 0001 C CNN +F 3 "" H 2850 4050 60 0001 C CNN + 1 2850 4050 + 1 0 0 -1 +$EndComp +$Comp +L NOR X1 +U 1 1 62B822A5 +P 2800 4950 +F 0 "X1" H 2900 5050 60 0000 C CNN +F 1 "NOR" H 2950 4900 60 0000 C CNN +F 2 "" H 2800 4950 60 0001 C CNN +F 3 "" H 2800 4950 60 0001 C CNN + 1 2800 4950 + 1 0 0 -1 +$EndComp +$Comp +L NOR X3 +U 1 1 62B8239B +P 2850 5850 +F 0 "X3" H 2950 5950 60 0000 C CNN +F 1 "NOR" H 3000 5800 60 0000 C CNN +F 2 "" H 2850 5850 60 0001 C CNN +F 3 "" H 2850 5850 60 0001 C CNN + 1 2850 5850 + 1 0 0 -1 +$EndComp +$Comp +L NOR X4 +U 1 1 62B82472 +P 2850 6650 +F 0 "X4" H 2950 6750 60 0000 C CNN +F 1 "NOR" H 3000 6600 60 0000 C CNN +F 2 "" H 2850 6650 60 0001 C CNN +F 3 "" H 2850 6650 60 0001 C CNN + 1 2850 6650 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X8 +U 1 1 62B829B4 +P 4950 1050 +F 0 "X8" H 5100 1100 60 0000 C CNN +F 1 "AND_gate" H 5100 950 60 0000 C CNN +F 2 "" H 4950 1050 60 0001 C CNN +F 3 "" H 4950 1050 60 0001 C CNN + 1 4950 1050 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X9 +U 1 1 62B82D5D +P 4950 1900 +F 0 "X9" H 5100 1950 60 0000 C CNN +F 1 "AND_gate" H 5100 1800 60 0000 C CNN +F 2 "" H 4950 1900 60 0001 C CNN +F 3 "" H 4950 1900 60 0001 C CNN + 1 4950 1900 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X10 +U 1 1 62B82D9A +P 4950 2650 +F 0 "X10" H 5100 2700 60 0000 C CNN +F 1 "AND_gate" H 5100 2550 60 0000 C CNN +F 2 "" H 4950 2650 60 0001 C CNN +F 3 "" H 4950 2650 60 0001 C CNN + 1 4950 2650 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X11 +U 1 1 62B82DFB +P 4950 3450 +F 0 "X11" H 5100 3500 60 0000 C CNN +F 1 "AND_gate" H 5100 3350 60 0000 C CNN +F 2 "" H 4950 3450 60 0001 C CNN +F 3 "" H 4950 3450 60 0001 C CNN + 1 4950 3450 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X12 +U 1 1 62B82E50 +P 4950 4200 +F 0 "X12" H 5100 4250 60 0000 C CNN +F 1 "AND_gate" H 5100 4100 60 0000 C CNN +F 2 "" H 4950 4200 60 0001 C CNN +F 3 "" H 4950 4200 60 0001 C CNN + 1 4950 4200 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X13 +U 1 1 62B82FFD +P 4950 5000 +F 0 "X13" H 5100 5050 60 0000 C CNN +F 1 "AND_gate" H 5100 4900 60 0000 C CNN +F 2 "" H 4950 5000 60 0001 C CNN +F 3 "" H 4950 5000 60 0001 C CNN + 1 4950 5000 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X14 +U 1 1 62B83048 +P 4950 5750 +F 0 "X14" H 5100 5800 60 0000 C CNN +F 1 "AND_gate" H 5100 5650 60 0000 C CNN +F 2 "" H 4950 5750 60 0001 C CNN +F 3 "" H 4950 5750 60 0001 C CNN + 1 4950 5750 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X15 +U 1 1 62B83307 +P 4950 6550 +F 0 "X15" H 5100 6600 60 0000 C CNN +F 1 "AND_gate" H 5100 6450 60 0000 C CNN +F 2 "" H 4950 6550 60 0001 C CNN +F 3 "" H 4950 6550 60 0001 C CNN + 1 4950 6550 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X16 +U 1 1 62B83368 +P 7600 5150 +F 0 "X16" H 7750 5200 60 0000 C CNN +F 1 "AND_gate" H 7750 5050 60 0000 C CNN +F 2 "" H 7600 5150 60 0001 C CNN +F 3 "" H 7600 5150 60 0001 C CNN + 1 7600 5150 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X17 +U 1 1 62B83411 +P 7600 5950 +F 0 "X17" H 7750 6000 60 0000 C CNN +F 1 "AND_gate" H 7750 5850 60 0000 C CNN +F 2 "" H 7600 5950 60 0001 C CNN +F 3 "" H 7600 5950 60 0001 C CNN + 1 7600 5950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 62B84DD0 +P 1500 1650 +F 0 "M8" H 1450 1700 50 0000 R CNN +F 1 "eSim_MOS_P" H 1550 1800 50 0000 R CNN +F 2 "" H 1750 1750 29 0000 C CNN +F 3 "" H 1550 1650 60 0000 C CNN + 1 1500 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 62B84E21 +P 1450 2000 +F 0 "M4" H 1450 1850 50 0000 R CNN +F 1 "eSim_MOS_N" H 1550 1950 50 0000 R CNN +F 2 "" H 1750 1700 29 0000 C CNN +F 3 "" H 1550 1800 60 0000 C CNN + 1 1450 2000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 62B853D4 +P 1450 3200 +F 0 "M5" H 1400 3250 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 3350 50 0000 R CNN +F 2 "" H 1700 3300 29 0000 C CNN +F 3 "" H 1500 3200 60 0000 C CNN + 1 1450 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62B853DA +P 1400 3550 +F 0 "M1" H 1400 3400 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 3500 50 0000 R CNN +F 2 "" H 1700 3250 29 0000 C CNN +F 3 "" H 1500 3350 60 0000 C CNN + 1 1400 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62B8576A +P 1450 4650 +F 0 "M6" H 1400 4700 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 4800 50 0000 R CNN +F 2 "" H 1700 4750 29 0000 C CNN +F 3 "" H 1500 4650 60 0000 C CNN + 1 1450 4650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62B85770 +P 1400 5000 +F 0 "M2" H 1400 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 4950 50 0000 R CNN +F 2 "" H 1700 4700 29 0000 C CNN +F 3 "" H 1500 4800 60 0000 C CNN + 1 1400 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 62B857E4 +P 1450 6000 +F 0 "M7" H 1400 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 6150 50 0000 R CNN +F 2 "" H 1700 6100 29 0000 C CNN +F 3 "" H 1500 6000 60 0000 C CNN + 1 1450 6000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 62B857EA +P 1400 6350 +F 0 "M3" H 1400 6200 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 6300 50 0000 R CNN +F 2 "" H 1700 6050 29 0000 C CNN +F 3 "" H 1500 6150 60 0000 C CNN + 1 1400 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 1650 1350 2200 +Wire Wire Line + 1650 1450 1750 1450 +Wire Wire Line + 1750 1450 1750 1500 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Wire Line + 5650 3500 6900 3500 +Wire Wire Line + 5650 5050 5900 5050 +Wire Wire Line + 5900 5050 5900 4450 +Wire Wire Line + 5900 4450 6950 4450 +Wire Wire Line + 5650 4250 6900 4250 +Wire Wire Line + 5650 5800 6250 5800 +Wire Wire Line + 6250 5800 6250 4550 +Wire Wire Line + 6250 4550 8850 4550 +Wire Wire Line + 5650 6600 6150 6600 +Wire Wire Line + 6150 6600 6150 4750 +Wire Wire Line + 6150 4750 8900 4750 +Wire Wire Line + 2900 1850 2900 1900 +Wire Wire Line + 2900 1900 2400 1900 +Wire Wire Line + 2400 1900 2400 2800 +Connection ~ 2400 2800 +$Comp +L PORT U1 +U 2 1 62B8A45F +P 7150 2700 +F 0 "U1" H 7200 2800 30 0000 C CNN +F 1 "PORT" H 7150 2700 30 0000 C CNN +F 2 "" H 7150 2700 60 0000 C CNN +F 3 "" H 7150 2700 60 0000 C CNN + 2 7150 2700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B8A7E0 +P 7150 4250 +F 0 "U1" H 7200 4350 30 0000 C CNN +F 1 "PORT" H 7150 4250 30 0000 C CNN +F 2 "" H 7150 4250 60 0000 C CNN +F 3 "" H 7150 4250 60 0000 C CNN + 1 7150 4250 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62B8AE80 +P 7150 1100 +F 0 "U1" H 7200 1200 30 0000 C CNN +F 1 "PORT" H 7150 1100 30 0000 C CNN +F 2 "" H 7150 1100 60 0000 C CNN +F 3 "" H 7150 1100 60 0000 C CNN + 3 7150 1100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B8AFD9 +P 9150 4750 +F 0 "U1" H 9200 4850 30 0000 C CNN +F 1 "PORT" H 9150 4750 30 0000 C CNN +F 2 "" H 9150 4750 60 0000 C CNN +F 3 "" H 9150 4750 60 0000 C CNN + 4 9150 4750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62B8B2B9 +P 9200 6000 +F 0 "U1" H 9250 6100 30 0000 C CNN +F 1 "PORT" H 9200 6000 30 0000 C CNN +F 2 "" H 9200 6000 60 0000 C CNN +F 3 "" H 9200 6000 60 0000 C CNN + 5 9200 6000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62B8B3EE +P 7200 4450 +F 0 "U1" H 7250 4550 30 0000 C CNN +F 1 "PORT" H 7200 4450 30 0000 C CNN +F 2 "" H 7200 4450 60 0000 C CNN +F 3 "" H 7200 4450 60 0000 C CNN + 6 7200 4450 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62B8B4A7 +P 9100 4550 +F 0 "U1" H 9150 4650 30 0000 C CNN +F 1 "PORT" H 9100 4550 30 0000 C CNN +F 2 "" H 9100 4550 60 0000 C CNN +F 3 "" H 9100 4550 60 0000 C CNN + 7 9100 4550 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62B8B62F +P 9200 5200 +F 0 "U1" H 9250 5300 30 0000 C CNN +F 1 "PORT" H 9200 5200 30 0000 C CNN +F 2 "" H 9200 5200 60 0000 C CNN +F 3 "" H 9200 5200 60 0000 C CNN + 9 9200 5200 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62B8C927 +P 1300 7250 +F 0 "U1" H 1350 7350 30 0000 C CNN +F 1 "PORT" H 1300 7250 30 0000 C CNN +F 2 "" H 1300 7250 60 0000 C CNN +F 3 "" H 1300 7250 60 0000 C CNN + 8 1300 7250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62B8CB64 +P 800 1900 +F 0 "U1" H 850 2000 30 0000 C CNN +F 1 "PORT" H 800 1900 30 0000 C CNN +F 2 "" H 800 1900 60 0000 C CNN +F 3 "" H 800 1900 60 0000 C CNN + 10 800 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62B8CC31 +P 900 6300 +F 0 "U1" H 950 6400 30 0000 C CNN +F 1 "PORT" H 900 6300 30 0000 C CNN +F 2 "" H 900 6300 60 0000 C CNN +F 3 "" H 900 6300 60 0000 C CNN + 11 900 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62B8CCFC +P 850 4900 +F 0 "U1" H 900 5000 30 0000 C CNN +F 1 "PORT" H 850 4900 30 0000 C CNN +F 2 "" H 850 4900 60 0000 C CNN +F 3 "" H 850 4900 60 0000 C CNN + 12 850 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62B8CDE1 +P 850 3450 +F 0 "U1" H 900 3550 30 0000 C CNN +F 1 "PORT" H 850 3450 30 0000 C CNN +F 2 "" H 850 3450 60 0000 C CNN +F 3 "" H 850 3450 60 0000 C CNN + 13 850 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62B8D384 +P 7150 1950 +F 0 "U1" H 7200 2050 30 0000 C CNN +F 1 "PORT" H 7150 1950 30 0000 C CNN +F 2 "" H 7150 1950 60 0000 C CNN +F 3 "" H 7150 1950 60 0000 C CNN + 14 7150 1950 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62B8D53F +P 7150 3500 +F 0 "U1" H 7200 3600 30 0000 C CNN +F 1 "PORT" H 7150 3500 30 0000 C CNN +F 2 "" H 7150 3500 60 0000 C CNN +F 3 "" H 7150 3500 60 0000 C CNN + 15 7150 3500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62B8D8EA +P 850 700 +F 0 "U1" H 900 800 30 0000 C CNN +F 1 "PORT" H 850 700 30 0000 C CNN +F 2 "" H 850 700 60 0000 C CNN +F 3 "" H 850 700 60 0000 C CNN + 16 850 700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub new file mode 100644 index 00000000..f43f7ea9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub @@ -0,0 +1,35 @@ +* Subcircuit CD4028_B +.subckt CD4028_B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_m4-pad2_ net-_m3-pad2_ net-_m2-pad2_ net-_m1-pad2_ net-_u1-pad14_ net-_u1-pad15_ net-_m5-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4028_b\cd4028_b.cir +.include AND_Gate.sub +.include NOR_Gate.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x5 net-_x12-pad2_ net-_m4-pad2_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x6 net-_x13-pad2_ net-_m4-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x7 net-_x10-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x2 net-_x11-pad2_ net-_m4-pad1_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x1 net-_x1-pad1_ net-_m2-pad2_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x3 net-_x12-pad3_ net-_m2-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x4 net-_x16-pad3_ net-_m2-pad2_ net-_m3-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x8 net-_u1-pad3_ net-_x12-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x9 net-_u1-pad14_ net-_x13-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x10 net-_u1-pad2_ net-_x10-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x11 net-_u1-pad15_ net-_x11-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x12 net-_u1-pad1_ net-_x12-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x13 net-_u1-pad6_ net-_x13-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x14 net-_u1-pad7_ net-_x10-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x15 net-_u1-pad4_ net-_x11-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x16 net-_u1-pad9_ net-_x12-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x17 net-_u1-pad5_ net-_x13-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD4028_B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml new file mode 100644 index 00000000..d5185cb2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_GateC:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib b/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir new file mode 100644 index 00000000..51675c6f --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate\NOR_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 11:08:33 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out new file mode 100644 index 00000000..9bf686dc --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\nor_gate\nor_gate.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m2-pad3_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch new file mode 100644 index 00000000..e1d72f85 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:NOR_Gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 62B6BCF2 +P 4800 2350 +F 0 "M2" H 4750 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 2500 50 0000 R CNN +F 2 "" H 5050 2450 29 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 1 4800 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62B6BD21 +P 4500 3350 +F 0 "M1" H 4500 3200 50 0000 R CNN +F 1 "eSim_MOS_N" H 4600 3300 50 0000 R CNN +F 2 "" H 4800 3050 29 0000 C CNN +F 3 "" H 4600 3150 60 0000 C CNN + 1 4500 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 62B6BD52 +P 4800 2850 +F 0 "M3" H 4750 2900 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 3000 50 0000 R CNN +F 2 "" H 5050 2950 29 0000 C CNN +F 3 "" H 4850 2850 60 0000 C CNN + 1 4800 2850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 62B6BE27 +P 5350 3350 +F 0 "M4" H 5350 3200 50 0000 R CNN +F 1 "eSim_MOS_N" H 5450 3300 50 0000 R CNN +F 2 "" H 5650 3050 29 0000 C CNN +F 3 "" H 5450 3150 60 0000 C CNN + 1 5350 3350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4950 2550 4950 2650 +Wire Wire Line + 4950 3050 4950 3250 +Wire Wire Line + 4700 3350 4700 3250 +Wire Wire Line + 4700 3250 5150 3250 +Wire Wire Line + 5150 3250 5150 3350 +Connection ~ 4950 3250 +Wire Wire Line + 4800 3700 4800 3750 +Wire Wire Line + 4700 3750 5150 3750 +Wire Wire Line + 5050 3750 5050 3700 +Wire Wire Line + 5050 2200 5050 2150 +Wire Wire Line + 5050 2150 4950 2150 +Wire Wire Line + 5050 2700 5050 2650 +Wire Wire Line + 5050 2650 4950 2650 +Connection ~ 5050 3750 +Connection ~ 4800 3750 +Wire Wire Line + 4650 2350 4250 2350 +Wire Wire Line + 4250 2350 4250 3550 +Wire Wire Line + 4250 3550 4400 3550 +Wire Wire Line + 5450 3550 5450 3200 +Wire Wire Line + 5450 3200 4650 3200 +Wire Wire Line + 4650 3200 4650 2850 +Wire Wire Line + 4950 3050 5800 3050 +Wire Wire Line + 4250 2450 4000 2450 +Connection ~ 4250 2450 +Wire Wire Line + 4650 2950 4000 2950 +Connection ~ 4650 2950 +Wire Wire Line + 5000 2150 5000 2100 +Wire Wire Line + 5000 2100 4000 2100 +Connection ~ 5000 2150 +Wire Wire Line + 4950 3750 4950 3850 +Wire Wire Line + 4950 3850 4050 3850 +Connection ~ 4950 3750 +$Comp +L PORT U1 +U 5 1 62B6C047 +P 3800 3850 +F 0 "U1" H 3850 3950 30 0000 C CNN +F 1 "PORT" H 3800 3850 30 0000 C CNN +F 2 "" H 3800 3850 60 0000 C CNN +F 3 "" H 3800 3850 60 0000 C CNN + 5 3800 3850 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 62B6C0A2 +P 3750 2450 +F 0 "U1" H 3800 2550 30 0000 C CNN +F 1 "PORT" H 3750 2450 30 0000 C CNN +F 2 "" H 3750 2450 60 0000 C CNN +F 3 "" H 3750 2450 60 0000 C CNN + 2 3750 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62B6C0DB +P 3750 2950 +F 0 "U1" H 3800 3050 30 0000 C CNN +F 1 "PORT" H 3750 2950 30 0000 C CNN +F 2 "" H 3750 2950 60 0000 C CNN +F 3 "" H 3750 2950 60 0000 C CNN + 3 3750 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B6C112 +P 6050 3050 +F 0 "U1" H 6100 3150 30 0000 C CNN +F 1 "PORT" H 6050 3050 30 0000 C CNN +F 2 "" H 6050 3050 60 0000 C CNN +F 3 "" H 6050 3050 60 0000 C CNN + 1 6050 3050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B6C165 +P 3750 2100 +F 0 "U1" H 3800 2200 30 0000 C CNN +F 1 "PORT" H 3750 2100 30 0000 C CNN +F 2 "" H 3750 2100 60 0000 C CNN +F 3 "" H 3750 2100 60 0000 C CNN + 4 3750 2100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub new file mode 100644 index 00000000..7ce33167 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub @@ -0,0 +1,12 @@ +* Subcircuit NOR_Gate +.subckt NOR_Gate net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m2-pad3_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\nor_gate\nor_gate.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends NOR_Gate \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml new file mode 100644 index 00000000..31ba7357 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4028_B/README.md b/library/SubcircuitLibrary/CD4028_B/README.md new file mode 100644 index 00000000..2a53ca39 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/README.md @@ -0,0 +1,27 @@ + +# CD4028 IC + +It is BCD to Decimal converter IC. CD4028 IC is designed with 180nm CMOS technology in eSim. It is 16 pin IC. +## Usage/Examples + +Code Conversion + +Indication-Tube Decoder + +Address Decoding + +Memory Selection Control +## Documentation + +To know the details of CD4028 IC please go through with the documentation : [CD4028_datasheet](https://www.ti.com/lit/gpn/cd4028b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/analysis b/library/SubcircuitLibrary/CD4028_B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From fc59d1f54d2f569106ee2007684f331612b3e21a Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:05:20 +0530 Subject: CD4069 is NOT gate IC. --- library/SubcircuitLibrary/CD4069/CD4069-cache.lib | 100 +++++ library/SubcircuitLibrary/CD4069/CD4069.cir | 23 + library/SubcircuitLibrary/CD4069/CD4069.cir.out | 26 ++ library/SubcircuitLibrary/CD4069/CD4069.pro | 71 ++++ library/SubcircuitLibrary/CD4069/CD4069.sch | 463 +++++++++++++++++++++ library/SubcircuitLibrary/CD4069/CD4069.sub | 20 + .../CD4069/CD4069_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD4069/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD4069/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD4069/README.md | 27 ++ library/SubcircuitLibrary/CD4069/analysis | 1 + 11 files changed, 756 insertions(+) create mode 100644 library/SubcircuitLibrary/CD4069/CD4069-cache.lib create mode 100644 library/SubcircuitLibrary/CD4069/CD4069.cir create mode 100644 library/SubcircuitLibrary/CD4069/CD4069.cir.out create mode 100644 library/SubcircuitLibrary/CD4069/CD4069.pro create mode 100644 library/SubcircuitLibrary/CD4069/CD4069.sch create mode 100644 library/SubcircuitLibrary/CD4069/CD4069.sub create mode 100644 library/SubcircuitLibrary/CD4069/CD4069_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4069/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4069/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD4069/README.md create mode 100644 library/SubcircuitLibrary/CD4069/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD4069/CD4069-cache.lib b/library/SubcircuitLibrary/CD4069/CD4069-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4069/CD4069.cir b/library/SubcircuitLibrary/CD4069/CD4069.cir new file mode 100644 index 00000000..d7fb6c17 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069.cir @@ -0,0 +1,23 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4069\CD4069.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/22 15:25:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M9 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M12 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M6 Net-_M5-Pad1_ Net-_M5-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M7 Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M8 Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M4 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M5-Pad2_ Net-_M5-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad3_ Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4069/CD4069.cir.out b/library/SubcircuitLibrary/CD4069/CD4069.cir.out new file mode 100644 index 00000000..30d857e9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069.cir.out @@ -0,0 +1,26 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4069\cd4069.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m9 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m11-pad1_ net-_m11-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m5-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad1_ net-_m3-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m1-pad1_ net-_m5-pad2_ net-_m5-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m10-pad3_ net-_m11-pad1_ net-_m11-pad2_ net-_m7-pad1_ net-_m7-pad2_ net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4069/CD4069.pro b/library/SubcircuitLibrary/CD4069/CD4069.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4069/CD4069.sch b/library/SubcircuitLibrary/CD4069/CD4069.sch new file mode 100644 index 00000000..3f09dcf2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069.sch @@ -0,0 +1,463 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4069-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M9 +U 1 1 629B270D +P 5250 3900 +F 0 "M9" H 5200 3950 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 4050 50 0000 R CNN +F 2 "" H 5500 4000 29 0000 C CNN +F 3 "" H 5300 3900 60 0000 C CNN + 1 5250 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 629B270E +P 5200 4150 +F 0 "M10" H 5200 4000 50 0000 R CNN +F 1 "eSim_MOS_N" H 5300 4100 50 0000 R CNN +F 2 "" H 5500 3850 29 0000 C CNN +F 3 "" H 5300 3950 60 0000 C CNN + 1 5200 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 4100 5400 4150 +Wire Wire Line + 5100 3900 5100 4350 +Wire Wire Line + 5400 3700 7450 3700 +Wire Wire Line + 5500 3700 5500 3750 +Wire Wire Line + 5400 4550 7450 4550 +Wire Wire Line + 5500 4550 5500 4500 +$Comp +L eSim_MOS_P M11 +U 1 1 629B270F +P 7600 3900 +F 0 "M11" H 7550 3950 50 0000 R CNN +F 1 "eSim_MOS_P" H 7650 4050 50 0000 R CNN +F 2 "" H 7850 4000 29 0000 C CNN +F 3 "" H 7650 3900 60 0000 C CNN + 1 7600 3900 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M12 +U 1 1 629B2710 +P 7650 4150 +F 0 "M12" H 7650 4000 50 0000 R CNN +F 1 "eSim_MOS_N" H 7750 4100 50 0000 R CNN +F 2 "" H 7950 3850 29 0000 C CNN +F 3 "" H 7750 3950 60 0000 C CNN + 1 7650 4150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7450 4100 7450 4150 +Wire Wire Line + 7750 3900 7750 4350 +Wire Wire Line + 7350 3700 7350 3750 +Wire Wire Line + 7350 4550 7350 4500 +$Comp +L eSim_MOS_P M5 +U 1 1 629B2711 +P 5250 2800 +F 0 "M5" H 5200 2850 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 2950 50 0000 R CNN +F 2 "" H 5500 2900 29 0000 C CNN +F 3 "" H 5300 2800 60 0000 C CNN + 1 5250 2800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M6 +U 1 1 629B2712 +P 5200 3050 +F 0 "M6" H 5200 2900 50 0000 R CNN +F 1 "eSim_MOS_N" H 5300 3000 50 0000 R CNN +F 2 "" H 5500 2750 29 0000 C CNN +F 3 "" H 5300 2850 60 0000 C CNN + 1 5200 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3000 5400 3050 +Wire Wire Line + 5100 2800 5100 3250 +Wire Wire Line + 5400 2600 7450 2600 +Wire Wire Line + 5500 2600 5500 2650 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 5500 3450 5500 3400 +$Comp +L eSim_MOS_P M7 +U 1 1 629B2713 +P 7600 2800 +F 0 "M7" H 7550 2850 50 0000 R CNN +F 1 "eSim_MOS_P" H 7650 2950 50 0000 R CNN +F 2 "" H 7850 2900 29 0000 C CNN +F 3 "" H 7650 2800 60 0000 C CNN + 1 7600 2800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 629B2714 +P 7650 3050 +F 0 "M8" H 7650 2900 50 0000 R CNN +F 1 "eSim_MOS_N" H 7750 3000 50 0000 R CNN +F 2 "" H 7950 2750 29 0000 C CNN +F 3 "" H 7750 2850 60 0000 C CNN + 1 7650 3050 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7450 3000 7450 3050 +Wire Wire Line + 7750 2800 7750 3250 +Wire Wire Line + 7350 2600 7350 2650 +Wire Wire Line + 7350 3450 7350 3400 +$Comp +L eSim_MOS_P M1 +U 1 1 629B2715 +P 5250 1650 +F 0 "M1" H 5200 1700 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 1800 50 0000 R CNN +F 2 "" H 5500 1750 29 0000 C CNN +F 3 "" H 5300 1650 60 0000 C CNN + 1 5250 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 629B2716 +P 5200 1900 +F 0 "M2" H 5200 1750 50 0000 R CNN +F 1 "eSim_MOS_N" H 5300 1850 50 0000 R CNN +F 2 "" H 5500 1600 29 0000 C CNN +F 3 "" H 5300 1700 60 0000 C CNN + 1 5200 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 1850 5400 1900 +Wire Wire Line + 5100 1650 5100 2100 +Wire Wire Line + 5400 1450 7450 1450 +Wire Wire Line + 5500 1450 5500 1500 +Wire Wire Line + 5400 2300 7450 2300 +Wire Wire Line + 5500 2300 5500 2250 +$Comp +L eSim_MOS_P M3 +U 1 1 629B2717 +P 7600 1650 +F 0 "M3" H 7550 1700 50 0000 R CNN +F 1 "eSim_MOS_P" H 7650 1800 50 0000 R CNN +F 2 "" H 7850 1750 29 0000 C CNN +F 3 "" H 7650 1650 60 0000 C CNN + 1 7600 1650 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 629B2718 +P 7650 1900 +F 0 "M4" H 7650 1750 50 0000 R CNN +F 1 "eSim_MOS_N" H 7750 1850 50 0000 R CNN +F 2 "" H 7950 1600 29 0000 C CNN +F 3 "" H 7750 1700 60 0000 C CNN + 1 7650 1900 + -1 0 0 -1 +$EndComp +Wire Wire Line + 7450 1850 7450 1900 +Wire Wire Line + 7750 1650 7750 2100 +Wire Wire Line + 7350 1450 7350 1500 +Wire Wire Line + 7350 2300 7350 2250 +Wire Wire Line + 5100 1850 4450 1850 +Connection ~ 5100 1850 +Wire Wire Line + 5100 4150 4450 4150 +Connection ~ 5100 4150 +Connection ~ 7350 4550 +Connection ~ 5500 4550 +Connection ~ 7350 1450 +Connection ~ 5500 1450 +Connection ~ 7350 2300 +Connection ~ 5500 2300 +Connection ~ 7350 2600 +Connection ~ 5500 2600 +Connection ~ 7350 3700 +Connection ~ 5500 3700 +Wire Wire Line + 5850 1450 5850 3700 +Connection ~ 5850 2600 +Connection ~ 5850 1450 +Connection ~ 5850 3700 +Connection ~ 7350 3450 +Connection ~ 5500 3450 +Wire Wire Line + 7750 1850 8350 1850 +Connection ~ 7750 1850 +Wire Wire Line + 7750 3050 8350 3050 +Connection ~ 7750 3050 +Wire Wire Line + 7750 4100 8350 4100 +Connection ~ 7750 4100 +Wire Wire Line + 6450 2300 6450 4550 +Connection ~ 6450 3450 +Connection ~ 6450 2300 +Connection ~ 6450 4550 +Wire Wire Line + 5400 1850 6150 1850 +Wire Wire Line + 7450 1850 6950 1850 +Wire Wire Line + 5400 3000 6050 3000 +Wire Wire Line + 7450 3000 7050 3000 +Wire Wire Line + 7450 4150 7050 4150 +Wire Wire Line + 6500 1450 6500 1250 +Wire Wire Line + 6500 1250 6750 1250 +Connection ~ 6500 1450 +Wire Wire Line + 6600 4550 6600 4850 +Wire Wire Line + 6600 4850 6100 4850 +Connection ~ 6600 4550 +$Comp +L PORT U1 +U 1 1 629B29FC +P 4200 1850 +F 0 "U1" H 4250 1950 30 0000 C CNN +F 1 "PORT" H 4200 1850 30 0000 C CNN +F 2 "" H 4200 1850 60 0000 C CNN +F 3 "" H 4200 1850 60 0000 C CNN + 1 4200 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 629B2A53 +P 6400 1850 +F 0 "U1" H 6450 1950 30 0000 C CNN +F 1 "PORT" H 6400 1850 30 0000 C CNN +F 2 "" H 6400 1850 60 0000 C CNN +F 3 "" H 6400 1850 60 0000 C CNN + 2 6400 1850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 629B2ABC +P 4200 3050 +F 0 "U1" H 4250 3150 30 0000 C CNN +F 1 "PORT" H 4200 3050 30 0000 C CNN +F 2 "" H 4200 3050 60 0000 C CNN +F 3 "" H 4200 3050 60 0000 C CNN + 3 4200 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 629B2BB9 +P 6300 3000 +F 0 "U1" H 6350 3100 30 0000 C CNN +F 1 "PORT" H 6300 3000 30 0000 C CNN +F 2 "" H 6300 3000 60 0000 C CNN +F 3 "" H 6300 3000 60 0000 C CNN + 4 6300 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 4450 3050 5100 3050 +Connection ~ 5100 3050 +$Comp +L PORT U1 +U 5 1 629B2E02 +P 4200 4150 +F 0 "U1" H 4250 4250 30 0000 C CNN +F 1 "PORT" H 4200 4150 30 0000 C CNN +F 2 "" H 4200 4150 60 0000 C CNN +F 3 "" H 4200 4150 60 0000 C CNN + 5 4200 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 629B2EE5 +P 6200 4150 +F 0 "U1" H 6250 4250 30 0000 C CNN +F 1 "PORT" H 6200 4150 30 0000 C CNN +F 2 "" H 6200 4150 60 0000 C CNN +F 3 "" H 6200 4150 60 0000 C CNN + 6 6200 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 629B2F78 +P 5850 4850 +F 0 "U1" H 5900 4950 30 0000 C CNN +F 1 "PORT" H 5850 4850 30 0000 C CNN +F 2 "" H 5850 4850 60 0000 C CNN +F 3 "" H 5850 4850 60 0000 C CNN + 7 5850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 629B3086 +P 6800 4150 +F 0 "U1" H 6850 4250 30 0000 C CNN +F 1 "PORT" H 6800 4150 30 0000 C CNN +F 2 "" H 6800 4150 60 0000 C CNN +F 3 "" H 6800 4150 60 0000 C CNN + 8 6800 4150 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 629B319B +P 8600 4100 +F 0 "U1" H 8650 4200 30 0000 C CNN +F 1 "PORT" H 8600 4100 30 0000 C CNN +F 2 "" H 8600 4100 60 0000 C CNN +F 3 "" H 8600 4100 60 0000 C CNN + 9 8600 4100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 629B3200 +P 6800 3000 +F 0 "U1" H 6850 3100 30 0000 C CNN +F 1 "PORT" H 6800 3000 30 0000 C CNN +F 2 "" H 6800 3000 60 0000 C CNN +F 3 "" H 6800 3000 60 0000 C CNN + 10 6800 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 629B328D +P 8600 3050 +F 0 "U1" H 8650 3150 30 0000 C CNN +F 1 "PORT" H 8600 3050 30 0000 C CNN +F 2 "" H 8600 3050 60 0000 C CNN +F 3 "" H 8600 3050 60 0000 C CNN + 11 8600 3050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 629B32F8 +P 6700 1850 +F 0 "U1" H 6750 1950 30 0000 C CNN +F 1 "PORT" H 6700 1850 30 0000 C CNN +F 2 "" H 6700 1850 60 0000 C CNN +F 3 "" H 6700 1850 60 0000 C CNN + 12 6700 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 629B3367 +P 8600 1850 +F 0 "U1" H 8650 1950 30 0000 C CNN +F 1 "PORT" H 8600 1850 30 0000 C CNN +F 2 "" H 8600 1850 60 0000 C CNN +F 3 "" H 8600 1850 60 0000 C CNN + 13 8600 1850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 629B33CE +P 7000 1250 +F 0 "U1" H 7050 1350 30 0000 C CNN +F 1 "PORT" H 7000 1250 30 0000 C CNN +F 2 "" H 7000 1250 60 0000 C CNN +F 3 "" H 7000 1250 60 0000 C CNN + 14 7000 1250 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5400 4150 5950 4150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4069/CD4069.sub b/library/SubcircuitLibrary/CD4069/CD4069.sub new file mode 100644 index 00000000..da6e5ff7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069.sub @@ -0,0 +1,20 @@ +* Subcircuit CD4069 +.subckt CD4069 net-_m1-pad2_ net-_m1-pad1_ net-_m5-pad2_ net-_m5-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m10-pad3_ net-_m11-pad1_ net-_m11-pad2_ net-_m7-pad1_ net-_m7-pad2_ net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4069\cd4069.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m9 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m12 net-_m11-pad1_ net-_m11-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m5-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m3-pad1_ net-_m3-pad2_ net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD4069 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4069/CD4069_Previous_Values.xml b/library/SubcircuitLibrary/CD4069/CD4069_Previous_Values.xml new file mode 100644 index 00000000..31124b00 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/CD4069_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4069/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4069/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4069/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4069/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4069/README.md b/library/SubcircuitLibrary/CD4069/README.md new file mode 100644 index 00000000..5e356565 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/README.md @@ -0,0 +1,27 @@ + +# CD4069 IC + +CD4069 is Hex NOT Gate IC. It is designed with 180nm CMOS technology in eSim consisting six NOR Gates. When all the input is LOW, then only output is HIGH, and vice-versa. It is also known as Inverter Gate. +## Usage/Examples + +Logic inversion + +Pulse shaping + +Oscillators + +High-input-impedance amplifiers +## Documentation + +To know the details of CD4069 IC please go through with the documentation : [CD4069_datasheet](https://www.ti.com/lit/gpn/cd4069ub) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4069/analysis b/library/SubcircuitLibrary/CD4069/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4069/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 384063ac62c38df8d042c22c27ddb5f4a9417f78 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:06:38 +0530 Subject: CD54HC157 is 2x1 Multiplexer IC. --- .../SubcircuitLibrary/CD54_157/CD54_157-cache.lib | 100 ++ library/SubcircuitLibrary/CD54_157/CD54_157.cir | 75 + .../SubcircuitLibrary/CD54_157/CD54_157.cir.out | 78 + library/SubcircuitLibrary/CD54_157/CD54_157.pro | 71 + library/SubcircuitLibrary/CD54_157/CD54_157.sch | 1721 ++++++++++++++++++++ library/SubcircuitLibrary/CD54_157/CD54_157.sub | 72 + .../CD54_157/CD54_157_Previous_Values.xml | 1 + library/SubcircuitLibrary/CD54_157/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/CD54_157/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD54_157/README.md | 21 + library/SubcircuitLibrary/CD54_157/analysis | 1 + 11 files changed, 2164 insertions(+) create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157-cache.lib create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157.cir create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157.cir.out create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157.pro create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157.sch create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157.sub create mode 100644 library/SubcircuitLibrary/CD54_157/CD54_157_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54_157/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_157/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_157/README.md create mode 100644 library/SubcircuitLibrary/CD54_157/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157-cache.lib b/library/SubcircuitLibrary/CD54_157/CD54_157-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157.cir b/library/SubcircuitLibrary/CD54_157/CD54_157.cir new file mode 100644 index 00000000..8a833fef --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157.cir @@ -0,0 +1,75 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157\CD54_157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/14/22 12:01:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M55 Net-_M55-Pad1_ /i0_3 /vcc /vcc eSim_MOS_P +M60 Net-_M55-Pad1_ Net-_M58-Pad2_ /vcc /vcc eSim_MOS_P +M65 Net-_M55-Pad1_ Net-_M57-Pad2_ /vcc /vcc eSim_MOS_P +M56 /y3_bar /i1_3 Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M61 /y3_bar Net-_M58-Pad2_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M66 /y3_bar /s Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M57 /y3_bar Net-_M57-Pad2_ Net-_M57-Pad3_ Net-_M57-Pad3_ eSim_MOS_N +M58 Net-_M57-Pad3_ Net-_M58-Pad2_ Net-_M58-Pad3_ Net-_M58-Pad3_ eSim_MOS_N +M59 Net-_M58-Pad3_ /i0_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M62 /y3_bar /s Net-_M62-Pad3_ Net-_M62-Pad3_ eSim_MOS_N +M63 Net-_M62-Pad3_ Net-_M58-Pad2_ Net-_M63-Pad3_ Net-_M63-Pad3_ eSim_MOS_N +M64 Net-_M63-Pad3_ /i1_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M68 Net-_M57-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M67 Net-_M57-Pad2_ /s /vcc /vcc eSim_MOS_P +M71 Net-_M58-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M72 Net-_M58-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M1 Net-_M1-Pad1_ /i0_1 /vcc /vcc eSim_MOS_P +M11 Net-_M1-Pad1_ Net-_M11-Pad2_ /vcc /vcc eSim_MOS_P +M18 Net-_M1-Pad1_ Net-_M18-Pad2_ /vcc /vcc eSim_MOS_P +M2 /y1_bar /i1_1 Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M12 /y1_bar Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M19 /y1_bar /s Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M3 /y1_bar Net-_M18-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M11-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ eSim_MOS_N +M5 Net-_M4-Pad3_ /i0_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M15 /y1_bar /s Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N +M16 Net-_M15-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M17 Net-_M16-Pad3_ /i1_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M26 Net-_M18-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M25 Net-_M18-Pad2_ /s /vcc /vcc eSim_MOS_P +M33 Net-_M11-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M34 Net-_M11-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M6 Net-_M13-Pad1_ /i0_2 /vcc /vcc eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ /vcc /vcc eSim_MOS_P +M23 Net-_M13-Pad1_ Net-_M23-Pad2_ /vcc /vcc eSim_MOS_P +M7 /y2_bar /i1_2 Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M14 /y2_bar Net-_M13-Pad2_ Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M24 /y2_bar /s Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M8 /y2_bar Net-_M23-Pad2_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_N +M9 Net-_M8-Pad3_ Net-_M13-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M10 Net-_M10-Pad1_ /i0_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M20 /y2_bar /s Net-_M20-Pad3_ Net-_M20-Pad3_ eSim_MOS_N +M21 Net-_M20-Pad3_ Net-_M13-Pad2_ Net-_M21-Pad3_ Net-_M21-Pad3_ eSim_MOS_N +M22 Net-_M21-Pad3_ /i1_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M30 Net-_M23-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M29 Net-_M23-Pad2_ /s /vcc /vcc eSim_MOS_P +M35 Net-_M13-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M36 Net-_M13-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M37 Net-_M37-Pad1_ /i0_4 /vcc /vcc eSim_MOS_P +M42 Net-_M37-Pad1_ Net-_M40-Pad2_ /vcc /vcc eSim_MOS_P +M47 Net-_M37-Pad1_ Net-_M39-Pad2_ /vcc /vcc eSim_MOS_P +M38 /y4_bar /i1_4 Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M43 /y4_bar Net-_M40-Pad2_ Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M48 /y4_bar /s Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M39 /y4_bar Net-_M39-Pad2_ Net-_M39-Pad3_ Net-_M39-Pad3_ eSim_MOS_N +M40 Net-_M39-Pad3_ Net-_M40-Pad2_ Net-_M40-Pad3_ Net-_M40-Pad3_ eSim_MOS_N +M41 Net-_M40-Pad3_ /i0_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M44 /y4_bar /s Net-_M44-Pad3_ Net-_M44-Pad3_ eSim_MOS_N +M45 Net-_M44-Pad3_ Net-_M40-Pad2_ Net-_M45-Pad3_ Net-_M45-Pad3_ eSim_MOS_N +M46 Net-_M45-Pad3_ /i1_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M50 Net-_M39-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M49 Net-_M39-Pad2_ /s /vcc /vcc eSim_MOS_P +M53 Net-_M40-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M54 Net-_M40-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +U1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar Net-_M10-Pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc PORT + +.end diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157.cir.out b/library/SubcircuitLibrary/CD54_157/CD54_157.cir.out new file mode 100644 index 00000000..1f4b4837 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157.cir.out @@ -0,0 +1,78 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* u1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157.pro b/library/SubcircuitLibrary/CD54_157/CD54_157.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157.sch b/library/SubcircuitLibrary/CD54_157/CD54_157.sch new file mode 100644 index 00000000..1e92f660 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157.sch @@ -0,0 +1,1721 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD54_157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M55 +U 1 1 62A758F3 +P 6850 1300 +F 0 "M55" H 6800 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 6900 1450 50 0000 R CNN +F 2 "" H 7100 1400 29 0000 C CNN +F 3 "" H 6900 1300 60 0000 C CNN + 1 6850 1300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M60 +U 1 1 62A758F4 +P 7700 1300 +F 0 "M60" H 7650 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 7750 1450 50 0000 R CNN +F 2 "" H 7950 1400 29 0000 C CNN +F 3 "" H 7750 1300 60 0000 C CNN + 1 7700 1300 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M65 +U 1 1 62A758F5 +P 8350 1300 +F 0 "M65" H 8300 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 8400 1450 50 0000 R CNN +F 2 "" H 8600 1400 29 0000 C CNN +F 3 "" H 8400 1300 60 0000 C CNN + 1 8350 1300 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M56 +U 1 1 62A758F6 +P 6850 1850 +F 0 "M56" H 6800 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 6900 2000 50 0000 R CNN +F 2 "" H 7100 1950 29 0000 C CNN +F 3 "" H 6900 1850 60 0000 C CNN + 1 6850 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M61 +U 1 1 62A758F7 +P 7700 1850 +F 0 "M61" H 7650 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 7750 2000 50 0000 R CNN +F 2 "" H 7950 1950 29 0000 C CNN +F 3 "" H 7750 1850 60 0000 C CNN + 1 7700 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M66 +U 1 1 62A758F8 +P 8350 1850 +F 0 "M66" H 8300 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 8400 2000 50 0000 R CNN +F 2 "" H 8600 1950 29 0000 C CNN +F 3 "" H 8400 1850 60 0000 C CNN + 1 8350 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M57 +U 1 1 62A758F9 +P 7000 2550 +F 0 "M57" H 7000 2400 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 2500 50 0000 R CNN +F 2 "" H 7300 2250 29 0000 C CNN +F 3 "" H 7100 2350 60 0000 C CNN + 1 7000 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M58 +U 1 1 62A758FA +P 7000 3100 +F 0 "M58" H 7000 2950 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 3050 50 0000 R CNN +F 2 "" H 7300 2800 29 0000 C CNN +F 3 "" H 7100 2900 60 0000 C CNN + 1 7000 3100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M59 +U 1 1 62A758FB +P 7000 3650 +F 0 "M59" H 7000 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 3600 50 0000 R CNN +F 2 "" H 7300 3350 29 0000 C CNN +F 3 "" H 7100 3450 60 0000 C CNN + 1 7000 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M62 +U 1 1 62A758FC +P 8250 2550 +F 0 "M62" H 8250 2400 50 0000 R CNN +F 1 "eSim_MOS_N" H 8350 2500 50 0000 R CNN +F 2 "" H 8550 2250 29 0000 C CNN +F 3 "" H 8350 2350 60 0000 C CNN + 1 8250 2550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M63 +U 1 1 62A758FD +P 8250 3100 +F 0 "M63" H 8250 2950 50 0000 R CNN +F 1 "eSim_MOS_N" H 8350 3050 50 0000 R CNN +F 2 "" H 8550 2800 29 0000 C CNN +F 3 "" H 8350 2900 60 0000 C CNN + 1 8250 3100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M64 +U 1 1 62A758FE +P 8250 3650 +F 0 "M64" H 8250 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 8350 3600 50 0000 R CNN +F 2 "" H 8550 3350 29 0000 C CNN +F 3 "" H 8350 3450 60 0000 C CNN + 1 8250 3650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M68 +U 1 1 62A758FF +P 9450 1700 +F 0 "M68" H 9450 1550 50 0000 R CNN +F 1 "eSim_MOS_N" H 9550 1650 50 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-2100 1700 +Connection ~ -4300 1700 +Wire Wire Line + -4300 1700 -2100 1700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157.sub b/library/SubcircuitLibrary/CD54_157/CD54_157.sub new file mode 100644 index 00000000..9d85337b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157.sub @@ -0,0 +1,72 @@ +* Subcircuit CD54_157 +.subckt CD54_157 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD54_157 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_157/CD54_157_Previous_Values.xml b/library/SubcircuitLibrary/CD54_157/CD54_157_Previous_Values.xml new file mode 100644 index 00000000..850ea0ff --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/CD54_157_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_157/NMOS-180nm.lib b/library/SubcircuitLibrary/CD54_157/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD54_157/PMOS-180nm.lib b/library/SubcircuitLibrary/CD54_157/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD54_157/README.md b/library/SubcircuitLibrary/CD54_157/README.md new file mode 100644 index 00000000..de2f8c9a --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/README.md @@ -0,0 +1,21 @@ + +# CD54HC157 IC + +CD54HC157 is 2:1 Multiplexer IC. It is designed with 180nm CMOS technology in eSim. It is 16 pin IC. The output depends on the select lines. +## Usage/Examples + +Multiplexers +## Documentation + +To know the details of CD54HC157 IC please go through with the documentation : [CD54HC157_datasheet](https://www.ti.com/lit/gpn/cd54hc157) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_157/analysis b/library/SubcircuitLibrary/CD54_157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 2ca7e025d9b51c163c35a5eec449eb6243da3d16 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:09:41 +0530 Subject: CD54HC153 is 4x1 Multiplexer IC. --- .../CD54_HC153/CD54_157-cache.lib | 100 ++ library/SubcircuitLibrary/CD54_HC153/CD54_157.cir | 75 + .../SubcircuitLibrary/CD54_HC153/CD54_157.cir.out | 78 + library/SubcircuitLibrary/CD54_HC153/CD54_157.pro | 71 + library/SubcircuitLibrary/CD54_HC153/CD54_157.sch | 1721 ++++++++++++++++++++ library/SubcircuitLibrary/CD54_HC153/CD54_157.sub | 72 + .../CD54_HC153/CD54_157_Previous_Values.xml | 1 + .../CD54_HC153/CD54_HC153-cache.lib | 147 ++ .../SubcircuitLibrary/CD54_HC153/CD54_HC153.cir | 35 + .../CD54_HC153/CD54_HC153.cir.out | 39 + .../SubcircuitLibrary/CD54_HC153/CD54_HC153.pro | 71 + .../SubcircuitLibrary/CD54_HC153/CD54_HC153.sch | 940 +++++++++++ .../SubcircuitLibrary/CD54_HC153/CD54_HC153.sub | 33 + .../CD54_HC153/CD54_HC153_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD54_HC153/NMOS-180nm.lib | 13 + .../SubcircuitLibrary/CD54_HC153/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD54_HC153/README.md | 21 + library/SubcircuitLibrary/CD54_HC153/analysis | 1 + 18 files changed, 3430 insertions(+) create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157-cache.lib create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157.cir create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157.cir.out create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157.pro create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157.sch create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157.sub create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_157_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153-cache.lib create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir.out create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153.pro create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sch create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sub create mode 100644 library/SubcircuitLibrary/CD54_HC153/CD54_HC153_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54_HC153/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_HC153/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_HC153/README.md create mode 100644 library/SubcircuitLibrary/CD54_HC153/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157-cache.lib b/library/SubcircuitLibrary/CD54_HC153/CD54_157-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir b/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir new file mode 100644 index 00000000..8a833fef --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir @@ -0,0 +1,75 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157\CD54_157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/14/22 12:01:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M55 Net-_M55-Pad1_ /i0_3 /vcc /vcc eSim_MOS_P +M60 Net-_M55-Pad1_ Net-_M58-Pad2_ /vcc /vcc eSim_MOS_P +M65 Net-_M55-Pad1_ Net-_M57-Pad2_ /vcc /vcc eSim_MOS_P +M56 /y3_bar /i1_3 Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M61 /y3_bar Net-_M58-Pad2_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M66 /y3_bar /s Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M57 /y3_bar Net-_M57-Pad2_ Net-_M57-Pad3_ Net-_M57-Pad3_ eSim_MOS_N +M58 Net-_M57-Pad3_ Net-_M58-Pad2_ Net-_M58-Pad3_ Net-_M58-Pad3_ eSim_MOS_N +M59 Net-_M58-Pad3_ /i0_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M62 /y3_bar /s Net-_M62-Pad3_ Net-_M62-Pad3_ eSim_MOS_N +M63 Net-_M62-Pad3_ Net-_M58-Pad2_ Net-_M63-Pad3_ Net-_M63-Pad3_ eSim_MOS_N +M64 Net-_M63-Pad3_ /i1_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M68 Net-_M57-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M67 Net-_M57-Pad2_ /s /vcc /vcc eSim_MOS_P +M71 Net-_M58-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M72 Net-_M58-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M1 Net-_M1-Pad1_ /i0_1 /vcc /vcc eSim_MOS_P +M11 Net-_M1-Pad1_ Net-_M11-Pad2_ /vcc /vcc eSim_MOS_P +M18 Net-_M1-Pad1_ Net-_M18-Pad2_ /vcc /vcc eSim_MOS_P +M2 /y1_bar /i1_1 Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M12 /y1_bar Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M19 /y1_bar /s Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M3 /y1_bar Net-_M18-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M11-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ eSim_MOS_N +M5 Net-_M4-Pad3_ /i0_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M15 /y1_bar /s Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N +M16 Net-_M15-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M17 Net-_M16-Pad3_ /i1_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M26 Net-_M18-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M25 Net-_M18-Pad2_ /s /vcc /vcc eSim_MOS_P +M33 Net-_M11-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M34 Net-_M11-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M6 Net-_M13-Pad1_ /i0_2 /vcc /vcc eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ /vcc /vcc eSim_MOS_P +M23 Net-_M13-Pad1_ Net-_M23-Pad2_ /vcc /vcc eSim_MOS_P +M7 /y2_bar /i1_2 Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M14 /y2_bar Net-_M13-Pad2_ Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M24 /y2_bar /s Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M8 /y2_bar Net-_M23-Pad2_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_N +M9 Net-_M8-Pad3_ Net-_M13-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M10 Net-_M10-Pad1_ /i0_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M20 /y2_bar /s Net-_M20-Pad3_ Net-_M20-Pad3_ eSim_MOS_N +M21 Net-_M20-Pad3_ Net-_M13-Pad2_ Net-_M21-Pad3_ Net-_M21-Pad3_ eSim_MOS_N +M22 Net-_M21-Pad3_ /i1_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M30 Net-_M23-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M29 Net-_M23-Pad2_ /s /vcc /vcc eSim_MOS_P +M35 Net-_M13-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M36 Net-_M13-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M37 Net-_M37-Pad1_ /i0_4 /vcc /vcc eSim_MOS_P +M42 Net-_M37-Pad1_ Net-_M40-Pad2_ /vcc /vcc eSim_MOS_P +M47 Net-_M37-Pad1_ Net-_M39-Pad2_ /vcc /vcc eSim_MOS_P +M38 /y4_bar /i1_4 Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M43 /y4_bar Net-_M40-Pad2_ Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M48 /y4_bar /s Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M39 /y4_bar Net-_M39-Pad2_ Net-_M39-Pad3_ Net-_M39-Pad3_ eSim_MOS_N +M40 Net-_M39-Pad3_ Net-_M40-Pad2_ Net-_M40-Pad3_ Net-_M40-Pad3_ eSim_MOS_N +M41 Net-_M40-Pad3_ /i0_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M44 /y4_bar /s Net-_M44-Pad3_ Net-_M44-Pad3_ eSim_MOS_N +M45 Net-_M44-Pad3_ Net-_M40-Pad2_ Net-_M45-Pad3_ Net-_M45-Pad3_ eSim_MOS_N +M46 Net-_M45-Pad3_ /i1_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M50 Net-_M39-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M49 Net-_M39-Pad2_ /s /vcc /vcc eSim_MOS_P +M53 Net-_M40-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M54 Net-_M40-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +U1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar Net-_M10-Pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc PORT + +.end diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir.out b/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir.out new file mode 100644 index 00000000..1f4b4837 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157.cir.out @@ -0,0 +1,78 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* u1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157.pro b/library/SubcircuitLibrary/CD54_HC153/CD54_157.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157.sch b/library/SubcircuitLibrary/CD54_HC153/CD54_157.sch new file mode 100644 index 00000000..1e92f660 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157.sch @@ -0,0 +1,1721 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD54_157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M55 +U 1 1 62A758F3 +P 6850 1300 +F 0 "M55" H 6800 1350 50 0000 R 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13 1 62ACABE8 +P 3600 1850 +F 0 "U1" H 3650 1950 30 0000 C CNN +F 1 "PORT" H 3600 1850 30 0000 C CNN +F 2 "" H 3600 1850 60 0000 C CNN +F 3 "" H 3600 1850 60 0000 C CNN + 13 3600 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62ACACE3 +P 3600 1300 +F 0 "U1" H 3650 1400 30 0000 C CNN +F 1 "PORT" H 3600 1300 30 0000 C CNN +F 2 "" H 3600 1300 60 0000 C CNN +F 3 "" H 3600 1300 60 0000 C CNN + 14 3600 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62ACADBC +P 12300 4450 +F 0 "U1" H 12350 4550 30 0000 C CNN +F 1 "PORT" H 12300 4450 30 0000 C CNN +F 2 "" H 12300 4450 60 0000 C CNN +F 3 "" H 12300 4450 60 0000 C CNN + 15 12300 4450 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62AD09D5 +P -8850 100 +F 0 "U1" H -8800 200 30 0000 C CNN +F 1 "PORT" H -8850 100 30 0000 C CNN +F 2 "" H -8850 100 60 0000 C CNN +F 3 "" H -8850 100 60 0000 C CNN + 16 -8850 100 + 1 0 0 -1 +$EndComp +Connection ~ -2100 1700 +Connection ~ -4300 1700 +Wire Wire Line + -4300 1700 -2100 1700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157.sub b/library/SubcircuitLibrary/CD54_HC153/CD54_157.sub new file mode 100644 index 00000000..9d85337b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157.sub @@ -0,0 +1,72 @@ +* Subcircuit CD54_157 +.subckt CD54_157 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD54_157 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_157_Previous_Values.xml b/library/SubcircuitLibrary/CD54_HC153/CD54_157_Previous_Values.xml new file mode 100644 index 00000000..850ea0ff --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_157_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153-cache.lib b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153-cache.lib new file mode 100644 index 00000000..fe4a08da --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CD_54157 +# +DEF CD_54157 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "CD_54157" 0 -250 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -600 0 1 0 N +X Sel 1 -550 150 200 R 50 50 1 1 I +X I0_1 2 -550 50 200 R 50 50 1 1 I +X I1_1 3 -550 -50 200 R 50 50 1 1 I +X Y1_bar 4 -550 -150 200 R 50 50 1 1 O +X I0_2 5 -550 -250 200 R 50 50 1 1 I +X I1_2 6 -550 -350 200 R 50 50 1 1 I +X Y2_bar 7 -550 -450 200 R 50 50 1 1 O +X GND 8 -550 -550 200 R 50 50 1 1 I +X Y3_bar 9 550 -550 200 L 50 50 1 1 O +X I1_3 10 550 -450 200 L 50 50 1 1 I +X I0_3 11 550 -350 200 L 50 50 1 1 I +X Y4_bar 12 550 -250 200 L 50 50 1 1 O +X I1_4 13 550 -150 200 L 50 50 1 1 I +X I0_4 14 550 -50 200 L 50 50 1 1 I +X E_bar 15 550 50 200 L 50 50 1 1 I +X VCC 16 550 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir new file mode 100644 index 00000000..c9b072a5 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir @@ -0,0 +1,35 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_HC153\CD54_HC153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/22 13:33:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 /s0 ? ? ? ? ? ? /gnd Net-_M1-Pad2_ /i1_1 /i0_1 ? ? ? /e_bar_1 /vcc CD_54157 +X2 /s0 ? ? ? ? ? ? /gnd Net-_M3-Pad2_ /i3_1 /i2_1 ? ? ? /e_bar_1 /vcc CD_54157 +X5 /s1 ? ? ? Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_R5-Pad1_ /gnd ? ? ? ? ? ? /e_bar_1 /vcc CD_54157 +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ /vcc /vcc eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ /gnd /gnd eSim_MOS_N +M4 Net-_M3-Pad1_ Net-_M3-Pad2_ /vcc /vcc eSim_MOS_P +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ /gnd /gnd eSim_MOS_N +M10 /y1 Net-_M10-Pad2_ /vcc /vcc eSim_MOS_P +M9 /y1 Net-_M10-Pad2_ /gnd /gnd eSim_MOS_N +R1 Net-_M1-Pad1_ Net-_R1-Pad2_ 1 +R2 Net-_M3-Pad1_ Net-_R2-Pad2_ 1 +R5 Net-_R5-Pad1_ Net-_M10-Pad2_ 1 +X3 /s0 ? ? ? ? ? ? /gnd Net-_M5-Pad2_ /i1_2 /i0_2 ? ? ? /e_bar_2 /vcc CD_54157 +X4 /s0 ? ? ? ? ? ? /gnd Net-_M7-Pad2_ /i3_2 /i2_2 ? ? ? /e_bar_2 /vcc CD_54157 +X6 /s1 ? ? ? Net-_R3-Pad2_ Net-_R4-Pad2_ Net-_R6-Pad1_ /gnd ? ? ? ? ? ? /e_bar_2 /vcc CD_54157 +M6 Net-_M5-Pad1_ Net-_M5-Pad2_ /vcc /vcc eSim_MOS_P +M5 Net-_M5-Pad1_ Net-_M5-Pad2_ /gnd /gnd eSim_MOS_N +M8 Net-_M7-Pad1_ Net-_M7-Pad2_ /vcc /vcc eSim_MOS_P +M7 Net-_M7-Pad1_ Net-_M7-Pad2_ /gnd /gnd eSim_MOS_N +M12 /y2 Net-_M11-Pad2_ /vcc /vcc eSim_MOS_P +M11 /y2 Net-_M11-Pad2_ /gnd /gnd eSim_MOS_N +R3 Net-_M5-Pad1_ Net-_R3-Pad2_ 1 +R4 Net-_M7-Pad1_ Net-_R4-Pad2_ 1 +R6 Net-_R6-Pad1_ Net-_M11-Pad2_ 1 +U1 /e_bar_1 /s1 /i3_1 /i2_1 /i1_1 /i0_1 /y1 /gnd /y2 /i0_2 /i1_2 /i2_2 /i3_2 /s0 /e_bar_2 /vcc PORT + +.end diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir.out b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir.out new file mode 100644 index 00000000..4a86e695 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.cir.out @@ -0,0 +1,39 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54_hc153\cd54_hc153.cir + +.include CD54_157.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x1 /s0 ? ? ? ? ? ? /gnd net-_m1-pad2_ /i1_1 /i0_1 ? ? ? /e_bar_1 /vcc CD54_157 +x2 /s0 ? ? ? ? ? ? /gnd net-_m3-pad2_ /i3_1 /i2_1 ? ? ? /e_bar_1 /vcc CD54_157 +x5 /s1 ? ? ? net-_r1-pad2_ net-_r2-pad2_ net-_r5-pad1_ /gnd ? ? ? ? ? ? /e_bar_1 /vcc CD54_157 +m2 net-_m1-pad1_ net-_m1-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m4 net-_m3-pad1_ net-_m3-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m10 /y1 net-_m10-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m9 /y1 net-_m10-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +r1 net-_m1-pad1_ net-_r1-pad2_ 1 +r2 net-_m3-pad1_ net-_r2-pad2_ 1 +r5 net-_r5-pad1_ net-_m10-pad2_ 1 +x3 /s0 ? ? ? ? ? ? /gnd net-_m5-pad2_ /i1_2 /i0_2 ? ? ? /e_bar_2 /vcc CD54_157 +x4 /s0 ? ? ? ? ? ? /gnd net-_m7-pad2_ /i3_2 /i2_2 ? ? ? /e_bar_2 /vcc CD54_157 +x6 /s1 ? ? ? net-_r3-pad2_ net-_r4-pad2_ net-_r6-pad1_ /gnd ? ? ? ? ? ? /e_bar_2 /vcc CD54_157 +m6 net-_m5-pad1_ net-_m5-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m12 /y2 net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m11 /y2 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +r3 net-_m5-pad1_ net-_r3-pad2_ 1 +r4 net-_m7-pad1_ net-_r4-pad2_ 1 +r6 net-_r6-pad1_ net-_m11-pad2_ 1 +* u1 /e_bar_1 /s1 /i3_1 /i2_1 /i1_1 /i0_1 /y1 /gnd /y2 /i0_2 /i1_2 /i2_2 /i3_2 /s0 /e_bar_2 /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.pro b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sch b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sch new file mode 100644 index 00000000..04e4711c --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sch @@ -0,0 +1,940 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD54HC153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CD_54157 X1 +U 1 1 62AC2C84 +P 2150 1300 +F 0 "X1" H 2150 1350 60 0000 C CNN +F 1 "CD_54157" V 2150 1050 60 0000 C CNN +F 2 "" H 2150 1300 60 0001 C CNN +F 3 "" H 2150 1300 60 0001 C CNN + 1 2150 1300 + 1 0 0 -1 +$EndComp +$Comp +L CD_54157 X2 +U 1 1 62AC2C85 +P 2150 2450 +F 0 "X2" H 2150 2500 60 0000 C CNN +F 1 "CD_54157" V 2150 2200 60 0000 C CNN +F 2 "" H 2150 2450 60 0001 C CNN +F 3 "" H 2150 2450 60 0001 C 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3900 5800 3800 5800 +Wire Wire Line + 3800 5800 3800 6350 +Wire Wire Line + 3800 6350 3900 6350 +Wire Wire Line + 4200 5600 4300 5600 +Wire Wire Line + 4300 5600 4300 5650 +Wire Wire Line + 4300 6550 4300 6500 +Wire Wire Line + 6150 4800 6350 4800 +Wire Wire Line + 6350 4800 6350 4300 +Wire Wire Line + 1200 4050 3400 4050 +Wire Wire Line + 3250 4900 3650 4900 +Connection ~ 3650 4900 +Wire Wire Line + 3250 6050 3800 6050 +Connection ~ 3800 6050 +$Comp +L eSim_MOS_P M12 +U 1 1 62AC3D85 +P 6550 5500 +F 0 "M12" H 6500 5550 50 0000 R CNN +F 1 "eSim_MOS_P" H 6600 5650 50 0000 R CNN +F 2 "" H 6800 5600 29 0000 C CNN +F 3 "" H 6600 5500 60 0000 C CNN + 1 6550 5500 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M11 +U 1 1 62AC3D8B +P 6500 5850 +F 0 "M11" H 6500 5700 50 0000 R CNN +F 1 "eSim_MOS_N" H 6600 5800 50 0000 R CNN +F 2 "" H 6800 5550 29 0000 C CNN +F 3 "" H 6600 5650 60 0000 C CNN + 1 6500 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 5700 6700 5850 +Wire Wire Line + 6400 5500 6300 5500 +Wire Wire Line + 6300 5500 6300 6050 +Wire Wire Line + 6300 6050 6400 6050 +Wire Wire Line + 6700 5300 6800 5300 +Wire Wire Line + 6800 5300 6800 5350 +Wire Wire Line + 6800 6250 6800 6200 +Wire Wire Line + 6700 6250 6800 6250 +Wire Wire Line + 6700 5750 7350 5750 +Connection ~ 6700 5750 +Wire Wire Line + 4900 5750 5300 5750 +Wire Wire Line + 5600 5750 6300 5750 +Connection ~ 6300 5750 +Wire Wire Line + 5050 5300 4900 5300 +Wire Wire Line + 4900 5300 4900 5750 +Wire Wire Line + 3250 4200 6750 4200 +Wire Wire Line + 4100 750 4100 4450 +Connection ~ 4100 4450 +Connection ~ 4100 4200 +Wire Wire Line + 2150 4900 1900 4900 +Wire Wire Line + 1900 4900 1900 6550 +Wire Wire Line + 1900 6050 2150 6050 +Wire Wire Line + 5050 6550 5050 5400 +Connection ~ 4300 6550 +Connection ~ 4200 6550 +Connection ~ 1900 6050 +Wire Wire Line + 3550 5400 3550 6550 +Connection ~ 3550 6550 +Connection ~ 4050 5400 +Wire Wire Line + 4250 4200 4250 5600 +Connection ~ 4250 5600 +Wire Wire Line + 6750 4200 6750 5300 +Connection ~ 4250 4200 +Connection ~ 6750 5300 +Wire Wire Line + 6750 6550 6750 6250 +Connection ~ 5050 6550 +Connection ~ 6750 6250 +Wire Wire Line + 3250 4700 3350 4700 +Wire Wire Line + 3350 4700 3350 5000 +Wire Wire Line + 3350 5000 1550 5000 +Wire Wire Line + 3250 5850 3400 5850 +Wire Wire Line + 3400 5850 3400 6150 +Wire Wire Line + 3400 6150 1550 6150 +Wire Wire Line + 3250 5950 3350 5950 +Wire Wire Line + 3350 5950 3350 6300 +Wire Wire Line + 3350 6300 1450 6300 +Connection ~ 2000 4200 +Wire Wire Line + 5050 4700 3500 4700 +Wire Wire Line + 3500 4700 3500 4350 +Wire Wire Line + 3500 4350 1400 4350 +Text Label 7000 5750 0 60 ~ 0 +y2 +Text Label 1700 5000 0 60 ~ 0 +i0_2 +Text Label 2050 4050 0 60 ~ 0 +e_bar_2 +$Comp +L resistor R3 +U 1 1 62AC3DCA +P 4500 5000 +F 0 "R3" H 4550 5130 50 0000 C CNN +F 1 "1" H 4550 4950 50 0000 C CNN +F 2 "" H 4550 4980 30 0000 C CNN +F 3 "" V 4550 5050 30 0000 C CNN + 1 4500 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 5100 4850 5100 +Wire Wire Line + 4850 5100 4850 4950 +Wire Wire Line + 4850 4950 4700 4950 +Wire Wire Line + 4400 4950 4050 4950 +Connection ~ 4050 4950 +$Comp +L resistor R4 +U 1 1 62AC3DD5 +P 4500 6100 +F 0 "R4" H 4550 6230 50 0000 C CNN +F 1 "1" H 4550 6050 50 0000 C CNN +F 2 "" H 4550 6080 30 0000 C CNN +F 3 "" V 4550 6150 30 0000 C CNN + 1 4500 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 5200 4850 5200 +Wire Wire Line + 4850 5200 4850 6050 +Wire Wire Line + 4850 6050 4700 6050 +Wire Wire Line + 4400 6050 4200 6050 +Connection ~ 4200 6050 +NoConn ~ 2150 4300 +NoConn ~ 2150 4400 +NoConn ~ 2150 4500 +NoConn ~ 2150 4600 +NoConn ~ 2150 4700 +NoConn ~ 2150 4800 +NoConn ~ 3250 4400 +NoConn ~ 3250 4500 +NoConn ~ 3250 4600 +NoConn ~ 2150 5450 +NoConn ~ 2150 5550 +NoConn ~ 2150 5650 +NoConn ~ 2150 5750 +NoConn ~ 2150 5850 +NoConn ~ 2150 5950 +NoConn ~ 3250 5550 +NoConn ~ 3250 5650 +NoConn ~ 3250 5750 +NoConn ~ 5050 4800 +NoConn ~ 5050 4900 +NoConn ~ 5050 5000 +NoConn ~ 6150 4900 +NoConn ~ 6150 5000 +NoConn ~ 6150 5100 +NoConn ~ 6150 5200 +NoConn ~ 6150 5300 +NoConn ~ 6150 5400 +Wire Wire Line + 3250 5350 3550 5350 +Wire Wire Line + 3550 5350 3550 4200 +Connection ~ 3550 4200 +Wire Wire Line + 6150 4700 6150 4200 +Connection ~ 6150 4200 +$Comp +L resistor R6 +U 1 1 62AC3E01 +P 5400 5800 +F 0 "R6" H 5450 5930 50 0000 C CNN +F 1 "1" H 5450 5750 50 0000 C CNN +F 2 "" H 5450 5780 30 0000 C CNN +F 3 "" V 5450 5850 30 0000 C CNN + 1 5400 5800 + 1 0 0 -1 +$EndComp +Text Label 1700 5100 0 60 ~ 0 +i1_2 +Wire Wire Line + 3250 4800 3300 4800 +Wire Wire Line + 3300 4800 3300 5100 +Wire Wire Line + 3300 5100 1450 5100 +Text Label 1700 6150 0 60 ~ 0 +i2_2 +Text Label 1650 6300 0 60 ~ 0 +i3_2 +Wire Wire Line + 1900 6550 6750 6550 +Connection ~ 3550 750 +Connection ~ 4500 6550 +Wire Wire Line + 1550 4200 1550 1150 +Connection ~ 1550 1150 +Wire Wire Line + 1400 4350 1400 1300 +Connection ~ 1400 1300 +$Comp +L PORT U1 +U 1 1 62AC5307 +P 1000 1000 +F 0 "U1" H 1050 1100 30 0000 C CNN +F 1 "PORT" H 1000 1000 30 0000 C CNN +F 2 "" H 1000 1000 60 0000 C CNN +F 3 "" H 1000 1000 60 0000 C CNN + 1 1000 1000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62AC69FB +P 650 1300 +F 0 "U1" H 700 1400 30 0000 C CNN +F 1 "PORT" H 650 1300 30 0000 C CNN +F 2 "" H 650 1300 60 0000 C CNN +F 3 "" H 650 1300 60 0000 C CNN + 2 650 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62AC6B04 +P 650 3250 +F 0 "U1" H 700 3350 30 0000 C CNN +F 1 "PORT" H 650 3250 30 0000 C CNN +F 2 "" H 650 3250 60 0000 C CNN +F 3 "" H 650 3250 60 0000 C CNN + 3 650 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62AC6B8F +P 750 3100 +F 0 "U1" H 800 3200 30 0000 C CNN +F 1 "PORT" H 750 3100 30 0000 C CNN +F 2 "" H 750 3100 60 0000 C CNN +F 3 "" H 750 3100 60 0000 C CNN + 4 750 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62AC6C24 +P 650 2050 +F 0 "U1" H 700 2150 30 0000 C CNN +F 1 "PORT" H 650 2050 30 0000 C CNN +F 2 "" H 650 2050 60 0000 C CNN +F 3 "" H 650 2050 60 0000 C CNN + 5 650 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62AC6C8D +P 750 1950 +F 0 "U1" H 800 2050 30 0000 C CNN +F 1 "PORT" H 750 1950 30 0000 C CNN +F 2 "" H 750 1950 60 0000 C CNN +F 3 "" H 750 1950 60 0000 C CNN + 6 750 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62AC6D04 +P 7050 2700 +F 0 "U1" H 7100 2800 30 0000 C CNN +F 1 "PORT" H 7050 2700 30 0000 C CNN +F 2 "" H 7050 2700 60 0000 C CNN +F 3 "" H 7050 2700 60 0000 C CNN + 7 7050 2700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62AC6E0E +P 850 3500 +F 0 "U1" H 900 3600 30 0000 C CNN +F 1 "PORT" H 850 3500 30 0000 C CNN +F 2 "" H 850 3500 60 0000 C CNN +F 3 "" H 850 3500 60 0000 C CNN + 8 850 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62AC6FE7 +P 7600 5750 +F 0 "U1" H 7650 5850 30 0000 C CNN +F 1 "PORT" H 7600 5750 30 0000 C CNN +F 2 "" H 7600 5750 60 0000 C CNN +F 3 "" H 7600 5750 60 0000 C CNN + 9 7600 5750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62AC70DD +P 1300 5000 +F 0 "U1" H 1350 5100 30 0000 C CNN +F 1 "PORT" H 1300 5000 30 0000 C CNN +F 2 "" H 1300 5000 60 0000 C CNN +F 3 "" H 1300 5000 60 0000 C CNN + 10 1300 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62AC71F2 +P 1200 5100 +F 0 "U1" H 1250 5200 30 0000 C CNN +F 1 "PORT" H 1200 5100 30 0000 C CNN +F 2 "" H 1200 5100 60 0000 C CNN +F 3 "" H 1200 5100 60 0000 C CNN + 11 1200 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62AC72E5 +P 1300 6150 +F 0 "U1" H 1350 6250 30 0000 C CNN +F 1 "PORT" H 1300 6150 30 0000 C CNN +F 2 "" H 1300 6150 60 0000 C CNN +F 3 "" H 1300 6150 60 0000 C CNN + 12 1300 6150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62AC7362 +P 1200 6300 +F 0 "U1" H 1250 6400 30 0000 C CNN +F 1 "PORT" H 1200 6300 30 0000 C CNN +F 2 "" H 1200 6300 60 0000 C CNN +F 3 "" H 1200 6300 60 0000 C CNN + 13 1200 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62AC74E2 +P 750 1150 +F 0 "U1" H 800 1250 30 0000 C CNN +F 1 "PORT" H 750 1150 30 0000 C CNN +F 2 "" H 750 1150 60 0000 C CNN +F 3 "" H 750 1150 60 0000 C CNN + 14 750 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62AC763B +P 950 4050 +F 0 "U1" H 1000 4150 30 0000 C CNN +F 1 "PORT" H 950 4050 30 0000 C CNN +F 2 "" H 950 4050 60 0000 C CNN +F 3 "" H 950 4050 60 0000 C CNN + 15 950 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62AC7715 +P 1000 750 +F 0 "U1" H 1050 850 30 0000 C CNN +F 1 "PORT" H 1000 750 30 0000 C CNN +F 2 "" H 1000 750 60 0000 C CNN +F 3 "" H 1000 750 60 0000 C CNN + 16 1000 750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sub b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sub new file mode 100644 index 00000000..6152bbf1 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153.sub @@ -0,0 +1,33 @@ +* Subcircuit CD54_HC153 +.subckt CD54_HC153 /e_bar_1 /s1 /i3_1 /i2_1 /i1_1 /i0_1 /y1 /gnd /y2 /i0_2 /i1_2 /i2_2 /i3_2 /s0 /e_bar_2 /vcc +* c:\fossee\esim\library\subcircuitlibrary\cd54_hc153\cd54_hc153.cir +.include CD54_157.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x1 /s0 ? ? ? ? ? ? /gnd net-_m1-pad2_ /i1_1 /i0_1 ? ? ? /e_bar_1 /vcc CD54_157 +x2 /s0 ? ? ? ? ? ? /gnd net-_m3-pad2_ /i3_1 /i2_1 ? ? ? /e_bar_1 /vcc CD54_157 +x5 /s1 ? ? ? net-_r1-pad2_ net-_r2-pad2_ net-_r5-pad1_ /gnd ? ? ? ? ? ? /e_bar_1 /vcc CD54_157 +m2 net-_m1-pad1_ net-_m1-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m4 net-_m3-pad1_ net-_m3-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m10 /y1 net-_m10-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m9 /y1 net-_m10-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +r1 net-_m1-pad1_ net-_r1-pad2_ 1 +r2 net-_m3-pad1_ net-_r2-pad2_ 1 +r5 net-_r5-pad1_ net-_m10-pad2_ 1 +x3 /s0 ? ? ? ? ? ? /gnd net-_m5-pad2_ /i1_2 /i0_2 ? ? ? /e_bar_2 /vcc CD54_157 +x4 /s0 ? ? ? ? ? ? /gnd net-_m7-pad2_ /i3_2 /i2_2 ? ? ? /e_bar_2 /vcc CD54_157 +x6 /s1 ? ? ? net-_r3-pad2_ net-_r4-pad2_ net-_r6-pad1_ /gnd ? ? ? ? ? ? /e_bar_2 /vcc CD54_157 +m6 net-_m5-pad1_ net-_m5-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m5-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m7-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m7-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m12 /y2 net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m11 /y2 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +r3 net-_m5-pad1_ net-_r3-pad2_ 1 +r4 net-_m7-pad1_ net-_r4-pad2_ 1 +r6 net-_r6-pad1_ net-_m11-pad2_ 1 +* Control Statements + +.ends CD54_HC153 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC153/CD54_HC153_Previous_Values.xml b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153_Previous_Values.xml new file mode 100644 index 00000000..a2652f75 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/CD54_HC153_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC153/NMOS-180nm.lib b/library/SubcircuitLibrary/CD54_HC153/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD54_HC153/PMOS-180nm.lib b/library/SubcircuitLibrary/CD54_HC153/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD54_HC153/README.md b/library/SubcircuitLibrary/CD54_HC153/README.md new file mode 100644 index 00000000..de49a7cf --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/README.md @@ -0,0 +1,21 @@ + +# CD54HC153 IC + +It is 4:1 Multiplexer IC. CD54153 IC is designed with 180nm CMOS technology in eSim. It is 16 pin IC. The output depends on the select lines. +## Usage/Examples + +Multiplexers +## Documentation + +To know the details of CD54HC153 IC please go through with the documentation : [CD54HC153_datasheet](https://www.ti.com/lit/gpn/cd54hc153) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC153/analysis b/library/SubcircuitLibrary/CD54_HC153/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC153/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From ec998692f698ceef68d8ccdb97c2132bd5bd1021 Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 24 Aug 2022 23:11:02 +0530 Subject: CD54HC151 is 8x1 Multiplexer IC. --- .../CD54_HC_151/CD54_157-cache.lib | 100 ++ library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir | 75 + .../SubcircuitLibrary/CD54_HC_151/CD54_157.cir.out | 78 + library/SubcircuitLibrary/CD54_HC_151/CD54_157.pro | 71 + library/SubcircuitLibrary/CD54_HC_151/CD54_157.sch | 1721 ++++++++++++++++++++ library/SubcircuitLibrary/CD54_HC_151/CD54_157.sub | 72 + .../CD54_HC_151/CD54_157_Previous_Values.xml | 1 + .../CD54_HC_151/CD54_HC_151-cache.lib | 128 ++ .../SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir | 32 + .../CD54_HC_151/CD54_HC_151.cir.out | 36 + .../SubcircuitLibrary/CD54_HC_151/CD54_HC_151.pro | 71 + .../SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sch | 893 ++++++++++ .../SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sub | 30 + .../CD54_HC_151/CD54_HC_151_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD54_HC_151/NMOS-180nm.lib | 13 + .../SubcircuitLibrary/CD54_HC_151/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CD54_HC_151/README.md | 21 + library/SubcircuitLibrary/CD54_HC_151/analysis | 1 + 18 files changed, 3355 insertions(+) create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157-cache.lib create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir.out create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157.pro create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157.sch create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157.sub create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_157_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151-cache.lib create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir.out create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.pro create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sch create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sub create mode 100644 library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD54_HC_151/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_HC_151/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CD54_HC_151/README.md create mode 100644 library/SubcircuitLibrary/CD54_HC_151/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157-cache.lib b/library/SubcircuitLibrary/CD54_HC_151/CD54_157-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir new file mode 100644 index 00000000..8a833fef --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir @@ -0,0 +1,75 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157\CD54_157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/14/22 12:01:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M55 Net-_M55-Pad1_ /i0_3 /vcc /vcc eSim_MOS_P +M60 Net-_M55-Pad1_ Net-_M58-Pad2_ /vcc /vcc eSim_MOS_P +M65 Net-_M55-Pad1_ Net-_M57-Pad2_ /vcc /vcc eSim_MOS_P +M56 /y3_bar /i1_3 Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M61 /y3_bar Net-_M58-Pad2_ Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M66 /y3_bar /s Net-_M55-Pad1_ Net-_M55-Pad1_ eSim_MOS_P +M57 /y3_bar Net-_M57-Pad2_ Net-_M57-Pad3_ Net-_M57-Pad3_ eSim_MOS_N +M58 Net-_M57-Pad3_ Net-_M58-Pad2_ Net-_M58-Pad3_ Net-_M58-Pad3_ eSim_MOS_N +M59 Net-_M58-Pad3_ /i0_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M62 /y3_bar /s Net-_M62-Pad3_ Net-_M62-Pad3_ eSim_MOS_N +M63 Net-_M62-Pad3_ Net-_M58-Pad2_ Net-_M63-Pad3_ Net-_M63-Pad3_ eSim_MOS_N +M64 Net-_M63-Pad3_ /i1_3 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M68 Net-_M57-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M67 Net-_M57-Pad2_ /s /vcc /vcc eSim_MOS_P +M71 Net-_M58-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M72 Net-_M58-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M1 Net-_M1-Pad1_ /i0_1 /vcc /vcc eSim_MOS_P +M11 Net-_M1-Pad1_ Net-_M11-Pad2_ /vcc /vcc eSim_MOS_P +M18 Net-_M1-Pad1_ Net-_M18-Pad2_ /vcc /vcc eSim_MOS_P +M2 /y1_bar /i1_1 Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M12 /y1_bar Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M19 /y1_bar /s Net-_M1-Pad1_ Net-_M1-Pad1_ eSim_MOS_P +M3 /y1_bar Net-_M18-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M4 Net-_M3-Pad3_ Net-_M11-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ eSim_MOS_N +M5 Net-_M4-Pad3_ /i0_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M15 /y1_bar /s Net-_M15-Pad3_ Net-_M15-Pad3_ eSim_MOS_N +M16 Net-_M15-Pad3_ Net-_M11-Pad2_ Net-_M16-Pad3_ Net-_M16-Pad3_ eSim_MOS_N +M17 Net-_M16-Pad3_ /i1_1 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M26 Net-_M18-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M25 Net-_M18-Pad2_ /s /vcc /vcc eSim_MOS_P +M33 Net-_M11-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M34 Net-_M11-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M6 Net-_M13-Pad1_ /i0_2 /vcc /vcc eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ /vcc /vcc eSim_MOS_P +M23 Net-_M13-Pad1_ Net-_M23-Pad2_ /vcc /vcc eSim_MOS_P +M7 /y2_bar /i1_2 Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M14 /y2_bar Net-_M13-Pad2_ Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M24 /y2_bar /s Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P +M8 /y2_bar Net-_M23-Pad2_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_N +M9 Net-_M8-Pad3_ Net-_M13-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N +M10 Net-_M10-Pad1_ /i0_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M20 /y2_bar /s Net-_M20-Pad3_ Net-_M20-Pad3_ eSim_MOS_N +M21 Net-_M20-Pad3_ Net-_M13-Pad2_ Net-_M21-Pad3_ Net-_M21-Pad3_ eSim_MOS_N +M22 Net-_M21-Pad3_ /i1_2 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M30 Net-_M23-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M29 Net-_M23-Pad2_ /s /vcc /vcc eSim_MOS_P +M35 Net-_M13-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M36 Net-_M13-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M37 Net-_M37-Pad1_ /i0_4 /vcc /vcc eSim_MOS_P +M42 Net-_M37-Pad1_ Net-_M40-Pad2_ /vcc /vcc eSim_MOS_P +M47 Net-_M37-Pad1_ Net-_M39-Pad2_ /vcc /vcc eSim_MOS_P +M38 /y4_bar /i1_4 Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M43 /y4_bar Net-_M40-Pad2_ Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M48 /y4_bar /s Net-_M37-Pad1_ Net-_M37-Pad1_ eSim_MOS_P +M39 /y4_bar Net-_M39-Pad2_ Net-_M39-Pad3_ Net-_M39-Pad3_ eSim_MOS_N +M40 Net-_M39-Pad3_ Net-_M40-Pad2_ Net-_M40-Pad3_ Net-_M40-Pad3_ eSim_MOS_N +M41 Net-_M40-Pad3_ /i0_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M44 /y4_bar /s Net-_M44-Pad3_ Net-_M44-Pad3_ eSim_MOS_N +M45 Net-_M44-Pad3_ Net-_M40-Pad2_ Net-_M45-Pad3_ Net-_M45-Pad3_ eSim_MOS_N +M46 Net-_M45-Pad3_ /i1_4 Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M50 Net-_M39-Pad2_ /s Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +M49 Net-_M39-Pad2_ /s /vcc /vcc eSim_MOS_P +M53 Net-_M40-Pad2_ /enable_bar /vcc /vcc eSim_MOS_P +M54 Net-_M40-Pad2_ /enable_bar Net-_M10-Pad3_ Net-_M10-Pad3_ eSim_MOS_N +U1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar Net-_M10-Pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc PORT + +.end diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir.out b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir.out new file mode 100644 index 00000000..1f4b4837 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.cir.out @@ -0,0 +1,78 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* u1 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157.pro b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sch b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sch new file mode 100644 index 00000000..1e92f660 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sch @@ -0,0 +1,1721 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD54_157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M55 +U 1 1 62A758F3 +P 6850 1300 +F 0 "M55" H 6800 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 6900 1450 50 0000 R CNN +F 2 "" H 7100 1400 29 0000 C CNN +F 3 "" H 6900 1300 60 0000 C CNN + 1 6850 1300 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M60 +U 1 1 62A758F4 +P 7700 1300 +F 0 "M60" H 7650 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 7750 1450 50 0000 R CNN +F 2 "" H 7950 1400 29 0000 C CNN +F 3 "" H 7750 1300 60 0000 C CNN + 1 7700 1300 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M65 +U 1 1 62A758F5 +P 8350 1300 +F 0 "M65" H 8300 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 8400 1450 50 0000 R CNN +F 2 "" H 8600 1400 29 0000 C CNN +F 3 "" H 8400 1300 60 0000 C CNN + 1 8350 1300 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M56 +U 1 1 62A758F6 +P 6850 1850 +F 0 "M56" H 6800 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 6900 2000 50 0000 R CNN +F 2 "" H 7100 1950 29 0000 C CNN +F 3 "" H 6900 1850 60 0000 C CNN + 1 6850 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M61 +U 1 1 62A758F7 +P 7700 1850 +F 0 "M61" H 7650 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 7750 2000 50 0000 R CNN +F 2 "" H 7950 1950 29 0000 C CNN +F 3 "" H 7750 1850 60 0000 C CNN + 1 7700 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M66 +U 1 1 62A758F8 +P 8350 1850 +F 0 "M66" H 8300 1900 50 0000 R CNN +F 1 "eSim_MOS_P" H 8400 2000 50 0000 R CNN +F 2 "" H 8600 1950 29 0000 C CNN +F 3 "" H 8400 1850 60 0000 C CNN + 1 8350 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M57 +U 1 1 62A758F9 +P 7000 2550 +F 0 "M57" H 7000 2400 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 2500 50 0000 R CNN +F 2 "" H 7300 2250 29 0000 C CNN +F 3 "" H 7100 2350 60 0000 C CNN + 1 7000 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M58 +U 1 1 62A758FA +P 7000 3100 +F 0 "M58" H 7000 2950 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 3050 50 0000 R CNN +F 2 "" H 7300 2800 29 0000 C CNN +F 3 "" H 7100 2900 60 0000 C CNN + 1 7000 3100 + 1 0 0 -1 +$EndComp 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9450 1700 +F 0 "M68" H 9450 1550 50 0000 R CNN +F 1 "eSim_MOS_N" H 9550 1650 50 0000 R CNN +F 2 "" H 9750 1400 29 0000 C CNN +F 3 "" H 9550 1500 60 0000 C CNN + 1 9450 1700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M67 +U 1 1 62A75900 +P 9400 1300 +F 0 "M67" H 9350 1350 50 0000 R CNN +F 1 "eSim_MOS_P" H 9450 1450 50 0000 R CNN +F 2 "" H 9650 1400 29 0000 C CNN +F 3 "" H 9450 1300 60 0000 C CNN + 1 9400 1300 + -1 0 0 1 +$EndComp +Text Label 6550 1300 0 60 ~ 0 +i0_3 +Text Label 6450 1850 0 60 ~ 0 +i1_3 +Text Label 11550 1100 0 60 ~ 0 +sel +Text Label 9050 2300 0 60 ~ 0 +y3_bar +$Comp +L eSim_MOS_P M71 +U 1 1 62A7D356 +P 10250 2800 +F 0 "M71" H 10200 2850 50 0000 R CNN +F 1 "eSim_MOS_P" H 10300 2950 50 0000 R CNN +F 2 "" H 10500 2900 29 0000 C CNN +F 3 "" H 10300 2800 60 0000 C CNN + 1 10250 2800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M72 +U 1 1 62A7D35C +P 10300 3150 +F 0 "M72" H 10300 3000 50 0000 R CNN +F 1 "eSim_MOS_N" H 10400 3100 50 0000 R CNN +F 2 "" H 10600 2850 29 0000 C CNN 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62A8A1E2 +P -5200 2300 +F 0 "M5" H -5200 2150 50 0000 R CNN +F 1 "eSim_MOS_N" H -5100 2250 50 0000 R CNN +F 2 "" H -4900 2000 29 0000 C CNN +F 3 "" H -5100 2100 60 0000 C CNN + 1 -5200 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M15 +U 1 1 62A8A1E8 +P -3950 1200 +F 0 "M15" H -3950 1050 50 0000 R CNN +F 1 "eSim_MOS_N" H -3850 1150 50 0000 R CNN +F 2 "" H -3650 900 29 0000 C CNN +F 3 "" H -3850 1000 60 0000 C CNN + 1 -3950 1200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M16 +U 1 1 62A8A1EE +P -3950 1750 +F 0 "M16" H -3950 1600 50 0000 R CNN +F 1 "eSim_MOS_N" H -3850 1700 50 0000 R CNN +F 2 "" H -3650 1450 29 0000 C CNN +F 3 "" H -3850 1550 60 0000 C CNN + 1 -3950 1750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M17 +U 1 1 62A8A1F4 +P -3950 2300 +F 0 "M17" H -3950 2150 50 0000 R CNN +F 1 "eSim_MOS_N" H -3850 2250 50 0000 R CNN +F 2 "" H -3650 2000 29 0000 C CNN +F 3 "" H -3850 2100 60 0000 C CNN + 1 -3950 2300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M26 +U 1 1 62A8A1FA +P -2750 350 +F 0 "M26" H -2750 200 50 0000 R CNN +F 1 "eSim_MOS_N" H -2650 300 50 0000 R CNN +F 2 "" H -2450 50 29 0000 C CNN +F 3 "" H -2650 150 60 0000 C CNN + 1 -2750 350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M25 +U 1 1 62A8A200 +P -2800 -50 +F 0 "M25" H -2850 0 50 0000 R CNN +F 1 "eSim_MOS_P" H -2750 100 50 0000 R CNN +F 2 "" H -2550 50 29 0000 C CNN +F 3 "" H -2750 -50 60 0000 C CNN + 1 -2800 -50 + -1 0 0 1 +$EndComp +Text Label -5650 -50 0 60 ~ 0 +i0_1 +Text Label -5750 500 0 60 ~ 0 +i1_1 +Text Label -2350 250 0 60 ~ 0 +s +Text Label -8300 100 0 60 ~ 0 +vcc +Text Label -3000 950 2 60 ~ 0 +y1_bar +$Comp +L eSim_MOS_P M33 +U 1 1 62A8A287 +P -1950 1450 +F 0 "M33" H -2000 1500 50 0000 R CNN +F 1 "eSim_MOS_P" H -1900 1600 50 0000 R CNN +F 2 "" H -1700 1550 29 0000 C CNN +F 3 "" H -1900 1450 60 0000 C CNN + 1 -1950 1450 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M34 +U 1 1 62A8A28D +P -1900 1800 +F 0 "M34" H -1900 1650 50 0000 R CNN +F 1 "eSim_MOS_N" H -1800 1750 50 0000 R CNN +F 2 "" H -1600 1500 29 0000 C CNN +F 3 "" H -1800 1600 60 0000 C CNN + 1 -1900 1800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62A8A727 +P -5200 4400 +F 0 "M6" H -5250 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H -5150 4550 50 0000 R CNN +F 2 "" H -4950 4500 29 0000 C CNN +F 3 "" H -5150 4400 60 0000 C CNN + 1 -5200 4400 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M13 +U 1 1 62A8A72D +P -4350 4400 +F 0 "M13" H -4400 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H -4300 4550 50 0000 R CNN +F 2 "" H -4100 4500 29 0000 C CNN +F 3 "" H -4300 4400 60 0000 C CNN + 1 -4350 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M23 +U 1 1 62A8A733 +P -3700 4400 +F 0 "M23" H -3750 4450 50 0000 R CNN +F 1 "eSim_MOS_P" H -3650 4550 50 0000 R CNN +F 2 "" H -3450 4500 29 0000 C CNN +F 3 "" H -3650 4400 60 0000 C CNN + 1 -3700 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 62A8A739 +P -5200 4950 +F 0 "M7" H -5250 5000 50 0000 R CNN +F 1 "eSim_MOS_P" H -5150 5100 50 0000 R CNN +F 2 "" H -4950 5050 29 0000 C CNN +F 3 "" H -5150 4950 60 0000 C CNN + 1 -5200 4950 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 62A8A73F +P -4350 4950 +F 0 "M14" H -4400 5000 50 0000 R CNN +F 1 "eSim_MOS_P" H -4300 5100 50 0000 R CNN +F 2 "" H -4100 5050 29 0000 C CNN +F 3 "" H -4300 4950 60 0000 C CNN + 1 -4350 4950 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_P M24 +U 1 1 62A8A745 +P -3700 4950 +F 0 "M24" H -3750 5000 50 0000 R CNN +F 1 "eSim_MOS_P" H -3650 5100 50 0000 R CNN +F 2 "" H -3450 5050 29 0000 C CNN +F 3 "" H -3650 4950 60 0000 C CNN + 1 -3700 4950 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M8 +U 1 1 62A8A74B +P -5050 5650 +F 0 "M8" H -5050 5500 50 0000 R CNN +F 1 "eSim_MOS_N" H -4950 5600 50 0000 R CNN +F 2 "" H -4750 5350 29 0000 C CNN +F 3 "" H -4950 5450 60 0000 C CNN + 1 -5050 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 62A8A751 +P -5050 6200 +F 0 "M9" H -5050 6050 50 0000 R CNN +F 1 "eSim_MOS_N" H -4950 6150 50 0000 R CNN +F 2 "" H -4750 5900 29 0000 C CNN +F 3 "" H -4950 6000 60 0000 C CNN + 1 -5050 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 62A8A757 +P -5050 6750 +F 0 "M10" H -5050 6600 50 0000 R CNN +F 1 "eSim_MOS_N" H -4950 6700 50 0000 R CNN +F 2 "" H -4750 6450 29 0000 C CNN +F 3 "" H -4950 6550 60 0000 C CNN + 1 -5050 6750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M20 +U 1 1 62A8A75D +P -3800 5650 +F 0 "M20" H -3800 5500 50 0000 R CNN +F 1 "eSim_MOS_N" H -3700 5600 50 0000 R CNN +F 2 "" H -3500 5350 29 0000 C CNN +F 3 "" H -3700 5450 60 0000 C CNN + 1 -3800 5650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M21 +U 1 1 62A8A763 +P -3800 6200 +F 0 "M21" H -3800 6050 50 0000 R CNN +F 1 "eSim_MOS_N" H -3700 6150 50 0000 R CNN +F 2 "" H -3500 5900 29 0000 C CNN +F 3 "" H -3700 6000 60 0000 C CNN + 1 -3800 6200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M22 +U 1 1 62A8A769 +P -3800 6750 +F 0 "M22" H -3800 6600 50 0000 R CNN +F 1 "eSim_MOS_N" H -3700 6700 50 0000 R CNN +F 2 "" H -3500 6450 29 0000 C CNN +F 3 "" H -3700 6550 60 0000 C CNN + 1 -3800 6750 + -1 0 0 -1 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PORT U1 +U 8 1 62ABD427 +P -1950 7750 +F 0 "U1" H -1900 7850 30 0000 C CNN +F 1 "PORT" H -1950 7750 30 0000 C CNN +F 2 "" H -1950 7750 60 0000 C CNN +F 3 "" H -1950 7750 60 0000 C CNN + 8 -1950 7750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62AC19FC +P 5400 4850 +F 0 "U1" H 5450 4950 30 0000 C CNN +F 1 "PORT" H 5400 4850 30 0000 C CNN +F 2 "" H 5400 4850 60 0000 C CNN +F 3 "" H 5400 4850 60 0000 C CNN + 9 5400 4850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62AC2D09 +P 1100 4400 +F 0 "U1" H 1150 4500 30 0000 C CNN +F 1 "PORT" H 1100 4400 30 0000 C CNN +F 2 "" H 1100 4400 60 0000 C CNN +F 3 "" H 1100 4400 60 0000 C CNN + 10 1100 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62AC2E02 +P 1100 3850 +F 0 "U1" H 1150 3950 30 0000 C CNN +F 1 "PORT" H 1100 3850 30 0000 C CNN +F 2 "" H 1100 3850 60 0000 C CNN +F 3 "" H 1100 3850 60 0000 C CNN + 11 1100 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62AC91B4 +P 9650 2300 +F 0 "U1" H 9700 2400 30 0000 C CNN +F 1 "PORT" H 9650 2300 30 0000 C CNN +F 2 "" H 9650 2300 60 0000 C CNN +F 3 "" H 9650 2300 60 0000 C CNN + 12 9650 2300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62ACABE8 +P 3600 1850 +F 0 "U1" H 3650 1950 30 0000 C CNN +F 1 "PORT" H 3600 1850 30 0000 C CNN +F 2 "" H 3600 1850 60 0000 C CNN +F 3 "" H 3600 1850 60 0000 C CNN + 13 3600 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62ACACE3 +P 3600 1300 +F 0 "U1" H 3650 1400 30 0000 C CNN +F 1 "PORT" H 3600 1300 30 0000 C CNN +F 2 "" H 3600 1300 60 0000 C CNN +F 3 "" H 3600 1300 60 0000 C CNN + 14 3600 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62ACADBC +P 12300 4450 +F 0 "U1" H 12350 4550 30 0000 C CNN +F 1 "PORT" H 12300 4450 30 0000 C CNN +F 2 "" H 12300 4450 60 0000 C CNN +F 3 "" H 12300 4450 60 0000 C CNN + 15 12300 4450 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62AD09D5 +P -8850 100 +F 0 "U1" H -8800 200 30 0000 C CNN +F 1 "PORT" H -8850 100 30 0000 C CNN +F 2 "" H -8850 100 60 0000 C CNN +F 3 "" H -8850 100 60 0000 C CNN + 16 -8850 100 + 1 0 0 -1 +$EndComp +Connection ~ -2100 1700 +Connection ~ -4300 1700 +Wire Wire Line + -4300 1700 -2100 1700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sub b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sub new file mode 100644 index 00000000..9d85337b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157.sub @@ -0,0 +1,72 @@ +* Subcircuit CD54_157 +.subckt CD54_157 /s /i0_1 /i1_1 /y1_bar /i0_2 /i1_2 /y2_bar net-_m10-pad3_ /y4_bar /i1_4 /i0_4 /y3_bar /i1_3 /i0_3 /enable_bar /vcc +* c:\fossee\esim\library\subcircuitlibrary\cd54_157\cd54_157.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m55 net-_m55-pad1_ /i0_3 /vcc /vcc CMOSP W=100u L=100u M=1 +m60 net-_m55-pad1_ net-_m58-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m65 net-_m55-pad1_ net-_m57-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m56 /y3_bar /i1_3 net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m61 /y3_bar net-_m58-pad2_ net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m66 /y3_bar /s net-_m55-pad1_ net-_m55-pad1_ CMOSP W=100u L=100u M=1 +m57 /y3_bar net-_m57-pad2_ net-_m57-pad3_ net-_m57-pad3_ CMOSN W=100u L=100u M=1 +m58 net-_m57-pad3_ net-_m58-pad2_ net-_m58-pad3_ net-_m58-pad3_ CMOSN W=100u L=100u M=1 +m59 net-_m58-pad3_ /i0_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m62 /y3_bar /s net-_m62-pad3_ net-_m62-pad3_ CMOSN W=100u L=100u M=1 +m63 net-_m62-pad3_ net-_m58-pad2_ net-_m63-pad3_ net-_m63-pad3_ CMOSN W=100u L=100u M=1 +m64 net-_m63-pad3_ /i1_3 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m68 net-_m57-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m67 net-_m57-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m71 net-_m58-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m72 net-_m58-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ /i0_1 /vcc /vcc CMOSP W=100u L=100u M=1 +m11 net-_m1-pad1_ net-_m11-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m18 net-_m1-pad1_ net-_m18-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m2 /y1_bar /i1_1 net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m12 /y1_bar net-_m11-pad2_ net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m19 /y1_bar /s net-_m1-pad1_ net-_m1-pad1_ CMOSP W=100u L=100u M=1 +m3 /y1_bar net-_m18-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m3-pad3_ net-_m11-pad2_ net-_m4-pad3_ net-_m4-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m4-pad3_ /i0_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m15 /y1_bar /s net-_m15-pad3_ net-_m15-pad3_ CMOSN W=100u L=100u M=1 +m16 net-_m15-pad3_ net-_m11-pad2_ net-_m16-pad3_ net-_m16-pad3_ CMOSN W=100u L=100u M=1 +m17 net-_m16-pad3_ /i1_1 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m26 net-_m18-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m25 net-_m18-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m33 net-_m11-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m34 net-_m11-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m13-pad1_ /i0_2 /vcc /vcc CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m23 net-_m13-pad1_ net-_m23-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m7 /y2_bar /i1_2 net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m14 /y2_bar net-_m13-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m24 /y2_bar /s net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1 +m8 /y2_bar net-_m23-pad2_ net-_m8-pad3_ net-_m8-pad3_ CMOSN W=100u L=100u M=1 +m9 net-_m8-pad3_ net-_m13-pad2_ net-_m10-pad1_ net-_m10-pad1_ CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ /i0_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m20 /y2_bar /s net-_m20-pad3_ net-_m20-pad3_ CMOSN W=100u L=100u M=1 +m21 net-_m20-pad3_ net-_m13-pad2_ net-_m21-pad3_ net-_m21-pad3_ CMOSN W=100u L=100u M=1 +m22 net-_m21-pad3_ /i1_2 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m30 net-_m23-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m29 net-_m23-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m35 net-_m13-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m36 net-_m13-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m37 net-_m37-pad1_ /i0_4 /vcc /vcc CMOSP W=100u L=100u M=1 +m42 net-_m37-pad1_ net-_m40-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m47 net-_m37-pad1_ net-_m39-pad2_ /vcc /vcc CMOSP W=100u L=100u M=1 +m38 /y4_bar /i1_4 net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m43 /y4_bar net-_m40-pad2_ net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m48 /y4_bar /s net-_m37-pad1_ net-_m37-pad1_ CMOSP W=100u L=100u M=1 +m39 /y4_bar net-_m39-pad2_ net-_m39-pad3_ net-_m39-pad3_ CMOSN W=100u L=100u M=1 +m40 net-_m39-pad3_ net-_m40-pad2_ net-_m40-pad3_ net-_m40-pad3_ CMOSN W=100u L=100u M=1 +m41 net-_m40-pad3_ /i0_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m44 /y4_bar /s net-_m44-pad3_ net-_m44-pad3_ CMOSN W=100u L=100u M=1 +m45 net-_m44-pad3_ net-_m40-pad2_ net-_m45-pad3_ net-_m45-pad3_ CMOSN W=100u L=100u M=1 +m46 net-_m45-pad3_ /i1_4 net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m50 net-_m39-pad2_ /s net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +m49 net-_m39-pad2_ /s /vcc /vcc CMOSP W=100u L=100u M=1 +m53 net-_m40-pad2_ /enable_bar /vcc /vcc CMOSP W=100u L=100u M=1 +m54 net-_m40-pad2_ /enable_bar net-_m10-pad3_ net-_m10-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD54_157 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_157_Previous_Values.xml b/library/SubcircuitLibrary/CD54_HC_151/CD54_157_Previous_Values.xml new file mode 100644 index 00000000..850ea0ff --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_157_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151-cache.lib b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151-cache.lib new file mode 100644 index 00000000..645582cd --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CD_54157 +# +DEF CD_54157 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "CD_54157" 0 -250 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -600 0 1 0 N +X Sel 1 -550 150 200 R 50 50 1 1 I +X I0_1 2 -550 50 200 R 50 50 1 1 I +X I1_1 3 -550 -50 200 R 50 50 1 1 I +X Y1_bar 4 -550 -150 200 R 50 50 1 1 O +X I0_2 5 -550 -250 200 R 50 50 1 1 I +X I1_2 6 -550 -350 200 R 50 50 1 1 I +X Y2_bar 7 -550 -450 200 R 50 50 1 1 O +X GND 8 -550 -550 200 R 50 50 1 1 I +X Y3_bar 9 550 -550 200 L 50 50 1 1 O +X I1_3 10 550 -450 200 L 50 50 1 1 I +X I0_3 11 550 -350 200 L 50 50 1 1 I +X Y4_bar 12 550 -250 200 L 50 50 1 1 O +X I1_4 13 550 -150 200 L 50 50 1 1 I +X I0_4 14 550 -50 200 L 50 50 1 1 I +X E_bar 15 550 50 200 L 50 50 1 1 I +X VCC 16 550 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir new file mode 100644 index 00000000..11a9f3b9 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir @@ -0,0 +1,32 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_HC_151\CD54_HC_151.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/28/22 12:24:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_U1-Pad11_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X1 Net-_U1-Pad11_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M4-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X3 Net-_U1-Pad11_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X4 Net-_U1-Pad11_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M3-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X6 Net-_U1-Pad10_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M10-Pad2_ Net-_M3-Pad1_ Net-_M2-Pad1_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X5 Net-_U1-Pad10_ ? ? ? ? ? ? Net-_M1-Pad3_ Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M4-Pad1_ ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +X7 Net-_U1-Pad9_ ? ? ? Net-_M11-Pad1_ Net-_M10-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ ? ? ? ? ? ? Net-_U1-Pad7_ Net-_M11-Pad3_ CD_54157 +M8 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M9 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M12 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M14 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P +M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_M13-Pad2_ Net-_M13-Pad1_ Net-_U1-Pad7_ Net-_M1-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_M11-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir.out b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir.out new file mode 100644 index 00000000..e598a9f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.cir.out @@ -0,0 +1,36 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd54_hc_151\cd54_hc_151.cir + +.include CD54_157.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +x2 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m1-pad2_ net-_u1-pad1_ net-_u1-pad2_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x1 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m4-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x3 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m2-pad2_ net-_u1-pad14_ net-_u1-pad15_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x4 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m3-pad2_ net-_u1-pad12_ net-_u1-pad13_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x6 net-_u1-pad10_ ? ? ? ? ? ? net-_m1-pad3_ net-_m10-pad2_ net-_m3-pad1_ net-_m2-pad1_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x5 net-_u1-pad10_ ? ? ? ? ? ? net-_m1-pad3_ net-_m11-pad2_ net-_m1-pad1_ net-_m4-pad1_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x7 net-_u1-pad9_ ? ? ? net-_m11-pad1_ net-_m10-pad1_ net-_m13-pad2_ net-_m1-pad3_ ? ? ? ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_m13-pad2_ net-_m13-pad1_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_m11-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.pro b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sch b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sch new file mode 100644 index 00000000..15f83455 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sch @@ -0,0 +1,893 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD54HC151-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CD_54157 X2 +U 1 1 62BAA15B +P 3200 3150 +F 0 "X2" H 3200 3200 60 0000 C CNN +F 1 "CD_54157" V 3200 2900 60 0000 C CNN +F 2 "" H 3200 3150 60 0001 C CNN +F 3 "" H 3200 3150 60 0001 C CNN + 1 3200 3150 + 1 0 0 -1 +$EndComp +$Comp +L CD_54157 X1 +U 1 1 62BAA15C +P 3200 1900 +F 0 "X1" H 3200 1950 60 0000 C CNN +F 1 "CD_54157" V 3200 1650 60 0000 C CNN +F 2 "" H 3200 1900 60 0001 C CNN +F 3 "" H 3200 1900 60 0001 C CNN + 1 3200 1900 + 1 0 0 -1 +$EndComp +$Comp +L CD_54157 X3 +U 1 1 62BAA15D +P 3200 4450 +F 0 "X3" H 3200 4500 60 0000 C CNN +F 1 "CD_54157" V 3200 4200 60 0000 C CNN +F 2 "" H 3200 4450 60 0001 C CNN +F 3 "" H 3200 4450 60 0001 C CNN + 1 3200 4450 + 1 0 0 -1 +$EndComp +NoConn ~ 2650 4400 +NoConn ~ 2650 4500 +NoConn ~ 2650 4600 +$Comp +L CD_54157 X4 +U 1 1 62BAA15E +P 3200 5750 +F 0 "X4" H 3200 5800 60 0000 C CNN +F 1 "CD_54157" V 3200 5500 60 0000 C CNN +F 2 "" H 3200 5750 60 0001 C CNN +F 3 "" H 3200 5750 60 0001 C CNN + 1 3200 5750 + 1 0 0 -1 +$EndComp +NoConn ~ 2650 5800 +NoConn ~ 2650 5900 +NoConn ~ 2650 6000 +NoConn ~ 3750 6000 +$Comp +L CD_54157 X6 +U 1 1 62BAA15F +P 5750 4550 +F 0 "X6" H 5750 4600 60 0000 C CNN +F 1 "CD_54157" V 5750 4300 60 0000 C CNN +F 2 "" H 5750 4550 60 0001 C CNN +F 3 "" H 5750 4550 60 0001 C CNN + 1 5750 4550 + 1 0 0 -1 +$EndComp +$Comp +L CD_54157 X5 +U 1 1 62BAA160 +P 5750 3300 +F 0 "X5" H 5750 3350 60 0000 C CNN +F 1 "CD_54157" V 5750 3050 60 0000 C CNN +F 2 "" H 5750 3300 60 0001 C CNN +F 3 "" H 5750 3300 60 0001 C CNN + 1 5750 3300 + 1 0 0 -1 +$EndComp +$Comp +L CD_54157 X7 +U 1 1 62BAA161 +P 8550 3900 +F 0 "X7" H 8550 3950 60 0000 C CNN +F 1 "CD_54157" V 8550 3650 60 0000 C CNN +F 2 "" H 8550 3900 60 0001 C CNN +F 3 "" H 8550 3900 60 0001 C CNN + 1 8550 3900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 62BAA162 +P 4550 2450 +F 0 "M8" H 4500 2500 50 0000 R CNN +F 1 "eSim_MOS_P" H 4600 2600 50 0000 R CNN +F 2 "" H 4800 2550 29 0000 C CNN +F 3 "" H 4600 2450 60 0000 C CNN + 1 4550 2450 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 62BAA163 +P 4500 2750 +F 0 "M4" H 4500 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 4600 2700 50 0000 R CNN +F 2 "" H 4800 2450 29 0000 C CNN +F 3 "" H 4600 2550 60 0000 C CNN + 1 4500 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 62BAA164 +P 4500 3550 +F 0 "M5" H 4450 3600 50 0000 R CNN +F 1 "eSim_MOS_P" H 4550 3700 50 0000 R CNN +F 2 "" H 4750 3650 29 0000 C CNN +F 3 "" H 4550 3550 60 0000 C CNN + 1 4500 3550 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62BAA165 +P 4450 3850 +F 0 "M1" H 4450 3700 50 0000 R CNN +F 1 "eSim_MOS_N" H 4550 3800 50 0000 R CNN +F 2 "" H 4750 3550 29 0000 C CNN +F 3 "" H 4550 3650 60 0000 C CNN + 1 4450 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62BAA166 +P 4500 4900 +F 0 "M6" H 4450 4950 50 0000 R CNN +F 1 "eSim_MOS_P" H 4550 5050 50 0000 R CNN +F 2 "" H 4750 5000 29 0000 C CNN +F 3 "" H 4550 4900 60 0000 C CNN + 1 4500 4900 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62BAA167 +P 4450 5200 +F 0 "M2" H 4450 5050 50 0000 R CNN +F 1 "eSim_MOS_N" H 4550 5150 50 0000 R CNN +F 2 "" H 4750 4900 29 0000 C CNN +F 3 "" H 4550 5000 60 0000 C CNN + 1 4450 5200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 62BAA168 +P 4500 6000 +F 0 "M7" H 4450 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 4550 6150 50 0000 R CNN +F 2 "" H 4750 6100 29 0000 C CNN +F 3 "" H 4550 6000 60 0000 C CNN + 1 4500 6000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 62BAA169 +P 4450 6300 +F 0 "M3" H 4450 6150 50 0000 R CNN +F 1 "eSim_MOS_N" H 4550 6250 50 0000 R CNN +F 2 "" H 4750 6000 29 0000 C CNN +F 3 "" H 4550 6100 60 0000 C CNN + 1 4450 6300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M11 +U 1 1 62BAA16A +P 7050 3750 +F 0 "M11" H 7000 3800 50 0000 R CNN +F 1 "eSim_MOS_P" H 7100 3900 50 0000 R CNN +F 2 "" H 7300 3850 29 0000 C CNN +F 3 "" H 7100 3750 60 0000 C CNN + 1 7050 3750 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M9 +U 1 1 62BAA16B +P 7000 4050 +F 0 "M9" H 7000 3900 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 4000 50 0000 R CNN +F 2 "" H 7300 3750 29 0000 C CNN +F 3 "" H 7100 3850 60 0000 C CNN + 1 7000 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M12 +U 1 1 62BAA16C +P 7050 5000 +F 0 "M12" H 7000 5050 50 0000 R CNN +F 1 "eSim_MOS_P" H 7100 5150 50 0000 R CNN +F 2 "" H 7300 5100 29 0000 C CNN +F 3 "" H 7100 5000 60 0000 C CNN + 1 7050 5000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M10 +U 1 1 62BAA16D +P 7000 5300 +F 0 "M10" H 7000 5150 50 0000 R CNN +F 1 "eSim_MOS_N" H 7100 5250 50 0000 R CNN +F 2 "" H 7300 5000 29 0000 C CNN +F 3 "" H 7100 5100 60 0000 C CNN + 1 7000 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M14 +U 1 1 62BAA16E +P 8750 5150 +F 0 "M14" H 8700 5200 50 0000 R CNN +F 1 "eSim_MOS_P" H 8800 5300 50 0000 R CNN +F 2 "" H 9000 5250 29 0000 C CNN +F 3 "" H 8800 5150 60 0000 C CNN + 1 8750 5150 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M13 +U 1 1 62BAA16F +P 8700 5450 +F 0 "M13" H 8700 5300 50 0000 R CNN +F 1 "eSim_MOS_N" H 8800 5400 50 0000 R CNN +F 2 "" H 9000 5150 29 0000 C CNN +F 3 "" H 8800 5250 60 0000 C CNN + 1 8700 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 2450 4400 2950 +Wire Wire Line + 4700 2250 9100 2250 +Wire Wire Line + 4800 2250 4800 2300 +Wire Wire Line + 4800 3150 4800 3100 +Wire Wire Line + 4700 3150 4800 3150 +Wire Wire Line + 4700 2650 4700 2750 +Wire Wire Line + 4350 3550 4350 4050 +Wire Wire Line + 5000 3350 4650 3350 +Wire Wire Line + 4750 3350 4750 3400 +Wire Wire Line + 4750 4200 4750 4250 +Wire Wire Line + 4650 4250 4850 4250 +Wire Wire Line + 4650 3750 4650 3850 +Wire Wire Line + 4350 4900 4350 5400 +Wire Wire Line + 5000 4700 4650 4700 +Wire Wire Line + 4750 4700 4750 4750 +Wire Wire Line + 4750 5550 4750 5600 +Wire Wire Line + 4850 5600 4650 5600 +Wire Wire Line + 4650 5100 4650 5200 +Wire Wire Line + 4350 6000 4350 6500 +Wire Wire Line + 5000 5800 4650 5800 +Wire Wire Line + 4750 5800 4750 5850 +Wire Wire Line + 4750 6650 4750 6700 +Wire Wire Line + 2550 6700 8950 6700 +Wire Wire Line + 4650 6200 4650 6300 +Wire Wire Line + 3750 2450 4050 2450 +Wire Wire Line + 4050 2450 4050 2650 +Wire Wire Line + 4050 2650 4400 2650 +Connection ~ 4400 2650 +Wire Wire Line + 3750 3700 4350 3700 +Connection ~ 4350 3700 +Wire Wire Line + 4700 2700 6450 2700 +Wire Wire Line + 6450 2700 6450 3650 +Wire Wire Line + 6450 3650 6300 3650 +Connection ~ 4700 2700 +Wire Wire Line + 4650 3800 4950 3800 +Wire Wire Line + 4950 3800 4950 2750 +Wire Wire Line + 4950 2750 6500 2750 +Wire Wire Line + 6500 2750 6500 3750 +Wire Wire Line + 6500 3750 6300 3750 +Connection ~ 4650 3800 +Wire Wire Line + 3750 5000 4350 5000 +Connection ~ 4350 5000 +Wire Wire Line + 4650 5150 4900 5150 +Wire Wire Line + 4900 5150 4900 4250 +Wire Wire Line + 4900 4250 6500 4250 +Wire Wire Line + 6500 4250 6500 4900 +Wire Wire Line + 6500 4900 6300 4900 +Connection ~ 4650 5150 +Wire Wire Line + 3750 6300 4350 6300 +Connection ~ 4350 6300 +Wire Wire Line + 4650 6250 6550 6250 +Wire Wire Line + 6550 6250 6550 5000 +Wire Wire Line + 6550 5000 6300 5000 +Connection ~ 4650 6250 +Wire Wire Line + 6900 3750 6900 4250 +Wire Wire Line + 7200 3550 7300 3550 +Wire Wire Line + 7300 3550 7300 3600 +Wire Wire Line + 7300 4400 7300 4450 +Wire Wire Line + 7200 4450 7450 4450 +Wire Wire Line + 7200 3950 7200 4050 +Wire Wire Line + 6300 3850 6900 3850 +Connection ~ 6900 3850 +Wire Wire Line + 7200 4000 7600 4000 +Connection ~ 7200 4000 +Wire Wire Line + 6900 5000 6900 5500 +Wire Wire Line + 7500 4800 7200 4800 +Wire Wire Line + 7300 4800 7300 4850 +Wire Wire Line + 7300 5650 7300 5700 +Wire Wire Line + 7200 5700 7450 5700 +Wire Wire Line + 7200 5200 7200 5300 +Wire Wire Line + 6300 5100 6900 5100 +Connection ~ 6900 5100 +Wire Wire Line + 7200 5250 7600 5250 +Connection ~ 7200 5250 +Wire Wire Line + 7600 4000 7600 4150 +Wire Wire Line + 7600 4150 8000 4150 +Wire Wire Line + 7600 5250 7600 4250 +Wire Wire Line + 7600 4250 8000 4250 +Wire Wire Line + 8000 4350 7700 4350 +Wire Wire Line + 7700 4350 7700 5250 +Wire Wire Line + 7700 4800 9550 4800 +Wire Wire Line + 4750 3150 4750 3250 +Wire Wire Line + 4750 3250 4850 3250 +Wire Wire Line + 4850 3250 4850 6700 +Connection ~ 4750 4250 +Connection ~ 4750 3150 +Connection ~ 4750 5600 +Connection ~ 4850 4250 +Connection ~ 4750 6700 +Connection ~ 4850 5600 +Wire Wire Line + 7450 5700 7450 4450 +Connection ~ 7300 5700 +Connection ~ 7300 4450 +Wire Wire Line + 7350 6700 7350 5700 +Connection ~ 4850 6700 +Connection ~ 7350 5700 +Wire Wire Line + 7250 3550 7250 3450 +Wire Wire Line + 7250 3450 7500 3450 +Wire Wire Line + 7500 2250 7500 4850 +Connection ~ 7300 4800 +Connection ~ 7250 3550 +Wire Wire Line + 5000 1750 5000 5800 +Connection ~ 4750 3350 +Connection ~ 4750 4700 +Connection ~ 4750 5800 +Connection ~ 5000 4700 +Connection ~ 4800 2250 +Connection ~ 5000 3350 +Connection ~ 5000 2250 +Connection ~ 7500 3450 +Wire Wire Line + 3750 3000 3950 3000 +Wire Wire Line + 3950 1750 3950 5600 +Wire Wire Line + 3750 1750 6300 1750 +Wire Wire Line + 3950 4300 3750 4300 +Connection ~ 3950 3000 +Wire Wire Line + 3950 5600 3750 5600 +Connection ~ 3950 4300 +Wire Wire Line + 6300 900 6300 3150 +Connection ~ 3950 1750 +Wire Wire Line + 6300 4400 6600 4400 +Wire Wire Line + 6600 4400 6600 3150 +Wire Wire Line + 6600 3150 6300 3150 +Connection ~ 5000 1750 +Wire Wire Line + 3750 3100 3850 3100 +Wire Wire Line + 3850 1850 3850 5700 +Wire Wire Line + 3750 1850 6700 1850 +Wire Wire Line + 3850 4400 3750 4400 +Connection ~ 3850 3100 +Wire Wire Line + 3850 5700 3750 5700 +Connection ~ 3850 4400 +Wire Wire Line + 6700 1150 6700 4500 +Wire Wire Line + 6300 3250 9200 3250 +Connection ~ 3850 1850 +Wire Wire Line + 6700 4500 6300 4500 +Connection ~ 6700 3250 +Wire Wire Line + 9100 2250 9100 3750 +Connection ~ 7500 2250 +Wire Wire Line + 9100 3850 9200 3850 +Wire Wire Line + 9200 3850 9200 3250 +Wire Wire Line + 2650 3000 2500 3000 +Wire Wire Line + 2500 1750 2500 5600 +Wire Wire Line + 2050 1750 2650 1750 +Wire Wire Line + 2500 4300 2650 4300 +Connection ~ 2500 3000 +Wire Wire Line + 2500 5600 2650 5600 +Connection ~ 2500 4300 +Wire Wire Line + 3750 2250 3800 2250 +Wire Wire Line + 3800 2250 3800 2550 +Wire Wire Line + 3800 2550 2050 2550 +Wire Wire Line + 3750 2350 3750 2800 +Wire Wire Line + 3750 2800 2050 2800 +Wire Wire Line + 3750 3500 3800 3500 +Wire Wire Line + 3800 3500 3800 3900 +Wire Wire Line + 3800 3900 2100 3900 +Wire Wire Line + 3750 3600 3750 4100 +Wire Wire Line + 3750 4100 2100 4100 +Wire Wire Line + 3750 4800 3800 4800 +Wire Wire Line + 3800 4800 3800 5100 +Wire Wire Line + 3800 5100 2150 5100 +Wire Wire Line + 3750 4900 3750 5300 +Wire Wire Line + 3750 5300 2150 5300 +Wire Wire Line + 3750 6100 3900 6100 +Wire Wire Line + 3900 6100 3900 6450 +Wire Wire Line + 3900 6450 2200 6450 +Wire Wire Line + 3750 6200 3750 6650 +Wire Wire Line + 3750 6650 2200 6650 +Wire Wire Line + 7700 5250 8600 5250 +Connection ~ 7700 4800 +Wire Wire Line + 8600 5150 8600 5650 +Wire Wire Line + 8900 4950 9000 4950 +Wire Wire Line + 9000 4950 9000 5000 +Wire Wire Line + 9000 5800 9000 5850 +Wire Wire Line + 9000 5850 8900 5850 +Wire Wire Line + 8900 5350 8900 5450 +Connection ~ 8600 5250 +Wire Wire Line + 8900 5400 9550 5400 +Connection ~ 8900 5400 +Wire Wire Line + 8950 4950 8950 4850 +Connection ~ 8950 4950 +Wire Wire Line + 8950 4850 7500 4850 +Connection ~ 7500 4800 +Wire Wire Line + 8950 6700 8950 5850 +Connection ~ 7350 6700 +Connection ~ 8950 5850 +Wire Wire Line + 5100 4400 5200 4400 +Wire Wire Line + 5100 1550 5100 4400 +Wire Wire Line + 5100 3150 5200 3150 +Wire Wire Line + 8000 3750 8000 1350 +Wire Wire Line + 8000 1350 2050 1350 +Connection ~ 2500 1750 +Wire Wire Line + 5100 1550 2050 1550 +Connection ~ 5100 3150 +NoConn ~ 2650 1850 +NoConn ~ 2650 1950 +NoConn ~ 2650 2050 +NoConn ~ 2650 2150 +NoConn ~ 2650 2250 +NoConn ~ 2650 2350 +NoConn ~ 3750 1950 +NoConn ~ 3750 2050 +NoConn ~ 3750 2150 +NoConn ~ 6300 3350 +NoConn ~ 6300 3450 +NoConn ~ 6300 3550 +NoConn ~ 5200 3250 +NoConn ~ 5200 3350 +NoConn ~ 5200 3450 +NoConn ~ 5200 3550 +NoConn ~ 5200 3650 +NoConn ~ 5200 3750 +NoConn ~ 5200 4500 +NoConn ~ 5200 4600 +NoConn ~ 5200 4700 +NoConn ~ 5200 4800 +NoConn ~ 5200 4900 +NoConn ~ 5200 5000 +NoConn ~ 2650 4700 +NoConn ~ 2650 4800 +NoConn ~ 2650 4900 +NoConn ~ 2650 3600 +NoConn ~ 2650 3500 +NoConn ~ 2650 3400 +NoConn ~ 2650 3300 +NoConn ~ 2650 3200 +NoConn ~ 2650 3100 +NoConn ~ 2650 6100 +NoConn ~ 2650 6200 +NoConn ~ 2650 5700 +NoConn ~ 8000 3850 +NoConn ~ 8000 3950 +NoConn ~ 8000 4050 +NoConn ~ 9100 3950 +NoConn ~ 9100 4050 +NoConn ~ 9100 4150 +NoConn ~ 9100 4250 +NoConn ~ 9100 4350 +NoConn ~ 9100 4450 +Wire Wire Line + 2650 2450 2550 2450 +Wire Wire Line + 2550 2450 2550 6950 +Wire Wire Line + 2550 3700 2650 3700 +Wire Wire Line + 2550 5000 2650 5000 +Connection ~ 2550 3700 +Wire Wire Line + 2550 6300 2650 6300 +Connection ~ 2550 5000 +Connection ~ 4650 6700 +Connection ~ 2550 6300 +Wire Wire Line + 5200 3850 5150 3850 +Wire Wire Line + 5150 3850 5150 6700 +Wire Wire Line + 5150 5100 5200 5100 +Connection ~ 5150 6700 +Connection ~ 5150 5100 +Wire Wire Line + 8000 4450 7950 4450 +Wire Wire Line + 7950 4450 7950 6700 +Connection ~ 7950 6700 +Wire Wire Line + 2550 6950 2200 6950 +Connection ~ 2550 6700 +Wire Wire Line + 6300 900 2050 900 +Connection ~ 6300 1750 +$Comp +L PORT U1 +U 1 1 62BAA683 +P 1850 4100 +F 0 "U1" H 1900 4200 30 0000 C CNN +F 1 "PORT" H 1850 4100 30 0000 C CNN +F 2 "" H 1850 4100 60 0000 C CNN +F 3 "" H 1850 4100 60 0000 C CNN + 1 1850 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62BAB5C7 +P 1850 3900 +F 0 "U1" H 1900 4000 30 0000 C CNN +F 1 "PORT" H 1850 3900 30 0000 C CNN +F 2 "" H 1850 3900 60 0000 C CNN +F 3 "" H 1850 3900 60 0000 C CNN + 2 1850 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62BAB6FC +P 1800 2800 +F 0 "U1" H 1850 2900 30 0000 C CNN +F 1 "PORT" H 1800 2800 30 0000 C CNN +F 2 "" H 1800 2800 60 0000 C CNN +F 3 "" H 1800 2800 60 0000 C CNN + 3 1800 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62BAB81F +P 1800 2550 +F 0 "U1" H 1850 2650 30 0000 C CNN +F 1 "PORT" H 1800 2550 30 0000 C CNN +F 2 "" H 1800 2550 60 0000 C CNN +F 3 "" H 1800 2550 60 0000 C CNN + 4 1800 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62BAB9C0 +P 9800 4800 +F 0 "U1" H 9850 4900 30 0000 C CNN +F 1 "PORT" H 9800 4800 30 0000 C CNN +F 2 "" H 9800 4800 60 0000 C CNN +F 3 "" H 9800 4800 60 0000 C CNN + 5 9800 4800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62BABAEF +P 9800 5400 +F 0 "U1" H 9850 5500 30 0000 C CNN +F 1 "PORT" H 9800 5400 30 0000 C CNN +F 2 "" H 9800 5400 60 0000 C CNN +F 3 "" H 9800 5400 60 0000 C CNN + 6 9800 5400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62BABD56 +P 1650 1150 +F 0 "U1" H 1700 1250 30 0000 C CNN +F 1 "PORT" H 1650 1150 30 0000 C CNN +F 2 "" H 1650 1150 60 0000 C CNN +F 3 "" H 1650 1150 60 0000 C CNN + 7 1650 1150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 1150 1900 1150 +Connection ~ 6700 1850 +$Comp +L PORT U1 +U 8 1 62BAC0A7 +P 1950 6950 +F 0 "U1" H 2000 7050 30 0000 C CNN +F 1 "PORT" H 1950 6950 30 0000 C CNN +F 2 "" H 1950 6950 60 0000 C CNN +F 3 "" H 1950 6950 60 0000 C CNN + 8 1950 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62BAC3B0 +P 1800 1350 +F 0 "U1" H 1850 1450 30 0000 C CNN +F 1 "PORT" H 1800 1350 30 0000 C CNN +F 2 "" H 1800 1350 60 0000 C CNN +F 3 "" H 1800 1350 60 0000 C CNN + 9 1800 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62BAC4A9 +P 1800 1550 +F 0 "U1" H 1850 1650 30 0000 C CNN +F 1 "PORT" H 1800 1550 30 0000 C CNN +F 2 "" H 1800 1550 60 0000 C CNN +F 3 "" H 1800 1550 60 0000 C CNN + 10 1800 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62BAC516 +P 1800 1750 +F 0 "U1" H 1850 1850 30 0000 C CNN +F 1 "PORT" H 1800 1750 30 0000 C CNN +F 2 "" H 1800 1750 60 0000 C CNN +F 3 "" H 1800 1750 60 0000 C CNN + 11 1800 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62BAC7C5 +P 1950 6650 +F 0 "U1" H 2000 6750 30 0000 C CNN +F 1 "PORT" H 1950 6650 30 0000 C CNN +F 2 "" H 1950 6650 60 0000 C CNN +F 3 "" H 1950 6650 60 0000 C CNN + 12 1950 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62BAC8FA +P 1950 6450 +F 0 "U1" H 2000 6550 30 0000 C CNN +F 1 "PORT" H 1950 6450 30 0000 C CNN +F 2 "" H 1950 6450 60 0000 C CNN +F 3 "" H 1950 6450 60 0000 C CNN + 13 1950 6450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62BACA31 +P 1900 5300 +F 0 "U1" H 1950 5400 30 0000 C CNN +F 1 "PORT" H 1900 5300 30 0000 C CNN +F 2 "" H 1900 5300 60 0000 C CNN +F 3 "" H 1900 5300 60 0000 C CNN + 14 1900 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62BACB72 +P 1900 5100 +F 0 "U1" H 1950 5200 30 0000 C CNN +F 1 "PORT" H 1900 5100 30 0000 C CNN +F 2 "" H 1900 5100 60 0000 C CNN +F 3 "" H 1900 5100 60 0000 C CNN + 15 1900 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62BACE4B +P 1800 900 +F 0 "U1" H 1850 1000 30 0000 C CNN +F 1 "PORT" H 1800 900 30 0000 C CNN +F 2 "" H 1800 900 60 0000 C CNN +F 3 "" H 1800 900 60 0000 C CNN + 16 1800 900 + 1 0 0 -1 +$EndComp +NoConn ~ 3750 3200 +NoConn ~ 3750 3300 +NoConn ~ 3750 3400 +NoConn ~ 3750 4500 +NoConn ~ 3750 4600 +NoConn ~ 3750 4700 +NoConn ~ 3750 5800 +NoConn ~ 3750 5900 +NoConn ~ 6300 4600 +NoConn ~ 6300 4700 +NoConn ~ 6300 4800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sub b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sub new file mode 100644 index 00000000..22b9bf48 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151.sub @@ -0,0 +1,30 @@ +* Subcircuit CD54_HC_151 +.subckt CD54_HC_151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_m13-pad2_ net-_m13-pad1_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_m11-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd54_hc_151\cd54_hc_151.cir +.include CD54_157.sub +.include PMOS-180nm.lib +.include NMOS-180nm.lib +x2 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m1-pad2_ net-_u1-pad1_ net-_u1-pad2_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x1 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m4-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x3 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m2-pad2_ net-_u1-pad14_ net-_u1-pad15_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x4 net-_u1-pad11_ ? ? ? ? ? ? net-_m1-pad3_ net-_m3-pad2_ net-_u1-pad12_ net-_u1-pad13_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x6 net-_u1-pad10_ ? ? ? ? ? ? net-_m1-pad3_ net-_m10-pad2_ net-_m3-pad1_ net-_m2-pad1_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x5 net-_u1-pad10_ ? ? ? ? ? ? net-_m1-pad3_ net-_m11-pad2_ net-_m1-pad1_ net-_m4-pad1_ ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +x7 net-_u1-pad9_ ? ? ? net-_m11-pad1_ net-_m10-pad1_ net-_m13-pad2_ net-_m1-pad3_ ? ? ? ? ? ? net-_u1-pad7_ net-_m11-pad3_ CD54_157 +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m9 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m12 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m14 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1 +m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD54_HC_151 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151_Previous_Values.xml b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151_Previous_Values.xml new file mode 100644 index 00000000..df20a2c2 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/CD54_HC_151_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157C:\FOSSEE\eSim\library\SubcircuitLibrary\CD54_157 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC_151/NMOS-180nm.lib b/library/SubcircuitLibrary/CD54_HC_151/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD54_HC_151/PMOS-180nm.lib b/library/SubcircuitLibrary/CD54_HC_151/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD54_HC_151/README.md b/library/SubcircuitLibrary/CD54_HC_151/README.md new file mode 100644 index 00000000..cc739100 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/README.md @@ -0,0 +1,21 @@ + +# CD54HC151 IC + +It is 8:1 Multiplexer IC. CD54151 IC is designed with 180nm CMOS technology in eSim. It is 16 pin IC. The output depends on the select lines. +## Usage/Examples + +Multiplexers +## Documentation + +To know the details of CD54HC151 IC please go through with the documentation : [CD54HC151_datasheet](https://www.ti.com/lit/gpn/cd54hc151) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD54_HC_151/analysis b/library/SubcircuitLibrary/CD54_HC_151/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD54_HC_151/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 0fa7cd5ab4a888272d03ad47d0eabfc9095bbbbb Mon Sep 17 00:00:00 2001 From: AnkushECE Date: Wed, 12 Oct 2022 01:20:05 +0530 Subject: This is eSim_Subckt.lib file --- .../kicad_eSim-Library/eSim_Subckt.lib | 548 ++++++++++++++++++--- 1 file changed, 488 insertions(+), 60 deletions(-) (limited to 'library') diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index ce0c8f05..cb462b9b 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -24,22 +24,6 @@ X AnalogOut 11 600 350 200 L 50 50 1 1 O ENDDRAW ENDDEF # -# Clock_pulse_generator -# -DEF Clock_pulse_generator X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Clock_pulse_generator" 0 -100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 200 600 -300 0 1 0 N -X Vdd 1 -750 100 200 R 50 50 1 1 I -X R 2 -750 -50 200 R 50 50 1 1 I -X C 3 -750 -200 200 R 50 50 1 1 I -X Clkout 4 800 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# # 2BITMUL # DEF 2BITMUL X 0 40 Y Y 1 F N @@ -164,6 +148,40 @@ X out 6 550 0 200 L 50 50 1 1 O ENDDRAW ENDDEF # +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# # IC_4002 # DEF IC_4002 X 0 40 Y Y 1 F N @@ -190,24 +208,6 @@ X VCC 14 450 250 200 L 50 50 1 1 I ENDDRAW ENDDEF # -# CMOS_NAND -# -DEF CMOS_NAND X 0 40 Y Y 1 F N -F0 "X" -100 -150 60 H V C CNN -F1 "CMOS_NAND" 0 -50 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 -C 550 0 50 0 1 0 N -P 2 0 1 0 -350 300 300 300 N -P 3 0 1 0 -350 300 -350 -400 300 -400 N -X in1 1 -550 250 200 R 50 50 1 1 I -X in2 2 -550 -300 200 R 50 50 1 1 I -X out 3 800 0 279 L 79 79 1 1 I -ENDDRAW -ENDDEF -# # IC_4012 # DEF IC_4012 X 0 40 Y Y 1 F N @@ -258,32 +258,6 @@ X CLK 12 -550 350 200 R 50 50 1 1 I ENDDRAW ENDDEF # -# eSim_74LS04 -# -DEF eSim_74LS04 X 0 40 Y Y 1 F N -F0 "X" 0 100 60 H V C CNN -F1 "eSim_74LS04" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S 350 500 -350 -500 0 1 0 N -X ~ 1 -550 450 200 R 50 50 1 1 P -X ~ 2 -550 300 200 R 50 50 1 1 P I -X ~ 3 -550 150 200 R 50 50 1 1 P -X ~ 4 -550 0 200 R 50 50 1 1 P I -X ~ 5 -550 -150 200 R 50 50 1 1 P -X ~ 6 -550 -300 200 R 50 50 1 1 P I -X GND 7 -550 -450 200 R 50 50 1 1 P -X ~ 8 550 -450 200 L 50 50 1 1 P I -X ~ 9 550 -300 200 L 50 50 1 1 P -X ~ 10 550 -150 200 L 50 50 1 1 P I -X ~ 11 550 0 200 L 50 50 1 1 P -X ~ 12 550 150 200 L 50 50 1 1 P I -X ~ 13 550 300 200 L 50 50 1 1 P -X VCC 14 550 450 200 L 50 50 1 1 P -ENDDRAW -ENDDEF -# # IC_4023 # DEF IC_4023 X 0 40 Y Y 1 F N @@ -523,6 +497,21 @@ X VCC 8 0 600 200 D 50 50 1 1 W ENDDRAW ENDDEF # +# LM_7809_VR +# +DEF LM_7809_VR X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7809_VR" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X OUT 2 550 0 200 L 50 50 1 1 O +X GND 3 0 -400 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# # LM_7812 # DEF LM_7812 X 0 40 Y Y 1 F N @@ -590,6 +579,32 @@ X B2 3 0 350 200 D 50 50 1 1 B ENDDRAW ENDDEF # +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# # full_adder # DEF full_adder X 0 40 Y Y 1 F N @@ -676,4 +691,417 @@ X NC 8 150 -300 200 U 50 38 1 1 N ENDDRAW ENDDEF # +# CD_4081 +# +DEF CD_4081 X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "CD_4081" 100 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 300 750 -300 0 1 0 N +X A1 1 -500 -500 200 U 50 50 1 1 I +X B1 2 -300 -500 200 U 50 50 1 1 I +X Y1 3 -100 -500 200 U 50 50 1 1 O +X Y2 4 100 -500 200 U 50 50 1 1 O +X A2 5 300 -500 200 U 50 50 1 1 I +X B2 6 500 -500 200 U 50 50 1 1 I +X GND 7 700 -500 200 U 50 50 1 1 I +X A3 8 700 500 200 D 50 50 1 1 I +X B3 9 500 500 200 D 50 50 1 1 I +X Y3 10 300 500 200 D 50 50 1 1 O +X Y4 11 100 500 200 D 50 50 1 1 O +X A4 12 -100 500 200 D 50 50 1 1 I +X B4 13 -300 500 200 D 50 50 1 1 I +X VCC 14 -500 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4077 +# +DEF CD4077 X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "CD4077" 0 50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 250 550 -250 0 1 0 N +X A1 1 -400 -450 200 U 50 50 1 1 I +X B1 2 -250 -450 200 U 50 50 1 1 I +X Y1 3 -100 -450 200 U 50 50 1 1 O +X Y2 4 50 -450 200 U 50 50 1 1 O +X A2 5 200 -450 200 U 50 50 1 1 I +X B2 6 350 -450 200 U 50 50 1 1 I +X GND 7 500 -450 200 U 50 50 1 1 I +X A3 8 500 450 200 D 50 50 1 1 I +X B3 9 350 450 200 D 50 50 1 1 I +X Y3 10 200 450 200 D 50 50 1 1 O +X Y4 11 50 450 200 D 50 50 1 1 O +X B4 12 -100 450 200 D 50 50 1 1 I +X A4 13 -250 450 200 D 50 50 1 1 I +X VCC 14 -400 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4071 +# +DEF CD_4071 X 0 40 Y Y 1 F N +F0 "X" -200 -50 60 H V C CNN +F1 "CD_4071" 100 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 600 -250 0 1 0 N +X A1 1 -350 -450 200 U 50 50 1 1 I +X B1 2 -200 -450 200 U 50 50 1 1 I +X Q1 3 -50 -450 200 U 50 50 1 1 O +X Q2 4 100 -450 200 U 50 50 1 1 O +X A2 5 250 -450 200 U 50 50 1 1 I +X B2 6 400 -450 200 U 50 50 1 1 I +X GND 7 550 -450 200 U 50 50 1 1 I +X A3 8 550 400 200 D 50 50 1 1 I +X B3 9 400 400 200 D 50 50 1 1 I +X Q3 10 250 400 200 D 50 50 1 1 O +X Q4 11 100 400 200 D 50 50 1 1 O +X A4 12 -50 400 200 D 50 50 1 1 I +X B4 13 -200 400 200 D 50 50 1 1 I +X VCC 14 -350 400 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4070 +# +DEF CD_4070 X 0 40 Y Y 1 F N +F0 "X" -250 -50 60 H V C CNN +F1 "CD_4070" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 250 550 -250 0 1 0 N +X A1 1 -450 -450 200 U 50 50 1 1 I +X B1 2 -300 -450 200 U 50 50 1 1 I +X Y1 3 -150 -450 200 U 50 50 1 1 O +X Y2 4 0 -450 200 U 50 50 1 1 O +X A2 5 150 -450 200 U 50 50 1 1 I +X B2 6 300 -450 200 U 50 50 1 1 I +X GND 7 450 -450 200 U 50 50 1 1 I +X A3 8 450 450 200 D 50 50 1 1 I +X B3 9 300 450 200 D 50 50 1 1 I +X Y3 10 150 450 200 D 50 50 1 1 O +X Y4 11 0 450 200 D 50 50 1 1 O +X A4 12 -150 450 200 D 50 50 1 1 I +X B4 13 -300 450 200 D 50 50 1 1 I +X VCC 14 -450 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4069 +# +DEF CD_4069 X 0 40 Y Y 1 F N +F0 "X" -250 100 60 H V C CNN +F1 "CD_4069" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -450 0 1 0 N +X IN_1 1 -500 350 200 R 50 50 1 1 I +X OUT_1 2 -500 200 200 R 50 50 1 1 O +X IN_3 3 -500 0 200 R 50 50 1 1 I +X OUT_2 4 -500 -100 200 R 50 50 1 1 O +X IN_5 5 -500 -200 200 R 50 50 1 1 I +X OUT_3 6 -500 -300 200 R 50 50 1 1 O +X GND 7 -500 -400 200 R 50 50 1 1 I +X OUT_4 8 500 -400 200 L 50 50 1 1 O +X IN_4 9 500 -300 200 L 50 50 1 1 I +X OUT_5 10 500 -200 200 L 50 50 1 1 O +X IN_5 11 500 -100 200 L 50 50 1 1 I +X OUT_6 12 500 0 200 L 50 50 1 1 O +X IN_6 13 500 200 200 L 50 50 1 1 I +X VDD 14 500 350 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4028B_IC +# +DEF CD4028B_IC X 0 40 Y Y 1 F N +F0 "X" 100 150 60 H V C CNN +F1 "CD4028B_IC" 100 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 450 600 -700 0 1 0 N +X Y_4 1 -600 400 200 R 50 50 1 1 O +X Y_2 2 -600 250 200 R 50 50 1 1 O +X Y_0 3 -600 100 200 R 50 50 1 1 O +X Y_7 4 -600 -50 200 R 50 50 1 1 O +X Y_9 5 -600 -200 200 R 50 50 1 1 O +X Y_5 6 -600 -350 200 R 50 50 1 1 O +X Y_6 7 -600 -500 200 R 50 50 1 1 O +X VSS 8 -600 -650 200 R 50 50 1 1 I +X Y_8 9 800 -650 200 L 50 50 1 1 O +X A 10 800 -500 200 L 50 50 1 1 I +X D 11 800 -350 200 L 50 50 1 1 I +X C 12 800 -200 200 L 50 50 1 1 I +X B 13 800 -50 200 L 50 50 1 1 I +X Y_1 14 800 100 200 L 50 50 1 1 O +X Y_3 15 800 250 200 L 50 50 1 1 O +X VDD 16 800 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4023 +# +DEF CD_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4023" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 250 450 -300 0 1 0 N +X A1 1 -500 -500 200 U 50 50 1 1 I +X B1 2 -350 -500 200 U 50 50 1 1 I +X A2 3 -200 -500 200 U 50 50 1 1 I +X B2 4 -50 -500 200 U 50 50 1 1 I +X C2 5 100 -500 200 U 50 50 1 1 I +X Y2 6 250 -500 200 U 50 50 1 1 O +X GND 7 400 -500 200 U 50 50 1 1 I +X C1 8 400 450 200 D 50 50 1 1 I +X Y1 9 250 450 200 D 50 50 1 1 O +X Y3 10 100 450 200 D 50 50 1 1 O +X A3 11 -50 450 200 D 50 50 1 1 I +X B3 12 -200 450 200 D 50 50 1 1 I +X C3 13 -350 450 200 D 50 50 1 1 I +X VCC 14 -500 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4011 +# +DEF CD_4011 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4011" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 250 550 -300 0 1 0 N +X A1 1 -400 -500 200 U 50 50 1 1 I +X B1 2 -250 -500 200 U 50 50 1 1 I +X Y1 3 -100 -500 200 U 50 50 1 1 O +X Y2 4 50 -500 200 U 50 50 1 1 O +X A2 5 200 -500 200 U 50 50 1 1 I +X B2 6 350 -500 200 U 50 50 1 1 I +X GND 7 500 -500 200 U 50 50 1 1 I +X A3 8 500 450 200 D 50 50 1 1 I +X B3 9 350 450 200 D 50 50 1 1 I +X Y3 10 200 450 200 D 50 50 1 1 O +X Y4 11 50 450 200 D 50 50 1 1 O +X A4 12 -100 450 200 D 50 50 1 1 I +X B4 13 -250 450 200 D 50 50 1 1 I +X VCC 14 -400 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4001 +# +DEF CD_4001 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4001" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 250 500 -300 0 1 0 N +X A1 1 -450 -500 200 U 50 50 1 1 I +X B1 2 -300 -500 200 U 50 50 1 1 I +X Y1 3 -150 -500 200 U 50 50 1 1 O +X Y2 4 0 -500 200 U 50 50 1 1 O +X A2 5 150 -500 200 U 50 50 1 1 I +X B2 6 300 -500 200 U 50 50 1 1 I +X GND 7 450 -500 200 U 50 50 1 1 I +X A3 8 450 450 200 D 50 50 1 1 I +X B3 9 300 450 200 D 50 50 1 1 I +X VCC ~ -450 450 200 D 50 50 1 1 I +X Y3 10 150 450 200 D 50 50 1 1 O +X Y4 11 0 450 200 D 50 50 1 1 O +X A4 12 -150 450 200 D 50 50 1 1 I +X B4 13 -300 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_54HC_153 +# +DEF CD_54HC_153 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "CD_54HC_153" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 450 550 -700 0 1 0 N +X E1_bar 1 -750 400 200 R 50 50 1 1 I +X S1 2 -750 250 200 R 50 50 1 1 I +X I3_1 3 -750 100 200 R 50 50 1 1 I +X I2_1 4 -750 -50 200 R 50 50 1 1 I +X I1_1 5 -750 -200 200 R 50 50 1 1 I +X I0_1 6 -750 -350 200 R 50 50 1 1 I +X Y1 7 -750 -500 200 R 50 50 1 1 O +X GND 8 -750 -650 200 R 50 50 1 1 I +X Y2 9 750 -650 200 L 50 50 1 1 O +X I0_2 10 750 -500 200 L 50 50 1 1 I +X I1_2 11 750 -350 200 L 50 50 1 1 I +X I2_2 12 750 -200 200 L 50 50 1 1 I +X I3_2 13 750 -50 200 L 50 50 1 1 I +X S0 14 750 100 200 L 50 50 1 1 I +X E2_bar 15 750 250 200 L 50 50 1 1 I +X VCC 16 750 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_54157 +# +DEF CD_54157 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "CD_54157" 0 -250 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -600 0 1 0 N +X Sel 1 -550 150 200 R 50 50 1 1 I +X I0_1 2 -550 50 200 R 50 50 1 1 I +X I1_1 3 -550 -50 200 R 50 50 1 1 I +X Y1_bar 4 -550 -150 200 R 50 50 1 1 O +X I0_2 5 -550 -250 200 R 50 50 1 1 I +X I1_2 6 -550 -350 200 R 50 50 1 1 I +X Y2_bar 7 -550 -450 200 R 50 50 1 1 O +X GND 8 -550 -550 200 R 50 50 1 1 I +X Y3_bar 9 550 -550 200 L 50 50 1 1 O +X I1_3 10 550 -450 200 L 50 50 1 1 I +X I0_3 11 550 -350 200 L 50 50 1 1 I +X Y4_bar 12 550 -250 200 L 50 50 1 1 O +X I1_4 13 550 -150 200 L 50 50 1 1 I +X I0_4 14 550 -50 200 L 50 50 1 1 I +X E_bar 15 550 50 200 L 50 50 1 1 I +X VCC 16 550 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# AD620_IC +# +DEF AD620_IC X 0 40 Y Y 1 F N +F0 "X" 50 200 60 H V C CNN +F1 "AD620_IC" 0 -100 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 400 350 -450 0 1 0 N +X RG1 1 -550 300 200 R 50 50 1 1 I +X IN- 2 -550 100 200 R 50 50 1 1 I +X IN+ 3 -550 -150 200 R 50 50 1 1 I +X VS- 4 -550 -350 200 R 50 50 1 1 I +X REF 5 550 -350 200 L 50 50 1 1 I +X OUT 6 550 -150 200 L 50 50 1 1 O +X VS+ 7 550 100 200 L 50 50 1 1 I +X RG2 8 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4008 +# +DEF CD_4008 X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "CD_4008" 0 50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 500 350 -650 0 1 0 N +X A3 1 -550 450 200 R 50 50 1 1 I +X B2 2 -550 300 200 R 50 50 1 1 I +X A2 3 -550 150 200 R 50 50 1 1 I +X B1 4 -550 0 200 R 50 50 1 1 I +X A1 5 -550 -150 200 R 50 50 1 1 I +X B0 6 -550 -300 200 R 50 50 1 1 I +X A0 7 -550 -450 200 R 50 50 1 1 I +X GND 8 -550 -600 200 R 50 50 1 1 I +X Cin 9 550 -600 200 L 50 50 1 1 I +X S0 10 550 -450 200 L 50 50 1 1 O +X S1 11 550 -300 200 L 50 50 1 1 O +X S2 12 550 -150 200 L 50 50 1 1 O +X S3 13 550 0 200 L 50 50 1 1 O +X COUT 14 550 150 200 L 50 50 1 1 O +X B3 15 550 300 200 L 50 50 1 1 I +X VDD 16 550 450 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD54HC151 +# +DEF CD54HC151 X 0 40 Y Y 1 F N +F0 "X" 50 -150 60 H V C CNN +F1 "CD54HC151" 50 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 500 550 -650 0 1 0 N +X I3 1 -700 450 200 R 50 50 1 1 I +X I2 2 -700 300 200 R 50 50 1 1 I +X I1 3 -700 150 200 R 50 50 1 1 I +X I0 4 -700 0 200 R 50 50 1 1 I +X Y 5 -700 -150 200 R 50 50 1 1 O +X Y_bar 6 -700 -300 200 R 50 50 1 1 O +X E_bar 7 -700 -450 200 R 50 50 1 1 I +X GND 8 -700 -600 200 R 50 50 1 1 I +X S2 9 750 -600 200 L 50 50 1 1 I +X S1 10 750 -450 200 L 50 50 1 1 I +X S0 11 750 -300 200 L 50 50 1 1 I +X I7 12 750 -150 200 L 50 50 1 1 I +X I6 13 750 0 200 L 50 50 1 1 I +X I5 14 750 150 200 L 50 50 1 1 I +X I4 15 750 300 200 L 50 50 1 1 I +X VDD 16 750 450 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4000_NOR +# +DEF CD4000_NOR X 0 40 Y Y 1 F N +F0 "X" 50 350 60 H V C CNN +F1 "CD4000_NOR" 0 -100 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 -300 400 60 0 0 0 NC_1 Normal 0 C C +T 0 -300 250 60 0 0 0 NC_2 Normal 0 C C +S -450 450 450 -550 0 1 0 N +X IN1_1 3 -650 100 200 R 50 50 1 1 I +X IN1_2 4 -650 -50 200 R 50 50 1 1 I +X IN1_3 5 -650 -200 200 R 50 50 1 1 I +X OUT_1 6 -650 -350 200 R 50 50 1 1 O +X GND 7 -650 -500 200 R 50 50 1 1 I +X IN_inv 8 650 -500 200 L 50 50 1 1 I +X OUT_inv 9 650 -350 200 L 50 50 1 1 O +X OUT_2 10 650 -200 200 L 50 50 1 1 O +X IN2_1 11 650 -50 200 L 50 50 1 1 I +X IN2_2 12 650 100 200 L 50 50 1 1 I +X IN2_3 13 650 250 200 L 50 50 1 1 I +X VDD 14 650 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LM_386 +# +DEF LM_386 X 0 40 Y Y 1 F N +F0 "X" -100 100 60 H V C CNN +F1 "LM_386" 150 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -250 350 400 -150 0 1 0 N +X GAIN 1 -200 -350 200 U 50 50 1 1 I +X -IN 2 0 -350 200 U 50 50 1 1 I +X +IN 3 150 -350 200 U 50 50 1 1 I +X GND 4 350 -350 200 U 50 50 1 1 I +X OUT 5 350 550 200 D 50 50 1 1 O +X VDD 6 150 550 200 D 50 50 1 1 I +X ByP 7 0 550 200 D 50 50 1 1 I +X GAIN 8 -200 550 200 D 50 50 1 1 I +ENDDRAW +ENDDEF #End Library -- cgit From 718255ce3a8e4d6f47dbfdf6e321d9502ddb5362 Mon Sep 17 00:00:00 2001 From: Arpit Sharma Date: Fri, 21 Oct 2022 23:08:19 +0530 Subject: LM13700 Operational Transconductance Amplifier IC --- library/SubcircuitLibrary/LM13700/D.lib | 2 + .../SubcircuitLibrary/LM13700/LM13700-cache.lib | 107 +++ library/SubcircuitLibrary/LM13700/LM13700.cir | 47 + library/SubcircuitLibrary/LM13700/LM13700.cir.out | 51 ++ library/SubcircuitLibrary/LM13700/LM13700.pro | 81 ++ library/SubcircuitLibrary/LM13700/LM13700.sch | 991 +++++++++++++++++++++ library/SubcircuitLibrary/LM13700/LM13700.sub | 45 + .../LM13700/LM13700_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM13700/NPN.lib | 4 + library/SubcircuitLibrary/LM13700/PNP.lib | 4 + library/SubcircuitLibrary/LM13700/README.md | 34 + library/SubcircuitLibrary/LM13700/analysis | 1 + 12 files changed, 1368 insertions(+) create mode 100644 library/SubcircuitLibrary/LM13700/D.lib create mode 100644 library/SubcircuitLibrary/LM13700/LM13700-cache.lib create mode 100644 library/SubcircuitLibrary/LM13700/LM13700.cir create mode 100644 library/SubcircuitLibrary/LM13700/LM13700.cir.out create mode 100644 library/SubcircuitLibrary/LM13700/LM13700.pro create mode 100644 library/SubcircuitLibrary/LM13700/LM13700.sch create mode 100644 library/SubcircuitLibrary/LM13700/LM13700.sub create mode 100644 library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM13700/NPN.lib create mode 100644 library/SubcircuitLibrary/LM13700/PNP.lib create mode 100644 library/SubcircuitLibrary/LM13700/README.md create mode 100644 library/SubcircuitLibrary/LM13700/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/LM13700/D.lib b/library/SubcircuitLibrary/LM13700/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM13700/LM13700-cache.lib b/library/SubcircuitLibrary/LM13700/LM13700-cache.lib new file mode 100644 index 00000000..21197049 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM13700/LM13700.cir b/library/SubcircuitLibrary/LM13700/LM13700.cir new file mode 100644 index 00000000..675d216e --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.cir @@ -0,0 +1,47 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM13700\LM13700.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/28/22 23:24:01 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q3 Net-_Q2-Pad1_ Net-_D4-Pad2_ /V+ eSim_PNP +D4 /V+ Net-_D4-Pad2_ eSim_Diode +Q6 Net-_Q10-Pad2_ Net-_Q2-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q7 Net-_Q5-Pad1_ Net-_D5-Pad2_ /V+ eSim_PNP +D5 /V+ Net-_D5-Pad2_ eSim_Diode +Q9 /Output Net-_Q5-Pad1_ Net-_D5-Pad2_ eSim_PNP +Q11 /V+ /Buffer_input Net-_Q11-Pad3_ eSim_NPN +Q12 /V+ Net-_Q11-Pad3_ /Buffer_output eSim_NPN +Q2 Net-_Q2-Pad1_ /Input- Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ /Input+ Net-_Q2-Pad3_ eSim_NPN +D3 /Diode_bias /Input+ eSim_Diode +D1 /Diode_bias /Input- eSim_Diode +Q4 Net-_Q2-Pad3_ /Amp_bias_input Net-_D2-Pad1_ eSim_NPN +Q1 /Amp_bias_input Net-_D2-Pad1_ /V- eSim_NPN +D2 Net-_D2-Pad1_ /V- eSim_Diode +Q10 /Output Net-_Q10-Pad2_ Net-_D6-Pad1_ eSim_NPN +Q8 Net-_Q10-Pad2_ Net-_D6-Pad1_ /V- eSim_NPN +D6 Net-_D6-Pad1_ /V- eSim_Diode +Q15 Net-_Q14-Pad1_ Net-_D10-Pad2_ /V+ eSim_PNP +D10 /V+ Net-_D10-Pad2_ eSim_Diode +Q18 Net-_Q18-Pad1_ Net-_Q14-Pad1_ Net-_D10-Pad2_ eSim_PNP +Q19 Net-_Q17-Pad1_ Net-_D11-Pad2_ /V+ eSim_PNP +D11 /V+ Net-_D11-Pad2_ eSim_Diode +Q21 /Output Net-_Q17-Pad1_ Net-_D11-Pad2_ eSim_PNP +Q23 /V+ /Bufer_input Net-_Q23-Pad3_ eSim_NPN +Q24 /V+ Net-_Q23-Pad3_ /Buffer_output eSim_NPN +Q14 Net-_Q14-Pad1_ /Input- Net-_Q14-Pad3_ eSim_NPN +Q17 Net-_Q17-Pad1_ /Input+ Net-_Q14-Pad3_ eSim_NPN +D9 /Diode_bias /Input+ eSim_Diode +D7 /Diode_bias /Input- eSim_Diode +Q16 Net-_Q14-Pad3_ /Amp_bias_input Net-_D8-Pad1_ eSim_NPN +Q13 /Amp_bias_input Net-_D8-Pad1_ /V- eSim_NPN +D8 Net-_D8-Pad1_ /V- eSim_Diode +Q22 /Output Net-_Q18-Pad1_ Net-_D12-Pad1_ eSim_NPN +Q20 Net-_Q18-Pad1_ Net-_D12-Pad1_ /V- eSim_NPN +D12 Net-_D12-Pad1_ /V- eSim_Diode +U1 /V+ /Diode_bias /Input- /Input+ /Amp_bias_input /V- /Output /Diode_bias /Input- /Input+ /Amp_bias_input /Buffer_output /Buffer_input /Output /Buffer_output /Bufer_input PORT + +.end diff --git a/library/SubcircuitLibrary/LM13700/LM13700.cir.out b/library/SubcircuitLibrary/LM13700/LM13700.cir.out new file mode 100644 index 00000000..826d189b --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.cir.out @@ -0,0 +1,51 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm13700\lm13700.cir + +.include D.lib +.include PNP.lib +.include NPN.lib +q3 net-_q2-pad1_ net-_d4-pad2_ /v+ Q2N2907A +d4 /v+ net-_d4-pad2_ 1N4148 +q6 net-_q10-pad2_ net-_q2-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_q5-pad1_ net-_d5-pad2_ /v+ Q2N2907A +d5 /v+ net-_d5-pad2_ 1N4148 +q9 /output net-_q5-pad1_ net-_d5-pad2_ Q2N2907A +q11 /v+ /buffer_input net-_q11-pad3_ Q2N2222 +q12 /v+ net-_q11-pad3_ /buffer_output Q2N2222 +q2 net-_q2-pad1_ /input- net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ /input+ net-_q2-pad3_ Q2N2222 +d3 /diode_bias /input+ 1N4148 +d1 /diode_bias /input- 1N4148 +q4 net-_q2-pad3_ /amp_bias_input net-_d2-pad1_ Q2N2222 +q1 /amp_bias_input net-_d2-pad1_ /v- Q2N2222 +d2 net-_d2-pad1_ /v- 1N4148 +q10 /output net-_q10-pad2_ net-_d6-pad1_ Q2N2222 +q8 net-_q10-pad2_ net-_d6-pad1_ /v- Q2N2222 +d6 net-_d6-pad1_ /v- 1N4148 +q15 net-_q14-pad1_ net-_d10-pad2_ /v+ Q2N2907A +d10 /v+ net-_d10-pad2_ 1N4148 +q18 net-_q18-pad1_ net-_q14-pad1_ net-_d10-pad2_ Q2N2907A +q19 net-_q17-pad1_ net-_d11-pad2_ /v+ Q2N2907A +d11 /v+ net-_d11-pad2_ 1N4148 +q21 /output net-_q17-pad1_ net-_d11-pad2_ Q2N2907A +q23 /v+ /bufer_input net-_q23-pad3_ Q2N2222 +q24 /v+ net-_q23-pad3_ /buffer_output Q2N2222 +q14 net-_q14-pad1_ /input- net-_q14-pad3_ Q2N2222 +q17 net-_q17-pad1_ /input+ net-_q14-pad3_ Q2N2222 +d9 /diode_bias /input+ 1N4148 +d7 /diode_bias /input- 1N4148 +q16 net-_q14-pad3_ /amp_bias_input net-_d8-pad1_ Q2N2222 +q13 /amp_bias_input net-_d8-pad1_ /v- Q2N2222 +d8 net-_d8-pad1_ /v- 1N4148 +q22 /output net-_q18-pad1_ net-_d12-pad1_ Q2N2222 +q20 net-_q18-pad1_ net-_d12-pad1_ /v- Q2N2222 +d12 net-_d12-pad1_ /v- 1N4148 +* u1 /v+ /diode_bias /input- /input+ /amp_bias_input /v- /output /diode_bias /input- /input+ /amp_bias_input /buffer_output /buffer_input /output /buffer_output /bufer_input port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM13700/LM13700.pro b/library/SubcircuitLibrary/LM13700/LM13700.pro new file mode 100644 index 00000000..b4c76509 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:32:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM13700/LM13700.sch b/library/SubcircuitLibrary/LM13700/LM13700.sch new file mode 100644 index 00000000..cf335372 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.sch @@ -0,0 +1,991 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM13700-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q3 +U 1 1 62C1C504 +P 2500 1700 +F 0 "Q3" H 2400 1750 50 0000 R CNN +F 1 "eSim_PNP" H 2450 1850 50 0000 R CNN +F 2 "" H 2700 1800 29 0000 C CNN +F 3 "" H 2500 1700 60 0000 C CNN + 1 2500 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 62C1C505 +P 3200 1450 +F 0 "D4" H 3200 1550 50 0000 C CNN +F 1 "eSim_Diode" H 3200 1350 50 0000 C CNN +F 2 "" H 3200 1450 60 0000 C CNN +F 3 "" H 3200 1450 60 0000 C CNN + 1 3200 1450 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 62C1C506 +P 3100 2250 +F 0 "Q6" H 3000 2300 50 0000 R CNN +F 1 "eSim_PNP" H 3050 2400 50 0000 R CNN +F 2 "" H 3300 2350 29 0000 C CNN +F 3 "" H 3100 2250 60 0000 C CNN + 1 3100 2250 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 62C1C507 +P 3800 1700 +F 0 "Q7" H 3700 1750 50 0000 R CNN +F 1 "eSim_PNP" H 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+F 3 "" H 1200 5600 60 0000 C CNN + 6 1200 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62C1CF53 +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 7 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 62C1D0FB +P 6150 2000 +F 0 "U1" H 6200 2100 30 0000 C CNN +F 1 "PORT" H 6150 2000 30 0000 C CNN +F 2 "" H 6150 2000 60 0000 C CNN +F 3 "" H 6150 2000 60 0000 C CNN + 12 6150 2000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 62C1D208 +P 5650 2200 +F 0 "U1" H 5700 2300 30 0000 C CNN +F 1 "PORT" H 5650 2200 30 0000 C CNN +F 2 "" H 5650 2200 60 0000 C CNN +F 3 "" H 5650 2200 60 0000 C CNN + 13 5650 2200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 62C1D308 +P 5050 2800 +F 0 "U1" H 5100 2900 30 0000 C CNN +F 1 "PORT" H 5050 2800 30 0000 C CNN +F 2 "" H 5050 2800 60 0000 C CNN +F 3 "" H 5050 2800 60 0000 C CNN + 8 5050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 62C1D3E3 +P 5050 3350 +F 0 "U1" H 5100 3450 30 0000 C CNN +F 1 "PORT" H 5050 3350 30 0000 C CNN +F 2 "" H 5050 3350 60 0000 C CNN +F 3 "" H 5050 3350 60 0000 C CNN + 9 5050 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 62C1D4E9 +P 5050 3800 +F 0 "U1" H 5100 3900 30 0000 C CNN +F 1 "PORT" H 5050 3800 30 0000 C CNN +F 2 "" H 5050 3800 60 0000 C CNN +F 3 "" H 5050 3800 60 0000 C CNN + 10 5050 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62C1D56C +P 5050 4250 +F 0 "U1" H 5100 4350 30 0000 C CNN +F 1 "PORT" H 5050 4250 30 0000 C CNN +F 2 "" H 5050 4250 60 0000 C CNN +F 3 "" H 5050 4250 60 0000 C CNN + 11 5050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62C1D719 +P 9450 3250 +F 0 "U1" H 9500 3350 30 0000 C CNN +F 1 "PORT" H 9450 3250 30 0000 C CNN +F 2 "" H 9450 3250 60 0000 C CNN +F 3 "" H 9450 3250 60 0000 C CNN + 14 9450 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 62C1D7AC +P 9950 2100 +F 0 "U1" H 10000 2200 30 0000 C CNN +F 1 "PORT" H 9950 2100 30 0000 C CNN +F 2 "" H 9950 2100 60 0000 C CNN +F 3 "" H 9950 2100 60 0000 C CNN + 15 9950 2100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 62C1D875 +P 9700 2450 +F 0 "U1" H 9750 2550 30 0000 C CNN +F 1 "PORT" H 9700 2450 30 0000 C CNN +F 2 "" H 9700 2450 60 0000 C CNN +F 3 "" H 9700 2450 60 0000 C CNN + 16 9700 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 9600 2100 9600 1950 +Wire Wire Line + 7350 2800 7350 2900 +Wire Wire Line + 3200 2800 3200 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM13700/LM13700.sub b/library/SubcircuitLibrary/LM13700/LM13700.sub new file mode 100644 index 00000000..81d11235 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.sub @@ -0,0 +1,45 @@ +* Subcircuit LM13700 +.subckt LM13700 /v+ /diode_bias /input- /input+ /amp_bias_input /v- /output /diode_bias /input- /input+ /amp_bias_input /buffer_output /buffer_input /output /buffer_output /bufer_input +* c:\fossee\esim\library\subcircuitlibrary\lm13700\lm13700.cir +.include D.lib +.include PNP.lib +.include NPN.lib +q3 net-_q2-pad1_ net-_d4-pad2_ /v+ Q2N2907A +d4 /v+ net-_d4-pad2_ 1N4148 +q6 net-_q10-pad2_ net-_q2-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_q5-pad1_ net-_d5-pad2_ /v+ Q2N2907A +d5 /v+ net-_d5-pad2_ 1N4148 +q9 /output net-_q5-pad1_ net-_d5-pad2_ Q2N2907A +q11 /v+ /buffer_input net-_q11-pad3_ Q2N2222 +q12 /v+ net-_q11-pad3_ /buffer_output Q2N2222 +q2 net-_q2-pad1_ /input- net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ /input+ net-_q2-pad3_ Q2N2222 +d3 /diode_bias /input+ 1N4148 +d1 /diode_bias /input- 1N4148 +q4 net-_q2-pad3_ /amp_bias_input net-_d2-pad1_ Q2N2222 +q1 /amp_bias_input net-_d2-pad1_ /v- Q2N2222 +d2 net-_d2-pad1_ /v- 1N4148 +q10 /output net-_q10-pad2_ net-_d6-pad1_ Q2N2222 +q8 net-_q10-pad2_ net-_d6-pad1_ /v- Q2N2222 +d6 net-_d6-pad1_ /v- 1N4148 +q15 net-_q14-pad1_ net-_d10-pad2_ /v+ Q2N2907A +d10 /v+ net-_d10-pad2_ 1N4148 +q18 net-_q18-pad1_ net-_q14-pad1_ net-_d10-pad2_ Q2N2907A +q19 net-_q17-pad1_ net-_d11-pad2_ /v+ Q2N2907A +d11 /v+ net-_d11-pad2_ 1N4148 +q21 /output net-_q17-pad1_ net-_d11-pad2_ Q2N2907A +q23 /v+ /bufer_input net-_q23-pad3_ Q2N2222 +q24 /v+ net-_q23-pad3_ /buffer_output Q2N2222 +q14 net-_q14-pad1_ /input- net-_q14-pad3_ Q2N2222 +q17 net-_q17-pad1_ /input+ net-_q14-pad3_ Q2N2222 +d9 /diode_bias /input+ 1N4148 +d7 /diode_bias /input- 1N4148 +q16 net-_q14-pad3_ /amp_bias_input net-_d8-pad1_ Q2N2222 +q13 /amp_bias_input net-_d8-pad1_ /v- Q2N2222 +d8 net-_d8-pad1_ /v- 1N4148 +q22 /output net-_q18-pad1_ net-_d12-pad1_ Q2N2222 +q20 net-_q18-pad1_ net-_d12-pad1_ /v- Q2N2222 +d12 net-_d12-pad1_ /v- 1N4148 +* Control Statements + +.ends LM13700 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml b/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml new file mode 100644 index 00000000..68f6df1f --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13700/NPN.lib b/library/SubcircuitLibrary/LM13700/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM13700/PNP.lib b/library/SubcircuitLibrary/LM13700/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM13700/README.md b/library/SubcircuitLibrary/LM13700/README.md new file mode 100644 index 00000000..cca1cfed --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/README.md @@ -0,0 +1,34 @@ + +# LM13700 Operational Transconductance Amplifier IC + +The LM13700 is a current controlled, additional output buffer-equipped, differential input, transconductance amplifier with two channels. The two amplifiers operate independently, sharing a common supply. It makes use of linearizing diodes, using which higher input levels are permitted with less distortion. It has improved SNR also. + + +## Usage/Examples + +VCA (Voltage Controlled Amplifier) + +ACG (Automatic Gain Contol) Amplifier + +VCO (Voltage controlled Oscillator) + +PLL (Phase Locked loop) + +Four Quadrant Multiplier + +Amplitude Modulator + +## Documentation + +To know the details of LM13700 IC please refer to this link [LM13700_datasheet.](https://www.ti.com/lit/ds/symlink/lm13700.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. Due to the improper modeling of Darlington pair at the output terminals, this IC is producing improper output. The shape of the output waveform is fine but the output is highly DC shifted & also it's peak to peak value is very low. Therefore it is suggested to use this IC only after replacing the subcircuit with a proper working Darlington pair. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM13700/analysis b/library/SubcircuitLibrary/LM13700/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 28d78148e25db0a5cac9b7896184f191f8355217 Mon Sep 17 00:00:00 2001 From: Arpit Sharma Date: Fri, 21 Oct 2022 23:08:46 +0530 Subject: LM321 Op-Amp IC --- library/SubcircuitLibrary/LM321/LM321-cache.lib | 141 + library/SubcircuitLibrary/LM321/LM321.cir | 48 + library/SubcircuitLibrary/LM321/LM321.cir.out | 52 + library/SubcircuitLibrary/LM321/LM321.pro | 81 + library/SubcircuitLibrary/LM321/LM321.sch | 821 ++ library/SubcircuitLibrary/LM321/LM321.sch.svg | 10007 +++++++++++++++++++ library/SubcircuitLibrary/LM321/LM321.sub | 46 + .../LM321/LM321_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM321/NJF.lib | 4 + library/SubcircuitLibrary/LM321/NPN.lib | 4 + library/SubcircuitLibrary/LM321/PNP.lib | 4 + library/SubcircuitLibrary/LM321/README.md | 35 + library/SubcircuitLibrary/LM321/analysis | 1 + 13 files changed, 11245 insertions(+) create mode 100644 library/SubcircuitLibrary/LM321/LM321-cache.lib create mode 100644 library/SubcircuitLibrary/LM321/LM321.cir create mode 100644 library/SubcircuitLibrary/LM321/LM321.cir.out create mode 100644 library/SubcircuitLibrary/LM321/LM321.pro create mode 100644 library/SubcircuitLibrary/LM321/LM321.sch create mode 100644 library/SubcircuitLibrary/LM321/LM321.sch.svg create mode 100644 library/SubcircuitLibrary/LM321/LM321.sub create mode 100644 library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM321/NJF.lib create mode 100644 library/SubcircuitLibrary/LM321/NPN.lib create mode 100644 library/SubcircuitLibrary/LM321/PNP.lib create mode 100644 library/SubcircuitLibrary/LM321/README.md create mode 100644 library/SubcircuitLibrary/LM321/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/LM321/LM321-cache.lib b/library/SubcircuitLibrary/LM321/LM321-cache.lib new file mode 100644 index 00000000..7eda2392 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM321/LM321.cir b/library/SubcircuitLibrary/LM321/LM321.cir new file mode 100644 index 00000000..365f931d --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM321\LM321.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/04/22 16:17:25 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_Q12-Pad2_ Net-_Q3-Pad2_ Net-_J1-Pad1_ Net-_Q24-Pad3_ Net-_J1-Pad2_ PORT +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q19 Net-_Q1-Pad2_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q3-Pad3_ Net-_Q3-Pad3_ Net-_Q11-Pad3_ eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_PNP +Q3 Net-_J1-Pad2_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_PNP +Q12 Net-_J1-Pad2_ Net-_Q12-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q2 Net-_J1-Pad2_ Net-_Q2-Pad2_ Net-_Q1-Pad1_ eSim_PNP +Q9 Net-_C1-Pad2_ Net-_Q2-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q5 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q13 Net-_J1-Pad2_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q14-Pad1_ Net-_Q10-Pad1_ Net-_Q15-Pad3_ eSim_NPN +Q17 Net-_Q15-Pad3_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q18 Net-_J1-Pad2_ Net-_Q16-Pad1_ Net-_Q14-Pad1_ eSim_PNP +Q20 Net-_Q16-Pad1_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q21 Net-_C1-Pad1_ Net-_Q15-Pad3_ Net-_J1-Pad2_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5p +Q24 Net-_C1-Pad1_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_NPN +R1 Net-_Q23-Pad3_ Net-_Q24-Pad2_ 40k +Q23 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q23-Pad3_ eSim_NPN +Q25 Net-_J1-Pad1_ Net-_Q23-Pad3_ Net-_Q24-Pad2_ eSim_NPN +R2 Net-_Q24-Pad2_ Net-_Q24-Pad3_ 25 +Q26 Net-_J1-Pad2_ Net-_C1-Pad1_ Net-_Q24-Pad3_ eSim_PNP +Q27 Net-_Q24-Pad3_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q28 Net-_Q1-Pad2_ Net-_Q28-Pad2_ Net-_Q28-Pad3_ eSim_NPN +R3 Net-_Q28-Pad3_ Net-_J1-Pad2_ 2k +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +Q31 Net-_J1-Pad1_ Net-_J1-Pad3_ Net-_Q30-Pad2_ eSim_NPN +Q29 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q28-Pad2_ eSim_NPN +Q30 Net-_Q28-Pad2_ Net-_Q30-Pad2_ Net-_J1-Pad2_ eSim_NPN +R4 Net-_Q30-Pad2_ Net-_J1-Pad2_ 2.4k +Q7 Net-_Q11-Pad3_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q16 Net-_Q16-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q6 Net-_Q2-Pad2_ Net-_Q3-Pad3_ Net-_Q11-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_PNP +Q22 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/LM321/LM321.cir.out b/library/SubcircuitLibrary/LM321/LM321.cir.out new file mode 100644 index 00000000..17548c8f --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.cir.out @@ -0,0 +1,52 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm321\lm321.cir + +.include PNP.lib +.include NPN.lib +.include NJF.lib +* u1 net-_q12-pad2_ net-_q3-pad2_ net-_j1-pad1_ net-_q24-pad3_ net-_j1-pad2_ port +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q19 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q3-pad3_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A +q12 net-_j1-pad2_ net-_q12-pad2_ net-_q11-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q2-pad2_ net-_q1-pad1_ Q2N2907A +q9 net-_c1-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222 +q17 net-_q15-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q18 net-_j1-pad2_ net-_q16-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_q16-pad1_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q21 net-_c1-pad1_ net-_q15-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +q24 net-_c1-pad1_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r1 net-_q23-pad3_ net-_q24-pad2_ 40k +q23 net-_j1-pad1_ net-_c1-pad1_ net-_q23-pad3_ Q2N2222 +q25 net-_j1-pad1_ net-_q23-pad3_ net-_q24-pad2_ Q2N2222 +r2 net-_q24-pad2_ net-_q24-pad3_ 25 +q26 net-_j1-pad2_ net-_c1-pad1_ net-_q24-pad3_ Q2N2907A +q27 net-_q24-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_q1-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r3 net-_q28-pad3_ net-_j1-pad2_ 2k +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q31 net-_j1-pad1_ net-_j1-pad3_ net-_q30-pad2_ Q2N2222 +q29 net-_j1-pad3_ net-_j1-pad3_ net-_q28-pad2_ Q2N2222 +q30 net-_q28-pad2_ net-_q30-pad2_ net-_j1-pad2_ Q2N2222 +r4 net-_q30-pad2_ net-_j1-pad2_ 2.4k +q7 net-_q11-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q16 net-_q16-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_q2-pad2_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q8 net-_c1-pad2_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q22 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM321/LM321.pro b/library/SubcircuitLibrary/LM321/LM321.pro new file mode 100644 index 00000000..ef711b9b --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:32:10 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM321/LM321.sch b/library/SubcircuitLibrary/LM321/LM321.sch new file mode 100644 index 00000000..b7b73924 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.sch @@ -0,0 +1,821 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM321-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 62DAF186 +P 10300 950 +F 0 "U1" H 10350 1050 30 0000 C CNN +F 1 "PORT" H 10300 950 30 0000 C CNN +F 2 "" H 10300 950 60 0000 C CNN +F 3 "" H 10300 950 60 0000 C CNN + 3 10300 950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DAF1ED +P 10300 3200 +F 0 "U1" H 10350 3300 30 0000 C CNN +F 1 "PORT" H 10300 3200 30 0000 C CNN +F 2 "" H 10300 3200 60 0000 C CNN +F 3 "" H 10300 3200 60 0000 C CNN + 4 10300 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62DAF4F7 +P 10350 6000 +F 0 "U1" H 10400 6100 30 0000 C CNN +F 1 "PORT" H 10350 6000 30 0000 C CNN +F 2 "" H 10350 6000 60 0000 C CNN +F 3 "" H 10350 6000 60 0000 C CNN + 5 10350 6000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62DAF744 +P 850 3600 +F 0 "U1" H 900 3700 30 0000 C CNN +F 1 "PORT" H 850 3600 30 0000 C CNN +F 2 "" H 850 3600 60 0000 C CNN +F 3 "" H 850 3600 60 0000 C CNN + 1 850 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DAF7B7 +P 850 4550 +F 0 "U1" H 900 4650 30 0000 C CNN +F 1 "PORT" H 850 4550 30 0000 C CNN +F 2 "" H 850 4550 60 0000 C CNN +F 3 "" H 850 4550 60 0000 C CNN + 2 850 4550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 62E060F9 +P 1450 1650 +F 0 "Q1" H 1350 1700 50 0000 R CNN +F 1 "eSim_PNP" H 1400 1800 50 0000 R CNN +F 2 "" H 1650 1750 29 0000 C CNN +F 3 "" H 1450 1650 60 0000 C CNN + 1 1450 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 62E060FA +P 3950 1450 +F 0 "Q14" H 3850 1500 50 0000 R CNN +F 1 "eSim_PNP" H 3900 1600 50 0000 R CNN +F 2 "" H 4150 1550 29 0000 C CNN +F 3 "" H 3950 1450 60 0000 C CNN + 1 3950 1450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 62E060FB +P 6100 1400 +F 0 "Q19" H 6000 1450 50 0000 R CNN +F 1 "eSim_PNP" H 6050 1550 50 0000 R CNN +F 2 "" H 6300 1500 29 0000 C CNN +F 3 "" H 6100 1400 60 0000 C CNN + 1 6100 1400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 62E060FC +P 2300 3950 +F 0 "Q4" H 2200 4000 50 0000 R CNN +F 1 "eSim_PNP" H 2250 4100 50 0000 R CNN +F 2 "" H 2500 4050 29 0000 C CNN +F 3 "" H 2300 3950 60 0000 C CNN + 1 2300 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 62E060FD +P 3100 3950 +F 0 "Q11" H 3000 4000 50 0000 R CNN +F 1 "eSim_PNP" H 3050 4100 50 0000 R CNN +F 2 "" H 3300 4050 29 0000 C CNN +F 3 "" H 3100 3950 60 0000 C CNN + 1 3100 3950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 62E060FE +P 1900 4550 +F 0 "Q3" H 1800 4600 50 0000 R CNN +F 1 "eSim_PNP" H 1850 4700 50 0000 R CNN +F 2 "" H 2100 4650 29 0000 C CNN +F 3 "" H 1900 4550 60 0000 C CNN + 1 1900 4550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 62E060FF +P 3450 4650 +F 0 "Q12" H 3350 4700 50 0000 R CNN +F 1 "eSim_PNP" H 3400 4800 50 0000 R CNN +F 2 "" H 3650 4750 29 0000 C CNN +F 3 "" H 3450 4650 60 0000 C CNN + 1 3450 4650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 62E06100 +P 1650 5000 +F 0 "Q2" H 1550 5050 50 0000 R CNN +F 1 "eSim_PNP" H 1600 5150 50 0000 R CNN +F 2 "" H 1850 5100 29 0000 C CNN +F 3 "" H 1650 5000 60 0000 C CNN + 1 1650 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 62E06101 +P 3000 5500 +F 0 "Q9" H 2900 5550 50 0000 R CNN +F 1 "eSim_NPN" H 2950 5650 50 0000 R CNN +F 2 "" H 3200 5600 29 0000 C CNN +F 3 "" H 3000 5500 60 0000 C CNN + 1 3000 5500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 62E06102 +P 2400 5500 +F 0 "Q5" H 2300 5550 50 0000 R CNN +F 1 "eSim_NPN" H 2350 5650 50 0000 R CNN +F 2 "" H 2600 5600 29 0000 C CNN +F 3 "" H 2400 5500 60 0000 C CNN + 1 2400 5500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 62E06103 +P 3900 5000 +F 0 "Q13" H 3800 5050 50 0000 R CNN +F 1 "eSim_PNP" H 3850 5150 50 0000 R CNN +F 2 "" H 4100 5100 29 0000 C CNN +F 3 "" H 3900 5000 60 0000 C CNN + 1 3900 5000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 62E06104 +P 4500 4700 +F 0 "Q15" H 4400 4750 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4850 50 0000 R CNN +F 2 "" H 4700 4800 29 0000 C CNN +F 3 "" H 4500 4700 60 0000 C CNN + 1 4500 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 62E06105 +P 4700 5450 +F 0 "Q17" H 4600 5500 50 0000 R CNN +F 1 "eSim_NPN" H 4650 5600 50 0000 R CNN +F 2 "" H 4900 5550 29 0000 C CNN +F 3 "" H 4700 5450 60 0000 C CNN + 1 4700 5450 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 62E06106 +P 5400 4700 +F 0 "Q18" H 5300 4750 50 0000 R CNN +F 1 "eSim_PNP" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 62E06107 +P 6100 5200 +F 0 "Q20" H 6000 5250 50 0000 R CNN +F 1 "eSim_NPN" H 6050 5350 50 0000 R CNN +F 2 "" H 6300 5300 29 0000 C CNN +F 3 "" H 6100 5200 60 0000 C CNN + 1 6100 5200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 62E06108 +P 6300 4150 +F 0 "Q21" H 6200 4200 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4300 50 0000 R CNN +F 2 "" H 6500 4250 29 0000 C CNN +F 3 "" H 6300 4150 60 0000 C CNN + 1 6300 4150 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 62E06109 +P 4400 2950 +F 0 "C1" H 4425 3050 50 0000 L CNN +F 1 "5p" H 4425 2850 50 0000 L CNN +F 2 "" H 4438 2800 30 0000 C CNN +F 3 "" H 4400 2950 60 0000 C CNN + 1 4400 2950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 62E0610A +P 7200 2650 +F 0 "Q24" H 7100 2700 50 0000 R CNN +F 1 "eSim_NPN" H 7150 2800 50 0000 R CNN +F 2 "" H 7400 2750 29 0000 C CNN +F 3 "" H 7200 2650 60 0000 C CNN + 1 7200 2650 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62E0610B +P 7500 2100 +F 0 "R1" H 7550 2230 50 0000 C CNN +F 1 "40k" H 7550 2050 50 0000 C CNN +F 2 "" H 7550 2080 30 0000 C CNN +F 3 "" V 7550 2150 30 0000 C CNN + 1 7500 2100 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q23 +U 1 1 62E0610C +P 7000 1550 +F 0 "Q23" H 6900 1600 50 0000 R CNN +F 1 "eSim_NPN" H 6950 1700 50 0000 R CNN +F 2 "" H 7200 1650 29 0000 C CNN +F 3 "" H 7000 1550 60 0000 C CNN + 1 7000 1550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 62E0610D +P 7800 1900 +F 0 "Q25" H 7700 1950 50 0000 R CNN +F 1 "eSim_NPN" H 7750 2050 50 0000 R CNN +F 2 "" H 8000 2000 29 0000 C CNN +F 3 "" H 7800 1900 60 0000 C CNN + 1 7800 1900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 62E0610E +P 7850 2850 +F 0 "R2" H 7900 2980 50 0000 C CNN +F 1 "25" H 7900 2800 50 0000 C CNN +F 2 "" H 7900 2830 30 0000 C CNN +F 3 "" V 7900 2900 30 0000 C CNN + 1 7850 2850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 62E0610F +P 7800 3850 +F 0 "Q26" H 7700 3900 50 0000 R CNN +F 1 "eSim_PNP" H 7750 4000 50 0000 R CNN +F 2 "" H 8000 3950 29 0000 C CNN +F 3 "" H 7800 3850 60 0000 C CNN + 1 7800 3850 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 62E06110 +P 8050 5200 +F 0 "Q27" H 7950 5250 50 0000 R CNN +F 1 "eSim_NPN" H 8000 5350 50 0000 R CNN +F 2 "" H 8250 5300 29 0000 C CNN +F 3 "" H 8050 5200 60 0000 C CNN + 1 8050 5200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q28 +U 1 1 62E06111 +P 8650 3800 +F 0 "Q28" H 8550 3850 50 0000 R CNN +F 1 "eSim_NPN" H 8600 3950 50 0000 R CNN +F 2 "" H 8850 3900 29 0000 C CNN +F 3 "" H 8650 3800 60 0000 C CNN + 1 8650 3800 + -1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 62E06112 +P 8500 4500 +F 0 "R3" H 8550 4630 50 0000 C CNN +F 1 "2k" H 8550 4450 50 0000 C CNN +F 2 "" H 8550 4480 30 0000 C CNN +F 3 "" V 8550 4550 30 0000 C CNN + 1 8500 4500 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J1 +U 1 1 62E06113 +P 9100 1400 +F 0 "J1" H 9000 1450 50 0000 R CNN +F 1 "jfet_n" H 9050 1550 50 0000 R CNN +F 2 "" H 9300 1500 29 0000 C CNN +F 3 "" H 9100 1400 60 0000 C CNN + 1 9100 1400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 62E06114 +P 9550 2350 +F 0 "Q31" H 9450 2400 50 0000 R CNN +F 1 "eSim_NPN" H 9500 2500 50 0000 R CNN +F 2 "" H 9750 2450 29 0000 C CNN +F 3 "" H 9550 2350 60 0000 C CNN + 1 9550 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q29 +U 1 1 62E06115 +P 9100 2350 +F 0 "Q29" H 9000 2400 50 0000 R CNN +F 1 "eSim_NPN" H 9050 2500 50 0000 R CNN +F 2 "" H 9300 2450 29 0000 C CNN +F 3 "" H 9100 2350 60 0000 C CNN + 1 9100 2350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q30 +U 1 1 62E06116 +P 9100 4550 +F 0 "Q30" H 9000 4600 50 0000 R CNN +F 1 "eSim_NPN" H 9050 4700 50 0000 R CNN +F 2 "" H 9300 4650 29 0000 C CNN +F 3 "" H 9100 4550 60 0000 C CNN + 1 9100 4550 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 62E06117 +P 9600 5350 +F 0 "R4" H 9650 5480 50 0000 C CNN +F 1 "2.4k" H 9650 5300 50 0000 C CNN +F 2 "" H 9650 5330 30 0000 C CNN +F 3 "" V 9650 5400 30 0000 C CNN + 1 9600 5350 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 62E06118 +P 2600 1600 +F 0 "Q7" H 2500 1650 50 0000 R CNN +F 1 "eSim_PNP" H 2550 1750 50 0000 R CNN +F 2 "" H 2800 1700 29 0000 C CNN +F 3 "" H 2600 1600 60 0000 C CNN + 1 2600 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 62E06119 +P 3050 1650 +F 0 "Q10" H 2950 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3000 1800 50 0000 R CNN +F 2 "" H 3250 1750 29 0000 C CNN +F 3 "" H 3050 1650 60 0000 C CNN + 1 3050 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q16 +U 1 1 62E0611A +P 4550 1400 +F 0 "Q16" H 4450 1450 50 0000 R CNN +F 1 "eSim_PNP" H 4500 1550 50 0000 R CNN +F 2 "" H 4750 1500 29 0000 C CNN +F 3 "" H 4550 1400 60 0000 C CNN + 1 4550 1400 + 1 0 0 1 +$EndComp +Wire Wire Line + 1550 950 10050 950 +Wire Wire Line + 4050 1250 4050 950 +Connection ~ 4050 950 +Wire Wire Line + 6200 1200 6200 950 +Connection ~ 6200 950 +Wire Wire Line + 7100 1350 7100 950 +Connection ~ 7100 950 +Wire Wire Line + 7900 1700 7900 950 +Connection ~ 7900 950 +Wire Wire Line + 3750 1200 6300 1200 +Wire Wire Line + 7100 1750 7100 1900 +Wire Wire Line + 7100 1900 7600 1900 +Wire Wire Line + 2400 3750 3000 3750 +Wire Wire Line + 1550 1850 1550 4800 +Connection ~ 2700 3750 +Wire Wire Line + 2100 3950 2000 3950 +Wire Wire Line + 2000 3950 2000 4350 +Wire Wire Line + 1100 4550 1700 4550 +Wire Wire Line + 2000 4200 2400 4200 +Connection ~ 2000 4200 +Wire Wire Line + 2800 2950 2800 5000 +Wire Wire Line + 2800 2950 4250 2950 +Wire Wire Line + 3000 4200 3350 4200 +Wire Wire Line + 3300 3950 3350 3950 +Wire Wire Line + 3350 3950 3350 4450 +Wire Wire Line + 3000 4200 3000 4150 +Connection ~ 3350 4200 +Wire Wire Line + 2600 5500 2800 5500 +Wire Wire Line + 2400 4200 2400 4150 +Wire Wire Line + 2600 4500 2600 5500 +Connection ~ 2600 5500 +Wire Wire Line + 1850 5000 2600 5000 +Connection ~ 2600 5000 +Wire Wire Line + 2300 5300 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 2000 4750 2000 6000 +Wire Wire Line + 1550 5200 1550 6000 +Wire Wire Line + 2300 6000 2300 5700 +Wire Wire Line + 3100 6000 3100 5700 +Wire Wire Line + 2800 5000 3700 5000 +Wire Wire Line + 3350 6000 3350 4850 +Wire Wire Line + 3100 5300 3100 5000 +Connection ~ 3100 5000 +Wire Wire Line + 3650 4650 3750 4650 +Wire Wire Line + 3750 4650 3750 3600 +Wire Wire Line + 3750 3600 1100 3600 +Wire Wire Line + 4000 2200 4000 4800 +Wire Wire Line + 4000 4700 4300 4700 +Wire Wire Line + 6700 2950 4550 2950 +Wire Wire Line + 4000 6000 4000 5200 +Wire Wire Line + 4600 4450 5300 4450 +Connection ~ 4000 4700 +Wire Wire Line + 4600 6000 4600 5650 +Wire Wire Line + 4600 4900 4600 5250 +Wire Wire Line + 5300 4450 5300 4500 +Wire Wire Line + 4600 4500 4600 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/dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.sch.svg @@ -0,0 +1,10007 @@ + + + +SVG Picture created as LM321.sch.svg date 2022/09/24 18:05:04 + Picture generated by Eeschema-SVG + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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net-_j1-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\lm321\lm321.cir +.include PNP.lib +.include NPN.lib +.include NJF.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q19 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q3-pad3_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A +q12 net-_j1-pad2_ net-_q12-pad2_ net-_q11-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q2-pad2_ net-_q1-pad1_ Q2N2907A +q9 net-_c1-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222 +q17 net-_q15-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q18 net-_j1-pad2_ net-_q16-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_q16-pad1_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q21 net-_c1-pad1_ net-_q15-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +q24 net-_c1-pad1_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r1 net-_q23-pad3_ net-_q24-pad2_ 40k +q23 net-_j1-pad1_ net-_c1-pad1_ net-_q23-pad3_ Q2N2222 +q25 net-_j1-pad1_ net-_q23-pad3_ net-_q24-pad2_ Q2N2222 +r2 net-_q24-pad2_ net-_q24-pad3_ 25 +q26 net-_j1-pad2_ net-_c1-pad1_ net-_q24-pad3_ Q2N2907A +q27 net-_q24-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_q1-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r3 net-_q28-pad3_ net-_j1-pad2_ 2k +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q31 net-_j1-pad1_ net-_j1-pad3_ net-_q30-pad2_ Q2N2222 +q29 net-_j1-pad3_ net-_j1-pad3_ net-_q28-pad2_ Q2N2222 +q30 net-_q28-pad2_ net-_q30-pad2_ net-_j1-pad2_ Q2N2222 +r4 net-_q30-pad2_ net-_j1-pad2_ 2.4k +q7 net-_q11-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q16 net-_q16-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_q2-pad2_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q8 net-_c1-pad2_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q22 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +* Control Statements + +.ends LM321 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml b/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml new file mode 100644 index 00000000..8b38814c --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM321/NJF.lib b/library/SubcircuitLibrary/LM321/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM321/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM321/NPN.lib b/library/SubcircuitLibrary/LM321/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM321/PNP.lib b/library/SubcircuitLibrary/LM321/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM321/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM321/README.md b/library/SubcircuitLibrary/LM321/README.md new file mode 100644 index 00000000..ad011f2a --- /dev/null +++ b/library/SubcircuitLibrary/LM321/README.md @@ -0,0 +1,35 @@ + +# LM321 Operational Amplifier IC + +LM321 is a 5 pin Op-Amp IC. It has differential input, is internally compensated. Supply voltage ranges from 3V to 32V. Output is short circuit protected. Its output stage is class B, comprising of push-pull transistors. Hence output contains crossover distortion near mid-rail where neither push or pull transistor is conducting. + + +## Usage/Examples + +Inverting/Non-Inverting Amplifier + +Integrator/Summer + +Differential Amplifier + +Differentiator + +Schmitt Trigger + +Comparators + + +## Documentation + +To know the details of LM321 IC please refer to this link [LM321_datasheet.](https://www.onsemi.com/pdf/datasheet/lm321-d.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM321/analysis b/library/SubcircuitLibrary/LM321/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From a939d001f0acea4b750eb7e9aae4e15c3fce46bd Mon Sep 17 00:00:00 2001 From: Arpit Sharma Date: Fri, 21 Oct 2022 23:09:22 +0530 Subject: LM393 Analog Comparator IC --- library/SubcircuitLibrary/LM393/D.lib | 2 + library/SubcircuitLibrary/LM393/LM393-cache.lib | 146 +++ library/SubcircuitLibrary/LM393/LM393.cir | 61 ++ library/SubcircuitLibrary/LM393/LM393.cir.out | 66 ++ library/SubcircuitLibrary/LM393/LM393.pro | 81 ++ library/SubcircuitLibrary/LM393/LM393.sch | 1033 ++++++++++++++++++++ library/SubcircuitLibrary/LM393/LM393.sub | 60 ++ .../LM393/LM393_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM393/NJF.lib | 4 + library/SubcircuitLibrary/LM393/NPN.lib | 4 + library/SubcircuitLibrary/LM393/PNP.lib | 4 + library/SubcircuitLibrary/LM393/README.md | 35 + library/SubcircuitLibrary/LM393/analysis | 1 + 13 files changed, 1498 insertions(+) create mode 100644 library/SubcircuitLibrary/LM393/D.lib create mode 100644 library/SubcircuitLibrary/LM393/LM393-cache.lib create mode 100644 library/SubcircuitLibrary/LM393/LM393.cir create mode 100644 library/SubcircuitLibrary/LM393/LM393.cir.out create mode 100644 library/SubcircuitLibrary/LM393/LM393.pro create mode 100644 library/SubcircuitLibrary/LM393/LM393.sch create mode 100644 library/SubcircuitLibrary/LM393/LM393.sub create mode 100644 library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM393/NJF.lib create mode 100644 library/SubcircuitLibrary/LM393/NPN.lib create mode 100644 library/SubcircuitLibrary/LM393/PNP.lib create mode 100644 library/SubcircuitLibrary/LM393/README.md create mode 100644 library/SubcircuitLibrary/LM393/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/LM393/D.lib b/library/SubcircuitLibrary/LM393/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM393/LM393-cache.lib b/library/SubcircuitLibrary/LM393/LM393-cache.lib new file mode 100644 index 00000000..8ff65b6b --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM393/LM393.cir b/library/SubcircuitLibrary/LM393/LM393.cir new file mode 100644 index 00000000..4d9c6b46 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.cir @@ -0,0 +1,61 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM393\LM393.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/29/22 20:35:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +R2 Net-_Q1-Pad2_ Net-_Q1-Pad1_ 2k +Q4 Net-_J1-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q5 Net-_Q2-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q8 Net-_D4-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q2-Pad3_ eSim_NPN +R1 Net-_Q2-Pad3_ Net-_D3-Pad2_ 4.6k +J1 Net-_J1-Pad1_ Net-_D3-Pad2_ Net-_J1-Pad3_ jfet_n +Q3 Net-_J1-Pad3_ Net-_Q2-Pad3_ Net-_D3-Pad2_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q6 Net-_D3-Pad2_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q9 Net-_D3-Pad1_ Net-_D1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q12 Net-_Q11-Pad1_ Net-_D4-Pad2_ Net-_Q10-Pad1_ eSim_PNP +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q11 Net-_Q11-Pad1_ Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_NPN +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q13 Net-_D3-Pad2_ Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_PNP +D5 Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q15 Net-_Q14-Pad1_ Net-_Q11-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_D3-Pad2_ eSim_NPN +R3 Net-_J1-Pad1_ Net-_Q7-Pad3_ 2.1k +U1 Net-_J1-Pad1_ Net-_D1-Pad1_ Net-_D5-Pad1_ Net-_Q16-Pad1_ Net-_D3-Pad2_ Net-_D6-Pad1_ Net-_D10-Pad1_ Net-_Q32-Pad1_ PORT +Q7 Net-_D2-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_J1-Pad1_ eSim_PNP +R5 Net-_Q17-Pad2_ Net-_Q17-Pad1_ 2k +Q20 Net-_J2-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q21 Net-_Q18-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q24 Net-_D9-Pad1_ Net-_Q17-Pad1_ Net-_Q23-Pad3_ eSim_PNP +Q26 Net-_Q25-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q30 Net-_Q30-Pad1_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q18 Net-_Q17-Pad1_ Net-_J2-Pad3_ Net-_Q18-Pad3_ eSim_NPN +R4 Net-_Q18-Pad3_ Net-_D3-Pad2_ 4.6k +J2 Net-_J1-Pad1_ Net-_D3-Pad2_ Net-_J2-Pad3_ jfet_n +Q19 Net-_J2-Pad3_ Net-_Q18-Pad3_ Net-_D3-Pad2_ eSim_NPN +D7 Net-_D7-Pad1_ Net-_D6-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q22 Net-_D3-Pad2_ Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_PNP +Q25 Net-_D8-Pad1_ Net-_D6-Pad2_ Net-_Q25-Pad3_ eSim_PNP +Q28 Net-_Q27-Pad1_ Net-_D10-Pad2_ Net-_Q25-Pad3_ eSim_PNP +D8 Net-_D8-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q27 Net-_Q27-Pad1_ Net-_D8-Pad1_ Net-_D3-Pad2_ eSim_NPN +D9 Net-_D9-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q29 Net-_D3-Pad2_ Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_PNP +D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q31 Net-_Q30-Pad1_ Net-_Q27-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q32 Net-_Q32-Pad1_ Net-_Q30-Pad1_ Net-_D3-Pad2_ eSim_NPN +R6 Net-_J1-Pad1_ Net-_Q23-Pad3_ 2.1k +Q23 Net-_D7-Pad1_ Net-_Q17-Pad1_ Net-_Q23-Pad3_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/LM393/LM393.cir.out b/library/SubcircuitLibrary/LM393/LM393.cir.out new file mode 100644 index 00000000..57a7fed1 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.cir.out @@ -0,0 +1,66 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm393\lm393.cir + +.include PNP.lib +.include NPN.lib +.include NJF.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad2_ net-_q1-pad1_ 2k +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +r1 net-_q2-pad3_ net-_d3-pad2_ 4.6k +j1 net-_j1-pad1_ net-_d3-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_j1-pad3_ net-_q2-pad3_ net-_d3-pad2_ Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q13 net-_d3-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +q15 net-_q14-pad1_ net-_q11-pad1_ net-_d3-pad2_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d3-pad2_ Q2N2222 +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +* u1 net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ net-_d3-pad2_ net-_d6-pad1_ net-_d10-pad1_ net-_q32-pad1_ port +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad1_ Q2N2907A +r5 net-_q17-pad2_ net-_q17-pad1_ 2k +q20 net-_j2-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q21 net-_q18-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q24 net-_d9-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +q26 net-_q25-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q30 net-_q30-pad1_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q18 net-_q17-pad1_ net-_j2-pad3_ net-_q18-pad3_ Q2N2222 +r4 net-_q18-pad3_ net-_d3-pad2_ 4.6k +j2 net-_j1-pad1_ net-_d3-pad2_ net-_j2-pad3_ J2N3819 +q19 net-_j2-pad3_ net-_q18-pad3_ net-_d3-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +q22 net-_d3-pad2_ net-_d6-pad1_ net-_d6-pad2_ Q2N2907A +q25 net-_d8-pad1_ net-_d6-pad2_ net-_q25-pad3_ Q2N2907A +q28 net-_q27-pad1_ net-_d10-pad2_ net-_q25-pad3_ Q2N2907A +d8 net-_d8-pad1_ net-_d3-pad2_ 1N4148 +q27 net-_q27-pad1_ net-_d8-pad1_ net-_d3-pad2_ Q2N2222 +d9 net-_d9-pad1_ net-_d10-pad2_ 1N4148 +q29 net-_d3-pad2_ net-_d10-pad1_ net-_d10-pad2_ Q2N2907A +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q31 net-_q30-pad1_ net-_q27-pad1_ net-_d3-pad2_ Q2N2222 +q32 net-_q32-pad1_ net-_q30-pad1_ net-_d3-pad2_ Q2N2222 +r6 net-_j1-pad1_ net-_q23-pad3_ 2.1k +q23 net-_d7-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM393/LM393.pro b/library/SubcircuitLibrary/LM393/LM393.pro new file mode 100644 index 00000000..fd0582ba --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:31:43 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM393/LM393.sch b/library/SubcircuitLibrary/LM393/LM393.sch new file mode 100644 index 00000000..5fe92798 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.sch @@ -0,0 +1,1033 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM393-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 450 5800 11150 5800 +Wire Wire Line + 6000 5800 6000 6300 +$Comp +L PORT U1 +U 5 1 62EFFD91 +P 5750 6300 +F 0 "U1" H 5800 6400 30 0000 C CNN +F 1 "PORT" H 5750 6300 30 0000 C CNN +F 2 "" H 5750 6300 60 0000 C CNN +F 3 "" H 5750 6300 60 0000 C CNN + 5 5750 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62EFFD92 +P 350 1900 +F 0 "U1" H 400 2000 30 0000 C CNN +F 1 "PORT" H 350 1900 30 0000 C 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H 3300 2030 50 0000 C CNN +F 1 "2.1k" H 3300 1850 50 0000 C CNN +F 2 "" H 3300 1880 30 0000 C CNN +F 3 "" V 3300 1950 30 0000 C CNN + 1 3250 1900 + 0 1 1 0 +$EndComp +Wire Wire Line + 1250 2000 1250 2000 +Wire Wire Line + 1550 2000 1550 2300 +Wire Wire Line + 1550 2300 950 2300 +Wire Wire Line + 950 2200 950 4200 +Wire Wire Line + 950 1650 950 1800 +Wire Wire Line + 1600 2750 1600 4700 +Wire Wire Line + 2300 4900 2300 2750 +Wire Wire Line + 2900 2750 2900 3100 +Wire Wire Line + 4000 1650 4000 2350 +Wire Wire Line + 4000 2750 4000 3900 +Wire Wire Line + 5350 1650 5350 2100 +Connection ~ 4000 1650 +Wire Wire Line + 5350 2500 5350 4600 +Connection ~ 950 2300 +Wire Wire Line + 950 4600 950 5150 +Wire Wire Line + 950 5450 950 5800 +Wire Wire Line + 750 3750 750 4400 +Wire Wire Line + 450 5800 450 3550 +Wire Wire Line + 750 1650 750 3350 +Connection ~ 950 1650 +Connection ~ 1600 4400 +Wire Wire Line + 750 4400 1600 4400 +Connection ~ 1250 4400 +Wire Wire Line + 950 4900 2300 4900 +Connection ~ 950 4900 +Wire Wire Line + 1600 5800 1600 5100 +Connection ~ 950 5800 +Connection ~ 1300 4900 +Wire Wire Line + 2900 3400 2900 4100 +Wire Wire Line + 2450 1400 2450 4500 +Wire Wire Line + 2800 3700 2900 3700 +Connection ~ 2900 3700 +Wire Wire Line + 2500 3700 2450 3700 +Connection ~ 2450 3700 +Wire Wire Line + 2750 4300 2750 4100 +Wire Wire Line + 2750 4100 3300 4100 +Wire Wire Line + 2750 5800 2750 4700 +Connection ~ 1600 5800 +Connection ~ 2900 4100 +Wire Wire Line + 3600 3900 4100 3900 +Connection ~ 4000 3900 +Wire Wire Line + 3600 4300 3600 5300 +Wire Wire Line + 3600 5800 3600 5600 +Connection ~ 2750 5800 +Wire Wire Line + 3600 5150 3800 5150 +Connection ~ 3600 5150 +Wire Wire Line + 4100 5800 4100 5350 +Connection ~ 3600 5800 +Wire Wire Line + 4100 4300 4100 4950 +Wire Wire Line + 4500 2900 4500 3100 +Wire Wire Line + 4400 4100 4700 4100 +Wire Wire Line + 4700 4100 4700 4250 +Wire Wire Line + 4500 3400 4500 4100 +Connection ~ 4500 4100 +Wire Wire Line + 4700 5800 4700 4650 +Connection ~ 4100 5800 +Wire Wire Line + 4650 3650 4500 3650 +Connection ~ 4500 3650 +Wire Wire Line + 5100 4450 5000 4450 +Wire Wire Line + 5100 1400 5100 4450 +Wire Wire Line + 5100 3650 4950 3650 +Connection ~ 5100 3650 +Wire Wire Line + 5050 4800 4100 4800 +Connection ~ 4100 4800 +Wire Wire Line + 5350 5800 5350 5000 +Connection ~ 4700 5800 +Wire Wire Line + 5450 4400 5350 4400 +Connection ~ 5350 4400 +Wire Wire Line + 5750 5800 5750 4600 +Connection ~ 5350 5800 +Wire Wire Line + 5750 4200 5750 1500 +Connection ~ 750 1650 +$Comp +L PORT U? +U 1 1 632F6D0D +P 2200 1400 +F 0 "U?" H 2250 1500 30 0000 C CNN +F 1 "PORT" H 2200 1400 30 0000 C CNN +F 2 "" H 2200 1400 60 0000 C CNN +F 3 "" H 2200 1400 60 0000 C CNN + 1 2200 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 1 1 632F6D13 +P 4850 1400 +F 0 "U?" H 4900 1500 30 0000 C CNN +F 1 "PORT" H 4850 1400 30 0000 C CNN +F 2 "" H 4850 1400 60 0000 C CNN +F 3 "" H 4850 1400 60 0000 C CNN + 1 4850 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 1 1 632F6D19 +P 5750 1250 +F 0 "U?" H 5800 1350 30 0000 C CNN +F 1 "PORT" H 5750 1250 30 0000 C CNN +F 2 "" H 5750 1250 60 0000 C CNN +F 3 "" H 5750 1250 60 0000 C CNN + 1 5750 1250 + 0 1 1 0 +$EndComp +Wire Wire Line + 1600 2350 1600 1900 +Wire Wire Line + 1600 1900 2300 1900 +Wire Wire Line + 2300 1900 2300 2350 +Wire Wire Line + 2000 1900 2000 1650 +Connection ~ 2000 1650 +Connection ~ 2000 1900 +Wire Wire Line + 1900 2550 2000 2550 +Wire Wire Line + 1550 2150 1950 2150 +Wire Wire Line + 1950 2150 1950 2550 +Connection ~ 1950 2550 +Connection ~ 1550 2150 +$Comp +L eSim_PNP Q? +U 1 1 632F6D2D +P 3000 2550 +F 0 "Q?" H 2900 2600 50 0000 R CNN +F 1 "eSim_PNP" H 3300 2800 50 0000 R CNN +F 2 "" H 3200 2650 29 0000 C CNN +F 3 "" H 3000 2550 60 0000 C CNN + 1 3000 2550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 2550 3300 2550 +Wire Wire Line + 1950 2300 5050 2300 +Wire Wire Line + 3250 2300 3250 2550 +Connection ~ 3250 2550 +Connection ~ 1950 2300 +Wire Wire Line + 3300 1800 3300 1650 +Connection ~ 3300 1650 +Wire Wire Line + 2900 2350 2900 2200 +Wire Wire Line + 2900 2200 3600 2200 +Wire Wire Line + 3600 2200 3600 2350 +Wire Wire Line + 3300 2200 3300 2100 +Connection ~ 3300 2200 +Wire Wire Line + 4500 2900 3600 2900 +Wire Wire Line + 3600 2900 3600 2750 +Wire Wire Line + 3700 2300 3700 2550 +Connection ~ 3250 2300 +Connection ~ 3700 2300 +Connection ~ 5350 1650 +Connection ~ 5750 5800 +Connection ~ 6000 5800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM393/LM393.sub b/library/SubcircuitLibrary/LM393/LM393.sub new file mode 100644 index 00000000..b854038f --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.sub @@ -0,0 +1,60 @@ +* Subcircuit LM393 +.subckt LM393 net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ net-_d3-pad2_ net-_d6-pad1_ net-_d10-pad1_ net-_q32-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm393\lm393.cir +.include PNP.lib +.include NPN.lib +.include NJF.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad2_ net-_q1-pad1_ 2k +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +r1 net-_q2-pad3_ net-_d3-pad2_ 4.6k +j1 net-_j1-pad1_ net-_d3-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_j1-pad3_ net-_q2-pad3_ net-_d3-pad2_ Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q13 net-_d3-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +q15 net-_q14-pad1_ net-_q11-pad1_ net-_d3-pad2_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d3-pad2_ Q2N2222 +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad1_ Q2N2907A +r5 net-_q17-pad2_ net-_q17-pad1_ 2k +q20 net-_j2-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q21 net-_q18-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q24 net-_d9-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +q26 net-_q25-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q30 net-_q30-pad1_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q18 net-_q17-pad1_ net-_j2-pad3_ net-_q18-pad3_ Q2N2222 +r4 net-_q18-pad3_ net-_d3-pad2_ 4.6k +j2 net-_j1-pad1_ net-_d3-pad2_ net-_j2-pad3_ J2N3819 +q19 net-_j2-pad3_ net-_q18-pad3_ net-_d3-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +q22 net-_d3-pad2_ net-_d6-pad1_ net-_d6-pad2_ Q2N2907A +q25 net-_d8-pad1_ net-_d6-pad2_ net-_q25-pad3_ Q2N2907A +q28 net-_q27-pad1_ net-_d10-pad2_ net-_q25-pad3_ Q2N2907A +d8 net-_d8-pad1_ net-_d3-pad2_ 1N4148 +q27 net-_q27-pad1_ net-_d8-pad1_ net-_d3-pad2_ Q2N2222 +d9 net-_d9-pad1_ net-_d10-pad2_ 1N4148 +q29 net-_d3-pad2_ net-_d10-pad1_ net-_d10-pad2_ Q2N2907A +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q31 net-_q30-pad1_ net-_q27-pad1_ net-_d3-pad2_ Q2N2222 +q32 net-_q32-pad1_ net-_q30-pad1_ net-_d3-pad2_ Q2N2222 +r6 net-_j1-pad1_ net-_q23-pad3_ 2.1k +q23 net-_d7-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +* Control Statements + +.ends LM393 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml b/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml new file mode 100644 index 00000000..babb60e4 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM393/NJF.lib b/library/SubcircuitLibrary/LM393/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM393/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM393/NPN.lib b/library/SubcircuitLibrary/LM393/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM393/PNP.lib b/library/SubcircuitLibrary/LM393/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM393/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM393/README.md b/library/SubcircuitLibrary/LM393/README.md new file mode 100644 index 00000000..d0b0abaf --- /dev/null +++ b/library/SubcircuitLibrary/LM393/README.md @@ -0,0 +1,35 @@ + +# LM393 Comparator IC + +LM393 is a Low power, low offset voltage comparator IC. It has two channels sharing common biasing. It is a high precision comparator with a low offset voltage of 2 mV. It has various applications such as in limit comparators, A/D convertors, wave shaping circuits etc. + + +## Usage/Examples + +Basic Comparator + +CMOS/TTL Driver + +Pulse Train Generator + +Crystal Controlled Oscillator + +Positive/Negative Floating Regulator + +Two-Decade High Frequency VCO + + +## Documentation + +To know the details of LM393 IC please refer to this link [LM393_datasheet.](https://www.ti.com/lit/ds/symlink/lm393-n.pdf?ts=1665939843518&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM393/analysis b/library/SubcircuitLibrary/LM393/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 8bea2eb6540f75495e26b430c0dc6373489641e5 Mon Sep 17 00:00:00 2001 From: Arpit Sharma Date: Fri, 21 Oct 2022 23:09:53 +0530 Subject: LM723 Adjustable Voltage Regulator IC --- library/SubcircuitLibrary/LM723/D.lib | 2 + library/SubcircuitLibrary/LM723/LM723-cache.lib | 182 +++ library/SubcircuitLibrary/LM723/LM723.cir | 69 + library/SubcircuitLibrary/LM723/LM723.cir.out | 83 ++ library/SubcircuitLibrary/LM723/LM723.pro | 81 ++ library/SubcircuitLibrary/LM723/LM723.sch | 1388 ++++++++++++++++++++ library/SubcircuitLibrary/LM723/LM723.sub | 77 ++ .../LM723/LM723_Previous_Values.xml | 1 + library/SubcircuitLibrary/LM723/NJF.lib | 4 + library/SubcircuitLibrary/LM723/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/LM723/NPN.lib | 4 + library/SubcircuitLibrary/LM723/PNP.lib | 4 + library/SubcircuitLibrary/LM723/README.md | 36 + library/SubcircuitLibrary/LM723/analysis | 1 + 14 files changed, 1945 insertions(+) create mode 100644 library/SubcircuitLibrary/LM723/D.lib create mode 100644 library/SubcircuitLibrary/LM723/LM723-cache.lib create mode 100644 library/SubcircuitLibrary/LM723/LM723.cir create mode 100644 library/SubcircuitLibrary/LM723/LM723.cir.out create mode 100644 library/SubcircuitLibrary/LM723/LM723.pro create mode 100644 library/SubcircuitLibrary/LM723/LM723.sch create mode 100644 library/SubcircuitLibrary/LM723/LM723.sub create mode 100644 library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LM723/NJF.lib create mode 100644 library/SubcircuitLibrary/LM723/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/LM723/NPN.lib create mode 100644 library/SubcircuitLibrary/LM723/PNP.lib create mode 100644 library/SubcircuitLibrary/LM723/README.md create mode 100644 library/SubcircuitLibrary/LM723/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/LM723/D.lib b/library/SubcircuitLibrary/LM723/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM723/LM723-cache.lib b/library/SubcircuitLibrary/LM723/LM723-cache.lib new file mode 100644 index 00000000..3dddd3f6 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723-cache.lib @@ -0,0 +1,182 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM723/LM723.cir b/library/SubcircuitLibrary/LM723/LM723.cir new file mode 100644 index 00000000..d513ed3e --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.cir @@ -0,0 +1,69 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM723\LM723.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/28/22 22:27:49 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_J1-Pad3_ /V+ zener +R2 /V+ Net-_Q4-Pad3_ 900 +R5 Net-_Q25-Pad3_ /V+ 550 +Q4 Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q4-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q14-Pad2_ Net-_Q25-Pad3_ eSim_PNP +R3 Net-_Q14-Pad2_ Net-_J1-Pad3_ 22k +Q8 /V+ Net-_C1-Pad2_ /Vref eSim_NPN +Q2 /V- Net-_D1-Pad1_ Net-_Q2-Pad3_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q7 /V- Net-_C1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q9 Net-_C1-Pad1_ Net-_Q11-Pad1_ /Vref eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_C2-Pad1_ /Vref eSim_PNP +R8 Net-_Q11-Pad1_ Net-_C2-Pad1_ 1.8k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +C2 Net-_C2-Pad1_ Net-_C1-Pad2_ 5p +U2 /V- Net-_C1-Pad2_ zener +R16 /V+ Net-_Q14-Pad3_ 1.8k +R18 Net-_Q16-Pad3_ /V+ 1.8k +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_PNP +Q16 /Compensation Net-_Q14-Pad2_ Net-_Q16-Pad3_ eSim_PNP +Q19 /V+ /Compensation Net-_Q19-Pad3_ eSim_NPN +Q23 /Vc Net-_Q19-Pad3_ /Vout eSim_NPN +R21 Net-_Q19-Pad3_ /Vout 15k +U3 /Vz /Vout zener +Q12 Net-_Q11-Pad1_ Net-_D2-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q10 Net-_C1-Pad1_ Net-_D2-Pad2_ Net-_D2-Pad1_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R9 Net-_D2-Pad1_ Net-_Q12-Pad3_ 2k +R6 Net-_D2-Pad1_ Net-_R6-Pad2_ 11k +R7 Net-_R6-Pad2_ /V- 1k +Q6 Net-_J1-Pad3_ Net-_Q17-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q3 Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q1-Pad2_ eSim_NPN +Q1 Net-_J1-Pad1_ Net-_Q1-Pad2_ /V- eSim_NPN +R1 Net-_Q1-Pad2_ /V- 2.4k +R4 Net-_Q6-Pad3_ /V- 160 +R10 /Vref Net-_Q13-Pad1_ 409 +R11 Net-_Q13-Pad1_ Net-_D2-Pad2_ 11.89k +R12 Net-_D2-Pad2_ Net-_Q15-Pad2_ 1.1k +R13 Net-_Q15-Pad2_ Net-_Q13-Pad2_ 380 +R14 Net-_Q13-Pad2_ /V- 1.1k +Q15 Net-_Q13-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R17 Net-_Q15-Pad3_ /V- 1.1k +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +R15 Net-_Q13-Pad3_ /V- 1.7k +Q17 Net-_Q14-Pad1_ Net-_Q17-Pad2_ Net-_Q17-Pad3_ eSim_NPN +R19 Net-_Q17-Pad3_ /V- 300 +Q18 /Vref Net-_Q14-Pad1_ Net-_Q17-Pad2_ eSim_NPN +R20 Net-_Q17-Pad2_ /V- 10k +Q24 /Compensation Net-_Q24-Pad2_ /Current_sense eSim_NPN +R24 /Current_limit Net-_Q24-Pad2_ 400 +Q22 /Compensation /Inverting_input Net-_Q20-Pad3_ eSim_NPN +Q20 /Vref /Non-inverting_input Net-_Q20-Pad3_ eSim_NPN +Q21 Net-_Q20-Pad3_ Net-_Q17-Pad2_ Net-_Q21-Pad3_ eSim_NPN +R22 Net-_Q21-Pad3_ /V- 300 +R23 Net-_Q26-Pad3_ /V- 300 +U4 /V+ /Vc /Vout /Vz /Vref /Compensation /Current_limit /Current_sense /Inverting_input /Non-inverting_input ? ? ? /V- PORT +J1 Net-_J1-Pad1_ /V- Net-_J1-Pad3_ jfet_n +Q25 Net-_Q2-Pad3_ Net-_Q14-Pad2_ Net-_Q25-Pad3_ eSim_PNP +Q26 Net-_Q20-Pad3_ Net-_Q17-Pad2_ Net-_Q26-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/LM723/LM723.cir.out b/library/SubcircuitLibrary/LM723/LM723.cir.out new file mode 100644 index 00000000..6530b650 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.cir.out @@ -0,0 +1,83 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm723\lm723.cir + +.include D.lib +.include PNP.lib +.include NJF.lib +.include NPN.lib +* u1 net-_j1-pad3_ /v+ zener +r2 /v+ net-_q4-pad3_ 900 +r5 net-_q25-pad3_ /v+ 550 +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_c1-pad2_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +r3 net-_q14-pad2_ net-_j1-pad3_ 22k +q8 /v+ net-_c1-pad2_ /vref Q2N2222 +q2 /v- net-_d1-pad1_ net-_q2-pad3_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q7 /v- net-_c1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_c1-pad1_ net-_q11-pad1_ /vref Q2N2907A +q11 net-_q11-pad1_ net-_c2-pad1_ /vref Q2N2907A +r8 net-_q11-pad1_ net-_c2-pad1_ 1.8k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +c2 net-_c2-pad1_ net-_c1-pad2_ 5p +* u2 /v- net-_c1-pad2_ zener +r16 /v+ net-_q14-pad3_ 1.8k +r18 net-_q16-pad3_ /v+ 1.8k +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2907A +q16 /compensation net-_q14-pad2_ net-_q16-pad3_ Q2N2907A +q19 /v+ /compensation net-_q19-pad3_ Q2N2222 +q23 /vc net-_q19-pad3_ /vout Q2N2222 +r21 net-_q19-pad3_ /vout 15k +* u3 /vz /vout zener +q12 net-_q11-pad1_ net-_d2-pad2_ net-_q12-pad3_ Q2N2222 +q10 net-_c1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r9 net-_d2-pad1_ net-_q12-pad3_ 2k +r6 net-_d2-pad1_ net-_r6-pad2_ 11k +r7 net-_r6-pad2_ /v- 1k +q6 net-_j1-pad3_ net-_q17-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_j1-pad1_ net-_q1-pad2_ Q2N2222 +q1 net-_j1-pad1_ net-_q1-pad2_ /v- Q2N2222 +r1 net-_q1-pad2_ /v- 2.4k +r4 net-_q6-pad3_ /v- 160 +r10 /vref net-_q13-pad1_ 409 +r11 net-_q13-pad1_ net-_d2-pad2_ 11.89k +r12 net-_d2-pad2_ net-_q15-pad2_ 1.1k +r13 net-_q15-pad2_ net-_q13-pad2_ 380 +r14 net-_q13-pad2_ /v- 1.1k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r17 net-_q15-pad3_ /v- 1.1k +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r15 net-_q13-pad3_ /v- 1.7k +q17 net-_q14-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222 +r19 net-_q17-pad3_ /v- 300 +q18 /vref net-_q14-pad1_ net-_q17-pad2_ Q2N2222 +r20 net-_q17-pad2_ /v- 10k +q24 /compensation net-_q24-pad2_ /current_sense Q2N2222 +r24 /current_limit net-_q24-pad2_ 400 +q22 /compensation /inverting_input net-_q20-pad3_ Q2N2222 +q20 /vref /non-inverting_input net-_q20-pad3_ Q2N2222 +q21 net-_q20-pad3_ net-_q17-pad2_ net-_q21-pad3_ Q2N2222 +r22 net-_q21-pad3_ /v- 300 +r23 net-_q26-pad3_ /v- 300 +* u4 /v+ /vc /vout /vz /vref /compensation /current_limit /current_sense /inverting_input /non-inverting_input ? ? ? /v- port +j1 net-_j1-pad1_ /v- net-_j1-pad3_ J2N3819 +q25 net-_q2-pad3_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +q26 net-_q20-pad3_ net-_q17-pad2_ net-_q26-pad3_ Q2N2222 +a1 net-_j1-pad3_ /v+ u1 +a2 /v- net-_c1-pad2_ u2 +a3 /vz /vout u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.7 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM723/LM723.pro b/library/SubcircuitLibrary/LM723/LM723.pro new file mode 100644 index 00000000..b033facd --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:28:26 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM723/LM723.sch b/library/SubcircuitLibrary/LM723/LM723.sch new file mode 100644 index 00000000..98e57d33 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.sch @@ -0,0 +1,1388 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM723-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L zener U1 +U 1 1 62BC8919 +P 900 1400 +F 0 "U1" H 850 1300 60 0000 C CNN +F 1 "zener" H 900 1500 60 0000 C CNN +F 2 "" H 950 1400 60 0000 C CNN +F 3 "" H 950 1400 60 0000 C CNN + 1 900 1400 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 62BC891A +P 1550 800 +F 0 "R2" H 1600 930 50 0000 C CNN +F 1 "900" H 1600 750 50 0000 C CNN +F 2 "" H 1600 780 30 0000 C CNN +F 3 "" V 1600 850 30 0000 C CNN + 1 1550 800 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 62BC891B +P 2650 900 +F 0 "R5" H 2700 1030 50 0000 C CNN +F 1 "550" H 2700 850 50 0000 C CNN +F 2 "" H 2700 880 30 0000 C CNN +F 3 "" V 2700 950 30 0000 C CNN + 1 2650 900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 62BC891C +P 1700 1400 +F 0 "Q4" H 1600 1450 50 0000 R CNN +F 1 "eSim_PNP" H 1650 1550 50 0000 R CNN +F 2 "" H 1900 1500 29 0000 C CNN +F 3 "" H 1700 1400 60 0000 C CNN + 1 1700 1400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 62BC891D +P 2500 1400 +F 0 "Q5" H 2400 1450 50 0000 R CNN +F 1 "eSim_PNP" H 2450 1550 50 0000 R CNN +F 2 "" H 2700 1500 29 0000 C CNN +F 3 "" H 2500 1400 60 0000 C CNN + 1 2500 1400 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 62BC891E +P 1550 1800 +F 0 "R3" H 1600 1930 50 0000 C CNN +F 1 "22k" H 1600 1750 50 0000 C CNN +F 2 "" H 1600 1780 30 0000 C CNN +F 3 "" V 1600 1850 30 0000 C CNN + 1 1550 1800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 62BC891F +P 3000 1650 +F 0 "Q8" H 2900 1700 50 0000 R CNN +F 1 "eSim_NPN" H 2950 1800 50 0000 R CNN +F 2 "" H 3200 1750 29 0000 C CNN +F 3 "" H 3000 1650 60 0000 C CNN + 1 3000 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 62BC8920 +P 1300 2500 +F 0 "Q2" H 1200 2550 50 0000 R CNN +F 1 "eSim_PNP" H 1250 2650 50 0000 R CNN +F 2 "" H 1500 2600 29 0000 C CNN +F 3 "" H 1300 2500 60 0000 C CNN + 1 1300 2500 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 62BC8921 +P 1900 2500 +F 0 "D1" H 1900 2600 50 0000 C CNN +F 1 "eSim_Diode" H 1900 2400 50 0000 C CNN +F 2 "" H 1900 2500 60 0000 C CNN +F 3 "" H 1900 2500 60 0000 C CNN + 1 1900 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 62BC8922 +P 2700 2750 +F 0 "Q7" H 2600 2800 50 0000 R CNN +F 1 "eSim_PNP" H 2650 2900 50 0000 R CNN +F 2 "" H 2900 2850 29 0000 C CNN +F 3 "" H 2700 2750 60 0000 C CNN + 1 2700 2750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 62BC8923 +P 3550 2150 +F 0 "Q9" H 3450 2200 50 0000 R CNN +F 1 "eSim_PNP" H 3500 2300 50 0000 R CNN +F 2 "" H 3750 2250 29 0000 C CNN +F 3 "" H 3550 2150 60 0000 C CNN + 1 3550 2150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 62BC8924 +P 4500 2150 +F 0 "Q11" H 4400 2200 50 0000 R CNN +F 1 "eSim_PNP" H 4450 2300 50 0000 R CNN +F 2 "" H 4700 2250 29 0000 C CNN +F 3 "" H 4500 2150 60 0000 C CNN + 1 4500 2150 + 1 0 0 1 +$EndComp +$Comp +L resistor R8 +U 1 1 62BC8925 +P 4000 2200 +F 0 "R8" H 4050 2330 50 0000 C CNN +F 1 "1.8k" H 4050 2150 50 0000 C CNN +F 2 "" H 4050 2180 30 0000 C CNN +F 3 "" V 4050 2250 30 0000 C CNN + 1 4000 2200 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 62BC8926 +P 3250 2900 +F 0 "C1" H 3275 3000 50 0000 L CNN +F 1 "10p" H 3275 2800 50 0000 L CNN +F 2 "" H 3288 2750 30 0000 C CNN +F 3 "" H 3250 2900 60 0000 C CNN + 1 3250 2900 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 62BC8927 +P 4300 2900 +F 0 "C2" H 4325 3000 50 0000 L CNN +F 1 "5p" H 4325 2800 50 0000 L CNN +F 2 "" H 4338 2750 30 0000 C CNN +F 3 "" H 4300 2900 60 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L zener U2 +U 1 1 62BC8928 +P 2900 3500 +F 0 "U2" H 2850 3400 60 0000 C CNN +F 1 "zener" H 2900 3600 60 0000 C CNN +F 2 "" H 2950 3500 60 0000 C CNN +F 3 "" H 2950 3500 60 0000 C CNN + 1 2900 3500 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 62BC8929 +P 6050 800 +F 0 "R16" H 6100 930 50 0000 C CNN +F 1 "1.8k" H 6100 750 50 0000 C CNN +F 2 "" H 6100 780 30 0000 C CNN +F 3 "" V 6100 850 30 0000 C CNN + 1 6050 800 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 62BC892A +P 6950 900 +F 0 "R18" H 7000 1030 50 0000 C CNN +F 1 "1.8k" H 7000 850 50 0000 C CNN +F 2 "" H 7000 880 30 0000 C CNN +F 3 "" V 7000 950 30 0000 C CNN + 1 6950 900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 62BC892B +P 6000 1350 +F 0 "Q14" H 5900 1400 50 0000 R CNN +F 1 "eSim_PNP" H 5950 1500 50 0000 R CNN +F 2 "" H 6200 1450 29 0000 C CNN +F 3 "" H 6000 1350 60 0000 C CNN + 1 6000 1350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q16 +U 1 1 62BC892C +P 6800 1350 +F 0 "Q16" H 6700 1400 50 0000 R CNN +F 1 "eSim_PNP" H 6750 1500 50 0000 R CNN +F 2 "" H 7000 1450 29 0000 C CNN +F 3 "" H 6800 1350 60 0000 C CNN + 1 6800 1350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 62BC892D +P 7750 1350 +F 0 "Q19" H 7650 1400 50 0000 R CNN +F 1 "eSim_NPN" H 7700 1500 50 0000 R CNN +F 2 "" H 7950 1450 29 0000 C CNN +F 3 "" H 7750 1350 60 0000 C CNN + 1 7750 1350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q23 +U 1 1 62BC892E +P 8700 1350 +F 0 "Q23" H 8600 1400 50 0000 R CNN +F 1 "eSim_NPN" H 8650 1500 50 0000 R CNN +F 2 "" H 8900 1450 29 0000 C CNN +F 3 "" H 8700 1350 60 0000 C CNN + 1 8700 1350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 62BC892F +P 7800 1900 +F 0 "R21" H 7850 2030 50 0000 C CNN +F 1 "15k" H 7850 1850 50 0000 C CNN +F 2 "" H 7850 1880 30 0000 C CNN +F 3 "" V 7850 1950 30 0000 C CNN + 1 7800 1900 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 62BC8930 +P 8850 2150 +F 0 "U3" H 8800 2050 60 0000 C CNN +F 1 "zener" H 8850 2250 60 0000 C CNN +F 2 "" H 8900 2150 60 0000 C CNN +F 3 "" H 8900 2150 60 0000 C CNN + 1 8850 2150 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 62BC8931 +P 4700 4500 +F 0 "Q12" H 4600 4550 50 0000 R CNN +F 1 "eSim_NPN" H 4650 4650 50 0000 R CNN +F 2 "" H 4900 4600 29 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 62BC8932 +P 3550 4500 +F 0 "Q10" H 3450 4550 50 0000 R CNN +F 1 "eSim_NPN" H 3500 4650 50 0000 R CNN +F 2 "" H 3750 4600 29 0000 C CNN +F 3 "" H 3550 4500 60 0000 C CNN + 1 3550 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 62BC8933 +P 3850 4800 +F 0 "D2" H 3850 4900 50 0000 C CNN +F 1 "eSim_Diode" H 3850 4700 50 0000 C CNN +F 2 "" H 3850 4800 60 0000 C CNN +F 3 "" H 3850 4800 60 0000 C CNN + 1 3850 4800 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 62BC8934 +P 4200 5000 +F 0 "R9" H 4250 5130 50 0000 C CNN +F 1 "2k" H 4250 4950 50 0000 C CNN +F 2 "" H 4250 4980 30 0000 C CNN +F 3 "" V 4250 5050 30 0000 C CNN + 1 4200 5000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 62BC8935 +P 3400 5250 +F 0 "R6" H 3450 5380 50 0000 C CNN +F 1 "11k" H 3450 5200 50 0000 C CNN +F 2 "" H 3450 5230 30 0000 C CNN +F 3 "" V 3450 5300 30 0000 C CNN + 1 3400 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 62BC8936 +P 3400 6050 +F 0 "R7" H 3450 6180 50 0000 C CNN +F 1 "1k" H 3450 6000 50 0000 C CNN +F 2 "" H 3450 6030 30 0000 C CNN +F 3 "" V 3450 6100 30 0000 C CNN + 1 3400 6050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 62BC8937 +P 2600 5600 +F 0 "Q6" H 2500 5650 50 0000 R CNN +F 1 "eSim_NPN" H 2550 5750 50 0000 R CNN +F 2 "" H 2800 5700 29 0000 C CNN +F 3 "" H 2600 5600 60 0000 C CNN + 1 2600 5600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 62BC8938 +P 1650 5400 +F 0 "Q3" H 1550 5450 50 0000 R CNN +F 1 "eSim_NPN" H 1600 5550 50 0000 R CNN +F 2 "" H 1850 5500 29 0000 C CNN +F 3 "" H 1650 5400 60 0000 C CNN + 1 1650 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 62BC8939 +P 1000 5800 +F 0 "Q1" H 900 5850 50 0000 R CNN +F 1 "eSim_NPN" H 950 5950 50 0000 R CNN +F 2 "" H 1200 5900 29 0000 C CNN +F 3 "" H 1000 5800 60 0000 C CNN + 1 1000 5800 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62BC893B +P 1500 6050 +F 0 "R1" H 1550 6180 50 0000 C CNN +F 1 "2.4k" H 1550 6000 50 0000 C CNN +F 2 "" H 1550 6030 30 0000 C CNN +F 3 "" V 1550 6100 30 0000 C CNN + 1 1500 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 62BC893C +P 2450 6050 +F 0 "R4" H 2500 6180 50 0000 C CNN +F 1 "160" H 2500 6000 50 0000 C CNN +F 2 "" H 2500 6030 30 0000 C CNN +F 3 "" V 2500 6100 30 0000 C CNN + 1 2450 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 62BC893D +P 5250 3150 +F 0 "R10" H 5300 3280 50 0000 C CNN +F 1 "409" H 5300 3100 50 0000 C CNN +F 2 "" H 5300 3130 30 0000 C CNN +F 3 "" V 5300 3200 30 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 62BC893E +P 5250 3650 +F 0 "R11" H 5300 3780 50 0000 C CNN +F 1 "11.89k" H 5300 3600 50 0000 C CNN +F 2 "" H 5300 3630 30 0000 C CNN +F 3 "" V 5300 3700 30 0000 C CNN + 1 5250 3650 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 62BC893F +P 5250 4650 +F 0 "R12" H 5300 4780 50 0000 C CNN +F 1 "1.1k" H 5300 4600 50 0000 C CNN +F 2 "" H 5300 4630 30 0000 C CNN +F 3 "" V 5300 4700 30 0000 C CNN + 1 5250 4650 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 62BC8940 +P 5250 5250 +F 0 "R13" H 5300 5380 50 0000 C CNN +F 1 "380" H 5300 5200 50 0000 C CNN +F 2 "" H 5300 5230 30 0000 C CNN +F 3 "" V 5300 5300 30 0000 C CNN + 1 5250 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 62BC8941 +P 5250 6000 +F 0 "R14" H 5300 6130 50 0000 C CNN +F 1 "1.1k" H 5300 5950 50 0000 C CNN +F 2 "" H 5300 5980 30 0000 C CNN +F 3 "" V 5300 6050 30 0000 C CNN + 1 5250 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 62BC8942 +P 6450 5000 +F 0 "Q15" H 6350 5050 50 0000 R CNN +F 1 "eSim_NPN" H 6400 5150 50 0000 R CNN +F 2 "" H 6650 5100 29 0000 C CNN +F 3 "" H 6450 5000 60 0000 C CNN + 1 6450 5000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 62BC8943 +P 6500 6000 +F 0 "R17" H 6550 6130 50 0000 C CNN +F 1 "1.1k" H 6550 5950 50 0000 C CNN +F 2 "" H 6550 5980 30 0000 C CNN +F 3 "" V 6550 6050 30 0000 C CNN + 1 6500 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 62BC8944 +P 5850 5550 +F 0 "Q13" H 5750 5600 50 0000 R CNN +F 1 "eSim_NPN" H 5800 5700 50 0000 R CNN +F 2 "" H 6050 5650 29 0000 C CNN +F 3 "" H 5850 5550 60 0000 C CNN + 1 5850 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 900 600 1600 600 +Wire Wire Line + 1600 600 2600 600 +Wire Wire Line + 2600 600 3100 600 +Wire Wire Line + 3100 600 6100 600 +Wire Wire Line + 6100 600 6900 600 +Wire Wire Line + 6900 600 7850 600 +Wire Wire Line + 7850 600 9700 600 +Connection ~ 2600 600 +Wire Wire Line + 2600 700 2600 600 +Wire Wire Line + 1600 700 1600 600 +Wire Wire Line + 900 600 900 1100 +Connection ~ 1600 600 +Wire Wire Line + 1600 1200 1600 1000 +Wire Wire Line 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5550 5300 5550 +Connection ~ 5300 5550 +$Comp +L resistor R15 +U 1 1 62BC8945 +P 5900 6000 +F 0 "R15" H 5950 6130 50 0000 C CNN +F 1 "1.7k" H 5950 5950 50 0000 C CNN +F 2 "" H 5950 5980 30 0000 C CNN +F 3 "" V 5950 6050 30 0000 C CNN + 1 5900 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 5950 5750 5950 5900 +Wire Wire Line + 5950 6200 5950 6450 +Connection ~ 5950 6450 +Wire Wire Line + 6550 6200 6550 6450 +Connection ~ 6550 6450 +Wire Wire Line + 6100 3150 7000 3150 +Wire Wire Line + 7000 3150 7000 5100 +Wire Wire Line + 7000 5100 7000 5250 +$Comp +L eSim_NPN Q17 +U 1 1 62BC8946 +P 7100 5450 +F 0 "Q17" H 7000 5500 50 0000 R CNN +F 1 "eSim_NPN" H 7050 5600 50 0000 R CNN +F 2 "" H 7300 5550 29 0000 C CNN +F 3 "" H 7100 5450 60 0000 C CNN + 1 7100 5450 + -1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 62BC8947 +P 6950 6000 +F 0 "R19" H 7000 6130 50 0000 C CNN +F 1 "300" H 7000 5950 50 0000 C CNN +F 2 "" H 7000 5980 30 0000 C CNN +F 3 "" V 7000 6050 30 0000 C CNN + 1 6950 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 5900 7000 5650 +Wire Wire Line + 7000 6200 7000 6450 +Connection ~ 7000 6450 +Wire Wire Line + 7600 2900 7600 3850 +Wire Wire Line + 7600 3850 7600 4900 +Connection ~ 7600 2900 +$Comp +L eSim_NPN Q18 +U 1 1 62BC8948 +P 7500 5100 +F 0 "Q18" H 7400 5150 50 0000 R CNN +F 1 "eSim_NPN" H 7450 5250 50 0000 R CNN +F 2 "" H 7700 5200 29 0000 C CNN +F 3 "" H 7500 5100 60 0000 C CNN + 1 7500 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 5100 7000 5100 +Connection ~ 7000 5100 +Wire Wire Line + 7600 5300 7600 5450 +Wire Wire Line + 7600 5450 7600 5500 +Wire Wire Line + 7600 5500 7600 5900 +Wire Wire Line + 7300 5450 7350 5450 +Wire Wire Line + 7350 5450 7600 5450 +Connection ~ 7600 5450 +$Comp +L resistor R20 +U 1 1 62BC8949 +P 7550 6000 +F 0 "R20" H 7600 6130 50 0000 C CNN +F 1 "10k" H 7600 5950 50 0000 C CNN +F 2 "" H 7600 5980 30 0000 C CNN +F 3 "" V 7600 6050 30 0000 C CNN + 1 7550 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 6200 7600 6450 +Connection ~ 7600 6450 +$Comp +L eSim_NPN Q24 +U 1 1 62BC894A +P 8750 3650 +F 0 "Q24" H 8650 3700 50 0000 R CNN +F 1 "eSim_NPN" H 8700 3800 50 0000 R CNN +F 2 "" H 8950 3750 29 0000 C CNN +F 3 "" H 8750 3650 60 0000 C CNN + 1 8750 3650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 8400 3450 8650 3450 +Wire Wire Line + 8650 3950 9700 3950 +$Comp +L resistor R24 +U 1 1 62BC894B +P 9150 3600 +F 0 "R24" H 9200 3730 50 0000 C CNN +F 1 "400" H 9200 3550 50 0000 C CNN +F 2 "" H 9200 3580 30 0000 C CNN +F 3 "" V 9200 3650 30 0000 C CNN + 1 9150 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 8950 3650 8950 3650 +Wire Wire Line + 9250 3650 9700 3650 +Connection ~ 8400 3450 +Wire Wire Line + 7350 4050 7350 5450 +Connection ~ 7350 5450 +$Comp +L eSim_NPN Q22 +U 1 1 62BC894C +P 8500 4250 +F 0 "Q22" H 8400 4300 50 0000 R CNN +F 1 "eSim_NPN" H 8450 4400 50 0000 R CNN +F 2 "" H 8700 4350 29 0000 C CNN +F 3 "" H 8500 4250 60 0000 C CNN + 1 8500 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 62BC894D +P 8000 4250 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8250 5700 8250 5750 +Wire Wire Line + 8250 5750 8250 5900 +Wire Wire Line + 8800 5350 8800 5900 +Connection ~ 8250 5750 +$Comp +L resistor R22 +U 1 1 62BC894F +P 8200 6000 +F 0 "R22" H 8250 6130 50 0000 C CNN +F 1 "300" H 8250 5950 50 0000 C CNN +F 2 "" H 8250 5980 30 0000 C CNN +F 3 "" V 8250 6050 30 0000 C CNN + 1 8200 6000 + 0 1 1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 62BC8950 +P 8750 6000 +F 0 "R23" H 8800 6130 50 0000 C CNN +F 1 "300" H 8800 5950 50 0000 C CNN +F 2 "" H 8800 5980 30 0000 C CNN +F 3 "" V 8800 6050 30 0000 C CNN + 1 8750 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 8250 6200 8250 6450 +Connection ~ 8250 6450 +Wire Wire Line + 8800 6200 8800 6450 +Connection ~ 8800 6450 +Wire Wire Line + 1400 4250 1400 5150 +Wire Wire Line + 1400 5150 1550 5150 +Wire Wire Line + 1550 5150 1550 5200 +Connection ~ 1400 4250 +Wire Wire Line + 8650 3950 8650 3850 +Wire Wire Line + 8800 1150 8800 1000 +Wire Wire Line + 8800 1000 9700 1000 +Text Label 9200 600 0 60 ~ 0 +V+ +Text Label 9200 1000 0 60 ~ 0 +Vc +Text Label 9200 1850 0 60 ~ 0 +Vout +Text Label 9200 2400 0 60 ~ 0 +Vz +Text Label 9200 2900 0 60 ~ 0 +Vref +Text Label 9050 3250 0 60 ~ 0 +Compensation +Text Label 9250 3650 0 60 ~ 0 +Current_limit +Text Label 9050 3950 0 60 ~ 0 +Current_sense +Text Label 9050 4250 0 60 ~ 0 +Inverting_input +Text Label 8800 4600 0 60 ~ 0 +Non-inverting_input +Text Label 9350 6450 0 60 ~ 0 +V- +$Comp +L PORT U4 +U 1 1 62BC8951 +P 9950 600 +F 0 "U4" H 10000 700 30 0000 C CNN +F 1 "PORT" H 9950 600 30 0000 C CNN +F 2 "" H 9950 600 60 0000 C CNN +F 3 "" H 9950 600 60 0000 C CNN + 1 9950 600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 62BC8952 +P 9950 1000 +F 0 "U4" H 10000 1100 30 0000 C CNN +F 1 "PORT" H 9950 1000 30 0000 C CNN +F 2 "" H 9950 1000 60 0000 C CNN +F 3 "" H 9950 1000 60 0000 C CNN + 2 9950 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 3 1 62BC8953 +P 9950 1850 +F 0 "U4" H 10000 1950 30 0000 C CNN +F 1 "PORT" H 9950 1850 30 0000 C CNN +F 2 "" H 9950 1850 60 0000 C CNN +F 3 "" H 9950 1850 60 0000 C CNN + 3 9950 1850 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 4 1 62BC8954 +P 9950 2400 +F 0 "U4" H 10000 2500 30 0000 C CNN +F 1 "PORT" H 9950 2400 30 0000 C CNN +F 2 "" H 9950 2400 60 0000 C CNN +F 3 "" H 9950 2400 60 0000 C CNN + 4 9950 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 5 1 62BC8955 +P 9950 2900 +F 0 "U4" H 10000 3000 30 0000 C CNN +F 1 "PORT" H 9950 2900 30 0000 C CNN +F 2 "" H 9950 2900 60 0000 C CNN +F 3 "" H 9950 2900 60 0000 C CNN + 5 9950 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 6 1 62BC8956 +P 9950 3250 +F 0 "U4" H 10000 3350 30 0000 C CNN +F 1 "PORT" H 9950 3250 30 0000 C CNN +F 2 "" H 9950 3250 60 0000 C CNN +F 3 "" H 9950 3250 60 0000 C CNN + 6 9950 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 7 1 62BC8957 +P 9950 3650 +F 0 "U4" H 10000 3750 30 0000 C CNN +F 1 "PORT" H 9950 3650 30 0000 C CNN +F 2 "" H 9950 3650 60 0000 C CNN +F 3 "" H 9950 3650 60 0000 C CNN + 7 9950 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 8 1 62BC8958 +P 9950 3950 +F 0 "U4" H 10000 4050 30 0000 C CNN +F 1 "PORT" H 9950 3950 30 0000 C CNN +F 2 "" H 9950 3950 60 0000 C CNN +F 3 "" H 9950 3950 60 0000 C CNN + 8 9950 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 9 1 62BC8959 +P 9950 4250 +F 0 "U4" H 10000 4350 30 0000 C CNN +F 1 "PORT" H 9950 4250 30 0000 C CNN +F 2 "" H 9950 4250 60 0000 C CNN +F 3 "" H 9950 4250 60 0000 C CNN + 9 9950 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 10 1 62BC895A +P 9950 4600 +F 0 "U4" H 10000 4700 30 0000 C CNN +F 1 "PORT" H 9950 4600 30 0000 C CNN +F 2 "" H 9950 4600 60 0000 C CNN +F 3 "" H 9950 4600 60 0000 C CNN + 10 9950 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 11 1 62BC895B +P 9950 5000 +F 0 "U4" H 10000 5100 30 0000 C CNN +F 1 "PORT" H 9950 5000 30 0000 C CNN +F 2 "" H 9950 5000 60 0000 C CNN +F 3 "" H 9950 5000 60 0000 C CNN + 11 9950 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 12 1 62BC895C +P 9950 5300 +F 0 "U4" H 10000 5400 30 0000 C CNN +F 1 "PORT" H 9950 5300 30 0000 C CNN +F 2 "" H 9950 5300 60 0000 C CNN +F 3 "" H 9950 5300 60 0000 C CNN + 12 9950 5300 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 13 1 62BC895D +P 9950 5600 +F 0 "U4" H 10000 5700 30 0000 C CNN +F 1 "PORT" H 9950 5600 30 0000 C CNN +F 2 "" H 9950 5600 60 0000 C CNN +F 3 "" H 9950 5600 60 0000 C CNN + 13 9950 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 14 1 62BC895E +P 9950 6450 +F 0 "U4" H 10000 6550 30 0000 C CNN +F 1 "PORT" H 9950 6450 30 0000 C CNN +F 2 "" H 9950 6450 60 0000 C CNN +F 3 "" H 9950 6450 60 0000 C CNN + 14 9950 6450 + -1 0 0 1 +$EndComp +$Comp +L jfet_n J1 +U 1 1 62BE9EF0 +P 1800 4550 +F 0 "J1" H 1700 4600 50 0000 R CNN +F 1 "jfet_n" H 1750 4700 50 0000 R CNN +F 2 "" H 2000 4650 29 0000 C CNN +F 3 "" H 1800 4550 60 0000 C CNN + 1 1800 4550 + -1 0 0 1 +$EndComp +Wire Wire Line + 1600 2150 900 2150 +Connection ~ 900 2150 +$Comp +L eSim_PNP Q25 +U 1 1 62E05DAD +P 2250 1850 +F 0 "Q25" H 2150 1900 50 0000 R CNN +F 1 "eSim_PNP" H 2200 2000 50 0000 R CNN +F 2 "" H 2450 1950 29 0000 C CNN +F 3 "" H 2250 1850 60 0000 C CNN + 1 2250 1850 + 1 0 0 1 +$EndComp +Wire Wire Line + 2350 1650 2350 1100 +Wire Wire Line + 2350 1100 2600 1100 +Connection ~ 2600 1100 +Wire Wire Line + 2050 1850 2050 1400 +Connection ~ 2050 1400 +Wire Wire Line + 2350 2050 2350 2250 +Wire Wire Line + 2350 2250 1200 2250 +$Comp +L eSim_NPN Q26 +U 1 1 62E06C82 +P 8700 5150 +F 0 "Q26" H 8600 5200 50 0000 R CNN +F 1 "eSim_NPN" H 8650 5300 50 0000 R CNN +F 2 "" H 8900 5250 29 0000 C CNN +F 3 "" H 8700 5150 60 0000 C CNN + 1 8700 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 5150 7900 5500 +Connection ~ 7900 5500 +Wire Wire Line + 8800 4950 8250 4950 +Connection ~ 8250 4950 +Wire Wire Line + 7900 5150 8500 5150 +NoConn ~ 9700 5000 +NoConn ~ 9700 5300 +NoConn ~ 9700 5600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM723/LM723.sub b/library/SubcircuitLibrary/LM723/LM723.sub new file mode 100644 index 00000000..2d8b199b --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.sub @@ -0,0 +1,77 @@ +* Subcircuit LM723 +.subckt LM723 /v+ /vc /vout /vz /vref /compensation /current_limit /current_sense /inverting_input /non-inverting_input ? ? ? /v- +* c:\fossee\esim\library\subcircuitlibrary\lm723\lm723.cir +.include D.lib +.include PNP.lib +.include NJF.lib +.include NPN.lib +* u1 net-_j1-pad3_ /v+ zener +r2 /v+ net-_q4-pad3_ 900 +r5 net-_q25-pad3_ /v+ 550 +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_c1-pad2_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +r3 net-_q14-pad2_ net-_j1-pad3_ 22k +q8 /v+ net-_c1-pad2_ /vref Q2N2222 +q2 /v- net-_d1-pad1_ net-_q2-pad3_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q7 /v- net-_c1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_c1-pad1_ net-_q11-pad1_ /vref Q2N2907A +q11 net-_q11-pad1_ net-_c2-pad1_ /vref Q2N2907A +r8 net-_q11-pad1_ net-_c2-pad1_ 1.8k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +c2 net-_c2-pad1_ net-_c1-pad2_ 5p +* u2 /v- net-_c1-pad2_ zener +r16 /v+ net-_q14-pad3_ 1.8k +r18 net-_q16-pad3_ /v+ 1.8k +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2907A +q16 /compensation net-_q14-pad2_ net-_q16-pad3_ Q2N2907A +q19 /v+ /compensation net-_q19-pad3_ Q2N2222 +q23 /vc net-_q19-pad3_ /vout Q2N2222 +r21 net-_q19-pad3_ /vout 15k +* u3 /vz /vout zener +q12 net-_q11-pad1_ net-_d2-pad2_ net-_q12-pad3_ Q2N2222 +q10 net-_c1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r9 net-_d2-pad1_ net-_q12-pad3_ 2k +r6 net-_d2-pad1_ net-_r6-pad2_ 11k +r7 net-_r6-pad2_ /v- 1k +q6 net-_j1-pad3_ net-_q17-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_j1-pad1_ net-_q1-pad2_ Q2N2222 +q1 net-_j1-pad1_ net-_q1-pad2_ /v- Q2N2222 +r1 net-_q1-pad2_ /v- 2.4k +r4 net-_q6-pad3_ /v- 160 +r10 /vref net-_q13-pad1_ 409 +r11 net-_q13-pad1_ net-_d2-pad2_ 11.89k +r12 net-_d2-pad2_ net-_q15-pad2_ 1.1k +r13 net-_q15-pad2_ net-_q13-pad2_ 380 +r14 net-_q13-pad2_ /v- 1.1k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r17 net-_q15-pad3_ /v- 1.1k +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r15 net-_q13-pad3_ /v- 1.7k +q17 net-_q14-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222 +r19 net-_q17-pad3_ /v- 300 +q18 /vref net-_q14-pad1_ net-_q17-pad2_ Q2N2222 +r20 net-_q17-pad2_ /v- 10k +q24 /compensation net-_q24-pad2_ /current_sense Q2N2222 +r24 /current_limit net-_q24-pad2_ 400 +q22 /compensation /inverting_input net-_q20-pad3_ Q2N2222 +q20 /vref /non-inverting_input net-_q20-pad3_ Q2N2222 +q21 net-_q20-pad3_ net-_q17-pad2_ net-_q21-pad3_ Q2N2222 +r22 net-_q21-pad3_ /v- 300 +r23 net-_q26-pad3_ /v- 300 +j1 net-_j1-pad1_ /v- net-_j1-pad3_ J2N3819 +q25 net-_q2-pad3_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +q26 net-_q20-pad3_ net-_q17-pad2_ net-_q26-pad3_ Q2N2222 +a1 net-_j1-pad3_ /v+ u1 +a2 /v- net-_c1-pad2_ u2 +a3 /vz /vout u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.7 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM723 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml b/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml new file mode 100644 index 00000000..730dd730 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml @@ -0,0 +1 @@ +zener6.2zener5.7zenerC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM723/NJF.lib b/library/SubcircuitLibrary/LM723/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM723/NMOS-180nm.lib b/library/SubcircuitLibrary/LM723/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/LM723/NPN.lib b/library/SubcircuitLibrary/LM723/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM723/PNP.lib b/library/SubcircuitLibrary/LM723/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM723/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM723/README.md b/library/SubcircuitLibrary/LM723/README.md new file mode 100644 index 00000000..291d0bd9 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/README.md @@ -0,0 +1,36 @@ + +# LM723 Adjustable Voltage Regulator IC + +LM723 is an adjustable voltage regulator IC. It’s regulated output can be determined, by the external circuitry. It’s output can range from 2V to 37V. It can be used either as a linear regulator or a switching regulator. The Line Regulation & Load Regulation observed for this IC is 0.089% and 0.351% respectively. + + +## Usage/Examples + +Basic High Voltage Regulator + +Positive/Negative Voltage Regulator + +Positive/Negative Switching Regulator + +Foldback Current Limiting + +Positive/Negative Floating Regulator + +Shunt Regulator + + +## Documentation + +To know the details of LM723 IC please refer to this link [LM723_datasheet.](https://www.ti.com/lit/ds/symlink/lm723.pdf?ts=1665878014301&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 + diff --git a/library/SubcircuitLibrary/LM723/analysis b/library/SubcircuitLibrary/LM723/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From ab2a8d5a8371b5ca00292bb961ca07a56477d663 Mon Sep 17 00:00:00 2001 From: Arpit Sharma Date: Fri, 21 Oct 2022 23:10:18 +0530 Subject: LM1458 Op-Amp IC --- library/SubcircuitLibrary/lm1458/D.lib | 2 + library/SubcircuitLibrary/lm1458/NPN.lib | 4 + library/SubcircuitLibrary/lm1458/PNP.lib | 4 + library/SubcircuitLibrary/lm1458/README.md | 35 + library/SubcircuitLibrary/lm1458/analysis | 1 + library/SubcircuitLibrary/lm1458/lm1458-cache.lib | 145 +++ library/SubcircuitLibrary/lm1458/lm1458.cir | 81 ++ library/SubcircuitLibrary/lm1458/lm1458.cir.out | 85 ++ library/SubcircuitLibrary/lm1458/lm1458.pro | 81 ++ library/SubcircuitLibrary/lm1458/lm1458.sch | 1313 ++++++++++++++++++++ library/SubcircuitLibrary/lm1458/lm1458.sub | 79 ++ .../lm1458/lm1458_Previous_Values.xml | 1 + 12 files changed, 1831 insertions(+) create mode 100644 library/SubcircuitLibrary/lm1458/D.lib create mode 100644 library/SubcircuitLibrary/lm1458/NPN.lib create mode 100644 library/SubcircuitLibrary/lm1458/PNP.lib create mode 100644 library/SubcircuitLibrary/lm1458/README.md create mode 100644 library/SubcircuitLibrary/lm1458/analysis create mode 100644 library/SubcircuitLibrary/lm1458/lm1458-cache.lib create mode 100644 library/SubcircuitLibrary/lm1458/lm1458.cir create mode 100644 library/SubcircuitLibrary/lm1458/lm1458.cir.out create mode 100644 library/SubcircuitLibrary/lm1458/lm1458.pro create mode 100644 library/SubcircuitLibrary/lm1458/lm1458.sch create mode 100644 library/SubcircuitLibrary/lm1458/lm1458.sub create mode 100644 library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml (limited to 'library') diff --git a/library/SubcircuitLibrary/lm1458/D.lib b/library/SubcircuitLibrary/lm1458/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/lm1458/NPN.lib b/library/SubcircuitLibrary/lm1458/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm1458/PNP.lib b/library/SubcircuitLibrary/lm1458/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm1458/README.md b/library/SubcircuitLibrary/lm1458/README.md new file mode 100644 index 00000000..e3ed0ae9 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/README.md @@ -0,0 +1,35 @@ + +# LM1458 Dual Operational Amplifier IC + +LM1458 is a general purpose, Dual Channel Operational Amplifier IC. Both the Amplifiers operate independently but they share common supply. It has inbuilt short circuit protection & offers low power consumption. No frequency compensation is needed. + + +## Usage/Examples + +Inverting/Non-Inverting Amplifier + +Integrator/Summer + +Differential Amplifier + +Differentiator + +Schmitt Trigger + +Comparators + + +## Documentation + +To know the details of LM1458 IC please refer to this link [LM1458_datasheet.](https://www.ti.com/lit/ds/symlink/lm1458.pdf?ts=1665941946373&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/lm1458/analysis b/library/SubcircuitLibrary/lm1458/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm1458/lm1458-cache.lib b/library/SubcircuitLibrary/lm1458/lm1458-cache.lib new file mode 100644 index 00000000..d80602ef --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm1458/lm1458.cir b/library/SubcircuitLibrary/lm1458/lm1458.cir new file mode 100644 index 00000000..a870732e --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.cir @@ -0,0 +1,81 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm1458\lm1458.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/09/22 23:07:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q5 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q15 Net-_C1-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q10-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q8 Net-_Q1-Pad1_ Net-_Q8-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q6 Net-_C1-Pad2_ Net-_Q10-Pad1_ Net-_Q6-Pad3_ eSim_PNP +Q4 Net-_Q12-Pad3_ Net-_Q2-Pad1_ Net-_Q3-Pad2_ eSim_NPN +Q3 Net-_Q2-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q7 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q3-Pad3_ Net-_Q11-Pad3_ 1k +R2 Net-_Q3-Pad2_ Net-_Q11-Pad3_ 50k +R3 Net-_Q7-Pad3_ Net-_Q11-Pad3_ 1k +R5 Net-_Q12-Pad1_ Net-_R5-Pad2_ 19.5k +R6 Net-_R5-Pad2_ Net-_Q10-Pad2_ 19.5k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R4 Net-_Q10-Pad3_ Net-_Q11-Pad3_ 5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q13 Net-_C1-Pad2_ Net-_Q13-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q14 Net-_D1-Pad2_ Net-_C1-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R7 Net-_Q14-Pad3_ Net-_Q11-Pad3_ 50k +Q16 Net-_C1-Pad1_ Net-_Q16-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q17 Net-_D1-Pad2_ Net-_Q14-Pad3_ Net-_Q13-Pad2_ eSim_NPN +R10 Net-_Q13-Pad2_ Net-_Q11-Pad3_ 50 +R8 Net-_C1-Pad1_ Net-_Q16-Pad2_ 4.5k +R9 Net-_D1-Pad2_ Net-_Q16-Pad2_ 7.5k +Q18 Net-_C1-Pad1_ Net-_Q18-Pad2_ Net-_D2-Pad1_ eSim_NPN +Q19 Net-_Q12-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad2_ eSim_NPN +R11 Net-_Q18-Pad2_ Net-_D2-Pad1_ 25 +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D2-Pad1_ Net-_D1-Pad1_ eSim_Diode +R12 Net-_D2-Pad1_ Net-_Q20-Pad3_ 50 +Q20 Net-_Q11-Pad3_ Net-_D1-Pad2_ Net-_Q20-Pad3_ eSim_PNP +Q25 Net-_Q21-Pad1_ Net-_Q21-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q29 Net-_Q22-Pad2_ Net-_Q21-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q32 Net-_Q32-Pad1_ Net-_Q32-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q35 Net-_C2-Pad1_ Net-_Q32-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_Q21-Pad3_ eSim_NPN +Q22 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_Q21-Pad3_ eSim_PNP +Q28 Net-_Q21-Pad1_ Net-_Q28-Pad2_ Net-_Q26-Pad3_ eSim_NPN +Q26 Net-_C2-Pad2_ Net-_Q22-Pad2_ Net-_Q26-Pad3_ eSim_PNP +Q24 Net-_Q12-Pad3_ Net-_Q22-Pad1_ Net-_Q23-Pad2_ eSim_NPN +Q23 Net-_Q22-Pad1_ Net-_Q23-Pad2_ Net-_Q23-Pad3_ eSim_NPN +Q27 Net-_C2-Pad2_ Net-_Q23-Pad2_ Net-_Q27-Pad3_ eSim_NPN +R13 Net-_Q23-Pad3_ Net-_Q11-Pad3_ 1k +R14 Net-_Q23-Pad2_ Net-_Q11-Pad3_ 50k +R15 Net-_Q27-Pad3_ Net-_Q11-Pad3_ 1k +R17 Net-_Q32-Pad1_ Net-_R17-Pad2_ 19.5k +R18 Net-_R17-Pad2_ Net-_Q30-Pad2_ 19.5k +Q30 Net-_Q22-Pad2_ Net-_Q30-Pad2_ Net-_Q30-Pad3_ eSim_NPN +Q31 Net-_Q30-Pad2_ Net-_Q30-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R16 Net-_Q30-Pad3_ Net-_Q11-Pad3_ 5k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 30p +Q33 Net-_C2-Pad2_ Net-_Q33-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q34 Net-_D3-Pad2_ Net-_C2-Pad2_ Net-_Q34-Pad3_ eSim_NPN +R19 Net-_Q34-Pad3_ Net-_Q11-Pad3_ 50k +Q36 Net-_C2-Pad1_ Net-_Q36-Pad2_ Net-_D3-Pad2_ eSim_NPN +Q37 Net-_D3-Pad2_ Net-_Q34-Pad3_ Net-_Q33-Pad2_ eSim_NPN +R22 Net-_Q33-Pad2_ Net-_Q11-Pad3_ 50 +R20 Net-_C2-Pad1_ Net-_Q36-Pad2_ 4.5k +R21 Net-_D3-Pad2_ Net-_Q36-Pad2_ 7.5k +Q38 Net-_C2-Pad1_ Net-_Q38-Pad2_ Net-_D4-Pad1_ eSim_NPN +Q39 Net-_Q12-Pad3_ Net-_C2-Pad1_ Net-_Q38-Pad2_ eSim_NPN +R23 Net-_Q38-Pad2_ Net-_D4-Pad1_ 25 +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D4-Pad1_ Net-_D3-Pad1_ eSim_Diode +R24 Net-_D4-Pad1_ Net-_Q40-Pad3_ 50 +Q40 Net-_Q11-Pad3_ Net-_D3-Pad2_ Net-_Q40-Pad3_ eSim_PNP +U1 Net-_Q1-Pad2_ Net-_Q8-Pad2_ Net-_Q11-Pad3_ Net-_Q21-Pad2_ Net-_Q12-Pad3_ Net-_D2-Pad1_ Net-_Q28-Pad2_ Net-_D4-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/lm1458/lm1458.cir.out b/library/SubcircuitLibrary/lm1458/lm1458.cir.out new file mode 100644 index 00000000..0a97abf0 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.cir.out @@ -0,0 +1,85 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm1458\lm1458.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q15 net-_c1-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad1_ net-_q1-pad3_ Q2N2907A +q8 net-_q1-pad1_ net-_q8-pad2_ net-_q6-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q10-pad1_ net-_q6-pad3_ Q2N2907A +q4 net-_q12-pad3_ net-_q2-pad1_ net-_q3-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q11-pad3_ 1k +r2 net-_q3-pad2_ net-_q11-pad3_ 50k +r3 net-_q7-pad3_ net-_q11-pad3_ 1k +r5 net-_q12-pad1_ net-_r5-pad2_ 19.5k +r6 net-_r5-pad2_ net-_q10-pad2_ 19.5k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad2_ net-_q10-pad2_ net-_q11-pad3_ Q2N2222 +r4 net-_q10-pad3_ net-_q11-pad3_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q13 net-_c1-pad2_ net-_q13-pad2_ net-_q11-pad3_ Q2N2222 +q14 net-_d1-pad2_ net-_c1-pad2_ net-_q14-pad3_ Q2N2222 +r7 net-_q14-pad3_ net-_q11-pad3_ 50k +q16 net-_c1-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222 +q17 net-_d1-pad2_ net-_q14-pad3_ net-_q13-pad2_ Q2N2222 +r10 net-_q13-pad2_ net-_q11-pad3_ 50 +r8 net-_c1-pad1_ net-_q16-pad2_ 4.5k +r9 net-_d1-pad2_ net-_q16-pad2_ 7.5k +q18 net-_c1-pad1_ net-_q18-pad2_ net-_d2-pad1_ Q2N2222 +q19 net-_q12-pad3_ net-_c1-pad1_ net-_q18-pad2_ Q2N2222 +r11 net-_q18-pad2_ net-_d2-pad1_ 25 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d2-pad1_ net-_d1-pad1_ 1N4148 +r12 net-_d2-pad1_ net-_q20-pad3_ 50 +q20 net-_q11-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2907A +q25 net-_q21-pad1_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q29 net-_q22-pad2_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q35 net-_c2-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q21-pad3_ Q2N2907A +q28 net-_q21-pad1_ net-_q28-pad2_ net-_q26-pad3_ Q2N2222 +q26 net-_c2-pad2_ net-_q22-pad2_ net-_q26-pad3_ Q2N2907A +q24 net-_q12-pad3_ net-_q22-pad1_ net-_q23-pad2_ Q2N2222 +q23 net-_q22-pad1_ net-_q23-pad2_ net-_q23-pad3_ Q2N2222 +q27 net-_c2-pad2_ net-_q23-pad2_ net-_q27-pad3_ Q2N2222 +r13 net-_q23-pad3_ net-_q11-pad3_ 1k +r14 net-_q23-pad2_ net-_q11-pad3_ 50k +r15 net-_q27-pad3_ net-_q11-pad3_ 1k +r17 net-_q32-pad1_ net-_r17-pad2_ 19.5k +r18 net-_r17-pad2_ net-_q30-pad2_ 19.5k +q30 net-_q22-pad2_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222 +q31 net-_q30-pad2_ net-_q30-pad2_ net-_q11-pad3_ Q2N2222 +r16 net-_q30-pad3_ net-_q11-pad3_ 5k +c2 net-_c2-pad1_ net-_c2-pad2_ 30p +q33 net-_c2-pad2_ net-_q33-pad2_ net-_q11-pad3_ Q2N2222 +q34 net-_d3-pad2_ net-_c2-pad2_ net-_q34-pad3_ Q2N2222 +r19 net-_q34-pad3_ net-_q11-pad3_ 50k +q36 net-_c2-pad1_ net-_q36-pad2_ net-_d3-pad2_ Q2N2222 +q37 net-_d3-pad2_ net-_q34-pad3_ net-_q33-pad2_ Q2N2222 +r22 net-_q33-pad2_ net-_q11-pad3_ 50 +r20 net-_c2-pad1_ net-_q36-pad2_ 4.5k +r21 net-_d3-pad2_ net-_q36-pad2_ 7.5k +q38 net-_c2-pad1_ net-_q38-pad2_ net-_d4-pad1_ Q2N2222 +q39 net-_q12-pad3_ net-_c2-pad1_ net-_q38-pad2_ Q2N2222 +r23 net-_q38-pad2_ net-_d4-pad1_ 25 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad1_ 1N4148 +r24 net-_d4-pad1_ net-_q40-pad3_ 50 +q40 net-_q11-pad3_ net-_d3-pad2_ net-_q40-pad3_ Q2N2907A +* u1 net-_q1-pad2_ net-_q8-pad2_ net-_q11-pad3_ net-_q21-pad2_ net-_q12-pad3_ net-_d2-pad1_ net-_q28-pad2_ net-_d4-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm1458/lm1458.pro b/library/SubcircuitLibrary/lm1458/lm1458.pro new file mode 100644 index 00000000..1c549d98 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:31:22 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/lm1458/lm1458.sch b/library/SubcircuitLibrary/lm1458/lm1458.sch new file mode 100644 index 00000000..591e1bf7 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.sch @@ -0,0 +1,1313 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:lm1458-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q5 +U 1 1 631B7C0B +P 2100 1600 +F 0 "Q5" H 2000 1650 50 0000 R CNN +F 1 "eSim_PNP" H 2050 1750 50 0000 R CNN +F 2 "" H 2300 1700 29 0000 C CNN +F 3 "" H 2100 1600 60 0000 C CNN + 1 2100 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 631B7C0C +P 2700 1600 +F 0 "Q9" H 2600 1650 50 0000 R CNN +F 1 "eSim_PNP" H 2650 1750 50 0000 R CNN +F 2 "" H 2900 1700 29 0000 C CNN +F 3 "" H 2700 1600 60 0000 C CNN + 1 2700 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 631B7C0D +P 3650 1600 +F 0 "Q12" H 3550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 3600 1750 50 0000 R CNN +F 2 "" H 3850 1700 29 0000 C CNN +F 3 "" H 3650 1600 60 0000 C CNN + 1 3650 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 631B7C0E +P 4650 1600 +F 0 "Q15" H 4550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 4600 1750 50 0000 R CNN +F 2 "" H 4850 1700 29 0000 C CNN +F 3 "" H 4650 1600 60 0000 C CNN + 1 4650 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 631B7C0F +P 1150 2300 +F 0 "Q1" H 1050 2350 50 0000 R CNN +F 1 "eSim_NPN" H 1100 2450 50 0000 R CNN +F 2 "" H 1350 2400 29 0000 C CNN +F 3 "" H 1150 2300 60 0000 C CNN + 1 1150 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 1600 2500 1600 +Wire Wire Line + 2350 1600 2350 2100 +Wire Wire Line + 1250 1950 2350 1950 +Wire Wire Line + 1250 1950 1250 2100 +Connection ~ 2350 1600 +Wire Wire Line + 2000 1800 2000 1950 +Connection ~ 2000 1950 +$Comp +L eSim_PNP Q2 +U 1 1 631B7C10 +P 1350 3050 +F 0 "Q2" H 1250 3100 50 0000 R CNN +F 1 "eSim_PNP" H 1300 3200 50 0000 R CNN +F 2 "" H 1550 3150 29 0000 C CNN +F 3 "" H 1350 3050 60 0000 C CNN + 1 1350 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 1250 2500 1250 2850 +$Comp +L eSim_NPN Q8 +U 1 1 631B7C11 +P 2450 2300 +F 0 "Q8" H 2350 2350 50 0000 R CNN +F 1 "eSim_NPN" H 2400 2450 50 0000 R CNN +F 2 "" H 2650 2400 29 0000 C CNN +F 3 "" H 2450 2300 60 0000 C CNN + 1 2450 2300 + -1 0 0 -1 +$EndComp +Connection ~ 2350 1950 +$Comp +L eSim_PNP Q6 +U 1 1 631B7C12 +P 2250 3050 +F 0 "Q6" H 2150 3100 50 0000 R CNN +F 1 "eSim_PNP" H 2200 3200 50 0000 R CNN +F 2 "" H 2450 3150 29 0000 C CNN +F 3 "" H 2250 3050 60 0000 C CNN + 1 2250 3050 + 1 0 0 1 +$EndComp +Wire Wire Line + 2350 2850 2350 2500 +Wire Wire Line + 1550 3050 2050 3050 +Wire Wire Line + 2650 2300 2650 2650 +Wire Wire Line + 2650 2650 1000 2650 +Wire Wire Line + 950 2300 750 2300 +$Comp +L eSim_NPN Q4 +U 1 1 631B7C13 +P 1550 3700 +F 0 "Q4" H 1450 3750 50 0000 R CNN +F 1 "eSim_NPN" H 1500 3850 50 0000 R CNN +F 2 "" H 1750 3800 29 0000 C CNN +F 3 "" H 1550 3700 60 0000 C CNN + 1 1550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 3700 1250 3700 +Wire Wire Line + 1250 3250 1250 4200 +Wire Wire Line + 2000 1400 2000 1200 +Wire Wire Line + 1650 1200 10650 1200 +Wire Wire Line + 1650 1200 1650 3500 +Wire Wire Line + 2800 1200 2800 1400 +Connection ~ 2000 1200 +Wire Wire Line + 2800 1800 2800 4200 +Wire Wire Line + 2800 2850 2000 2850 +Wire Wire Line + 2000 2850 2000 3050 +Connection ~ 2000 3050 +Connection ~ 2800 2850 +$Comp +L eSim_NPN Q3 +U 1 1 631B7C14 +P 1350 4400 +F 0 "Q3" H 1250 4450 50 0000 R CNN +F 1 "eSim_NPN" H 1300 4550 50 0000 R CNN +F 2 "" H 1550 4500 29 0000 C CNN +F 3 "" H 1350 4400 60 0000 C CNN + 1 1350 4400 + -1 0 0 -1 +$EndComp +Connection ~ 1250 3700 +Wire Wire Line + 1550 4400 2050 4400 +Wire Wire Line + 1650 4400 1650 3900 +$Comp +L eSim_NPN Q7 +U 1 1 631B7C15 +P 2250 4400 +F 0 "Q7" H 2150 4450 50 0000 R CNN +F 1 "eSim_NPN" H 2200 4550 50 0000 R CNN +F 2 "" H 2450 4500 29 0000 C CNN +F 3 "" H 2250 4400 60 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +Connection ~ 1650 4400 +Wire Wire Line + 2350 3250 2350 4200 +$Comp +L resistor R1 +U 1 1 631B7C16 +P 1200 4850 +F 0 "R1" H 1250 4980 50 0000 C CNN +F 1 "1k" H 1250 4800 50 0000 C CNN +F 2 "" H 1250 4830 30 0000 C CNN +F 3 "" V 1250 4900 30 0000 C CNN + 1 1200 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 631B7C17 +P 1950 4850 +F 0 "R2" H 2000 4980 50 0000 C CNN +F 1 "50k" H 2000 4800 50 0000 C CNN +F 2 "" H 2000 4830 30 0000 C CNN +F 3 "" V 2000 4900 30 0000 C CNN + 1 1950 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 631B7C18 +P 2300 4850 +F 0 "R3" H 2350 4980 50 0000 C CNN +F 1 "1k" H 2350 4800 50 0000 C CNN +F 2 "" H 2350 4830 30 0000 C CNN +F 3 "" V 2350 4900 30 0000 C CNN + 1 2300 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 4750 2350 4600 +Wire Wire Line + 2000 4750 2000 4400 +Connection ~ 2000 4400 +Wire Wire Line + 1250 4750 1250 4600 +Wire Wire Line + 1250 5050 1250 5200 +Wire Wire Line + 2350 5200 2350 5050 +Wire Wire Line + 1250 5200 10650 5200 +Wire Wire Line + 2000 5200 2000 5050 +Connection ~ 2000 5200 +Wire Wire Line + 3550 1200 3550 1400 +Connection ~ 2800 1200 +Wire Wire Line + 3850 1600 4450 1600 +Wire Wire Line + 3900 1600 3900 1850 +Wire Wire Line + 3900 1850 3550 1850 +Wire Wire Line + 3550 1800 3550 2250 +$Comp +L resistor R5 +U 1 1 631B7C19 +P 3500 2350 +F 0 "R5" H 3550 2480 50 0000 C CNN +F 1 "19.5k" H 3550 2300 50 0000 C CNN +F 2 "" H 3550 2330 30 0000 C CNN +F 3 "" V 3550 2400 30 0000 C CNN + 1 3500 2350 + 0 1 1 0 +$EndComp +Connection ~ 3550 1850 +$Comp +L resistor R6 +U 1 1 631B7C1A +P 3500 3250 +F 0 "R6" H 3550 3380 50 0000 C CNN +F 1 "19.5k" H 3550 3200 50 0000 C CNN +F 2 "" H 3550 3230 30 0000 C CNN +F 3 "" V 3550 3300 30 0000 C CNN + 1 3500 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 3550 2550 3550 3150 +$Comp +L eSim_NPN Q10 +U 1 1 631B7C1B +P 2900 4400 +F 0 "Q10" H 2800 4450 50 0000 R CNN +F 1 "eSim_NPN" H 2850 4550 50 0000 R CNN +F 2 "" H 3100 4500 29 0000 C CNN +F 3 "" H 2900 4400 60 0000 C CNN + 1 2900 4400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 631B7C1C +P 3450 4400 +F 0 "Q11" H 3350 4450 50 0000 R CNN +F 1 "eSim_NPN" H 3400 4550 50 0000 R CNN +F 2 "" H 3650 4500 29 0000 C CNN +F 3 "" H 3450 4400 60 0000 C CNN + 1 3450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 4400 3250 4400 +Wire Wire Line + 3550 3450 3550 4200 +$Comp +L resistor R4 +U 1 1 631B7C1D +P 2750 4850 +F 0 "R4" H 2800 4980 50 0000 C CNN +F 1 "5k" H 2800 4800 50 0000 C CNN +F 2 "" H 2800 4830 30 0000 C CNN +F 3 "" V 2800 4900 30 0000 C CNN + 1 2750 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 2800 4750 2800 4600 +Wire Wire Line + 2800 5200 2800 5050 +Connection ~ 2350 5200 +Wire Wire Line + 3550 5200 3550 4600 +Connection ~ 2800 5200 +Wire Wire Line + 4750 1200 4750 1400 +Connection ~ 3550 1200 +Connection ~ 3900 1600 +Wire Wire Line + 2350 3900 3900 3900 +Connection ~ 2350 3900 +$Comp +L capacitor C1 +U 1 1 631B7C1E +P 3800 2900 +F 0 "C1" H 3825 3000 50 0000 L CNN +F 1 "30p" H 3825 2800 50 0000 L CNN +F 2 "" H 3838 2750 30 0000 C CNN +F 3 "" H 3800 2900 60 0000 C CNN + 1 3800 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 3050 3800 4350 +Wire Wire Line + 3800 2750 3800 1900 +Wire Wire Line + 3800 1900 5350 1900 +Wire Wire Line + 4750 1800 4750 2400 +Wire Wire Line + 3200 4400 3200 4150 +Wire Wire Line + 3200 4150 3550 4150 +Connection ~ 3550 4150 +Connection ~ 3200 4400 +$Comp +L eSim_NPN Q13 +U 1 1 631B7C1F +P 3900 4550 +F 0 "Q13" H 3800 4600 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4700 50 0000 R CNN +F 2 "" H 4100 4650 29 0000 C CNN +F 3 "" H 3900 4550 60 0000 C CNN + 1 3900 4550 + -1 0 0 -1 +$EndComp +Connection ~ 3800 3900 +Wire Wire Line + 3800 5200 3800 4750 +Connection ~ 3550 5200 +$Comp +L eSim_NPN Q14 +U 1 1 631B7C20 +P 4100 3900 +F 0 "Q14" H 4000 3950 50 0000 R CNN +F 1 "eSim_NPN" H 4050 4050 50 0000 R CNN +F 2 "" H 4300 4000 29 0000 C CNN +F 3 "" H 4100 3900 60 0000 C CNN + 1 4100 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 4550 4750 4550 +Wire Wire Line + 4200 4100 4200 4700 +$Comp +L resistor R7 +U 1 1 631B7C21 +P 4150 4800 +F 0 "R7" H 4200 4930 50 0000 C CNN +F 1 "50k" H 4200 4750 50 0000 C CNN +F 2 "" H 4200 4780 30 0000 C CNN +F 3 "" V 4200 4850 30 0000 C CNN + 1 4150 4800 + 0 1 1 0 +$EndComp +Wire Wire Line + 4200 5200 4200 5000 +Connection ~ 3800 5200 +Wire Wire Line + 4200 3700 4200 3550 +Wire Wire Line + 4200 3550 4900 3550 +$Comp +L eSim_NPN Q16 +U 1 1 631B7C22 +P 4650 2600 +F 0 "Q16" H 4550 2650 50 0000 R CNN +F 1 "eSim_NPN" H 4600 2750 50 0000 R CNN +F 2 "" H 4850 2700 29 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 1 4650 2600 + 1 0 0 -1 +$EndComp +Connection ~ 4750 1900 +Wire Wire Line + 4750 2800 4750 4050 +Connection ~ 4750 3550 +$Comp +L eSim_NPN Q17 +U 1 1 631B7C23 +P 4650 4250 +F 0 "Q17" H 4550 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4600 4400 50 0000 R CNN +F 2 "" H 4850 4350 29 0000 C CNN +F 3 "" H 4650 4250 60 0000 C CNN + 1 4650 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 4250 4200 4250 +Connection ~ 4200 4250 +Wire Wire Line + 4750 4450 4750 4700 +$Comp +L resistor R10 +U 1 1 631B7C24 +P 4700 4800 +F 0 "R10" H 4750 4930 50 0000 C CNN +F 1 "50" H 4750 4750 50 0000 C CNN +F 2 "" H 4750 4780 30 0000 C CNN +F 3 "" V 4750 4850 30 0000 C CNN + 1 4700 4800 + 0 1 1 0 +$EndComp +Connection ~ 4750 4550 +Wire Wire Line + 4750 5200 4750 5000 +Connection ~ 4200 5200 +$Comp +L resistor R8 +U 1 1 631B7C25 +P 4500 2150 +F 0 "R8" H 4550 2280 50 0000 C CNN +F 1 "4.5k" H 4550 2100 50 0000 C CNN +F 2 "" H 4550 2130 30 0000 C CNN +F 3 "" V 4550 2200 30 0000 C CNN + 1 4500 2150 + -1 0 0 1 +$EndComp +$Comp +L resistor R9 +U 1 1 631B7C26 +P 4500 2900 +F 0 "R9" H 4550 3030 50 0000 C CNN +F 1 "7.5k" H 4550 2850 50 0000 C CNN +F 2 "" H 4550 2880 30 0000 C CNN +F 3 "" V 4550 2950 30 0000 C CNN + 1 4500 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 4600 2200 4750 2200 +Connection ~ 4750 2200 +Wire Wire Line + 4600 2950 4750 2950 +Connection ~ 4750 2950 +Wire Wire Line + 4450 2600 4100 2600 +Wire Wire Line + 4100 2200 4100 2950 +Wire Wire Line + 4100 2200 4300 2200 +Wire Wire Line + 4100 2950 4300 2950 +Connection ~ 4100 2600 +$Comp +L eSim_NPN Q18 +U 1 1 631B7C27 +P 5250 2500 +F 0 "Q18" H 5150 2550 50 0000 R CNN +F 1 "eSim_NPN" H 5200 2650 50 0000 R CNN +F 2 "" H 5450 2600 29 0000 C CNN +F 3 "" H 5250 2500 60 0000 C CNN + 1 5250 2500 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1200 +Wire Wire Line + 5150 1900 5150 2300 +$Comp +L eSim_NPN Q19 +U 1 1 631B7C28 +P 5550 1900 +F 0 "Q19" H 5450 1950 50 0000 R CNN +F 1 "eSim_NPN" H 5500 2050 50 0000 R CNN +F 2 "" H 5750 2000 29 0000 C CNN +F 3 "" H 5550 1900 60 0000 C CNN + 1 5550 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5650 1700 5650 1200 +Connection ~ 5650 1200 +Connection ~ 5150 1900 +Wire Wire Line + 5450 2500 5650 2500 +Wire Wire Line + 5650 2100 5650 2750 +$Comp +L resistor R11 +U 1 1 631B7C29 +P 5600 2850 +F 0 "R11" H 5650 2980 50 0000 C CNN +F 1 "25" H 5650 2800 50 0000 C CNN +F 2 "" H 5650 2830 30 0000 C CNN +F 3 "" V 5650 2900 30 0000 C CNN + 1 5600 2850 + 0 1 1 0 +$EndComp +Connection ~ 5650 2500 +Wire Wire Line + 5150 2700 5150 3300 +Wire Wire Line + 5150 3300 5650 3300 +Wire Wire Line + 5650 3050 5650 3800 +$Comp +L eSim_Diode D1 +U 1 1 631B7C2A +P 5050 3550 +F 0 "D1" H 5050 3650 50 0000 C CNN +F 1 "eSim_Diode" H 5050 3450 50 0000 C CNN +F 2 "" H 5050 3550 60 0000 C CNN +F 3 "" H 5050 3550 60 0000 C CNN + 1 5050 3550 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 631B7C2B +P 5400 3550 +F 0 "D2" H 5400 3650 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3450 50 0000 C CNN +F 2 "" H 5400 3550 60 0000 C CNN +F 3 "" H 5400 3550 60 0000 C CNN + 1 5400 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 5250 3550 5200 3550 +Wire Wire Line + 5550 3550 5950 3550 +Connection ~ 5650 3300 +$Comp +L resistor R12 +U 1 1 631B7C2C +P 5600 3900 +F 0 "R12" H 5650 4030 50 0000 C CNN +F 1 "50" H 5650 3850 50 0000 C CNN +F 2 "" H 5650 3880 30 0000 C CNN +F 3 "" V 5650 3950 30 0000 C CNN + 1 5600 3900 + 0 1 1 0 +$EndComp +Connection ~ 5650 3550 +$Comp +L eSim_PNP Q20 +U 1 1 631B7C2D +P 5550 4550 +F 0 "Q20" H 5450 4600 50 0000 R CNN +F 1 "eSim_PNP" H 5500 4700 50 0000 R CNN +F 2 "" H 5750 4650 29 0000 C CNN +F 3 "" H 5550 4550 60 0000 C CNN + 1 5550 4550 + 1 0 0 1 +$EndComp +Wire Wire Line + 5650 4350 5650 4100 +Wire Wire Line + 4750 3850 4900 3850 +Wire Wire Line + 4900 3850 4900 4550 +Wire Wire Line + 4900 4550 5350 4550 +Connection ~ 4750 3850 +Wire Wire Line + 5650 5200 5650 4750 +Connection ~ 4750 5200 +Connection ~ 5650 5200 +$Comp +L eSim_PNP Q25 +U 1 1 631B7C2E +P 7100 1600 +F 0 "Q25" H 7000 1650 50 0000 R CNN +F 1 "eSim_PNP" H 7050 1750 50 0000 R CNN +F 2 "" H 7300 1700 29 0000 C CNN +F 3 "" H 7100 1600 60 0000 C CNN + 1 7100 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 631B7C2F +P 7700 1600 +F 0 "Q29" H 7600 1650 50 0000 R CNN +F 1 "eSim_PNP" H 7650 1750 50 0000 R CNN +F 2 "" H 7900 1700 29 0000 C CNN +F 3 "" H 7700 1600 60 0000 C CNN + 1 7700 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 631B7C30 +P 8650 1600 +F 0 "Q32" H 8550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 8600 1750 50 0000 R CNN +F 2 "" H 8850 1700 29 0000 C CNN +F 3 "" H 8650 1600 60 0000 C CNN + 1 8650 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q35 +U 1 1 631B7C31 +P 9650 1600 +F 0 "Q35" H 9550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 9600 1750 50 0000 R CNN +F 2 "" H 9850 1700 29 0000 C CNN +F 3 "" H 9650 1600 60 0000 C CNN + 1 9650 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 631B7C32 +P 6150 2300 +F 0 "Q21" H 6050 2350 50 0000 R CNN +F 1 "eSim_NPN" H 6100 2450 50 0000 R CNN +F 2 "" H 6350 2400 29 0000 C CNN +F 3 "" H 6150 2300 60 0000 C CNN + 1 6150 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 1600 7500 1600 +Wire Wire Line + 7350 1600 7350 2100 +Wire Wire Line + 6250 1950 7350 1950 +Wire Wire Line + 6250 1950 6250 2100 +Connection ~ 7350 1600 +Wire Wire Line + 7000 1800 7000 1950 +Connection ~ 7000 1950 +$Comp +L eSim_PNP Q22 +U 1 1 631B7C33 +P 6350 3050 +F 0 "Q22" H 6250 3100 50 0000 R CNN +F 1 "eSim_PNP" H 6300 3200 50 0000 R CNN +F 2 "" H 6550 3150 29 0000 C CNN +F 3 "" H 6350 3050 60 0000 C CNN + 1 6350 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6250 2500 6250 2850 +$Comp +L eSim_NPN Q28 +U 1 1 631B7C34 +P 7450 2300 +F 0 "Q28" H 7350 2350 50 0000 R CNN +F 1 "eSim_NPN" H 7400 2450 50 0000 R CNN +F 2 "" H 7650 2400 29 0000 C CNN +F 3 "" H 7450 2300 60 0000 C CNN + 1 7450 2300 + -1 0 0 -1 +$EndComp +Connection ~ 7350 1950 +$Comp +L eSim_PNP Q26 +U 1 1 631B7C35 +P 7250 3050 +F 0 "Q26" H 7150 3100 50 0000 R CNN +F 1 "eSim_PNP" H 7200 3200 50 0000 R CNN +F 2 "" H 7450 3150 29 0000 C CNN +F 3 "" H 7250 3050 60 0000 C CNN + 1 7250 3050 + 1 0 0 1 +$EndComp +Wire Wire Line + 7350 2850 7350 2500 +Wire Wire Line + 6550 3050 7050 3050 +Wire Wire Line + 7650 2300 7650 2650 +Wire Wire Line + 7650 2650 6650 2650 +Wire Wire Line + 5950 2300 5900 2300 +$Comp +L eSim_NPN Q24 +U 1 1 631B7C36 +P 6550 3700 +F 0 "Q24" H 6450 3750 50 0000 R CNN +F 1 "eSim_NPN" H 6500 3850 50 0000 R CNN +F 2 "" H 6750 3800 29 0000 C CNN +F 3 "" H 6550 3700 60 0000 C CNN + 1 6550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6350 3700 6250 3700 +Wire Wire Line + 6250 3250 6250 4200 +Wire Wire Line + 7000 1200 7000 1400 +Wire Wire Line + 6650 1200 6650 3500 +Wire Wire Line + 7800 1200 7800 1400 +Connection ~ 7000 1200 +Wire Wire Line + 7800 1800 7800 4200 +Wire Wire Line + 7800 2850 7000 2850 +Wire Wire Line + 7000 2850 7000 3050 +Connection ~ 7000 3050 +Connection ~ 7800 2850 +$Comp +L eSim_NPN Q23 +U 1 1 631B7C37 +P 6350 4400 +F 0 "Q23" H 6250 4450 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4550 50 0000 R CNN +F 2 "" H 6550 4500 29 0000 C CNN +F 3 "" H 6350 4400 60 0000 C CNN + 1 6350 4400 + -1 0 0 -1 +$EndComp +Connection ~ 6250 3700 +Wire Wire Line + 6550 4400 7050 4400 +Wire Wire Line + 6650 4400 6650 3900 +$Comp +L eSim_NPN Q27 +U 1 1 631B7C38 +P 7250 4400 +F 0 "Q27" H 7150 4450 50 0000 R CNN +F 1 "eSim_NPN" H 7200 4550 50 0000 R CNN +F 2 "" H 7450 4500 29 0000 C CNN +F 3 "" H 7250 4400 60 0000 C CNN + 1 7250 4400 + 1 0 0 -1 +$EndComp +Connection ~ 6650 4400 +Wire Wire Line + 7350 3250 7350 4200 +$Comp +L resistor R13 +U 1 1 631B7C39 +P 6200 4850 +F 0 "R13" H 6250 4980 50 0000 C CNN +F 1 "1k" H 6250 4800 50 0000 C CNN +F 2 "" H 6250 4830 30 0000 C CNN +F 3 "" V 6250 4900 30 0000 C CNN + 1 6200 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 631B7C3A +P 6950 4850 +F 0 "R14" H 7000 4980 50 0000 C CNN +F 1 "50k" H 7000 4800 50 0000 C CNN +F 2 "" H 7000 4830 30 0000 C CNN +F 3 "" V 7000 4900 30 0000 C CNN + 1 6950 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 631B7C3B +P 7300 4850 +F 0 "R15" H 7350 4980 50 0000 C CNN +F 1 "1k" H 7350 4800 50 0000 C CNN +F 2 "" H 7350 4830 30 0000 C CNN +F 3 "" V 7350 4900 30 0000 C CNN + 1 7300 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 7350 4750 7350 4600 +Wire Wire Line + 7000 4750 7000 4400 +Connection ~ 7000 4400 +Wire Wire Line + 6250 4750 6250 4600 +Wire Wire Line + 6250 5200 6250 5050 +Wire Wire Line + 7350 5200 7350 5050 +Wire Wire Line + 7000 5200 7000 5050 +Connection ~ 7000 5200 +Wire Wire Line + 8550 1200 8550 1400 +Connection ~ 7800 1200 +Wire Wire Line + 8850 1600 9450 1600 +Wire Wire Line + 8900 1600 8900 1850 +Wire Wire Line + 8900 1850 8550 1850 +Wire Wire Line + 8550 1800 8550 2250 +$Comp +L resistor R17 +U 1 1 631B7C3C +P 8500 2350 +F 0 "R17" H 8550 2480 50 0000 C CNN +F 1 "19.5k" H 8550 2300 50 0000 C CNN +F 2 "" H 8550 2330 30 0000 C CNN +F 3 "" V 8550 2400 30 0000 C CNN + 1 8500 2350 + 0 1 1 0 +$EndComp +Connection ~ 8550 1850 +$Comp +L resistor R18 +U 1 1 631B7C3D +P 8500 3250 +F 0 "R18" H 8550 3380 50 0000 C CNN +F 1 "19.5k" H 8550 3200 50 0000 C CNN +F 2 "" H 8550 3230 30 0000 C CNN +F 3 "" V 8550 3300 30 0000 C CNN + 1 8500 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 8550 2550 8550 3150 +$Comp +L eSim_NPN Q30 +U 1 1 631B7C3E +P 7900 4400 +F 0 "Q30" H 7800 4450 50 0000 R CNN +F 1 "eSim_NPN" H 7850 4550 50 0000 R CNN +F 2 "" H 8100 4500 29 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 1 7900 4400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 631B7C3F +P 8450 4400 +F 0 "Q31" H 8350 4450 50 0000 R CNN +F 1 "eSim_NPN" H 8400 4550 50 0000 R CNN +F 2 "" H 8650 4500 29 0000 C CNN +F 3 "" H 8450 4400 60 0000 C CNN + 1 8450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8100 4400 8250 4400 +Wire Wire Line + 8550 3450 8550 4200 +$Comp +L resistor R16 +U 1 1 631B7C40 +P 7750 4850 +F 0 "R16" H 7800 4980 50 0000 C CNN +F 1 "5k" H 7800 4800 50 0000 C CNN +F 2 "" H 7800 4830 30 0000 C CNN +F 3 "" V 7800 4900 30 0000 C CNN + 1 7750 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 7800 4750 7800 4600 +Wire Wire Line + 7800 5200 7800 5050 +Connection ~ 7350 5200 +Wire Wire Line + 8550 5200 8550 4600 +Connection ~ 7800 5200 +Wire Wire Line + 9750 1200 9750 1400 +Connection ~ 8550 1200 +Connection ~ 8900 1600 +Wire Wire Line + 7350 3900 8900 3900 +Connection ~ 7350 3900 +$Comp +L capacitor C2 +U 1 1 631B7C41 +P 8800 2900 +F 0 "C2" H 8825 3000 50 0000 L CNN +F 1 "30p" H 8825 2800 50 0000 L CNN +F 2 "" H 8838 2750 30 0000 C CNN +F 3 "" H 8800 2900 60 0000 C CNN + 1 8800 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 3050 8800 4350 +Wire Wire Line + 8800 2750 8800 1900 +Wire Wire Line + 8800 1900 10350 1900 +Wire Wire Line + 9750 1800 9750 2400 +Wire Wire Line + 8200 4400 8200 4150 +Wire Wire Line + 8200 4150 8550 4150 +Connection ~ 8550 4150 +Connection ~ 8200 4400 +$Comp +L eSim_NPN Q33 +U 1 1 631B7C42 +P 8900 4550 +F 0 "Q33" H 8800 4600 50 0000 R CNN +F 1 "eSim_NPN" H 8850 4700 50 0000 R CNN +F 2 "" H 9100 4650 29 0000 C CNN +F 3 "" H 8900 4550 60 0000 C CNN + 1 8900 4550 + -1 0 0 -1 +$EndComp +Connection ~ 8800 3900 +Wire Wire Line + 8800 5200 8800 4750 +Connection ~ 8550 5200 +$Comp +L eSim_NPN Q34 +U 1 1 631B7C43 +P 9100 3900 +F 0 "Q34" H 9000 3950 50 0000 R CNN +F 1 "eSim_NPN" H 9050 4050 50 0000 R CNN +F 2 "" H 9300 4000 29 0000 C CNN +F 3 "" H 9100 3900 60 0000 C CNN + 1 9100 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9100 4550 9750 4550 +Wire Wire Line + 9200 4100 9200 4700 +$Comp +L resistor R19 +U 1 1 631B7C44 +P 9150 4800 +F 0 "R19" H 9200 4930 50 0000 C CNN +F 1 "50k" H 9200 4750 50 0000 C CNN +F 2 "" H 9200 4780 30 0000 C CNN +F 3 "" V 9200 4850 30 0000 C CNN + 1 9150 4800 + 0 1 1 0 +$EndComp +Wire Wire Line + 9200 5200 9200 5000 +Connection ~ 8800 5200 +Wire Wire Line + 9200 3700 9200 3550 +Wire Wire Line + 9200 3550 9900 3550 +$Comp +L eSim_NPN Q36 +U 1 1 631B7C45 +P 9650 2600 +F 0 "Q36" H 9550 2650 50 0000 R CNN +F 1 "eSim_NPN" H 9600 2750 50 0000 R CNN +F 2 "" H 9850 2700 29 0000 C CNN +F 3 "" H 9650 2600 60 0000 C CNN + 1 9650 2600 + 1 0 0 -1 +$EndComp +Connection ~ 9750 1900 +Wire Wire Line + 9750 2800 9750 4050 +Connection ~ 9750 3550 +$Comp +L eSim_NPN Q37 +U 1 1 631B7C46 +P 9650 4250 +F 0 "Q37" H 9550 4300 50 0000 R CNN +F 1 "eSim_NPN" H 9600 4400 50 0000 R CNN +F 2 "" H 9850 4350 29 0000 C CNN +F 3 "" H 9650 4250 60 0000 C CNN + 1 9650 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 4250 9200 4250 +Connection ~ 9200 4250 +Wire Wire Line + 9750 4450 9750 4700 +$Comp +L resistor R22 +U 1 1 631B7C47 +P 9700 4800 +F 0 "R22" H 9750 4930 50 0000 C CNN +F 1 "50" H 9750 4750 50 0000 C CNN +F 2 "" H 9750 4780 30 0000 C CNN +F 3 "" V 9750 4850 30 0000 C CNN + 1 9700 4800 + 0 1 1 0 +$EndComp +Connection ~ 9750 4550 +Wire Wire Line + 9750 5200 9750 5000 +Connection ~ 9200 5200 +$Comp +L resistor R20 +U 1 1 631B7C48 +P 9500 2150 +F 0 "R20" H 9550 2280 50 0000 C CNN +F 1 "4.5k" H 9550 2100 50 0000 C CNN +F 2 "" H 9550 2130 30 0000 C CNN +F 3 "" V 9550 2200 30 0000 C CNN + 1 9500 2150 + -1 0 0 1 +$EndComp +$Comp +L resistor R21 +U 1 1 631B7C49 +P 9500 2900 +F 0 "R21" H 9550 3030 50 0000 C CNN +F 1 "7.5k" H 9550 2850 50 0000 C CNN +F 2 "" H 9550 2880 30 0000 C CNN +F 3 "" V 9550 2950 30 0000 C CNN + 1 9500 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 9600 2200 9750 2200 +Connection ~ 9750 2200 +Wire Wire Line + 9600 2950 9750 2950 +Connection ~ 9750 2950 +Wire Wire Line + 9450 2600 9100 2600 +Wire Wire Line + 9100 2200 9100 2950 +Wire Wire Line + 9100 2200 9300 2200 +Wire Wire Line + 9100 2950 9300 2950 +Connection ~ 9100 2600 +$Comp +L eSim_NPN Q38 +U 1 1 631B7C4A +P 10250 2500 +F 0 "Q38" H 10150 2550 50 0000 R CNN +F 1 "eSim_NPN" H 10200 2650 50 0000 R CNN +F 2 "" H 10450 2600 29 0000 C CNN +F 3 "" H 10250 2500 60 0000 C CNN + 1 10250 2500 + -1 0 0 -1 +$EndComp +Connection ~ 9750 1200 +Wire Wire Line + 10150 1900 10150 2300 +$Comp +L eSim_NPN Q39 +U 1 1 631B7C4B +P 10550 1900 +F 0 "Q39" H 10450 1950 50 0000 R CNN +F 1 "eSim_NPN" H 10500 2050 50 0000 R CNN +F 2 "" H 10750 2000 29 0000 C CNN +F 3 "" H 10550 1900 60 0000 C CNN + 1 10550 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10650 1200 10650 1700 +Connection ~ 10150 1900 +Wire Wire Line + 10450 2500 10650 2500 +Wire Wire Line + 10650 2100 10650 2750 +$Comp +L resistor R23 +U 1 1 631B7C4C +P 10600 2850 +F 0 "R23" H 10650 2980 50 0000 C CNN +F 1 "25" H 10650 2800 50 0000 C CNN +F 2 "" H 10650 2830 30 0000 C CNN +F 3 "" V 10650 2900 30 0000 C CNN + 1 10600 2850 + 0 1 1 0 +$EndComp +Connection ~ 10650 2500 +Wire Wire Line + 10150 2700 10150 3300 +Wire Wire Line + 10150 3300 10650 3300 +Wire Wire Line + 10650 3050 10650 3800 +$Comp +L eSim_Diode D3 +U 1 1 631B7C4D +P 10050 3550 +F 0 "D3" H 10050 3650 50 0000 C CNN +F 1 "eSim_Diode" H 10050 3450 50 0000 C CNN +F 2 "" H 10050 3550 60 0000 C CNN +F 3 "" H 10050 3550 60 0000 C CNN + 1 10050 3550 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 631B7C4E +P 10400 3550 +F 0 "D4" H 10400 3650 50 0000 C CNN +F 1 "eSim_Diode" H 10400 3450 50 0000 C CNN +F 2 "" H 10400 3550 60 0000 C CNN +F 3 "" H 10400 3550 60 0000 C CNN + 1 10400 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 10250 3550 10200 3550 +Wire Wire Line + 10550 3550 10950 3550 +Connection ~ 10650 3300 +$Comp +L resistor R24 +U 1 1 631B7C4F +P 10600 3900 +F 0 "R24" H 10650 4030 50 0000 C CNN +F 1 "50" H 10650 3850 50 0000 C CNN +F 2 "" H 10650 3880 30 0000 C CNN +F 3 "" V 10650 3950 30 0000 C CNN + 1 10600 3900 + 0 1 1 0 +$EndComp +Connection ~ 10650 3550 +$Comp +L eSim_PNP Q40 +U 1 1 631B7C50 +P 10550 4550 +F 0 "Q40" H 10450 4600 50 0000 R CNN +F 1 "eSim_PNP" H 10500 4700 50 0000 R CNN +F 2 "" H 10750 4650 29 0000 C CNN +F 3 "" H 10550 4550 60 0000 C CNN + 1 10550 4550 + 1 0 0 1 +$EndComp +Wire Wire Line + 10650 4350 10650 4100 +Wire Wire Line + 9750 3850 9900 3850 +Wire Wire Line + 9900 3850 9900 4550 +Wire Wire Line + 9900 4550 10350 4550 +Connection ~ 9750 3850 +Wire Wire Line + 10650 5200 10650 4750 +Connection ~ 9750 5200 +Connection ~ 6650 1200 +Connection ~ 6250 5200 +$Comp +L PORT U1 +U 1 1 631B7C51 +P 750 2550 +F 0 "U1" H 800 2650 30 0000 C CNN +F 1 "PORT" H 750 2550 30 0000 C CNN +F 2 "" H 750 2550 60 0000 C CNN +F 3 "" H 750 2550 60 0000 C CNN + 1 750 2550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 631B7C52 +P 1000 2900 +F 0 "U1" H 1050 3000 30 0000 C CNN +F 1 "PORT" H 1000 2900 30 0000 C CNN +F 2 "" H 1000 2900 60 0000 C CNN +F 3 "" H 1000 2900 60 0000 C CNN + 2 1000 2900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 631B7C53 +P 5950 3800 +F 0 "U1" H 6000 3900 30 0000 C CNN +F 1 "PORT" H 5950 3800 30 0000 C CNN +F 2 "" H 5950 3800 60 0000 C CNN +F 3 "" H 5950 3800 60 0000 C CNN + 6 5950 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 631B7C54 +P 5900 2550 +F 0 "U1" H 5950 2650 30 0000 C CNN +F 1 "PORT" H 5900 2550 30 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 4 5900 2550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 631B7C55 +P 6400 2650 +F 0 "U1" H 6450 2750 30 0000 C CNN +F 1 "PORT" H 6400 2650 30 0000 C CNN +F 2 "" H 6400 2650 60 0000 C CNN +F 3 "" H 6400 2650 60 0000 C CNN + 7 6400 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 631B7C56 +P 10950 3800 +F 0 "U1" H 11000 3900 30 0000 C CNN +F 1 "PORT" H 10950 3800 30 0000 C CNN +F 2 "" H 10950 3800 60 0000 C CNN +F 3 "" H 10950 3800 60 0000 C CNN + 8 10950 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 631B7C57 +P 5700 5500 +F 0 "U1" H 5750 5600 30 0000 C CNN +F 1 "PORT" H 5700 5500 30 0000 C CNN +F 2 "" H 5700 5500 60 0000 C CNN +F 3 "" H 5700 5500 60 0000 C CNN + 3 5700 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 631B7C58 +P 5950 950 +F 0 "U1" H 6000 1050 30 0000 C CNN +F 1 "PORT" H 5950 950 30 0000 C CNN +F 2 "" H 5950 950 60 0000 C CNN +F 3 "" H 5950 950 60 0000 C CNN + 5 5950 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 950 6250 950 +Connection ~ 6250 1200 +Wire Wire Line + 5950 5500 6000 5500 +Wire Wire Line + 6000 5500 6000 5200 +Connection ~ 6000 5200 +Wire Wire Line + 6250 950 6250 1200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm1458/lm1458.sub b/library/SubcircuitLibrary/lm1458/lm1458.sub new file mode 100644 index 00000000..8c0eb086 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.sub @@ -0,0 +1,79 @@ +* Subcircuit lm1458 +.subckt lm1458 net-_q1-pad2_ net-_q8-pad2_ net-_q11-pad3_ net-_q21-pad2_ net-_q12-pad3_ net-_d2-pad1_ net-_q28-pad2_ net-_d4-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm1458\lm1458.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q15 net-_c1-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad1_ net-_q1-pad3_ Q2N2907A +q8 net-_q1-pad1_ net-_q8-pad2_ net-_q6-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q10-pad1_ net-_q6-pad3_ Q2N2907A +q4 net-_q12-pad3_ net-_q2-pad1_ net-_q3-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q11-pad3_ 1k +r2 net-_q3-pad2_ net-_q11-pad3_ 50k +r3 net-_q7-pad3_ net-_q11-pad3_ 1k +r5 net-_q12-pad1_ net-_r5-pad2_ 19.5k +r6 net-_r5-pad2_ net-_q10-pad2_ 19.5k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad2_ net-_q10-pad2_ net-_q11-pad3_ Q2N2222 +r4 net-_q10-pad3_ net-_q11-pad3_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q13 net-_c1-pad2_ net-_q13-pad2_ net-_q11-pad3_ Q2N2222 +q14 net-_d1-pad2_ net-_c1-pad2_ net-_q14-pad3_ Q2N2222 +r7 net-_q14-pad3_ net-_q11-pad3_ 50k +q16 net-_c1-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222 +q17 net-_d1-pad2_ net-_q14-pad3_ net-_q13-pad2_ Q2N2222 +r10 net-_q13-pad2_ net-_q11-pad3_ 50 +r8 net-_c1-pad1_ net-_q16-pad2_ 4.5k +r9 net-_d1-pad2_ net-_q16-pad2_ 7.5k +q18 net-_c1-pad1_ net-_q18-pad2_ net-_d2-pad1_ Q2N2222 +q19 net-_q12-pad3_ net-_c1-pad1_ net-_q18-pad2_ Q2N2222 +r11 net-_q18-pad2_ net-_d2-pad1_ 25 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d2-pad1_ net-_d1-pad1_ 1N4148 +r12 net-_d2-pad1_ net-_q20-pad3_ 50 +q20 net-_q11-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2907A +q25 net-_q21-pad1_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q29 net-_q22-pad2_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q35 net-_c2-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q21-pad3_ Q2N2907A +q28 net-_q21-pad1_ net-_q28-pad2_ net-_q26-pad3_ Q2N2222 +q26 net-_c2-pad2_ net-_q22-pad2_ net-_q26-pad3_ Q2N2907A +q24 net-_q12-pad3_ net-_q22-pad1_ net-_q23-pad2_ Q2N2222 +q23 net-_q22-pad1_ net-_q23-pad2_ net-_q23-pad3_ Q2N2222 +q27 net-_c2-pad2_ net-_q23-pad2_ net-_q27-pad3_ Q2N2222 +r13 net-_q23-pad3_ net-_q11-pad3_ 1k +r14 net-_q23-pad2_ net-_q11-pad3_ 50k +r15 net-_q27-pad3_ net-_q11-pad3_ 1k +r17 net-_q32-pad1_ net-_r17-pad2_ 19.5k +r18 net-_r17-pad2_ net-_q30-pad2_ 19.5k +q30 net-_q22-pad2_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222 +q31 net-_q30-pad2_ net-_q30-pad2_ net-_q11-pad3_ Q2N2222 +r16 net-_q30-pad3_ net-_q11-pad3_ 5k +c2 net-_c2-pad1_ net-_c2-pad2_ 30p +q33 net-_c2-pad2_ net-_q33-pad2_ net-_q11-pad3_ Q2N2222 +q34 net-_d3-pad2_ net-_c2-pad2_ net-_q34-pad3_ Q2N2222 +r19 net-_q34-pad3_ net-_q11-pad3_ 50k +q36 net-_c2-pad1_ net-_q36-pad2_ net-_d3-pad2_ Q2N2222 +q37 net-_d3-pad2_ net-_q34-pad3_ net-_q33-pad2_ Q2N2222 +r22 net-_q33-pad2_ net-_q11-pad3_ 50 +r20 net-_c2-pad1_ net-_q36-pad2_ 4.5k +r21 net-_d3-pad2_ net-_q36-pad2_ 7.5k +q38 net-_c2-pad1_ net-_q38-pad2_ net-_d4-pad1_ Q2N2222 +q39 net-_q12-pad3_ net-_c2-pad1_ net-_q38-pad2_ Q2N2222 +r23 net-_q38-pad2_ net-_d4-pad1_ 25 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad1_ 1N4148 +r24 net-_d4-pad1_ net-_q40-pad3_ 50 +q40 net-_q11-pad3_ net-_d3-pad2_ net-_q40-pad3_ Q2N2907A +* Control Statements + +.ends lm1458 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml b/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml new file mode 100644 index 00000000..0ce355b4 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib \ No newline at end of file -- cgit From 7b07b497d083a447c6a7e35d7a05a9d2e3cfa3f3 Mon Sep 17 00:00:00 2001 From: Vanshika Tanwar Date: Wed, 23 Nov 2022 22:00:57 +0530 Subject: INA106 Differential Amplifier IC --- .../Diffamp_INA106/Diffamp_INA106-cache.lib | 83 +++ .../Diffamp_INA106/Diffamp_INA106.cir | 16 + .../Diffamp_INA106/Diffamp_INA106.cir.out | 18 + .../Diffamp_INA106/Diffamp_INA106.pro | 71 +++ .../Diffamp_INA106/Diffamp_INA106.sch | 247 ++++++++ .../Diffamp_INA106/Diffamp_INA106.sub | 12 + .../Diffamp_INA106_Previous_Values.xml | 1 + library/SubcircuitLibrary/Diffamp_INA106/NPN.lib | 4 + library/SubcircuitLibrary/Diffamp_INA106/PNP.lib | 4 + library/SubcircuitLibrary/Diffamp_INA106/README.md | 36 ++ library/SubcircuitLibrary/Diffamp_INA106/analysis | 1 + .../Diffamp_INA106/lm_741-cache.lib | 119 ++++ .../SubcircuitLibrary/Diffamp_INA106/lm_741.cir | 43 ++ .../Diffamp_INA106/lm_741.cir.out | 46 ++ .../SubcircuitLibrary/Diffamp_INA106/lm_741.pro | 44 ++ .../SubcircuitLibrary/Diffamp_INA106/lm_741.sch | 697 +++++++++++++++++++++ .../SubcircuitLibrary/Diffamp_INA106/lm_741.sub | 40 ++ .../Diffamp_INA106/lm_741_Previous_Values.xml | 1 + library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib | 29 + library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib | 29 + 20 files changed, 1541 insertions(+) create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/NPN.lib create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/PNP.lib create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/README.md create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/analysis create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741.sub create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib create mode 100644 library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib (limited to 'library') diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib new file mode 100644 index 00000000..d1bbdfdd --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106-cache.lib @@ -0,0 +1,83 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir new file mode 100644 index 00000000..ca9bf959 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Diffamp_INA106\Diffamp_INA106.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 7/20/2022 1:33:22 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_R1-Pad2_ Net-_R2-Pad2_ /V- ? /Output /V+ ? lm_741 +R1 /-IN Net-_R1-Pad2_ 100k +R2 /+IN Net-_R2-Pad2_ 100k +R4 Net-_R1-Pad2_ /Sense 10k +R3 Net-_R2-Pad2_ /REF 10k +U1 /REF /-IN /+IN /V- /Sense /Output /V+ ? PORT + +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out new file mode 100644 index 00000000..464817c3 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\diffamp_ina106\diffamp_ina106.cir + +.include lm_741.sub +x1 ? net-_r1-pad2_ net-_r2-pad2_ /v- ? /output /v+ ? lm_741 +r1 /-in net-_r1-pad2_ 100k +r2 /+in net-_r2-pad2_ 100k +r4 net-_r1-pad2_ /sense 10k +r3 net-_r2-pad2_ /ref 10k +* u1 /ref /-in /+in /v- /sense /output /v+ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch new file mode 100644 index 00000000..19e9c3bb --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sch @@ -0,0 +1,247 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:Diffamp_INA106-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 62D11E03 +P 5050 3650 +F 0 "X1" H 4850 3650 60 0000 C CNN +F 1 "lm_741" H 4950 3400 60 0000 C CNN +F 2 "" H 5050 3650 60 0000 C CNN +F 3 "" H 5050 3650 60 0000 C CNN + 1 5050 3650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62D11E04 +P 3450 3550 +F 0 "R1" H 3500 3680 50 0000 C CIB +F 1 "100k" H 3500 3500 50 0000 C CNN +F 2 "" H 3500 3530 30 0000 C CNN +F 3 "" V 3500 3600 30 0000 C CNN + 1 3450 3550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 62D11E05 +P 3450 3800 +F 0 "R2" H 3500 3930 50 0000 C CIB +F 1 "100k" H 3500 3750 50 0000 C CNN +F 2 "" H 3500 3780 30 0000 C CNN +F 3 "" V 3500 3850 30 0000 C CNN + 1 3450 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 62D11E06 +P 5300 3050 +F 0 "R4" H 5350 3180 50 0000 C CIB +F 1 "10k" H 5350 3000 50 0000 C CNN +F 2 "" H 5350 3030 30 0000 C CNN +F 3 "" V 5350 3100 30 0000 C CNN + 1 5300 3050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 62D11E07 +P 4200 4400 +F 0 "R3" H 4250 4530 50 0000 C CIB +F 1 "10k" H 4250 4350 50 0000 C CNN +F 2 "" H 4250 4380 30 0000 C CNN +F 3 "" V 4250 4450 30 0000 C CNN + 1 4200 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 5500 3000 6650 3000 +Wire Wire Line + 3650 3750 4500 3750 +Wire Wire Line + 3650 3500 4500 3500 +Wire Wire Line + 4900 4100 4900 4350 +Wire Wire Line + 4250 3000 5200 3000 +Wire Wire Line + 4250 3000 4250 3500 +Connection ~ 4250 3500 +Wire Wire Line + 4250 4300 4250 3750 +Connection ~ 4250 3750 +Wire Wire Line + 4800 3150 4900 3150 +Wire Wire Line + 4900 3150 4900 3200 +Wire Wire Line + 2700 3500 3350 3500 +Wire Wire Line + 2700 3750 3350 3750 +Wire Wire Line + 3750 4650 4250 4650 +Wire Wire Line + 4250 4650 4250 4600 +Text Label 2900 3500 0 60 Italic 0 +-IN +Text Label 2900 3750 0 60 Italic 0 ++IN +Text Label 4850 3150 0 60 ~ 12 +V+ +Text Label 4900 4200 0 60 ~ 12 +V- +Text Label 6350 3000 0 60 ~ 0 +Sense +Text Label 3900 4650 0 60 ~ 0 +REF +Text Label 6350 3650 0 49 Italic 0 +Output +NoConn ~ 5000 3250 +NoConn ~ 5100 3300 +Wire Wire Line + 4900 4350 4850 4350 +$Comp +L PORT U1 +U 3 1 62D11F12 +P 2450 3750 +F 0 "U1" H 2500 3850 30 0000 C CNN +F 1 "PORT" H 2450 3750 30 0000 C CNN +F 2 "" H 2450 3750 60 0000 C CNN +F 3 "" H 2450 3750 60 0000 C CNN + 3 2450 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62D11F93 +P 3500 4650 +F 0 "U1" H 3550 4750 30 0000 C CNN +F 1 "PORT" H 3500 4650 30 0000 C CNN +F 2 "" H 3500 4650 60 0000 C CNN +F 3 "" H 3500 4650 60 0000 C CNN + 1 3500 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62D1202E +P 2450 3500 +F 0 "U1" H 2500 3600 30 0000 C CNN +F 1 "PORT" H 2450 3500 30 0000 C CNN +F 2 "" H 2450 3500 60 0000 C CNN +F 3 "" H 2450 3500 60 0000 C CNN + 2 2450 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62D12099 +P 6900 3000 +F 0 "U1" H 6950 3100 30 0000 C CNN +F 1 "PORT" H 6900 3000 30 0000 C CNN +F 2 "" H 6900 3000 60 0000 C CNN +F 3 "" H 6900 3000 60 0000 C CNN + 5 6900 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 62D12114 +P 4550 3150 +F 0 "U1" H 4600 3250 30 0000 C CNN +F 1 "PORT" H 4550 3150 30 0000 C CNN +F 2 "" H 4550 3150 60 0000 C CNN +F 3 "" H 4550 3150 60 0000 C CNN + 7 4550 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 62D121A7 +P 6200 4250 +F 0 "U1" H 6250 4350 30 0000 C CNN +F 1 "PORT" H 6200 4250 30 0000 C CNN +F 2 "" H 6200 4250 60 0000 C CNN +F 3 "" H 6200 4250 60 0000 C CNN + 8 6200 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62D121EE +P 4600 4350 +F 0 "U1" H 4650 4450 30 0000 C CNN +F 1 "PORT" H 4600 4350 30 0000 C CNN +F 2 "" H 4600 4350 60 0000 C CNN +F 3 "" H 4600 4350 60 0000 C CNN + 4 4600 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62D1221F +P 6900 3650 +F 0 "U1" H 6950 3750 30 0000 C CNN +F 1 "PORT" H 6900 3650 30 0000 C CNN +F 2 "" H 6900 3650 60 0000 C CNN +F 3 "" H 6900 3650 60 0000 C CNN + 6 6900 3650 + -1 0 0 1 +$EndComp +NoConn ~ 5950 4250 +Wire Wire Line + 5600 3650 6650 3650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub new file mode 100644 index 00000000..18c305cf --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106.sub @@ -0,0 +1,12 @@ +* Subcircuit Diffamp_INA106 +.subckt Diffamp_INA106 /ref /-in /+in /v- /sense /output /v+ ? +* c:\fossee\esim\library\subcircuitlibrary\diffamp_ina106\diffamp_ina106.cir +.include lm_741.sub +x1 ? net-_r1-pad2_ net-_r2-pad2_ /v- ? /output /v+ ? lm_741 +r1 /-in net-_r1-pad2_ 100k +r2 /+in net-_r2-pad2_ 100k +r4 net-_r1-pad2_ /sense 10k +r3 net-_r2-pad2_ /ref 10k +* Control Statements + +.ends Diffamp_INA106 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml new file mode 100644 index 00000000..a7f22b8a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/Diffamp_INA106_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib b/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib b/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/Diffamp_INA106/README.md b/library/SubcircuitLibrary/Diffamp_INA106/README.md new file mode 100644 index 00000000..e95e5fc5 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/README.md @@ -0,0 +1,36 @@ + +## Differential Amplifier IC + +Differential Amplifier is a type of amplifier circuit which is used to amplify the difference of input and give the output respectively. It is used to remove noise which is present in input signal. + +## Usage/Examples + +It is used in Amplitude Modulation. + +It is used in Audio Amplifier for exact and noiseless volume control. + +It is used in Digital and Analog data transmission system for noise cancellation. + +It is used for audio and video processing. + +It is used as an automatic gain control circuit. + +It is used as an electronic switch. + +It is used for motor control. + + +## Documentation + +To know the details of INA106 Differential Amplifier IC please refer to this link [INA106_Differential_Amplifier_datasheet.](https://www.ti.com/lit/ds/symlink/ina106.pdf?ts=1659516896123&ref_url=https%253A%252F%252Fwww.google.co.in%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/Diffamp_INA106/analysis b/library/SubcircuitLibrary/Diffamp_INA106/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib b/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro new file mode 100644 index 00000000..b56de1b0 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN 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mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib b/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib b/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/Diffamp_INA106/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file -- cgit From d896724e0d54dd42ad9f7e0f26b884623a9d1cb2 Mon Sep 17 00:00:00 2001 From: Vanshika Tanwar Date: Wed, 23 Nov 2022 22:03:17 +0530 Subject: 74LVC1G19 1:2 Demux IC --- library/SubcircuitLibrary/demux/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/demux/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/demux/README.md | 28 + library/SubcircuitLibrary/demux/analysis | 1 + library/SubcircuitLibrary/demux/demux-cache.lib | 100 ++++ library/SubcircuitLibrary/demux/demux.cir | 25 + library/SubcircuitLibrary/demux/demux.cir.out | 28 + library/SubcircuitLibrary/demux/demux.pro | 71 +++ library/SubcircuitLibrary/demux/demux.sch | 569 +++++++++++++++++++++ library/SubcircuitLibrary/demux/demux.sub | 22 + .../demux/demux_Previous_Values.xml | 1 + 11 files changed, 869 insertions(+) create mode 100644 library/SubcircuitLibrary/demux/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/demux/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/demux/README.md create mode 100644 library/SubcircuitLibrary/demux/analysis create mode 100644 library/SubcircuitLibrary/demux/demux-cache.lib create mode 100644 library/SubcircuitLibrary/demux/demux.cir create mode 100644 library/SubcircuitLibrary/demux/demux.cir.out create mode 100644 library/SubcircuitLibrary/demux/demux.pro create mode 100644 library/SubcircuitLibrary/demux/demux.sch create mode 100644 library/SubcircuitLibrary/demux/demux.sub create mode 100644 library/SubcircuitLibrary/demux/demux_Previous_Values.xml (limited to 'library') diff --git a/library/SubcircuitLibrary/demux/NMOS-180nm.lib b/library/SubcircuitLibrary/demux/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/demux/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/demux/PMOS-180nm.lib b/library/SubcircuitLibrary/demux/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/demux/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/demux/README.md b/library/SubcircuitLibrary/demux/README.md new file mode 100644 index 00000000..b2bb3cb4 --- /dev/null +++ b/library/SubcircuitLibrary/demux/README.md @@ -0,0 +1,28 @@ + +# Demux IC + +Demux is the de-multiplexer circuit that takes one input line and gives multiple output lines. Basically, it’s a combinational circuit and It always takes one input +line and gives 2n output line, where n is the number of select lines. It is also, known as a serial to parallel converter or data distributor circuit. The 1:2 Demux consist of 1 input line, 1 select line, and produces 2 output line. as, according to the formula no. of the output line is depends on no. of select line, here, in 1:2 demux, no. of output line = 2^n = 2^1 = 2. + + +## Usage/Examples + +It is used in communication systems. + +It is used in serial to parallel converter. + + +## Documentation + +To know the details of 74LVC1G19 IC please refer to this link [74LVC1G19_IC_datasheet.](https://assets.nexperia.com/documents/data-sheet/74LVC1G19.pdf) + +## Comments/Notes + +Please note this is a complete Digital IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/demux/analysis b/library/SubcircuitLibrary/demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/demux/demux-cache.lib b/library/SubcircuitLibrary/demux/demux-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/demux/demux.cir b/library/SubcircuitLibrary/demux/demux.cir new file mode 100644 index 00000000..720a8dff --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\demux\demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 8/18/2022 2:01:37 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 /Vcc /Ebar Net-_M1-Pad1_ /Vcc mosfet_p +M1 Net-_M1-Pad1_ /Ebar /GND /GND mosfet_n +M3 /Vcc Net-_M1-Pad1_ Net-_M11-Pad2_ /Vcc mosfet_p +M9 /Vcc /A Net-_M11-Pad2_ /Vcc mosfet_p +M4 /Vcc /Ebar Net-_M10-Pad3_ /Vcc mosfet_p +M10 /Vcc /A Net-_M10-Pad3_ /Vcc mosfet_p +M5 Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M5-Pad3_ /GND mosfet_n +M6 Net-_M5-Pad3_ /A /GND /GND mosfet_n +M7 Net-_M10-Pad3_ /Ebar Net-_M7-Pad3_ /GND mosfet_n +M8 Net-_M7-Pad3_ /A /GND /GND mosfet_n +M13 /Vcc Net-_M11-Pad2_ /Y1 /Vcc mosfet_p +M11 /Y1 Net-_M11-Pad2_ /GND /GND mosfet_n +M14 /Vcc Net-_M10-Pad3_ /Y2 /Vcc mosfet_p +M12 /Y2 Net-_M10-Pad3_ /GND /GND mosfet_n +U1 /A /GND /Ebar /Y2 /Vcc /Y1 PORT + +.end diff --git a/library/SubcircuitLibrary/demux/demux.cir.out b/library/SubcircuitLibrary/demux/demux.cir.out new file mode 100644 index 00000000..d5837005 --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.cir.out @@ -0,0 +1,28 @@ +* c:\fossee\esim\library\subcircuitlibrary\demux\demux.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 /vcc /ebar net-_m1-pad1_ /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ /ebar /gnd /gnd CMOSN W=100u L=100u M=1 +m3 /vcc net-_m1-pad1_ net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m9 /vcc /a net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m4 /vcc /ebar net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m10 /vcc /a net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m5 net-_m11-pad2_ net-_m1-pad1_ net-_m5-pad3_ /gnd CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m7 net-_m10-pad3_ /ebar net-_m7-pad3_ /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m13 /vcc net-_m11-pad2_ /y1 /vcc CMOSP W=100u L=100u M=1 +m11 /y1 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m14 /vcc net-_m10-pad3_ /y2 /vcc CMOSP W=100u L=100u M=1 +m12 /y2 net-_m10-pad3_ /gnd /gnd CMOSN W=100u L=100u M=1 +* u1 /a /gnd /ebar /y2 /vcc /y1 port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/demux/demux.pro b/library/SubcircuitLibrary/demux/demux.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/demux/demux.sch b/library/SubcircuitLibrary/demux/demux.sch new file mode 100644 index 00000000..90d6f38d --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.sch @@ -0,0 +1,569 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62F8023F +P 3000 2500 +F 0 "M2" H 2950 2550 50 0000 R CNN +F 1 "mosfet_p" H 3050 2650 50 0000 R CNN +F 2 "" H 3250 2600 29 0000 C CNN +F 3 "" H 3050 2500 60 0000 C CNN + 1 3000 2500 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62F80240 +P 2950 3000 +F 0 "M1" H 2950 2850 50 0000 R CNN +F 1 "mosfet_n" H 3050 2950 50 0000 R CNN +F 2 "" H 3250 2700 29 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 1 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62F80242 +P 4850 1900 +F 0 "M3" H 4800 1950 50 0000 R CNN +F 1 "mosfet_p" H 4900 2050 50 0000 R CNN +F 2 "" H 5100 2000 29 0000 C CNN +F 3 "" H 4900 1900 60 0000 C CNN + 1 4850 1900 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M9 +U 1 1 62F80243 +P 5850 1900 +F 0 "M9" H 5800 1950 50 0000 R CNN +F 1 "mosfet_p" H 5900 2050 50 0000 R CNN +F 2 "" H 6100 2000 29 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62F80244 +P 4950 5100 +F 0 "M4" H 4900 5150 50 0000 R CNN +F 1 "mosfet_p" H 5000 5250 50 0000 R CNN +F 2 "" H 5200 5200 29 0000 C CNN +F 3 "" H 5000 5100 60 0000 C CNN + 1 4950 5100 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M10 +U 1 1 62F80245 +P 5950 5100 +F 0 "M10" H 5900 5150 50 0000 R CNN +F 1 "mosfet_p" H 6000 5250 50 0000 R CNN +F 2 "" H 6200 5200 29 0000 C CNN +F 3 "" H 6000 5100 60 0000 C CNN + 1 5950 5100 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 62F80246 +P 5300 2750 +F 0 "M5" H 5300 2600 50 0000 R CNN +F 1 "mosfet_n" H 5400 2700 50 0000 R CNN +F 2 "" H 5600 2450 29 0000 C CNN +F 3 "" H 5400 2550 60 0000 C CNN + 1 5300 2750 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 62F80247 +P 5300 3550 +F 0 "M6" H 5300 3400 50 0000 R CNN +F 1 "mosfet_n" H 5400 3500 50 0000 R CNN +F 2 "" H 5600 3250 29 0000 C CNN +F 3 "" H 5400 3350 60 0000 C CNN + 1 5300 3550 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M7 +U 1 1 62F80249 +P 5450 5800 +F 0 "M7" H 5450 5650 50 0000 R CNN +F 1 "mosfet_n" H 5550 5750 50 0000 R CNN +F 2 "" H 5750 5500 29 0000 C CNN +F 3 "" H 5550 5600 60 0000 C CNN + 1 5450 5800 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M8 +U 1 1 62F8024A +P 5450 6500 +F 0 "M8" H 5450 6350 50 0000 R CNN +F 1 "mosfet_n" H 5550 6450 50 0000 R CNN +F 2 "" H 5750 6200 29 0000 C CNN +F 3 "" H 5550 6300 60 0000 C CNN + 1 5450 6500 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M13 +U 1 1 62F80250 +P 8000 2150 +F 0 "M13" H 7950 2200 50 0000 R CNN +F 1 "mosfet_p" H 8050 2300 50 0000 R CNN +F 2 "" H 8250 2250 29 0000 C CNN +F 3 "" H 8050 2150 60 0000 C CNN + 1 8000 2150 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M11 +U 1 1 62F80251 +P 7950 2800 +F 0 "M11" H 7950 2650 50 0000 R CNN +F 1 "mosfet_n" H 8050 2750 50 0000 R CNN +F 2 "" H 8250 2500 29 0000 C CNN +F 3 "" H 8050 2600 60 0000 C CNN + 1 7950 2800 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M14 +U 1 1 62F80252 +P 8000 5150 +F 0 "M14" H 7950 5200 50 0000 R CNN +F 1 "mosfet_p" H 8050 5300 50 0000 R CNN +F 2 "" H 8250 5250 29 0000 C CNN +F 3 "" H 8050 5150 60 0000 C CNN + 1 8000 5150 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M12 +U 1 1 62F80253 +P 7950 5750 +F 0 "M12" H 7950 5600 50 0000 R CNN +F 1 "mosfet_n" H 8050 5700 50 0000 R CNN +F 2 "" H 8250 5450 29 0000 C CNN +F 3 "" H 8050 5550 60 0000 C CNN + 1 7950 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62F8236C +P 5950 7600 +F 0 "U1" H 6000 7700 30 0000 C CNN +F 1 "PORT" H 5950 7600 30 0000 C CNN +F 2 "" H 5950 7600 60 0000 C CNN +F 3 "" H 5950 7600 60 0000 C CNN + 2 5950 7600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62F82472 +P 9200 5600 +F 0 "U1" H 9250 5700 30 0000 C CNN +F 1 "PORT" H 9200 5600 30 0000 C CNN +F 2 "" H 9200 5600 60 0000 C CNN +F 3 "" H 9200 5600 60 0000 C CNN + 4 9200 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62F824AB +P 1850 5300 +F 0 "U1" H 1900 5400 30 0000 C CNN +F 1 "PORT" H 1850 5300 30 0000 C CNN +F 2 "" H 1850 5300 60 0000 C CNN +F 3 "" H 1850 5300 60 0000 C CNN + 1 1850 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62F824F0 +P 5700 950 +F 0 "U1" H 5750 1050 30 0000 C CNN +F 1 "PORT" H 5700 950 30 0000 C CNN +F 2 "" H 5700 950 60 0000 C CNN +F 3 "" H 5700 950 60 0000 C CNN + 5 5700 950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 62F825BB +P 1550 2700 +F 0 "U1" H 1600 2800 30 0000 C CNN +F 1 "PORT" H 1550 2700 30 0000 C CNN +F 2 "" H 1550 2700 60 0000 C CNN +F 3 "" H 1550 2700 60 0000 C CNN + 3 1550 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 62F8264A +P 9400 2450 +F 0 "U1" H 9450 2550 30 0000 C CNN +F 1 "PORT" H 9400 2450 30 0000 C CNN +F 2 "" H 9400 2450 60 0000 C CNN +F 3 "" H 9400 2450 60 0000 C CNN + 6 9400 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2700 3150 3000 +Wire Wire Line + 3150 3400 3150 7400 +Wire Wire Line + 2850 2500 2550 2500 +Wire Wire Line + 2550 2500 2550 3200 +Wire Wire Line + 2550 3200 2850 3200 +Wire Wire Line + 5000 1700 5000 1550 +Wire Wire Line + 5000 1550 6000 1550 +Wire Wire Line + 6000 1550 6000 1700 +Wire Wire Line + 5000 2100 5000 2300 +Wire Wire Line + 5000 2300 6000 2300 +Wire Wire Line + 6000 2300 6000 2100 +Wire Wire Line + 5500 2300 5500 2750 +Connection ~ 5500 2300 +Wire Wire Line + 5500 3550 5500 3150 +Wire Wire Line + 5500 3950 5500 4150 +Wire Wire Line + 5100 4900 5100 4700 +Wire Wire Line + 5100 4700 6100 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5500 4050 +Wire Wire Line + 5100 2050 5200 2050 +Wire Wire Line + 5200 2050 5200 1550 +Connection ~ 5200 1550 +Wire Wire Line + 6100 2050 6200 2050 +Wire Wire Line + 6200 2050 6200 1650 +Wire Wire Line + 6200 1650 6000 1650 +Connection ~ 6000 1650 +Wire Wire Line + 3250 3350 3300 3350 +Wire Wire Line + 3300 3350 3300 3500 +Wire Wire Line + 3300 3500 3150 3500 +Connection ~ 3150 3500 +Wire Wire Line + 4700 1900 4500 1900 +Wire Wire Line + 4500 1900 4500 2850 +Wire Wire Line + 4500 2850 3150 2850 +Connection ~ 3150 2850 +Wire Wire Line + 5200 2950 5050 2950 +Wire Wire Line + 5050 2950 5050 2700 +Wire Wire Line + 5050 2700 4500 2700 +Connection ~ 4500 2700 +Wire Wire Line + 3150 1350 3150 2300 +Wire Wire Line + 3150 1350 5450 1350 +Connection ~ 5450 1550 +Wire Wire Line + 4200 1350 4200 4550 +Wire Wire Line + 4200 4550 5500 4550 +Wire Wire Line + 5500 4550 5500 4700 +Connection ~ 5500 4700 +Connection ~ 4200 1350 +Connection ~ 5450 1350 +Wire Wire Line + 1800 2700 2550 2700 +Connection ~ 2550 2700 +Wire Wire Line + 5350 6700 3800 6700 +Wire Wire Line + 5800 5300 5800 5100 +Wire Wire Line + 2100 5300 5800 5300 +Wire Wire Line + 3800 6700 3800 5300 +Connection ~ 3800 5300 +Wire Wire Line + 3650 3750 5200 3750 +Wire Wire Line + 3650 3750 3650 5300 +Connection ~ 3650 5300 +Wire Wire Line + 2250 5100 4800 5100 +Wire Wire Line + 2250 5100 2250 2700 +Connection ~ 2250 2700 +Wire Wire Line + 5350 6000 4300 6000 +Wire Wire Line + 4300 6000 4300 5100 +Connection ~ 4300 5100 +Wire Wire Line + 5700 1900 5700 2200 +Wire Wire Line + 5700 2200 4700 2200 +Wire Wire Line + 4700 2200 4700 3750 +Connection ~ 4700 3750 +Wire Wire Line + 3250 2650 3400 2650 +Wire Wire Line + 3400 2650 3400 2100 +Wire Wire Line + 3400 2100 3150 2100 +Connection ~ 3150 2100 +Wire Wire Line + 8150 2350 8150 2800 +Wire Wire Line + 7850 5150 7500 5150 +Wire Wire Line + 7500 5150 7500 5950 +Wire Wire Line + 7500 3000 7850 3000 +Wire Wire Line + 7500 2150 7500 3000 +Wire Wire Line + 7500 2150 7850 2150 +Wire Wire Line + 7500 2550 5500 2550 +Connection ~ 5500 2550 +Connection ~ 7500 2550 +Wire Wire Line + 5650 5700 7500 5700 +Connection ~ 7500 5700 +Connection ~ 5650 5700 +Wire Wire Line + 8150 3200 8150 4200 +Wire Wire Line + 8150 5350 8150 5750 +Wire Wire Line + 7500 5950 7850 5950 +Wire Wire Line + 8150 1450 8150 1950 +Wire Wire Line + 5450 1450 8150 1450 +Connection ~ 5450 1450 +Wire Wire Line + 8150 4650 8150 4950 +Wire Wire Line + 8150 4650 7000 4650 +Wire Wire Line + 7000 4650 7000 1450 +Connection ~ 7000 1450 +Wire Wire Line + 8150 6150 8150 6450 +Wire Wire Line + 8250 3150 8250 3300 +Wire Wire Line + 8250 3300 8150 3300 +Connection ~ 8150 3300 +Wire Wire Line + 8250 6100 8250 6200 +Wire Wire Line + 8250 6200 8150 6200 +Connection ~ 8150 6200 +Wire Wire Line + 8250 2300 8450 2300 +Wire Wire Line + 8450 2300 8450 1750 +Wire Wire Line + 8450 1750 8150 1750 +Connection ~ 8150 1750 +Wire Wire Line + 8250 5300 8250 5400 +Wire Wire Line + 8250 5400 8350 5400 +Wire Wire Line + 8350 5400 8350 4800 +Wire Wire Line + 8350 4800 8150 4800 +Connection ~ 8150 4800 +Connection ~ 8150 2550 +Wire Wire Line + 8150 5600 8950 5600 +Connection ~ 8150 5600 +Wire Wire Line + 8150 2550 9150 2550 +Wire Wire Line + 9150 2550 9150 2450 +Wire Wire Line + 5450 1550 5450 950 +Wire Wire Line + 8150 6450 6500 6450 +Wire Wire Line + 6500 6450 6500 7400 +Wire Wire Line + 6500 7400 5800 7400 +Wire Wire Line + 8150 4200 6400 4200 +Wire Wire Line + 6400 4200 6400 7350 +Wire Wire Line + 6400 7350 5700 7350 +Wire Wire Line + 5700 7350 5700 7550 +Wire Wire Line + 3150 7400 5650 7400 +Wire Wire Line + 2350 4150 2350 7450 +Wire Wire Line + 2350 7450 5650 7450 +Wire Wire Line + 5650 7600 5700 7600 +Connection ~ 5650 7450 +Wire Wire Line + 5700 7550 5650 7550 +Connection ~ 5650 7550 +Wire Wire Line + 5800 7400 5800 7500 +Wire Wire Line + 5800 7500 5650 7500 +Connection ~ 5650 7500 +Connection ~ 5650 7400 +Text Label 2200 5300 0 60 ~ 12 +A +Text Label 5700 7600 0 60 ~ 12 +GND +Text Label 1900 2700 0 60 ~ 12 +Ebar +Text Label 8800 5600 0 60 ~ 12 +Y2 +Text Label 5450 1100 0 60 ~ 12 +Vcc +Text Label 9050 2550 0 60 ~ 12 +Y1 +Wire Wire Line + 5500 4150 2350 4150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/demux/demux.sub b/library/SubcircuitLibrary/demux/demux.sub new file mode 100644 index 00000000..d96316ba --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux.sub @@ -0,0 +1,22 @@ +* Subcircuit demux +.subckt demux /a /gnd /ebar /y2 /vcc /y1 +* c:\fossee\esim\library\subcircuitlibrary\demux\demux.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 /vcc /ebar net-_m1-pad1_ /vcc CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ /ebar /gnd /gnd CMOSN W=100u L=100u M=1 +m3 /vcc net-_m1-pad1_ net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m9 /vcc /a net-_m11-pad2_ /vcc CMOSP W=100u L=100u M=1 +m4 /vcc /ebar net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m10 /vcc /a net-_m10-pad3_ /vcc CMOSP W=100u L=100u M=1 +m5 net-_m11-pad2_ net-_m1-pad1_ net-_m5-pad3_ /gnd CMOSN W=100u L=100u M=1 +m6 net-_m5-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m7 net-_m10-pad3_ /ebar net-_m7-pad3_ /gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad3_ /a /gnd /gnd CMOSN W=100u L=100u M=1 +m13 /vcc net-_m11-pad2_ /y1 /vcc CMOSP W=100u L=100u M=1 +m11 /y1 net-_m11-pad2_ /gnd /gnd CMOSN W=100u L=100u M=1 +m14 /vcc net-_m10-pad3_ /y2 /vcc CMOSP W=100u L=100u M=1 +m12 /y2 net-_m10-pad3_ /gnd /gnd CMOSN W=100u L=100u M=1 +* Control Statements + +.ends demux \ No newline at end of file diff --git a/library/SubcircuitLibrary/demux/demux_Previous_Values.xml b/library/SubcircuitLibrary/demux/demux_Previous_Values.xml new file mode 100644 index 00000000..5e4bb29c --- /dev/null +++ b/library/SubcircuitLibrary/demux/demux_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file -- cgit From da49c7dd71103fe6b8524e21b34e5b7fd4084f99 Mon Sep 17 00:00:00 2001 From: Vanshika Tanwar Date: Wed, 23 Nov 2022 22:06:53 +0530 Subject: 74V1G14 Schmitt Trigger IC --- .../SubcircuitLibrary/74V1G14/74V1G14-cache.lib | 100 ++++++++ library/SubcircuitLibrary/74V1G14/74V1G14.cir | 17 ++ library/SubcircuitLibrary/74V1G14/74V1G14.cir.out | 20 ++ library/SubcircuitLibrary/74V1G14/74V1G14.pro | 71 ++++++ library/SubcircuitLibrary/74V1G14/74V1G14.sch | 278 +++++++++++++++++++++ library/SubcircuitLibrary/74V1G14/74V1G14.sub | 14 ++ .../74V1G14/74V1G14_Previous_Values.xml | 1 + library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/74V1G14/README.md | 24 ++ library/SubcircuitLibrary/74V1G14/analysis | 1 + 11 files changed, 550 insertions(+) create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14.cir create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14.cir.out create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14.pro create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14.sch create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14.sub create mode 100644 library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/74V1G14/README.md create mode 100644 library/SubcircuitLibrary/74V1G14/analysis (limited to 'library') diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir b/library/SubcircuitLibrary/74V1G14/74V1G14.cir new file mode 100644 index 00000000..58637c1a --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74V1G14\74V1G14.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 8/3/2022 1:17:12 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 /Vout /Inp Net-_M1-Pad3_ /GND mosfet_n +M2 Net-_M1-Pad3_ /Inp /GND /GND mosfet_n +M3 /Vcc /Inp Net-_M3-Pad3_ /Vcc mosfet_p +M4 Net-_M3-Pad3_ /Inp /Vout /Vcc mosfet_p +M5 /GND /Vout Net-_M3-Pad3_ /Vcc mosfet_p +M6 /Vcc /Vout Net-_M1-Pad3_ /GND mosfet_n +U1 ? /Inp /GND /Vout /Vcc PORT + +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out new file mode 100644 index 00000000..43a6987d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* u1 ? /inp /gnd /vout /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.pro b/library/SubcircuitLibrary/74V1G14/74V1G14.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sch b/library/SubcircuitLibrary/74V1G14/74V1G14.sch new file mode 100644 index 00000000..3cab975e --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sch @@ -0,0 +1,278 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:74V1G14-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 62E8D877 +P 3550 3950 +F 0 "M1" H 3550 3800 50 0000 R CNN +F 1 "mosfet_n" H 3650 3900 50 0000 R CNN +F 2 "" H 3850 3650 29 0000 C CNN +F 3 "" H 3650 3750 60 0000 C CNN + 1 3550 3950 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62E8D878 +P 3550 5300 +F 0 "M2" H 3550 5150 50 0000 R CNN +F 1 "mosfet_n" H 3650 5250 50 0000 R CNN +F 2 "" H 3850 5000 29 0000 C CNN +F 3 "" H 3650 5100 60 0000 C CNN + 1 3550 5300 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62E8D879 +P 3650 1600 +F 0 "M3" H 3600 1650 50 0000 R CNN +F 1 "mosfet_p" H 3700 1750 50 0000 R CNN +F 2 "" H 3900 1700 29 0000 C CNN +F 3 "" H 3700 1600 60 0000 C CNN + 1 3650 1600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62E8D87A +P 3650 2650 +F 0 "M4" H 3600 2700 50 0000 R CNN +F 1 "mosfet_p" H 3700 2800 50 0000 R CNN +F 2 "" H 3900 2750 29 0000 C CNN +F 3 "" H 3700 2650 60 0000 C CNN + 1 3650 2650 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 62E8D87B +P 7250 2100 +F 0 "M5" H 7200 2150 50 0000 R CNN +F 1 "mosfet_p" H 7300 2250 50 0000 R CNN +F 2 "" H 7500 2200 29 0000 C CNN +F 3 "" H 7300 2100 60 0000 C CNN + 1 7250 2100 + 0 1 -1 0 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 62E8D87C +P 7450 4850 +F 0 "M6" H 7450 4700 50 0000 R CNN +F 1 "mosfet_n" H 7550 4800 50 0000 R CNN +F 2 "" H 7750 4550 29 0000 C CNN +F 3 "" H 7550 4650 60 0000 C CNN + 1 7450 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 3800 1800 3800 2450 +Wire Wire Line + 3800 2850 3800 3950 +Wire Wire Line + 3800 3950 3750 3950 +Wire Wire Line + 3750 4350 3750 5300 +Wire Wire Line + 7050 1950 3800 1950 +Connection ~ 3800 1950 +Wire Wire Line + 7100 1750 7100 1850 +Wire Wire Line + 3800 850 3800 1400 +Wire Wire Line + 3800 1300 4550 1300 +Wire Wire Line + 4550 1300 4550 2900 +Wire Wire Line + 4550 2900 3900 2900 +Wire Wire Line + 3900 2900 3900 2800 +Connection ~ 3800 1300 +Wire Wire Line + 3900 1750 7100 1750 +Connection ~ 4550 1750 +Wire Wire Line + 3750 5700 3750 6200 +Wire Wire Line + 3850 5650 3850 5850 +Wire Wire Line + 3850 5850 3750 5850 +Connection ~ 3750 5850 +Wire Wire Line + 3850 5700 4150 5700 +Wire Wire Line + 4150 5700 4150 4300 +Wire Wire Line + 4150 4300 3850 4300 +Connection ~ 3850 5700 +Wire Wire Line + 4150 5250 7100 5250 +Wire Wire Line + 7100 5250 7100 5150 +Connection ~ 4150 5250 +Wire Wire Line + 7050 5050 3750 5050 +Connection ~ 3750 5050 +Wire Wire Line + 7450 5050 9450 5050 +Wire Wire Line + 3800 3350 9200 3350 +Connection ~ 3800 3350 +Wire Wire Line + 2750 1600 2750 5500 +Wire Wire Line + 2750 5500 3450 5500 +Wire Wire Line + 3500 2650 3500 2550 +Wire Wire Line + 3500 2550 2750 2550 +Connection ~ 2750 2550 +Connection ~ 2750 4150 +Wire Wire Line + 2100 3300 2750 3300 +Connection ~ 2750 3300 +Wire Wire Line + 7450 1950 9700 1950 +Wire Wire Line + 9700 1950 9700 6050 +Wire Wire Line + 9700 6050 3750 6050 +Connection ~ 3750 6050 +Wire Wire Line + 3500 1600 2750 1600 +Wire Wire Line + 3450 4150 2750 4150 +Wire Wire Line + 3600 850 9450 850 +Wire Wire Line + 9450 850 9450 5050 +Connection ~ 3800 850 +Text Label 3600 850 0 60 ~ 0 +Vcc +Text Label 9100 3350 0 60 ~ 0 +Vout +Text Label 3750 6150 0 60 ~ 0 +GND +Text Label 2300 3300 0 60 ~ 0 +Inp +Text Label 2300 4100 0 60 ~ 0 +NC +NoConn ~ 2300 4100 +$Comp +L PORT U1 +U 2 1 62E8E2E7 +P 1850 3300 +F 0 "U1" H 1900 3400 30 0000 C CNN +F 1 "PORT" H 1850 3300 30 0000 C CNN +F 2 "" H 1850 3300 60 0000 C CNN +F 3 "" H 1850 3300 60 0000 C CNN + 2 1850 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62E8E33C +P 2050 4100 +F 0 "U1" H 2100 4200 30 0000 C CNN +F 1 "PORT" H 2050 4100 30 0000 C CNN +F 2 "" H 2050 4100 60 0000 C CNN +F 3 "" H 2050 4100 60 0000 C CNN + 1 2050 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62E8E47F +P 9450 3350 +F 0 "U1" H 9500 3450 30 0000 C CNN +F 1 "PORT" H 9450 3350 30 0000 C CNN +F 2 "" H 9450 3350 60 0000 C CNN +F 3 "" H 9450 3350 60 0000 C CNN + 4 9450 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62E8E9EE +P 3350 850 +F 0 "U1" H 3400 950 30 0000 C CNN +F 1 "PORT" H 3350 850 30 0000 C CNN +F 2 "" H 3350 850 60 0000 C CNN +F 3 "" H 3350 850 60 0000 C CNN + 5 3350 850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62E8ECBB +P 3500 6200 +F 0 "U1" H 3550 6300 30 0000 C CNN +F 1 "PORT" H 3500 6200 30 0000 C CNN +F 2 "" H 3500 6200 60 0000 C CNN +F 3 "" H 3500 6200 60 0000 C CNN + 3 3500 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 2250 6900 2250 +Wire Wire Line + 6900 2250 6900 3350 +Connection ~ 6900 3350 +Wire Wire Line + 7250 4750 7250 3350 +Connection ~ 7250 3350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sub b/library/SubcircuitLibrary/74V1G14/74V1G14.sub new file mode 100644 index 00000000..37c8151d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sub @@ -0,0 +1,14 @@ +* Subcircuit 74V1G14 +.subckt 74V1G14 ? /inp /gnd /vout /vcc +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* Control Statements + +.ends 74V1G14 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml new file mode 100644 index 00000000..b08ed607 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib25u0.25u1C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib25u0.25u1C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib75u0.25u1C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib75u0.25u1C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib75u0.25u1C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib25u0.25u1truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/74V1G14/README.md b/library/SubcircuitLibrary/74V1G14/README.md new file mode 100644 index 00000000..6d0656e5 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/README.md @@ -0,0 +1,24 @@ +# Sch_trig IC + +Schmitt trigger is a general purpose IC. It is the circuit that is used to convert any type of input signal into a square waveform + +## Usage/Examples + +It is used in simple oscillators. + +It is used in Switch Debouncing. + +## Documentation + +To know the details of 74V1G14 IC please refer to this link [74V1G14_datasheet.](https://www.st.com/resource/en/datasheet/74v1g14.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/74V1G14/analysis b/library/SubcircuitLibrary/74V1G14/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit From 4c767ca8d6f93f4026b7f01ba635f14a3e713a1d Mon Sep 17 00:00:00 2001 From: Vanshika Tanwar Date: Wed, 23 Nov 2022 22:10:10 +0530 Subject: Precision Rectifier IC --- library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib | 2 + .../SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib | 4 + .../SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib | 4 + .../Precision_Rectifier-cache.lib | 139 ++++ .../TINA_TI_Rectifier/Precision_Rectifier.sch | 412 ++++++++++++ .../SubcircuitLibrary/TINA_TI_Rectifier/README.md | 24 + .../TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib | 139 ++++ .../TINA_TI_Rectifier/TINA_TI_Rectifier.cir | 24 + .../TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out | 27 + .../TINA_TI_Rectifier/TINA_TI_Rectifier.pro | 71 +++ .../TINA_TI_Rectifier/TINA_TI_Rectifier.sch | 412 ++++++++++++ .../TINA_TI_Rectifier/TINA_TI_Rectifier.sub | 21 + .../TINA_TI_Rectifier_Previous_Values.xml | 1 + .../SubcircuitLibrary/TINA_TI_Rectifier/analysis | 1 + .../TINA_TI_Rectifier/lm_741-cache.lib | 119 ++++ .../SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir | 43 ++ .../TINA_TI_Rectifier/lm_741.cir.out | 46 ++ .../SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro | 44 ++ .../SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch | 697 +++++++++++++++++++++ .../SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub | 40 ++ .../TINA_TI_Rectifier/lm_741_Previous_Values.xml | 1 + .../SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib | 29 + .../SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib | 29 + 23 files changed, 2329 insertions(+) create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/README.md create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/analysis create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib create mode 100644 library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib (limited to 'library') diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib new file mode 100644 index 00000000..92e46ff3 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch new file mode 100644 index 00000000..ac46ef65 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/Precision_Rectifier.sch @@ -0,0 +1,412 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:TINA_TI_Rectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 630DEBC8 +P 4000 3500 +F 0 "X1" H 3800 3500 60 0000 C CNN +F 1 "lm_741" H 3900 3250 60 0000 C CNN +F 2 "" H 4000 3500 60 0000 C CNN +F 3 "" H 4000 3500 60 0000 C CNN + 1 4000 3500 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 630DEC2E +P 6700 3400 +F 0 "X2" H 6500 3400 60 0000 C CNN +F 1 "lm_741" H 6600 3150 60 0000 C CNN +F 2 "" H 6700 3400 60 0000 C CNN +F 3 "" H 6700 3400 60 0000 C CNN + 1 6700 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 630DED64 +P 3250 4100 +F 0 "R1" H 3300 4230 50 0000 C CNN +F 1 "49.9" H 3300 4050 50 0000 C CNN +F 2 "" H 3300 4080 30 0000 C CNN +F 3 "" V 3300 4150 30 0000 C CNN + 1 3250 4100 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 630DEE0E +P 5900 4100 +F 0 "R3" H 5950 4230 50 0000 C CNN +F 1 "1k" H 5950 4050 50 0000 C CNN +F 2 "" H 5950 4080 30 0000 C CNN +F 3 "" V 5950 4150 30 0000 C CNN + 1 5900 4100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 630DEEA8 +P 5400 3500 +F 0 "D2" H 5400 3600 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3400 50 0000 C CNN +F 2 "" H 5400 3500 60 0000 C CNN +F 3 "" H 5400 3500 60 0000 C CNN + 1 5400 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 630DEF23 +P 5000 2600 +F 0 "D1" H 5000 2700 50 0000 C CNN +F 1 "eSim_Diode" H 5000 2500 50 0000 C CNN +F 2 "" H 5000 2600 60 0000 C CNN +F 3 "" H 5000 2600 60 0000 C CNN + 1 5000 2600 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 630DEF6B +P 4600 2600 +F 0 "C1" H 4625 2700 50 0000 L CNN +F 1 "47p" H 4625 2500 50 0000 L CNN +F 2 "" H 4638 2450 30 0000 C CNN +F 3 "" H 4600 2600 60 0000 C CNN + 1 4600 2600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 630DF05D +P 5550 2050 +F 0 "R2" H 5600 2180 50 0000 C CNN +F 1 "1k" H 5600 2000 50 0000 C CNN +F 2 "" H 5600 2030 30 0000 C CNN +F 3 "" V 5600 2100 30 0000 C CNN + 1 5550 2050 + -1 0 0 1 +$EndComp +$Comp +L resistor R4 +U 1 1 630DF101 +P 6500 2050 +F 0 "R4" H 6550 2180 50 0000 C CNN +F 1 "1k" H 6550 2000 50 0000 C CNN +F 2 "" H 6550 2030 30 0000 C CNN +F 3 "" V 6550 2100 30 0000 C CNN + 1 6500 2050 + -1 0 0 1 +$EndComp +$Comp +L capacitor C3 +U 1 1 630DF148 +P 7100 2700 +F 0 "C3" H 7125 2800 50 0000 L CNN +F 1 "100p" H 7125 2600 50 0000 L CNN +F 2 "" H 7138 2550 30 0000 C CNN +F 3 "" H 7100 2700 60 0000 C CNN + 1 7100 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C5 +U 1 1 630DF1F2 +P 7500 2700 +F 0 "C5" H 7525 2800 50 0000 L CNN +F 1 "100n" H 7525 2600 50 0000 L CNN +F 2 "" H 7538 2550 30 0000 C CNN +F 3 "" H 7500 2700 60 0000 C CNN + 1 7500 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 630DF244 +P 6800 4550 +F 0 "C2" H 6825 4650 50 0000 L CNN +F 1 "100p" H 6825 4450 50 0000 L CNN +F 2 "" H 6838 4400 30 0000 C CNN +F 3 "" H 6800 4550 60 0000 C CNN + 1 6800 4550 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 630DF2AA +P 7250 4550 +F 0 "C4" H 7275 4650 50 0000 L CNN +F 1 "100n" H 7275 4450 50 0000 L CNN +F 2 "" H 7288 4400 30 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 1 7250 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 630DF502 +P 3350 5050 +F 0 "#PWR01" H 3350 4800 50 0001 C CNN +F 1 "GND" H 3350 4900 50 0000 C CNN +F 2 "" H 3350 5050 50 0001 C CNN +F 3 "" H 3350 5050 50 0001 C CNN + 1 3350 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 630DFA95 +P 5950 4800 +F 0 "#PWR02" H 5950 4550 50 0001 C CNN +F 1 "GND" H 5950 4650 50 0000 C CNN +F 2 "" H 5950 4800 50 0001 C CNN +F 3 "" H 5950 4800 50 0001 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 630DFAD1 +P 6800 4900 +F 0 "#PWR03" H 6800 4650 50 0001 C CNN +F 1 "GND" H 6800 4750 50 0000 C CNN +F 2 "" H 6800 4900 50 0001 C CNN +F 3 "" H 6800 4900 50 0001 C CNN + 1 6800 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 630DFB06 +P 7250 4900 +F 0 "#PWR04" H 7250 4650 50 0001 C CNN +F 1 "GND" H 7250 4750 50 0000 C CNN +F 2 "" H 7250 4900 50 0001 C CNN +F 3 "" H 7250 4900 50 0001 C CNN + 1 7250 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 630DFB3B +P 7100 3050 +F 0 "#PWR05" H 7100 2800 50 0001 C CNN +F 1 "GND" H 7100 2900 50 0000 C CNN +F 2 "" H 7100 3050 50 0001 C CNN +F 3 "" H 7100 3050 50 0001 C CNN + 1 7100 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 630DFB70 +P 7500 3050 +F 0 "#PWR06" H 7500 2800 50 0001 C CNN +F 1 "GND" H 7500 2900 50 0000 C CNN +F 2 "" H 7500 3050 50 0001 C CNN +F 3 "" H 7500 3050 50 0001 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +Text Label 8350 2350 0 60 Italic 12 +Vpos +Text Label 7950 4150 0 60 Italic 12 +Vneg +$Comp +L PORT U1 +U 1 1 631276E6 +P 2550 4000 +F 0 "U1" H 2600 4100 30 0000 C CNN +F 1 "PORT" H 2550 4000 30 0000 C CNN +F 2 "" H 2550 4000 60 0000 C CNN +F 3 "" H 2550 4000 60 0000 C CNN + 1 2550 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3500 5250 3500 +Wire Wire Line + 5550 3500 6150 3500 +Wire Wire Line + 5950 4000 5950 3500 +Connection ~ 5950 3500 +Wire Wire Line + 5950 4300 5950 4800 +Wire Wire Line + 6550 3850 6550 4150 +Wire Wire Line + 6450 4150 8150 4150 +Wire Wire Line + 6800 4400 6800 4150 +Connection ~ 6800 4150 +Wire Wire Line + 7250 4400 7250 4150 +Connection ~ 7250 4150 +Wire Wire Line + 6800 4700 6800 4900 +Wire Wire Line + 7250 4900 7250 4700 +Wire Wire Line + 6550 2350 6550 2950 +Wire Wire Line + 6550 2450 7950 2450 +Wire Wire Line + 7950 2450 7950 2350 +Wire Wire Line + 7100 2550 7100 2450 +Connection ~ 7100 2450 +Wire Wire Line + 7500 2550 7500 2450 +Connection ~ 7500 2450 +Wire Wire Line + 7100 2850 7100 3050 +Wire Wire Line + 7500 2850 7500 3050 +Wire Wire Line + 7250 3400 8450 3400 +Wire Wire Line + 6600 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3400 +Connection ~ 8250 3400 +Wire Wire Line + 6300 2100 5650 2100 +Wire Wire Line + 5350 2100 3250 2100 +Wire Wire Line + 3250 2100 3250 3350 +Wire Wire Line + 3250 3350 3450 3350 +Wire Wire Line + 5000 2450 5000 2100 +Connection ~ 5000 2100 +Wire Wire Line + 5000 2750 5000 3500 +Connection ~ 5000 3500 +Wire Wire Line + 4600 2750 4600 3500 +Connection ~ 4600 3500 +Wire Wire Line + 4600 2450 4600 2100 +Connection ~ 4600 2100 +Wire Wire Line + 3450 3600 2800 3600 +Wire Wire Line + 2800 3600 2800 4000 +Wire Wire Line + 3300 4300 3300 5050 +Wire Wire Line + 3300 5050 3350 5050 +Wire Wire Line + 3300 4000 3300 3600 +Connection ~ 3300 3600 +Wire Wire Line + 6150 3250 5850 3250 +Wire Wire Line + 5850 3250 5850 2100 +Wire Wire Line + 5850 2100 5900 2100 +Connection ~ 5900 2100 +Text Label 2800 3950 0 60 Italic 12 +Vin +Text Label 8300 3400 0 60 Italic 12 +Vout +$Comp +L PORT U1 +U 2 1 63128122 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 2 8400 4150 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 3050 3850 2350 +Wire Wire Line + 3850 2350 6550 2350 +Connection ~ 6550 2450 +Wire Wire Line + 3850 3950 6450 3950 +Wire Wire Line + 6450 3950 6450 4150 +Connection ~ 6550 4150 +$Comp +L PORT U1 +U 4 1 631984C4 +P 8800 2350 +F 0 "U1" H 8850 2450 30 0000 C CNN +F 1 "PORT" H 8800 2350 30 0000 C CNN +F 2 "" H 8800 2350 60 0000 C CNN +F 3 "" H 8800 2350 60 0000 C CNN + 4 8800 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 63198559 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 3 8700 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 2350 8550 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md b/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md new file mode 100644 index 00000000..d61b9e7d --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/README.md @@ -0,0 +1,24 @@ + +# Precision_Rectifier IC + +Precision Rectifier is a general purpose IC. The major drawback of the normal diode is that it can not be able to rectify the voltages below (0.6 v) which is the cut-in voltage. So, a special type of diode is used which is a precision diode that is capable of rectifying the input voltage signals in the order of milli volt. So, a circuit that uses this special type of diode(precision diode) is called a precision rectifie + +## Usage/Examples + +It is used in high-precision signal processing with few modification it can be used as Peak Detector. + + +## Documentation + +To know the details of Precision Rectifier IC please refer to this link [Precision_Rectifier_datasheet.](https://www.ti.com/lit/ug/tidu030/tidu030.pdf?ts=1661742834491&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib new file mode 100644 index 00000000..92e46ff3 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir new file mode 100644 index 00000000..f945869f --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir @@ -0,0 +1,24 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\TINA_TI_Rectifier\TINA_TI_Rectifier.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 9/8/2022 12:13:00 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_C1-Pad1_ /Vin /Vneg ? Net-_C1-Pad2_ /Vpos ? lm_741 +X2 ? Net-_R2-Pad1_ Net-_D2-Pad2_ /Vneg ? /Vout /Vpos ? lm_741 +R1 /Vin GND 49.9 +R3 Net-_D2-Pad2_ GND 1k +D2 Net-_C1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D1 Net-_C1-Pad1_ Net-_C1-Pad2_ eSim_Diode +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 47p +R2 Net-_R2-Pad1_ Net-_C1-Pad1_ 1k +R4 /Vout Net-_R2-Pad1_ 1k +C3 /Vpos GND 100p +C5 /Vpos GND 100n +C2 /Vneg GND 100p +C4 /Vneg GND 100n +U1 /Vin /Vneg /Vout /Vpos PORT + +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out new file mode 100644 index 00000000..433a1bdd --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.cir.out @@ -0,0 +1,27 @@ +* c:\fossee\esim\library\subcircuitlibrary\tina_ti_rectifier\tina_ti_rectifier.cir + +.include lm_741.sub +.include D.lib +x1 ? net-_c1-pad1_ /vin /vneg ? net-_c1-pad2_ /vpos ? lm_741 +x2 ? net-_r2-pad1_ net-_d2-pad2_ /vneg ? /vout /vpos ? lm_741 +r1 /vin gnd 49.9 +r3 net-_d2-pad2_ gnd 1k +d2 net-_c1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_c1-pad1_ net-_c1-pad2_ 1N4148 +c1 net-_c1-pad1_ net-_c1-pad2_ 47p +r2 net-_r2-pad1_ net-_c1-pad1_ 1k +r4 /vout net-_r2-pad1_ 1k +c3 /vpos gnd 100p +c5 /vpos gnd 100n +c2 /vneg gnd 100p +c4 /vneg gnd 100n +* u1 /vin /vneg /vout /vpos port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch new file mode 100644 index 00000000..ac46ef65 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sch @@ -0,0 +1,412 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:TINA_TI_Rectifier-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 630DEBC8 +P 4000 3500 +F 0 "X1" H 3800 3500 60 0000 C CNN +F 1 "lm_741" H 3900 3250 60 0000 C CNN +F 2 "" H 4000 3500 60 0000 C CNN +F 3 "" H 4000 3500 60 0000 C CNN + 1 4000 3500 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 630DEC2E +P 6700 3400 +F 0 "X2" H 6500 3400 60 0000 C CNN +F 1 "lm_741" H 6600 3150 60 0000 C CNN +F 2 "" H 6700 3400 60 0000 C CNN +F 3 "" H 6700 3400 60 0000 C CNN + 1 6700 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 630DED64 +P 3250 4100 +F 0 "R1" H 3300 4230 50 0000 C CNN +F 1 "49.9" H 3300 4050 50 0000 C CNN +F 2 "" H 3300 4080 30 0000 C CNN +F 3 "" V 3300 4150 30 0000 C CNN + 1 3250 4100 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 630DEE0E +P 5900 4100 +F 0 "R3" H 5950 4230 50 0000 C CNN +F 1 "1k" H 5950 4050 50 0000 C CNN +F 2 "" H 5950 4080 30 0000 C CNN +F 3 "" V 5950 4150 30 0000 C CNN + 1 5900 4100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 630DEEA8 +P 5400 3500 +F 0 "D2" H 5400 3600 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3400 50 0000 C CNN +F 2 "" H 5400 3500 60 0000 C CNN +F 3 "" H 5400 3500 60 0000 C CNN + 1 5400 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 630DEF23 +P 5000 2600 +F 0 "D1" H 5000 2700 50 0000 C CNN +F 1 "eSim_Diode" H 5000 2500 50 0000 C CNN +F 2 "" H 5000 2600 60 0000 C CNN +F 3 "" H 5000 2600 60 0000 C CNN + 1 5000 2600 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 630DEF6B +P 4600 2600 +F 0 "C1" H 4625 2700 50 0000 L CNN +F 1 "47p" H 4625 2500 50 0000 L CNN +F 2 "" H 4638 2450 30 0000 C CNN +F 3 "" H 4600 2600 60 0000 C CNN + 1 4600 2600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 630DF05D +P 5550 2050 +F 0 "R2" H 5600 2180 50 0000 C CNN +F 1 "1k" H 5600 2000 50 0000 C CNN +F 2 "" H 5600 2030 30 0000 C CNN +F 3 "" V 5600 2100 30 0000 C CNN + 1 5550 2050 + -1 0 0 1 +$EndComp +$Comp +L resistor R4 +U 1 1 630DF101 +P 6500 2050 +F 0 "R4" H 6550 2180 50 0000 C CNN +F 1 "1k" H 6550 2000 50 0000 C CNN +F 2 "" H 6550 2030 30 0000 C CNN +F 3 "" V 6550 2100 30 0000 C CNN + 1 6500 2050 + -1 0 0 1 +$EndComp +$Comp +L capacitor C3 +U 1 1 630DF148 +P 7100 2700 +F 0 "C3" H 7125 2800 50 0000 L CNN +F 1 "100p" H 7125 2600 50 0000 L CNN +F 2 "" H 7138 2550 30 0000 C CNN +F 3 "" H 7100 2700 60 0000 C CNN + 1 7100 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C5 +U 1 1 630DF1F2 +P 7500 2700 +F 0 "C5" H 7525 2800 50 0000 L CNN +F 1 "100n" H 7525 2600 50 0000 L CNN +F 2 "" H 7538 2550 30 0000 C CNN +F 3 "" H 7500 2700 60 0000 C CNN + 1 7500 2700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 630DF244 +P 6800 4550 +F 0 "C2" H 6825 4650 50 0000 L CNN +F 1 "100p" H 6825 4450 50 0000 L CNN +F 2 "" H 6838 4400 30 0000 C CNN +F 3 "" H 6800 4550 60 0000 C CNN + 1 6800 4550 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 630DF2AA +P 7250 4550 +F 0 "C4" H 7275 4650 50 0000 L CNN +F 1 "100n" H 7275 4450 50 0000 L CNN +F 2 "" H 7288 4400 30 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 1 7250 4550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 630DF502 +P 3350 5050 +F 0 "#PWR01" H 3350 4800 50 0001 C CNN +F 1 "GND" H 3350 4900 50 0000 C CNN +F 2 "" H 3350 5050 50 0001 C CNN +F 3 "" H 3350 5050 50 0001 C CNN + 1 3350 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 630DFA95 +P 5950 4800 +F 0 "#PWR02" H 5950 4550 50 0001 C CNN +F 1 "GND" H 5950 4650 50 0000 C CNN +F 2 "" H 5950 4800 50 0001 C CNN +F 3 "" H 5950 4800 50 0001 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 630DFAD1 +P 6800 4900 +F 0 "#PWR03" H 6800 4650 50 0001 C CNN +F 1 "GND" H 6800 4750 50 0000 C CNN +F 2 "" H 6800 4900 50 0001 C CNN +F 3 "" H 6800 4900 50 0001 C CNN + 1 6800 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 630DFB06 +P 7250 4900 +F 0 "#PWR04" H 7250 4650 50 0001 C CNN +F 1 "GND" H 7250 4750 50 0000 C CNN +F 2 "" H 7250 4900 50 0001 C CNN +F 3 "" H 7250 4900 50 0001 C CNN + 1 7250 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 630DFB3B +P 7100 3050 +F 0 "#PWR05" H 7100 2800 50 0001 C CNN +F 1 "GND" H 7100 2900 50 0000 C CNN +F 2 "" H 7100 3050 50 0001 C CNN +F 3 "" H 7100 3050 50 0001 C CNN + 1 7100 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 630DFB70 +P 7500 3050 +F 0 "#PWR06" H 7500 2800 50 0001 C CNN +F 1 "GND" H 7500 2900 50 0000 C CNN +F 2 "" H 7500 3050 50 0001 C CNN +F 3 "" H 7500 3050 50 0001 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +Text Label 8350 2350 0 60 Italic 12 +Vpos +Text Label 7950 4150 0 60 Italic 12 +Vneg +$Comp +L PORT U1 +U 1 1 631276E6 +P 2550 4000 +F 0 "U1" H 2600 4100 30 0000 C CNN +F 1 "PORT" H 2550 4000 30 0000 C CNN +F 2 "" H 2550 4000 60 0000 C CNN +F 3 "" H 2550 4000 60 0000 C CNN + 1 2550 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3500 5250 3500 +Wire Wire Line + 5550 3500 6150 3500 +Wire Wire Line + 5950 4000 5950 3500 +Connection ~ 5950 3500 +Wire Wire Line + 5950 4300 5950 4800 +Wire Wire Line + 6550 3850 6550 4150 +Wire Wire Line + 6450 4150 8150 4150 +Wire Wire Line + 6800 4400 6800 4150 +Connection ~ 6800 4150 +Wire Wire Line + 7250 4400 7250 4150 +Connection ~ 7250 4150 +Wire Wire Line + 6800 4700 6800 4900 +Wire Wire Line + 7250 4900 7250 4700 +Wire Wire Line + 6550 2350 6550 2950 +Wire Wire Line + 6550 2450 7950 2450 +Wire Wire Line + 7950 2450 7950 2350 +Wire Wire Line + 7100 2550 7100 2450 +Connection ~ 7100 2450 +Wire Wire Line + 7500 2550 7500 2450 +Connection ~ 7500 2450 +Wire Wire Line + 7100 2850 7100 3050 +Wire Wire Line + 7500 2850 7500 3050 +Wire Wire Line + 7250 3400 8450 3400 +Wire Wire Line + 6600 2100 8250 2100 +Wire Wire Line + 8250 2100 8250 3400 +Connection ~ 8250 3400 +Wire Wire Line + 6300 2100 5650 2100 +Wire Wire Line + 5350 2100 3250 2100 +Wire Wire Line + 3250 2100 3250 3350 +Wire Wire Line + 3250 3350 3450 3350 +Wire Wire Line + 5000 2450 5000 2100 +Connection ~ 5000 2100 +Wire Wire Line + 5000 2750 5000 3500 +Connection ~ 5000 3500 +Wire Wire Line + 4600 2750 4600 3500 +Connection ~ 4600 3500 +Wire Wire Line + 4600 2450 4600 2100 +Connection ~ 4600 2100 +Wire Wire Line + 3450 3600 2800 3600 +Wire Wire Line + 2800 3600 2800 4000 +Wire Wire Line + 3300 4300 3300 5050 +Wire Wire Line + 3300 5050 3350 5050 +Wire Wire Line + 3300 4000 3300 3600 +Connection ~ 3300 3600 +Wire Wire Line + 6150 3250 5850 3250 +Wire Wire Line + 5850 3250 5850 2100 +Wire Wire Line + 5850 2100 5900 2100 +Connection ~ 5900 2100 +Text Label 2800 3950 0 60 Italic 12 +Vin +Text Label 8300 3400 0 60 Italic 12 +Vout +$Comp +L PORT U1 +U 2 1 63128122 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 2 8400 4150 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 3050 3850 2350 +Wire Wire Line + 3850 2350 6550 2350 +Connection ~ 6550 2450 +Wire Wire Line + 3850 3950 6450 3950 +Wire Wire Line + 6450 3950 6450 4150 +Connection ~ 6550 4150 +$Comp +L PORT U1 +U 4 1 631984C4 +P 8800 2350 +F 0 "U1" H 8850 2450 30 0000 C CNN +F 1 "PORT" H 8800 2350 30 0000 C CNN +F 2 "" H 8800 2350 60 0000 C CNN +F 3 "" H 8800 2350 60 0000 C CNN + 4 8800 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 63198559 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 3 8700 3400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 2350 8550 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub new file mode 100644 index 00000000..dc6cb480 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier.sub @@ -0,0 +1,21 @@ +* Subcircuit TINA_TI_Rectifier +.subckt TINA_TI_Rectifier /vin /vneg /vout /vpos +* c:\fossee\esim\library\subcircuitlibrary\tina_ti_rectifier\tina_ti_rectifier.cir +.include lm_741.sub +.include D.lib +x1 ? net-_c1-pad1_ /vin /vneg ? net-_c1-pad2_ /vpos ? lm_741 +x2 ? net-_r2-pad1_ net-_d2-pad2_ /vneg ? /vout /vpos ? lm_741 +r1 /vin gnd 49.9 +r3 net-_d2-pad2_ gnd 1k +d2 net-_c1-pad2_ net-_d2-pad2_ 1N4148 +d1 net-_c1-pad1_ net-_c1-pad2_ 1N4148 +c1 net-_c1-pad1_ net-_c1-pad2_ 47p +r2 net-_r2-pad1_ net-_c1-pad1_ 1k +r4 /vout net-_r2-pad1_ 1k +c3 /vpos gnd 100p +c5 /vpos gnd 100n +c2 /vneg gnd 100p +c4 /vneg gnd 100n +* Control Statements + +.ends TINA_TI_Rectifier \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml new file mode 100644 index 00000000..b1ddedd6 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/TINA_TI_Rectifier_Previous_Values.xml @@ -0,0 +1 @@ +sine1515C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis b/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro new file mode 100644 index 00000000..b56de1b0 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.pro @@ -0,0 +1,44 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 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0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741 \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.libC:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib b/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/TINA_TI_Rectifier/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file -- cgit From 70abfb3a3ffdf3d62b6c09e7ede6afe30c195491 Mon Sep 17 00:00:00 2001 From: E BALAKRISHNA Date: Wed, 30 Nov 2022 01:16:08 +0530 Subject: Uploaded the Device Model File of Diode --- library/deviceModelLibrary/Diode/DIS2M/DI_S2M.lib | 1 + library/deviceModelLibrary/Diode/DIS2M/DI_S2M.xml | 1 + library/deviceModelLibrary/Diode/README.md | 46 +++++++++++++++++++++++ library/deviceModelLibrary/Diode/S1B/DI_S1B.lib | 1 + library/deviceModelLibrary/Diode/S1B/DI_S1B.xml | 1 + 5 files changed, 50 insertions(+) create mode 100644 library/deviceModelLibrary/Diode/DIS2M/DI_S2M.lib create mode 100644 library/deviceModelLibrary/Diode/DIS2M/DI_S2M.xml create mode 100644 library/deviceModelLibrary/Diode/README.md create mode 100644 library/deviceModelLibrary/Diode/S1B/DI_S1B.lib create mode 100644 library/deviceModelLibrary/Diode/S1B/DI_S1B.xml (limited to 'library') diff --git a/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.lib b/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.lib new file mode 100644 index 00000000..1f8a5556 --- /dev/null +++ b/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.lib @@ -0,0 +1 @@ +.MODEL DI_S2M D( Is=1.30u Rs=8.92m N=2.58 tt=4.32u Cjo=37.0p M=0.333 Vj=0.538 Bv=1.00k Ibv=5.00u ) diff --git a/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.xml b/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.xml new file mode 100644 index 00000000..a2dc1ca8 --- /dev/null +++ b/library/deviceModelLibrary/Diode/DIS2M/DI_S2M.xml @@ -0,0 +1 @@ +DDI_S2M1.30u8.92m2.584.32u37.0p0.3330.5381.00k5.00u \ No newline at end of file diff --git a/library/deviceModelLibrary/Diode/README.md b/library/deviceModelLibrary/Diode/README.md new file mode 100644 index 00000000..86674d39 --- /dev/null +++ b/library/deviceModelLibrary/Diode/README.md @@ -0,0 +1,46 @@ +# Diode + +Diode is a pn junction device, which allows the current to flow in one direction. In +this chapter different types of diodes have been discussed. The devices in this family are used in matching circuits for electronic tuning. + +## Diode(S2M) + +``` +* DI_S2M Diode model +.MODEL DI_S2M D( Is=1.30u Rs=8.92m N=2.58 tt=4.32u Cjo=37.0p M=0.333 Vj=0.538 Bv=1.00k Ibv=5.00u ) + + +``` + + +## Diode(S1B) + +``` +* DI_S1B Diode model +.MODEL DI_S1B D( Is=7.31E-018 Rs=42.0m N=0.775 tt=4.32u Cjo=42.4p M=0.333 Vj=1 Bv=100 Ibv=5.00u ) + +``` + +## Usage/Examples + +Digital logic + +Rectifying a voltage + +## Documentation + +To know the details of S2M Diode and S1B Diode please go through with the documentation : [S2M_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/14771/PANJIT/S2M.html) and [S1B_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/14765/PANJIT/S1B.html) + +## Comments/Notes + +Please note this is a complete Device modeling. + +## Contributer + +Name: E BALAKRISHNA + +Email: balakrishnaeppili0920@gmail.com + +Year: 2022 + +Position: FOSSEE Summer Fellow 2022 diff --git a/library/deviceModelLibrary/Diode/S1B/DI_S1B.lib b/library/deviceModelLibrary/Diode/S1B/DI_S1B.lib new file mode 100644 index 00000000..56a40639 --- /dev/null +++ b/library/deviceModelLibrary/Diode/S1B/DI_S1B.lib @@ -0,0 +1 @@ +.MODEL DI_S1B D( Is=7.31E-018 Rs=42.0m N=0.775 tt=4.32u Cjo=42.4p M=0.333 Vj=1 Bv=100 Ibv=5.00u ) diff --git a/library/deviceModelLibrary/Diode/S1B/DI_S1B.xml b/library/deviceModelLibrary/Diode/S1B/DI_S1B.xml new file mode 100644 index 00000000..f6b4b6ae --- /dev/null +++ b/library/deviceModelLibrary/Diode/S1B/DI_S1B.xml @@ -0,0 +1 @@ +DDI_S1B7.31E-01842.0m0.7754.32u42.4p0.33311005.00u \ No newline at end of file -- cgit From e9f3e31e8f60ffeb3b72a6c1a3b72116979df289 Mon Sep 17 00:00:00 2001 From: E BALAKRISHNA Date: Wed, 30 Nov 2022 01:18:03 +0530 Subject: Uploaded the Device Model File of JFET --- library/deviceModelLibrary/JFET/BF244B/BF244B.lib | 1 + library/deviceModelLibrary/JFET/BF244B/BF244B.xml | 1 + library/deviceModelLibrary/JFET/J204/J204.lib | 1 + library/deviceModelLibrary/JFET/J204/J204.xml | 1 + .../deviceModelLibrary/JFET/J2N3822/J2N3822.lib | 1 + .../deviceModelLibrary/JFET/J2N3822/J2N3822.xml | 1 + library/deviceModelLibrary/JFET/README.md | 60 ++++++++++++++++++++++ 7 files changed, 66 insertions(+) create mode 100644 library/deviceModelLibrary/JFET/BF244B/BF244B.lib create mode 100644 library/deviceModelLibrary/JFET/BF244B/BF244B.xml create mode 100644 library/deviceModelLibrary/JFET/J204/J204.lib create mode 100644 library/deviceModelLibrary/JFET/J204/J204.xml create mode 100644 library/deviceModelLibrary/JFET/J2N3822/J2N3822.lib create mode 100644 library/deviceModelLibrary/JFET/J2N3822/J2N3822.xml create mode 100644 library/deviceModelLibrary/JFET/README.md (limited to 'library') diff --git a/library/deviceModelLibrary/JFET/BF244B/BF244B.lib b/library/deviceModelLibrary/JFET/BF244B/BF244B.lib new file mode 100644 index 00000000..ca79f09e --- /dev/null +++ b/library/deviceModelLibrary/JFET/BF244B/BF244B.lib @@ -0,0 +1 @@ +.MODEL BF244B NJF( Beta=1.6m Betatce=-.5 Rd=1 Rs=1 Lambda=3.1m Vto=-2.29 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=3.35p M=.3622 Pb=1 Fc=.5 Cgs=3.736p Kf=13.56E-18 Af=1 ) diff --git a/library/deviceModelLibrary/JFET/BF244B/BF244B.xml b/library/deviceModelLibrary/JFET/BF244B/BF244B.xml new file mode 100644 index 00000000..8220a182 --- /dev/null +++ b/library/deviceModelLibrary/JFET/BF244B/BF244B.xml @@ -0,0 +1 @@ +NJFBF244B1.6m-.51 1 3.1m-2.29-2.5m33.57f 322.4f 123311.7u243.6 3.35p.3622 1.53.736p13.56E-181 \ No newline at end of file diff --git a/library/deviceModelLibrary/JFET/J204/J204.lib b/library/deviceModelLibrary/JFET/J204/J204.lib new file mode 100644 index 00000000..cb46cd07 --- /dev/null +++ b/library/deviceModelLibrary/JFET/J204/J204.lib @@ -0,0 +1 @@ +.MODEL J204 NJF( Beta=1.004m Betatce=-.5 Rd=1 Rs=1 Lambda=3.333m Vto=-1.139 Vtotc=-2.5m Is=29.04f Isr=281.9f N=1 Nr=2 Xti=3 Alpha=698u Vk=270.4 Cgd=3.58p M=.3601 Pb=1 Fc=.5 Cgs=5.4p Kf=165E-18 Af=1 ) diff --git a/library/deviceModelLibrary/JFET/J204/J204.xml b/library/deviceModelLibrary/JFET/J204/J204.xml new file mode 100644 index 00000000..5bc58beb --- /dev/null +++ b/library/deviceModelLibrary/JFET/J204/J204.xml @@ -0,0 +1 @@ +NJFJ2041.004m-.51 1 3.333m-1.139-2.5m29.04f281.9f123698u270.43.58p.36011.55.4p165E-181 \ No newline at end of file diff --git a/library/deviceModelLibrary/JFET/J2N3822/J2N3822.lib b/library/deviceModelLibrary/JFET/J2N3822/J2N3822.lib new file mode 100644 index 00000000..eab454f6 --- /dev/null +++ b/library/deviceModelLibrary/JFET/J2N3822/J2N3822.lib @@ -0,0 +1 @@ +.MODEL J2N3822 NJF( Beta=1.1m Betatce=-.5 Rd=1 Rs=1 Lambda=4.09m Vto=-1.962 Vtotc=-2.5m Is=181.3f Isr=1.747p N=1 Nr=2 Xti=3 Alpha=2.543u Vk=152.2 Cgd=4p M=.3114 Pb=0.5 Fc=.5 Cgs=4.627p Kf=10.2E-18 Af=1 ) diff --git a/library/deviceModelLibrary/JFET/J2N3822/J2N3822.xml b/library/deviceModelLibrary/JFET/J2N3822/J2N3822.xml new file mode 100644 index 00000000..5eca7ee4 --- /dev/null +++ b/library/deviceModelLibrary/JFET/J2N3822/J2N3822.xml @@ -0,0 +1 @@ +NJFJ2N38221.1m-.51 1 4.09m-1.962-2.5m181.3f1.747p1232.543u152.24p.31140.5.54.627p10.2E-181 \ No newline at end of file diff --git a/library/deviceModelLibrary/JFET/README.md b/library/deviceModelLibrary/JFET/README.md new file mode 100644 index 00000000..4c2f5a5d --- /dev/null +++ b/library/deviceModelLibrary/JFET/README.md @@ -0,0 +1,60 @@ +# JFET (Junction field-effect transistor) + +Junction Field Effect Transistor is one of the simplest types of field-effect transistor. It is opposite to the Bipolar Junction Transistor(BJT), It is a voltage-controlled devices. In JFET, the current flow is due to the majority of charge carriers, however, in BJTs, the current flow is due to both minority and majority charge carriers. Since only the majority of charge carriers are responsible for the current flow, JFETs are unidirectional. + +## JFET(J204) + +``` +* J204 Diode model +.MODEL J204 NJF( Beta=1.004m Betatce=-.5 Rd=1 Rs=1 Lambda=3.333m Vto=-1.139 Vtotc=-2.5m Is=29.04f Isr=281.9f N=1 Nr=2 Xti=3 Alpha=698u Vk=270.4 Cgd=3.58p M=.3601 Pb=1 Fc=.5 Cgs=5.4p Kf=165E-18 Af=1 ) + + +``` + + +## Documentation + +To know the details of J204 JFET please go through with the documentation : [J204_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/600341/VISHAY/J204.html) + + + +## JFET(J2N3822) + +``` +* J2N3822 Diode model +.MODEL J2N3822 NJF( Beta=1.1m Betatce=-.5 Rd=1 Rs=1 Lambda=4.09m Vto=-1.962 Vtotc=-2.5m Is=181.3f Isr=1.747p N=1 Nr=2 Xti=3 Alpha=2.543u Vk=152.2 Cgd=4p M=.3114 Pb=0.5 Fc=.5 Cgs=4.627p Kf=10.2E-18 Af=1 ) + + +``` + +## Documentation + +To know the details of J2N3822 JFET please go through with the documentation : [J2N3822_datasheet](https://www.st.com/resource/en/datasheet/2n3700hr.pdf) + + +## JFET(BF244B) + +``` +* BF244B Diode model +.MODEL BF244B NJF( Beta=1.6m Betatce=-.5 Rd=1 Rs=1 Lambda=3.1m Vto=-2.29 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=3.35p M=.3622 Pb=1 Fc=.5 Cgs=3.736p Kf=13.56E-18 Af=1 ) + + +``` + +## Documentation + +To know the details of BF244B JFET please go through with the documentation : [BF244B_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/50801/FAIRCHILD/BF244B.html) + +## Comments/Notes + +Please note this is a complete Device modeling. + +## Contributer + +Name: E BALAKRISHNA + +Email: balakrishnaeppili0920@gmail.com + +Year: 2022 + +Position: FOSSEE Summer Fellow 2022 -- cgit From 849b7c1b2f9604832935a3242816740033aa1549 Mon Sep 17 00:00:00 2001 From: E BALAKRISHNA Date: Wed, 30 Nov 2022 01:19:37 +0530 Subject: Uploaded the Device Model File of BJT --- .../deviceModelLibrary/Transistor/BC107/BC107.lib | 1 + .../deviceModelLibrary/Transistor/BC107/BC107.xml | 1 + .../Transistor/BC547B/BC547B.lib | 1 + .../Transistor/BC547B/BC547B.xml | 1 + .../deviceModelLibrary/Transistor/BC557/BC_557.lib | 1 + .../deviceModelLibrary/Transistor/BC557/BC_557.xml | 1 + library/deviceModelLibrary/Transistor/README.md | 63 ++++++++++++++++++++++ 7 files changed, 69 insertions(+) create mode 100644 library/deviceModelLibrary/Transistor/BC107/BC107.lib create mode 100644 library/deviceModelLibrary/Transistor/BC107/BC107.xml create mode 100644 library/deviceModelLibrary/Transistor/BC547B/BC547B.lib create mode 100644 library/deviceModelLibrary/Transistor/BC547B/BC547B.xml create mode 100644 library/deviceModelLibrary/Transistor/BC557/BC_557.lib create mode 100644 library/deviceModelLibrary/Transistor/BC557/BC_557.xml create mode 100644 library/deviceModelLibrary/Transistor/README.md (limited to 'library') diff --git a/library/deviceModelLibrary/Transistor/BC107/BC107.lib b/library/deviceModelLibrary/Transistor/BC107/BC107.lib new file mode 100644 index 00000000..86233eda --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC107/BC107.lib @@ -0,0 +1 @@ +.MODEL BC107 NPN( Is=1.527f Xti=3 Eg=1.11 Vaf=1.06.8 Bf=334.5 Ne=1.642 Ise=222f Ikf=0.1596 Xtb=1.5 Br=0788 Nc=2 Isc=0 Ikr=0 Rc=0.6 Cjc=6.072p Mjc=.3333 Vjc=.75 Fc=.5 Cje=10.67p Mje=.3333 Vje=.75 Tr=10n Tf=471.8p Itf=0 Vtf=0 Xtf=0 Rb=3 ) diff --git a/library/deviceModelLibrary/Transistor/BC107/BC107.xml b/library/deviceModelLibrary/Transistor/BC107/BC107.xml new file mode 100644 index 00000000..7c9e4814 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC107/BC107.xml @@ -0,0 +1 @@ +NPNBC1071.527f3 1.11 1.06.8334.51.642222f0.15961.5
0788
2 0 0 0.66.072p.3333.75 .5 10.67p.3333.75 10n471.8p0003 \ No newline at end of file diff --git a/library/deviceModelLibrary/Transistor/BC547B/BC547B.lib b/library/deviceModelLibrary/Transistor/BC547B/BC547B.lib new file mode 100644 index 00000000..723537a7 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC547B/BC547B.lib @@ -0,0 +1 @@ +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) diff --git a/library/deviceModelLibrary/Transistor/BC547B/BC547B.xml b/library/deviceModelLibrary/Transistor/BC547B/BC547B.xml new file mode 100644 index 00000000..da06e5c4 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC547B/BC547B.xml @@ -0,0 +1 @@ +NPNBC547B1.7 7.306p 2 46.91n 1.307 22.01p 0 1.5 10 1 411.1p 3 0 400 .5 14.34f
6.092
.2847 .377 .3416 74.03 .75 .75 3 .6 14.34f 1.11 \ No newline at end of file diff --git a/library/deviceModelLibrary/Transistor/BC557/BC_557.lib b/library/deviceModelLibrary/Transistor/BC557/BC_557.lib new file mode 100644 index 00000000..31eb3345 --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC557/BC_557.lib @@ -0,0 +1 @@ +.MODEL BC_557 PNP( Is=3.834E-14 Xti=3 Eg=1.11 Vaf=21.11 Bf=800 Ne=1.528 Ise=1.219E-14 Ikf=0.08039 Xtb=0 Br=14.84 Nc=1.28 Isc=2.852E-13 Ikr=0.047 Rc=0.5713 Cjc=1.084E-11 Mjc=0.3563 Vjc=0.1022 Fc=0.8027 Cje=1.23E-11 Mje=0.378 Vje=0.6106 Tr=1E-32 Tf=5.595E-10 Itf=0.1483 Vtf=5.23 Xtf=3.414 Rb=1 ) diff --git a/library/deviceModelLibrary/Transistor/BC557/BC_557.xml b/library/deviceModelLibrary/Transistor/BC557/BC_557.xml new file mode 100644 index 00000000..f6a138eb --- /dev/null +++ b/library/deviceModelLibrary/Transistor/BC557/BC_557.xml @@ -0,0 +1 @@ +PNPBC_5573.834E-1431.1121.118001.5281.219E-140.080390
14.84
1.282.852E-130.0470.57131.084E-110.35630.10220.80271.23E-110.3780.61061E-325.595E-100.14835.233.4141 \ No newline at end of file diff --git a/library/deviceModelLibrary/Transistor/README.md b/library/deviceModelLibrary/Transistor/README.md new file mode 100644 index 00000000..796d009d --- /dev/null +++ b/library/deviceModelLibrary/Transistor/README.md @@ -0,0 +1,63 @@ +# BJT(Bipolar junction transistor) + +BC557 is BJT. Bipolar Junction Transistors (BJTs) are three terminal semiconductor devices used to amplify signals They consist of 2 PN Junction diodes attached side by side helping to get an amplifying effect on input signals. It is a high voltage VCEO = -65 V, Switching and Amplifier. + +## BJT(BC557) + +``` +* BC557 BJT model +.MODEL BC_557 PNP( Is=3.834E-14 Xti=3 Eg=1.11 Vaf=21.11 Bf=800 Ne=1.528 Ise=1.219E-14 Ikf=0.08039 Xtb=0 Br=14.84 Nc=1.28 Isc=2.852E-13 Ikr=0.047 Rc=0.5713 Cjc=1.084E-11 Mjc=0.3563 Vjc=0.1022 Fc=0.8027 Cje=1.23E-11 Mje=0.378 Vje=0.6106 Tr=1E-32 Tf=5.595E-10 Itf=0.1483 Vtf=5.23 Xtf=3.414 Rb=1 ) + +``` + +## BJT(BC547B) + +``` +* BC547B BJT model +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) + +``` +## BJT(BC107) + +``` +* BC107 BJT model +.MODEL BC107 NPN( Is=1.527f Xti=3 Eg=1.11 Vaf=1.06.8 Bf=334.5 Ne=1.642 Ise=222f Ikf=0.1596 Xtb=1.5 Br=0788 Nc=2 Isc=0 Ikr=0 Rc=0.6 Cjc=6.072p Mjc=.3333 Vjc=.75 Fc=.5 Cje=10.67p Mje=.3333 Vje=.75 Tr=10n Tf=471.8p Itf=0 Vtf=0 Xtf=0 Rb=3 ) + +``` + + +## Usage/Examples + +Audio amplifiers in small radios + +Electronic buzzers + +Electronic bells + +## Documentation + +To know the details of BC557 BJT please go through with the documentation : [BC557_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/532903/FAIRCHILD/BC557.html) + +## Documentation + +To know the details of BC547B BJT please go through with the documentation : [BC547B_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/596621/FAIRCHILD/BC547.html) + +## Documentation + +To know the details of BC107 BJT please go through with the documentation : [BC107_datasheet](https://pdf1.alldatasheet.com/datasheet-pdf/view/16088/PHILIPS/BC107.html) + + + +## Comments/Notes + +Please note this is a complete Device modeling. + +## Contributer + +Name: E BALAKRISHNA + +Email: balakrishnaeppili0920@gmail.com + +Year: 2022 + +Position: FOSSEE Summer Fellow 2022 -- cgit From 57e4961612e7f0c21f1e2b8ef223f8fbaff84dba Mon Sep 17 00:00:00 2001 From: Sumanto Kar Date: Thu, 4 May 2023 13:47:38 +0530 Subject: Relocated eSim_Subckt.lib to kicad_eSim-library --- .../kicad_eSim-Library/eSim_Subckt.lib | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) (limited to 'library') diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index ce0c8f05..f5adf191 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -676,4 +676,85 @@ X NC 8 150 -300 200 U 50 38 1 1 N ENDDRAW ENDDEF # +# Precision_Rectifier +# +DEF Precision_Rectifier X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "Precision_Rectifier" 50 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 500 -200 0 1 0 N +X Vin 1 -600 150 200 R 50 50 1 1 I +X Vneg 2 -600 -150 200 R 50 50 1 1 I +X Vout 3 700 -150 200 L 50 50 1 1 O +X Vpos 4 700 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Diffamp_INA106 +# +DEF Diffamp_INA106 X 0 40 Y Y 1 F N +F0 "X" 0 -100 40 H V C CIN +F1 "Diffamp_INA106" 0 0 40 H V C CIN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -850 1000 -850 1000 0 1 0 N +S -250 200 250 -250 0 1 0 N +S -250 250 -250 250 0 1 0 N +X REF 1 -450 150 200 R 50 22 1 1 I +X -IN 2 -450 50 200 R 50 22 1 1 I +X +IN 3 -450 -100 200 R 50 22 1 1 I +X V- 4 -450 -200 200 R 50 22 1 1 I +X SENSE 5 450 -200 200 L 50 22 1 1 I +X Output 6 450 -100 200 L 50 22 1 1 O +X V+ 7 450 50 200 L 50 22 1 1 I +X NC 8 450 150 200 L 50 22 1 1 N +ENDDRAW +ENDDEF +# +# 74V1G14 +# +DEF 74V1G14 X 0 40 Y Y 1 F N +F0 "X" -50 50 31 H V C CNN +F1 "74V1G14" 0 0 35 H V C CNB +F2 "" -100 50 60 H I C CNN +F3 "" -100 50 60 H I C CNN +DRAW +T 0 0 250 31 0 0 0 Sch_Trig Italic 0 C C +C 250 0 50 0 1 0 N +C 1450 0 0 0 1 0 N +C 1900 150 0 0 1 0 N +S -250 300 350 -250 0 1 0 N +P 5 0 1 0 200 0 -150 -150 -150 100 -150 150 200 0 N +X NC 1 -200 -450 200 U 50 39 1 1 N +X Inp 2 50 -450 200 U 50 39 1 1 I +X GND 3 250 -450 200 U 50 39 1 1 I +X Vout 4 200 500 200 D 50 39 1 1 O +X Vcc 5 -200 500 200 D 50 39 1 1 I +ENDDRAW +ENDDEF +# +# 74LVC1G19 +# +DEF 74LVC1G19 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "74LVC1G19" 0 200 39 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 0 0 39 0 0 0 1:2~Demux Italic 0 C C +S -400 450 -400 450 0 1 0 N +S -300 500 -300 500 0 1 0 N +S 300 -250 -300 400 0 1 0 N +X A 1 -500 350 200 R 50 50 1 1 I +X GND 2 -500 100 200 R 50 50 1 1 I +X Ebar 3 -500 -200 200 R 50 50 1 1 I +X Y2 4 500 -200 200 L 50 50 1 1 O +X Vcc 5 500 100 200 L 50 50 1 1 I +X Y1 6 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# #End Library -- cgit From 427467420f97eef76fd0ecc067ebd426f5cac554 Mon Sep 17 00:00:00 2001 From: Sumanto Kar Date: Thu, 4 May 2023 13:51:04 +0530 Subject: Resolved merge conflicts --- .../kicad_eSim-Library/eSim_Subckt.lib | 549 ++++++++++++++++++--- 1 file changed, 489 insertions(+), 60 deletions(-) (limited to 'library') diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index f5adf191..306cff3f 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -24,22 +24,6 @@ X AnalogOut 11 600 350 200 L 50 50 1 1 O ENDDRAW ENDDEF # -# Clock_pulse_generator -# -DEF Clock_pulse_generator X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Clock_pulse_generator" 0 -100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 200 600 -300 0 1 0 N -X Vdd 1 -750 100 200 R 50 50 1 1 I -X R 2 -750 -50 200 R 50 50 1 1 I -X C 3 -750 -200 200 R 50 50 1 1 I -X Clkout 4 800 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# # 2BITMUL # DEF 2BITMUL X 0 40 Y Y 1 F N @@ -164,6 +148,40 @@ X out 6 550 0 200 L 50 50 1 1 O ENDDRAW ENDDEF # +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# # IC_4002 # DEF IC_4002 X 0 40 Y Y 1 F N @@ -190,24 +208,6 @@ X VCC 14 450 250 200 L 50 50 1 1 I ENDDRAW ENDDEF # -# CMOS_NAND -# -DEF CMOS_NAND X 0 40 Y Y 1 F N -F0 "X" -100 -150 60 H V C CNN -F1 "CMOS_NAND" 0 -50 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 -C 550 0 50 0 1 0 N -P 2 0 1 0 -350 300 300 300 N -P 3 0 1 0 -350 300 -350 -400 300 -400 N -X in1 1 -550 250 200 R 50 50 1 1 I -X in2 2 -550 -300 200 R 50 50 1 1 I -X out 3 800 0 279 L 79 79 1 1 I -ENDDRAW -ENDDEF -# # IC_4012 # DEF IC_4012 X 0 40 Y Y 1 F N @@ -258,32 +258,6 @@ X CLK 12 -550 350 200 R 50 50 1 1 I ENDDRAW ENDDEF # -# eSim_74LS04 -# -DEF eSim_74LS04 X 0 40 Y Y 1 F N -F0 "X" 0 100 60 H V C CNN -F1 "eSim_74LS04" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S 350 500 -350 -500 0 1 0 N -X ~ 1 -550 450 200 R 50 50 1 1 P -X ~ 2 -550 300 200 R 50 50 1 1 P I -X ~ 3 -550 150 200 R 50 50 1 1 P -X ~ 4 -550 0 200 R 50 50 1 1 P I -X ~ 5 -550 -150 200 R 50 50 1 1 P -X ~ 6 -550 -300 200 R 50 50 1 1 P I -X GND 7 -550 -450 200 R 50 50 1 1 P -X ~ 8 550 -450 200 L 50 50 1 1 P I -X ~ 9 550 -300 200 L 50 50 1 1 P -X ~ 10 550 -150 200 L 50 50 1 1 P I -X ~ 11 550 0 200 L 50 50 1 1 P -X ~ 12 550 150 200 L 50 50 1 1 P I -X ~ 13 550 300 200 L 50 50 1 1 P -X VCC 14 550 450 200 L 50 50 1 1 P -ENDDRAW -ENDDEF -# # IC_4023 # DEF IC_4023 X 0 40 Y Y 1 F N @@ -523,6 +497,21 @@ X VCC 8 0 600 200 D 50 50 1 1 W ENDDRAW ENDDEF # +# LM_7809_VR +# +DEF LM_7809_VR X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7809_VR" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X OUT 2 550 0 200 L 50 50 1 1 O +X GND 3 0 -400 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# # LM_7812 # DEF LM_7812 X 0 40 Y Y 1 F N @@ -590,6 +579,32 @@ X B2 3 0 350 200 D 50 50 1 1 B ENDDRAW ENDDEF # +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# # full_adder # DEF full_adder X 0 40 Y Y 1 F N @@ -676,6 +691,420 @@ X NC 8 150 -300 200 U 50 38 1 1 N ENDDRAW ENDDEF # +# CD_4081 +# +DEF CD_4081 X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "CD_4081" 100 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 300 750 -300 0 1 0 N +X A1 1 -500 -500 200 U 50 50 1 1 I +X B1 2 -300 -500 200 U 50 50 1 1 I +X Y1 3 -100 -500 200 U 50 50 1 1 O +X Y2 4 100 -500 200 U 50 50 1 1 O +X A2 5 300 -500 200 U 50 50 1 1 I +X B2 6 500 -500 200 U 50 50 1 1 I +X GND 7 700 -500 200 U 50 50 1 1 I +X A3 8 700 500 200 D 50 50 1 1 I +X B3 9 500 500 200 D 50 50 1 1 I +X Y3 10 300 500 200 D 50 50 1 1 O +X Y4 11 100 500 200 D 50 50 1 1 O +X A4 12 -100 500 200 D 50 50 1 1 I +X B4 13 -300 500 200 D 50 50 1 1 I +X VCC 14 -500 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4077 +# +DEF CD4077 X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "CD4077" 0 50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 250 550 -250 0 1 0 N +X A1 1 -400 -450 200 U 50 50 1 1 I +X B1 2 -250 -450 200 U 50 50 1 1 I +X Y1 3 -100 -450 200 U 50 50 1 1 O +X Y2 4 50 -450 200 U 50 50 1 1 O +X A2 5 200 -450 200 U 50 50 1 1 I +X B2 6 350 -450 200 U 50 50 1 1 I +X GND 7 500 -450 200 U 50 50 1 1 I +X A3 8 500 450 200 D 50 50 1 1 I +X B3 9 350 450 200 D 50 50 1 1 I +X Y3 10 200 450 200 D 50 50 1 1 O +X Y4 11 50 450 200 D 50 50 1 1 O +X B4 12 -100 450 200 D 50 50 1 1 I +X A4 13 -250 450 200 D 50 50 1 1 I +X VCC 14 -400 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4071 +# +DEF CD_4071 X 0 40 Y Y 1 F N +F0 "X" -200 -50 60 H V C CNN +F1 "CD_4071" 100 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 600 -250 0 1 0 N +X A1 1 -350 -450 200 U 50 50 1 1 I +X B1 2 -200 -450 200 U 50 50 1 1 I +X Q1 3 -50 -450 200 U 50 50 1 1 O +X Q2 4 100 -450 200 U 50 50 1 1 O +X A2 5 250 -450 200 U 50 50 1 1 I +X B2 6 400 -450 200 U 50 50 1 1 I +X GND 7 550 -450 200 U 50 50 1 1 I +X A3 8 550 400 200 D 50 50 1 1 I +X B3 9 400 400 200 D 50 50 1 1 I +X Q3 10 250 400 200 D 50 50 1 1 O +X Q4 11 100 400 200 D 50 50 1 1 O +X A4 12 -50 400 200 D 50 50 1 1 I +X B4 13 -200 400 200 D 50 50 1 1 I +X VCC 14 -350 400 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4070 +# +DEF CD_4070 X 0 40 Y Y 1 F N +F0 "X" -250 -50 60 H V C CNN +F1 "CD_4070" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 250 550 -250 0 1 0 N +X A1 1 -450 -450 200 U 50 50 1 1 I +X B1 2 -300 -450 200 U 50 50 1 1 I +X Y1 3 -150 -450 200 U 50 50 1 1 O +X Y2 4 0 -450 200 U 50 50 1 1 O +X A2 5 150 -450 200 U 50 50 1 1 I +X B2 6 300 -450 200 U 50 50 1 1 I +X GND 7 450 -450 200 U 50 50 1 1 I +X A3 8 450 450 200 D 50 50 1 1 I +X B3 9 300 450 200 D 50 50 1 1 I +X Y3 10 150 450 200 D 50 50 1 1 O +X Y4 11 0 450 200 D 50 50 1 1 O +X A4 12 -150 450 200 D 50 50 1 1 I +X B4 13 -300 450 200 D 50 50 1 1 I +X VCC 14 -450 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4069 +# +DEF CD_4069 X 0 40 Y Y 1 F N +F0 "X" -250 100 60 H V C CNN +F1 "CD_4069" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -450 0 1 0 N +X IN_1 1 -500 350 200 R 50 50 1 1 I +X OUT_1 2 -500 200 200 R 50 50 1 1 O +X IN_3 3 -500 0 200 R 50 50 1 1 I +X OUT_2 4 -500 -100 200 R 50 50 1 1 O +X IN_5 5 -500 -200 200 R 50 50 1 1 I +X OUT_3 6 -500 -300 200 R 50 50 1 1 O +X GND 7 -500 -400 200 R 50 50 1 1 I +X OUT_4 8 500 -400 200 L 50 50 1 1 O +X IN_4 9 500 -300 200 L 50 50 1 1 I +X OUT_5 10 500 -200 200 L 50 50 1 1 O +X IN_5 11 500 -100 200 L 50 50 1 1 I +X OUT_6 12 500 0 200 L 50 50 1 1 O +X IN_6 13 500 200 200 L 50 50 1 1 I +X VDD 14 500 350 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4028B_IC +# +DEF CD4028B_IC X 0 40 Y Y 1 F N +F0 "X" 100 150 60 H V C CNN +F1 "CD4028B_IC" 100 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 450 600 -700 0 1 0 N +X Y_4 1 -600 400 200 R 50 50 1 1 O +X Y_2 2 -600 250 200 R 50 50 1 1 O +X Y_0 3 -600 100 200 R 50 50 1 1 O +X Y_7 4 -600 -50 200 R 50 50 1 1 O +X Y_9 5 -600 -200 200 R 50 50 1 1 O +X Y_5 6 -600 -350 200 R 50 50 1 1 O +X Y_6 7 -600 -500 200 R 50 50 1 1 O +X VSS 8 -600 -650 200 R 50 50 1 1 I +X Y_8 9 800 -650 200 L 50 50 1 1 O +X A 10 800 -500 200 L 50 50 1 1 I +X D 11 800 -350 200 L 50 50 1 1 I +X C 12 800 -200 200 L 50 50 1 1 I +X B 13 800 -50 200 L 50 50 1 1 I +X Y_1 14 800 100 200 L 50 50 1 1 O +X Y_3 15 800 250 200 L 50 50 1 1 O +X VDD 16 800 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4023 +# +DEF CD_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4023" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 250 450 -300 0 1 0 N +X A1 1 -500 -500 200 U 50 50 1 1 I +X B1 2 -350 -500 200 U 50 50 1 1 I +X A2 3 -200 -500 200 U 50 50 1 1 I +X B2 4 -50 -500 200 U 50 50 1 1 I +X C2 5 100 -500 200 U 50 50 1 1 I +X Y2 6 250 -500 200 U 50 50 1 1 O +X GND 7 400 -500 200 U 50 50 1 1 I +X C1 8 400 450 200 D 50 50 1 1 I +X Y1 9 250 450 200 D 50 50 1 1 O +X Y3 10 100 450 200 D 50 50 1 1 O +X A3 11 -50 450 200 D 50 50 1 1 I +X B3 12 -200 450 200 D 50 50 1 1 I +X C3 13 -350 450 200 D 50 50 1 1 I +X VCC 14 -500 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4011 +# +DEF CD_4011 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4011" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -450 250 550 -300 0 1 0 N +X A1 1 -400 -500 200 U 50 50 1 1 I +X B1 2 -250 -500 200 U 50 50 1 1 I +X Y1 3 -100 -500 200 U 50 50 1 1 O +X Y2 4 50 -500 200 U 50 50 1 1 O +X A2 5 200 -500 200 U 50 50 1 1 I +X B2 6 350 -500 200 U 50 50 1 1 I +X GND 7 500 -500 200 U 50 50 1 1 I +X A3 8 500 450 200 D 50 50 1 1 I +X B3 9 350 450 200 D 50 50 1 1 I +X Y3 10 200 450 200 D 50 50 1 1 O +X Y4 11 50 450 200 D 50 50 1 1 O +X A4 12 -100 450 200 D 50 50 1 1 I +X B4 13 -250 450 200 D 50 50 1 1 I +X VCC 14 -400 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4001 +# +DEF CD_4001 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "CD_4001" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 250 500 -300 0 1 0 N +X A1 1 -450 -500 200 U 50 50 1 1 I +X B1 2 -300 -500 200 U 50 50 1 1 I +X Y1 3 -150 -500 200 U 50 50 1 1 O +X Y2 4 0 -500 200 U 50 50 1 1 O +X A2 5 150 -500 200 U 50 50 1 1 I +X B2 6 300 -500 200 U 50 50 1 1 I +X GND 7 450 -500 200 U 50 50 1 1 I +X A3 8 450 450 200 D 50 50 1 1 I +X B3 9 300 450 200 D 50 50 1 1 I +X VCC ~ -450 450 200 D 50 50 1 1 I +X Y3 10 150 450 200 D 50 50 1 1 O +X Y4 11 0 450 200 D 50 50 1 1 O +X A4 12 -150 450 200 D 50 50 1 1 I +X B4 13 -300 450 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_54HC_153 +# +DEF CD_54HC_153 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "CD_54HC_153" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 450 550 -700 0 1 0 N +X E1_bar 1 -750 400 200 R 50 50 1 1 I +X S1 2 -750 250 200 R 50 50 1 1 I +X I3_1 3 -750 100 200 R 50 50 1 1 I +X I2_1 4 -750 -50 200 R 50 50 1 1 I +X I1_1 5 -750 -200 200 R 50 50 1 1 I +X I0_1 6 -750 -350 200 R 50 50 1 1 I +X Y1 7 -750 -500 200 R 50 50 1 1 O +X GND 8 -750 -650 200 R 50 50 1 1 I +X Y2 9 750 -650 200 L 50 50 1 1 O +X I0_2 10 750 -500 200 L 50 50 1 1 I +X I1_2 11 750 -350 200 L 50 50 1 1 I +X I2_2 12 750 -200 200 L 50 50 1 1 I +X I3_2 13 750 -50 200 L 50 50 1 1 I +X S0 14 750 100 200 L 50 50 1 1 I +X E2_bar 15 750 250 200 L 50 50 1 1 I +X VCC 16 750 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_54157 +# +DEF CD_54157 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "CD_54157" 0 -250 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -600 0 1 0 N +X Sel 1 -550 150 200 R 50 50 1 1 I +X I0_1 2 -550 50 200 R 50 50 1 1 I +X I1_1 3 -550 -50 200 R 50 50 1 1 I +X Y1_bar 4 -550 -150 200 R 50 50 1 1 O +X I0_2 5 -550 -250 200 R 50 50 1 1 I +X I1_2 6 -550 -350 200 R 50 50 1 1 I +X Y2_bar 7 -550 -450 200 R 50 50 1 1 O +X GND 8 -550 -550 200 R 50 50 1 1 I +X Y3_bar 9 550 -550 200 L 50 50 1 1 O +X I1_3 10 550 -450 200 L 50 50 1 1 I +X I0_3 11 550 -350 200 L 50 50 1 1 I +X Y4_bar 12 550 -250 200 L 50 50 1 1 O +X I1_4 13 550 -150 200 L 50 50 1 1 I +X I0_4 14 550 -50 200 L 50 50 1 1 I +X E_bar 15 550 50 200 L 50 50 1 1 I +X VCC 16 550 150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# AD620_IC +# +DEF AD620_IC X 0 40 Y Y 1 F N +F0 "X" 50 200 60 H V C CNN +F1 "AD620_IC" 0 -100 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 400 350 -450 0 1 0 N +X RG1 1 -550 300 200 R 50 50 1 1 I +X IN- 2 -550 100 200 R 50 50 1 1 I +X IN+ 3 -550 -150 200 R 50 50 1 1 I +X VS- 4 -550 -350 200 R 50 50 1 1 I +X REF 5 550 -350 200 L 50 50 1 1 I +X OUT 6 550 -150 200 L 50 50 1 1 O +X VS+ 7 550 100 200 L 50 50 1 1 I +X RG2 8 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD_4008 +# +DEF CD_4008 X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "CD_4008" 0 50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 500 350 -650 0 1 0 N +X A3 1 -550 450 200 R 50 50 1 1 I +X B2 2 -550 300 200 R 50 50 1 1 I +X A2 3 -550 150 200 R 50 50 1 1 I +X B1 4 -550 0 200 R 50 50 1 1 I +X A1 5 -550 -150 200 R 50 50 1 1 I +X B0 6 -550 -300 200 R 50 50 1 1 I +X A0 7 -550 -450 200 R 50 50 1 1 I +X GND 8 -550 -600 200 R 50 50 1 1 I +X Cin 9 550 -600 200 L 50 50 1 1 I +X S0 10 550 -450 200 L 50 50 1 1 O +X S1 11 550 -300 200 L 50 50 1 1 O +X S2 12 550 -150 200 L 50 50 1 1 O +X S3 13 550 0 200 L 50 50 1 1 O +X COUT 14 550 150 200 L 50 50 1 1 O +X B3 15 550 300 200 L 50 50 1 1 I +X VDD 16 550 450 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD54HC151 +# +DEF CD54HC151 X 0 40 Y Y 1 F N +F0 "X" 50 -150 60 H V C CNN +F1 "CD54HC151" 50 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 500 550 -650 0 1 0 N +X I3 1 -700 450 200 R 50 50 1 1 I +X I2 2 -700 300 200 R 50 50 1 1 I +X I1 3 -700 150 200 R 50 50 1 1 I +X I0 4 -700 0 200 R 50 50 1 1 I +X Y 5 -700 -150 200 R 50 50 1 1 O +X Y_bar 6 -700 -300 200 R 50 50 1 1 O +X E_bar 7 -700 -450 200 R 50 50 1 1 I +X GND 8 -700 -600 200 R 50 50 1 1 I +X S2 9 750 -600 200 L 50 50 1 1 I +X S1 10 750 -450 200 L 50 50 1 1 I +X S0 11 750 -300 200 L 50 50 1 1 I +X I7 12 750 -150 200 L 50 50 1 1 I +X I6 13 750 0 200 L 50 50 1 1 I +X I5 14 750 150 200 L 50 50 1 1 I +X I4 15 750 300 200 L 50 50 1 1 I +X VDD 16 750 450 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CD4000_NOR +# +DEF CD4000_NOR X 0 40 Y Y 1 F N +F0 "X" 50 350 60 H V C CNN +F1 "CD4000_NOR" 0 -100 60 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 -300 400 60 0 0 0 NC_1 Normal 0 C C +T 0 -300 250 60 0 0 0 NC_2 Normal 0 C C +S -450 450 450 -550 0 1 0 N +X IN1_1 3 -650 100 200 R 50 50 1 1 I +X IN1_2 4 -650 -50 200 R 50 50 1 1 I +X IN1_3 5 -650 -200 200 R 50 50 1 1 I +X OUT_1 6 -650 -350 200 R 50 50 1 1 O +X GND 7 -650 -500 200 R 50 50 1 1 I +X IN_inv 8 650 -500 200 L 50 50 1 1 I +X OUT_inv 9 650 -350 200 L 50 50 1 1 O +X OUT_2 10 650 -200 200 L 50 50 1 1 O +X IN2_1 11 650 -50 200 L 50 50 1 1 I +X IN2_2 12 650 100 200 L 50 50 1 1 I +X IN2_3 13 650 250 200 L 50 50 1 1 I +X VDD 14 650 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LM_386 +# +DEF LM_386 X 0 40 Y Y 1 F N +F0 "X" -100 100 60 H V C CNN +F1 "LM_386" 150 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -250 350 400 -150 0 1 0 N +X GAIN 1 -200 -350 200 U 50 50 1 1 I +X -IN 2 0 -350 200 U 50 50 1 1 I +X +IN 3 150 -350 200 U 50 50 1 1 I +X GND 4 350 -350 200 U 50 50 1 1 I +X OUT 5 350 550 200 D 50 50 1 1 O +X VDD 6 150 550 200 D 50 50 1 1 I +X ByP 7 0 550 200 D 50 50 1 1 I +X GAIN 8 -200 550 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# # Precision_Rectifier # DEF Precision_Rectifier X 0 40 Y Y 1 F N -- cgit From add82494ea6cdcc8a37609cd54aa0c5e772b2668 Mon Sep 17 00:00:00 2001 From: Sumanto Kar Date: Thu, 4 May 2023 14:18:19 +0530 Subject: Relocated the eSim_Subckt.lib --- .../kicad_eSim-Library/eSim_Subckt.lib | 167 +++++++++++++++++++++ 1 file changed, 167 insertions(+) (limited to 'library') diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index 306cff3f..c49af970 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -1186,4 +1186,171 @@ X Y1 6 500 350 200 L 50 50 1 1 O ENDDRAW ENDDEF # +# lm1458 +# +DEF lm1458 X 0 40 N N 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "lm1458" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 -200 200 60 0 0 0 1 Normal 0 C C +T 0 -200 100 60 0 0 0 2 Normal 0 C C +T 0 -200 0 60 0 0 0 3 Normal 0 C C +T 0 -200 -100 60 0 0 0 4 Normal 0 C C +T 0 200 -100 60 0 0 0 5 Normal 0 C C +T 0 200 0 60 0 0 0 6 Normal 0 C C +T 0 200 100 60 0 0 0 7 Normal 0 C C +T 0 200 200 60 0 0 0 8 Normal 0 C C +A 0 300 50 -1799 -1 0 1 0 N -50 300 50 300 +S -250 300 250 -200 0 1 0 N +X 3 1 -450 0 200 R 50 50 1 1 I +X 2 2 -450 100 200 R 50 50 1 1 I +X 4 3 -450 -100 200 R 50 50 1 1 I +X 5 4 450 -100 200 L 50 50 1 1 I +X 8 5 450 200 200 L 50 50 1 1 I +X 1 6 -450 200 200 R 50 50 1 1 O +X 6 7 450 0 200 L 50 50 1 1 I +X 7 8 450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LM723 +# +DEF LM723 X 0 40 N Y 1 F N +F0 "X" -50 150 60 H V C CNN +F1 "LM723" -50 250 60 H V C CNN +F2 "" -50 150 60 H I C CNN +F3 "" -50 150 60 H I C CNN +DRAW +T 0 -500 350 60 0 0 0 1 Normal 0 C C +T 0 450 -50 60 0 0 0 10 Normal 0 C C +T 0 450 50 60 0 0 0 11 Normal 0 C C +T 0 450 150 60 0 0 0 12 Normal 0 C C +T 0 450 250 60 0 0 0 13 Normal 0 C C +T 0 450 350 60 0 0 0 14 Normal 0 C C +T 0 -500 250 60 0 0 0 2 Normal 0 C C +T 0 -500 150 60 0 0 0 3 Normal 0 C C +T 0 -500 50 60 0 0 0 4 Normal 0 C C +T 0 -500 -50 60 0 0 0 5 Normal 0 C C +T 0 -500 -150 60 0 0 0 6 Normal 0 C C +T 0 -500 -250 60 0 0 0 7 Normal 0 C C +T 0 450 -250 60 0 0 0 8 Normal 0 C C +T 0 450 -150 60 0 0 0 9 Normal 0 C C +A -25 400 25 -1799 -1 0 1 0 N -50 400 0 400 +S -400 400 350 -400 0 1 0 N +X V+ 1 550 100 200 L 50 50 1 1 B +X Vc 2 550 0 200 L 50 50 1 1 B +X Vout 3 550 -100 200 L 50 50 1 1 B +X Vz 4 550 -200 200 L 50 50 1 1 B +X Vref 5 -600 -200 200 R 50 50 1 1 B +X FC 6 550 200 200 L 50 50 1 1 B +X CL 7 -600 200 200 R 50 50 1 1 B +X CS 8 -600 100 200 R 50 50 1 1 B +X Vi 9 -600 0 200 R 50 50 1 1 B +X Vni 10 -600 -100 200 R 50 50 1 1 B +X NC 11 -600 300 200 R 50 50 1 1 N +X NC 12 550 300 200 L 50 50 1 1 N +X NC 13 550 -300 200 L 50 50 1 1 N +X V- 14 -600 -300 200 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +# LM393 +# +DEF LM393 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM393" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -300 200 60 0 0 0 1 Normal 0 C C +T 0 -300 100 60 0 0 0 2 Normal 0 C C +T 0 -300 0 60 0 0 0 3 Normal 0 C C +T 0 -300 -100 60 0 0 0 4 Normal 0 C C +T 0 250 -100 60 0 0 0 5 Normal 0 C C +T 0 250 0 60 0 0 0 6 Normal 0 C C +T 0 250 100 60 0 0 0 7 Normal 0 C C +T 0 250 200 60 0 0 0 8 Normal 0 C C +A 0 200 50 -1799 -1 0 1 0 N -50 200 50 200 +S -200 200 200 -200 0 1 0 N +X 8 1 400 150 200 L 50 50 1 1 I +X 3 2 -400 -50 200 R 50 50 1 1 I +X 2 3 -400 50 200 R 50 50 1 1 I +X 1 4 -400 150 200 R 50 50 1 1 O +X 4 5 -400 -150 200 R 50 50 1 1 I +X 5 6 400 -150 200 L 50 50 1 1 I +X 6 7 400 -50 200 L 50 50 1 1 I +X 7 8 400 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LM321 +# +DEF LM321 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM321" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -300 200 60 0 0 0 1 Normal 0 C C +T 0 -300 50 60 0 0 0 2 Normal 0 C C +T 0 -300 -100 60 0 0 0 3 Normal 0 C C +T 0 300 -100 60 0 0 0 4 Normal 0 C C +T 0 300 200 60 0 0 0 5 Normal 0 C C +A 0 200 50 -1799 -1 0 1 0 N -50 200 50 200 +S -200 200 200 -200 0 1 0 N +X V+ 1 -400 150 200 R 50 50 1 1 I +X V- 2 -400 -150 200 R 50 50 1 1 I +X Vcc 3 400 150 200 L 50 50 1 1 I +X Vout 4 400 -150 200 L 50 50 1 1 O +X Vee 5 -400 0 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LM13700 +# +DEF LM13700 X 0 40 N N 1 F N +F0 "X" -50 250 60 H V C CNN +F1 "LM13700" -50 400 60 H V C CNN +F2 "" -50 250 60 H I C CNN +F3 "" -50 250 60 H I C CNN +DRAW +A 0 550 50 -1799 -1 0 0 0 N -50 550 50 550 +T 0 -300 450 60 0 0 0 1 Normal 0 C C +T 0 250 -150 60 0 0 0 10 Normal 0 C C +T 0 250 -50 60 0 0 0 11 Normal 0 C C +T 0 250 50 60 0 0 0 12 Normal 0 C C +T 0 250 150 60 0 0 0 13 Normal 0 C C +T 0 250 250 60 0 0 0 14 Normal 0 C C +T 0 250 350 60 0 0 0 15 Normal 0 C C +T 0 250 450 60 0 0 0 16 Normal 0 C C +T 0 -300 350 60 0 0 0 2 Normal 0 C C +T 0 -300 250 60 0 0 0 3 Normal 0 C C +T 0 -300 150 60 0 0 0 4 Normal 0 C C +T 0 -300 50 60 0 0 0 5 Normal 0 C C +T 0 -300 -50 60 0 0 0 6 Normal 0 C C +T 0 -300 -150 60 0 0 0 7 Normal 0 C C +T 0 -300 -250 60 0 0 0 8 Normal 0 C C +T 0 250 -250 60 0 0 0 9 Normal 0 C C +S -350 550 350 -350 0 1 0 N +X V+ 1 550 -50 200 L 50 50 1 1 I +X Diode_bias 2 -550 350 200 R 50 50 1 1 I +X -Input 3 -550 150 200 R 50 50 1 1 B +X +Input 4 -550 250 200 R 50 50 1 1 B +X Amp_bias 5 -550 450 200 R 50 50 1 1 I +X V- 6 -550 -50 200 R 50 50 1 1 I +X Output 7 -550 50 200 R 50 50 1 1 O +X Diode_bias 8 550 350 200 L 50 50 1 1 I +X -Input 9 550 150 200 L 50 50 1 1 B +X +Input 10 550 250 200 L 50 50 1 1 B +X Amp_bias_input 11 550 450 200 L 50 50 1 1 I +X Buffer_output 12 -550 -250 200 R 50 50 1 1 B +X Buffer_Input 13 -550 -150 200 R 50 50 1 1 I +X Output 14 550 50 200 L 50 50 1 1 O +X Buffer_output 15 550 -250 200 L 50 50 1 1 B +X Buffer_input 16 550 -150 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# #End Library -- cgit From 5239a15af6468f13a2b6d248ffc132eb83420e0b Mon Sep 17 00:00:00 2001 From: Sumanto Kar Date: Thu, 4 May 2023 14:26:21 +0530 Subject: Minor changes to the description in files --- library/deviceModelLibrary/Diode/DRB168MM200.lib | 3 +-- library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'library') diff --git a/library/deviceModelLibrary/Diode/DRB168MM200.lib b/library/deviceModelLibrary/Diode/DRB168MM200.lib index 5801102c..f8e22700 100644 --- a/library/deviceModelLibrary/Diode/DRB168MM200.lib +++ b/library/deviceModelLibrary/Diode/DRB168MM200.lib @@ -1,2 +1 @@ -* Model Generated by ROHM -.MODEL DRB168MM200 D( IS=5.6001E-9 N=1.0413 RS=90.681E-3 IKF=2.9636E-3 XTI=2.0 EG=0.74 CJO=86.088E-12 M=0.4523 VJ=0.5 ISR=9.8101E-9 NR=1.3311 BV=200 TRS1=-3.7501E-3 ) \ No newline at end of file +.MODEL DRB168MM200 D( IS=5.6001E-9 N=1.0413 RS=90.681E-3 IKF=2.9636E-3 XTI=2.0 EG=0.74 CJO=86.088E-12 M=0.4523 VJ=0.5 ISR=9.8101E-9 NR=1.3311 BV=200 TRS1=-3.7501E-3 ) diff --git a/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib index 25e7b6b2..2bc85454 100644 --- a/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib +++ b/library/deviceModelLibrary/Diode/RF Diode/DRN142S.lib @@ -1,3 +1 @@ -* DRN142S Diode model -* Date: 2008/12/24 -.MODEL DRN142S D( IS=127.76E-12 N=1.7346 RS=.1581 IKF=.14089 CJO=385.59E-15 M=.11823 VJ=.78827 ISR=139.38E-12 NR=3 BV=60 TT=275.00E-9 ) \ No newline at end of file +.MODEL DRN142S D( IS=127.76E-12 N=1.7346 RS=.1581 IKF=.14089 CJO=385.59E-15 M=.11823 VJ=.78827 ISR=139.38E-12 NR=3 BV=60 TT=275.00E-9 ) -- cgit