From bbd8c77db976b69f2c653e9fa641a269a8b0cf29 Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 14:58:47 +0000
Subject: Added DAC0800 subcircuit to SubcircuitLibrary
---
library/SubcircuitLibrary/DAC0800/D.lib | 2 +
.../DAC0800/DAC0800_Subcircuit-cache.lib | 126 ++
.../DAC0800/DAC0800_Subcircuit.cir | 92 ++
.../DAC0800/DAC0800_Subcircuit.cir.out | 96 ++
.../DAC0800/DAC0800_Subcircuit.pro | 73 +
.../DAC0800/DAC0800_Subcircuit.sch | 1690 ++++++++++++++++++++
.../DAC0800/DAC0800_Subcircuit.sub | 90 ++
.../DAC0800/DAC0800_Subcircuit_Previous_Values.xml | 1 +
library/SubcircuitLibrary/DAC0800/NPN.lib | 4 +
library/SubcircuitLibrary/DAC0800/PNP.lib | 4 +
library/SubcircuitLibrary/DAC0800/analysis | 1 +
11 files changed, 2179 insertions(+)
create mode 100644 library/SubcircuitLibrary/DAC0800/D.lib
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub
create mode 100644 library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/DAC0800/NPN.lib
create mode 100644 library/SubcircuitLibrary/DAC0800/PNP.lib
create mode 100644 library/SubcircuitLibrary/DAC0800/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/DAC0800/D.lib b/library/SubcircuitLibrary/DAC0800/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib
new file mode 100644
index 00000000..6184ddb3
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir
new file mode 100644
index 00000000..242f8395
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir
@@ -0,0 +1,92 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\DAC0800_Subcircuit\DAC0800_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/28/24 13:16:39
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_Q1-Pad2_ Net-_Q3-Pad2_ Net-_Q4-Pad2_ Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_Q11-Pad2_ Net-_Q16-Pad2_ Net-_Q21-Pad2_ Net-_Q26-Pad2_ Net-_Q32-Pad2_ Net-_Q37-Pad2_ Net-_Q42-Pad2_ Net-_Q47-Pad2_ Net-_Q14-Pad1_ Net-_Q12-Pad1_ PORT
+D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
+D3 Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_Diode
+Q1 Net-_D1-Pad1_ Net-_Q1-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q3 Net-_Q2-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q2 Net-_Q2-Pad1_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+Q4 Net-_D2-Pad1_ Net-_Q4-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q8 Net-_Q8-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q13 Net-_Q13-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q16 Net-_Q16-Pad1_ Net-_Q16-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q18 Net-_Q18-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q23 Net-_Q23-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q26 Net-_Q26-Pad1_ Net-_Q26-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q29 Net-_Q29-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q32 Net-_Q32-Pad1_ Net-_Q32-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q34 Net-_Q34-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q37 Net-_Q37-Pad1_ Net-_Q37-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q39 Net-_Q39-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q42 Net-_Q42-Pad1_ Net-_Q42-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q45 Net-_D5-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q47 Net-_D6-Pad1_ Net-_Q47-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q9 Net-_Q14-Pad1_ Net-_Q8-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_Q11-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+R2 Net-_Q8-Pad1_ Net-_D2-Pad1_ 800
+R4 Net-_Q11-Pad1_ Net-_D2-Pad1_ 800
+Q6 Net-_Q1-Pad2_ Net-_D2-Pad1_ Net-_Q5-Pad1_ eSim_NPN
+Q5 Net-_Q5-Pad1_ Net-_D1-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+R1 Net-_Q5-Pad3_ Net-_D1-Pad2_ 5k
+Q14 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_Q14-Pad3_ eSim_NPN
+Q17 Net-_Q12-Pad1_ Net-_Q16-Pad1_ Net-_Q14-Pad3_ eSim_NPN
+R6 Net-_Q13-Pad1_ Net-_D2-Pad1_ 1.6k
+R8 Net-_Q16-Pad1_ Net-_D2-Pad1_ 1.6k
+Q19 Net-_Q14-Pad1_ Net-_Q18-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q22 Net-_Q12-Pad1_ Net-_Q21-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+R10 Net-_Q18-Pad1_ Net-_D2-Pad1_ 3.2k
+R12 Net-_Q21-Pad1_ Net-_D2-Pad1_ 3.2k
+Q24 Net-_Q14-Pad1_ Net-_Q23-Pad1_ Net-_Q24-Pad3_ eSim_NPN
+Q27 Net-_Q12-Pad1_ Net-_Q26-Pad1_ Net-_Q24-Pad3_ eSim_NPN
+R14 Net-_Q23-Pad1_ Net-_D2-Pad1_ 6.4k
+R17 Net-_Q26-Pad1_ Net-_D2-Pad1_ 6.4k
+Q30 Net-_Q14-Pad1_ Net-_Q29-Pad1_ Net-_Q30-Pad3_ eSim_NPN
+Q33 Net-_Q14-Pad1_ Net-_Q32-Pad1_ Net-_Q30-Pad3_ eSim_NPN
+R18 Net-_Q29-Pad1_ Net-_D2-Pad1_ 6.4k
+R20 Net-_Q32-Pad1_ Net-_D2-Pad1_ 6.4k
+Q35 Net-_Q14-Pad1_ Net-_Q34-Pad1_ Net-_Q35-Pad3_ eSim_NPN
+Q38 Net-_Q12-Pad1_ Net-_Q37-Pad1_ Net-_Q35-Pad3_ eSim_NPN
+R22 Net-_Q34-Pad1_ Net-_D2-Pad1_ 6.4k
+R23 Net-_Q37-Pad1_ Net-_D2-Pad1_ 6.4k
+Q40 Net-_Q14-Pad1_ Net-_Q39-Pad1_ Net-_Q40-Pad3_ eSim_NPN
+Q43 Net-_Q12-Pad1_ Net-_Q42-Pad1_ Net-_Q40-Pad3_ eSim_NPN
+R24 Net-_Q39-Pad1_ Net-_D2-Pad1_ 6.4k
+R25 Net-_Q42-Pad1_ Net-_D2-Pad1_ 6.4k
+Q44 Net-_Q14-Pad1_ Net-_D5-Pad1_ Net-_Q44-Pad3_ eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+D6 Net-_D6-Pad1_ Net-_D5-Pad2_ eSim_Diode
+R26 Net-_D5-Pad1_ Net-_D2-Pad1_ 6.4k
+R27 Net-_D6-Pad1_ Net-_D2-Pad1_ 6.4k
+Q48 Net-_Q12-Pad1_ Net-_D6-Pad1_ Net-_Q44-Pad3_ eSim_NPN
+D4 Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode
+Q10 Net-_Q10-Pad1_ Net-_D1-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q7 Net-_D1-Pad2_ Net-_D1-Pad2_ Net-_D4-Pad2_ eSim_PNP
+Q15 Net-_Q14-Pad3_ Net-_D1-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+Q20 Net-_Q19-Pad3_ Net-_D1-Pad2_ Net-_Q20-Pad3_ eSim_NPN
+Q25 Net-_Q24-Pad3_ Net-_D1-Pad2_ Net-_Q25-Pad3_ eSim_NPN
+Q31 Net-_Q30-Pad3_ Net-_D2-Pad1_ Net-_Q31-Pad3_ eSim_NPN
+Q36 Net-_Q35-Pad3_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q41 Net-_Q40-Pad3_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q46 Net-_D5-Pad2_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q28 Net-_Q28-Pad1_ Net-_D1-Pad2_ Net-_Q28-Pad3_ eSim_NPN
+R3 Net-_Q10-Pad3_ Net-_D1-Pad2_ 10k
+R7 Net-_Q15-Pad3_ Net-_R5-Pad1_ 10k
+R11 Net-_Q20-Pad3_ Net-_R11-Pad2_ 10k
+R15 Net-_Q25-Pad3_ Net-_R13-Pad1_ 10k
+R19 Net-_Q31-Pad3_ Net-_Q28-Pad1_ 5k
+R16 Net-_Q28-Pad3_ Net-_R13-Pad1_ 10k
+R13 Net-_R13-Pad1_ Net-_R11-Pad2_ 5k
+R9 Net-_R11-Pad2_ Net-_R5-Pad1_ 5k
+R5 Net-_R5-Pad1_ Net-_D1-Pad2_ 5k
+R21 Net-_Q36-Pad3_ Net-_Q28-Pad1_ 5k
+
+.end
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out
new file mode 100644
index 00000000..1f37ec14
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out
@@ -0,0 +1,96 @@
+* c:\fossee\esim\library\subcircuitlibrary\dac0800_subcircuit\dac0800_subcircuit.cir
+
+.include PNP.lib
+.include D.lib
+.include NPN.lib
+* u1 net-_q1-pad2_ net-_q3-pad2_ net-_q4-pad2_ net-_d2-pad1_ net-_d3-pad2_ net-_d1-pad2_ net-_q11-pad2_ net-_q16-pad2_ net-_q21-pad2_ net-_q26-pad2_ net-_q32-pad2_ net-_q37-pad2_ net-_q42-pad2_ net-_q47-pad2_ net-_q14-pad1_ net-_q12-pad1_ port
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148
+q1 net-_d1-pad1_ net-_q1-pad2_ net-_d2-pad1_ Q2N2907A
+q3 net-_q2-pad1_ net-_q3-pad2_ net-_d2-pad1_ Q2N2907A
+q2 net-_q2-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q4 net-_d2-pad1_ net-_q4-pad2_ net-_d1-pad2_ Q2N2222
+q8 net-_q8-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d2-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q16 net-_q16-pad1_ net-_q16-pad2_ net-_d2-pad1_ Q2N2907A
+q18 net-_q18-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d2-pad1_ Q2N2907A
+q23 net-_q23-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q26 net-_q26-pad1_ net-_q26-pad2_ net-_d2-pad1_ Q2N2907A
+q29 net-_q29-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q32 net-_q32-pad1_ net-_q32-pad2_ net-_d2-pad1_ Q2N2907A
+q34 net-_q34-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q37 net-_q37-pad1_ net-_q37-pad2_ net-_d2-pad1_ Q2N2907A
+q39 net-_q39-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q42 net-_q42-pad1_ net-_q42-pad2_ net-_d2-pad1_ Q2N2907A
+q45 net-_d5-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q47 net-_d6-pad1_ net-_q47-pad2_ net-_d2-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q8-pad1_ net-_q10-pad1_ Q2N2222
+q12 net-_q12-pad1_ net-_q11-pad1_ net-_q10-pad1_ Q2N2222
+r2 net-_q8-pad1_ net-_d2-pad1_ 800
+r4 net-_q11-pad1_ net-_d2-pad1_ 800
+q6 net-_q1-pad2_ net-_d2-pad1_ net-_q5-pad1_ Q2N2222
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q5-pad3_ net-_d1-pad2_ 5k
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_q14-pad3_ Q2N2222
+q17 net-_q12-pad1_ net-_q16-pad1_ net-_q14-pad3_ Q2N2222
+r6 net-_q13-pad1_ net-_d2-pad1_ 1.6k
+r8 net-_q16-pad1_ net-_d2-pad1_ 1.6k
+q19 net-_q14-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222
+q22 net-_q12-pad1_ net-_q21-pad1_ net-_q19-pad3_ Q2N2222
+r10 net-_q18-pad1_ net-_d2-pad1_ 3.2k
+r12 net-_q21-pad1_ net-_d2-pad1_ 3.2k
+q24 net-_q14-pad1_ net-_q23-pad1_ net-_q24-pad3_ Q2N2222
+q27 net-_q12-pad1_ net-_q26-pad1_ net-_q24-pad3_ Q2N2222
+r14 net-_q23-pad1_ net-_d2-pad1_ 6.4k
+r17 net-_q26-pad1_ net-_d2-pad1_ 6.4k
+q30 net-_q14-pad1_ net-_q29-pad1_ net-_q30-pad3_ Q2N2222
+q33 net-_q14-pad1_ net-_q32-pad1_ net-_q30-pad3_ Q2N2222
+r18 net-_q29-pad1_ net-_d2-pad1_ 6.4k
+r20 net-_q32-pad1_ net-_d2-pad1_ 6.4k
+q35 net-_q14-pad1_ net-_q34-pad1_ net-_q35-pad3_ Q2N2222
+q38 net-_q12-pad1_ net-_q37-pad1_ net-_q35-pad3_ Q2N2222
+r22 net-_q34-pad1_ net-_d2-pad1_ 6.4k
+r23 net-_q37-pad1_ net-_d2-pad1_ 6.4k
+q40 net-_q14-pad1_ net-_q39-pad1_ net-_q40-pad3_ Q2N2222
+q43 net-_q12-pad1_ net-_q42-pad1_ net-_q40-pad3_ Q2N2222
+r24 net-_q39-pad1_ net-_d2-pad1_ 6.4k
+r25 net-_q42-pad1_ net-_d2-pad1_ 6.4k
+q44 net-_q14-pad1_ net-_d5-pad1_ net-_q44-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+d6 net-_d6-pad1_ net-_d5-pad2_ 1N4148
+r26 net-_d5-pad1_ net-_d2-pad1_ 6.4k
+r27 net-_d6-pad1_ net-_d2-pad1_ 6.4k
+q48 net-_q12-pad1_ net-_d6-pad1_ net-_q44-pad3_ Q2N2222
+d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d1-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad2_ net-_d4-pad2_ Q2N2907A
+q15 net-_q14-pad3_ net-_d1-pad2_ net-_q15-pad3_ Q2N2222
+q20 net-_q19-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2222
+q25 net-_q24-pad3_ net-_d1-pad2_ net-_q25-pad3_ Q2N2222
+q31 net-_q30-pad3_ net-_d2-pad1_ net-_q31-pad3_ Q2N2222
+q36 net-_q35-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q41 net-_q40-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q46 net-_d5-pad2_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q28 net-_q28-pad1_ net-_d1-pad2_ net-_q28-pad3_ Q2N2222
+r3 net-_q10-pad3_ net-_d1-pad2_ 10k
+r7 net-_q15-pad3_ net-_r5-pad1_ 10k
+r11 net-_q20-pad3_ net-_r11-pad2_ 10k
+r15 net-_q25-pad3_ net-_r13-pad1_ 10k
+r19 net-_q31-pad3_ net-_q28-pad1_ 5k
+r16 net-_q28-pad3_ net-_r13-pad1_ 10k
+r13 net-_r13-pad1_ net-_r11-pad2_ 5k
+r9 net-_r11-pad2_ net-_r5-pad1_ 5k
+r5 net-_r5-pad1_ net-_d1-pad2_ 5k
+r21 net-_q36-pad3_ net-_q28-pad1_ 5k
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch
new file mode 100644
index 00000000..f083c62b
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch
@@ -0,0 +1,1690 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DAC0800_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+F 2 "" H 6950 3930 29 0000 C CNN
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+U 1 1 675EB79F
+P 7350 3830
+F 0 "Q33" H 7250 3880 50 0000 R CNN
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+F 2 "" H 7550 3930 29 0000 C CNN
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+ 1 7350 3830
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+L resistor R18
+U 1 1 675EB7AC
+P 6500 4200
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+F 3 "" V 6550 4250 30 0000 C CNN
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+ 0 1 1 0
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+U 1 1 675EB7B2
+P 7500 4220
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+F 3 "" V 7550 4270 30 0000 C CNN
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+ 0 1 1 0
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+U 1 1 675EB7BA
+P 8150 3830
+F 0 "Q35" H 8050 3880 50 0000 R CNN
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+U 1 1 675EB7C0
+P 8750 3830
+F 0 "Q38" H 8650 3880 50 0000 R CNN
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+ 1 8750 3830
+ -1 0 0 -1
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+$Comp
+L resistor R22
+U 1 1 675EB7CD
+P 7900 4200
+F 0 "R22" H 7950 4330 50 0000 C CNN
+F 1 "6.4k" H 7950 4150 50 0000 C CNN
+F 2 "" H 7950 4180 30 0000 C CNN
+F 3 "" V 7950 4250 30 0000 C CNN
+ 1 7900 4200
+ 0 1 1 0
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+$Comp
+L resistor R23
+U 1 1 675EB7D3
+P 8900 4220
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+F 1 "6.4k" H 8950 4170 50 0000 C CNN
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+F 3 "" V 8950 4270 30 0000 C CNN
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+ 0 1 1 0
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+U 1 1 675EC029
+P 9400 3830
+F 0 "Q40" H 9300 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 9350 3980 50 0000 R CNN
+F 2 "" H 9600 3930 29 0000 C CNN
+F 3 "" H 9400 3830 60 0000 C CNN
+ 1 9400 3830
+ 1 0 0 -1
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+L eSim_NPN Q43
+U 1 1 675EC02F
+P 10000 3830
+F 0 "Q43" H 9900 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 9950 3980 50 0000 R CNN
+F 2 "" H 10200 3930 29 0000 C CNN
+F 3 "" H 10000 3830 60 0000 C CNN
+ 1 10000 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R24
+U 1 1 675EC03C
+P 9150 4200
+F 0 "R24" H 9200 4330 50 0000 C CNN
+F 1 "6.4k" H 9200 4150 50 0000 C CNN
+F 2 "" H 9200 4180 30 0000 C CNN
+F 3 "" V 9200 4250 30 0000 C CNN
+ 1 9150 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R25
+U 1 1 675EC042
+P 10150 4220
+F 0 "R25" H 10200 4350 50 0000 C CNN
+F 1 "6.4k" H 10200 4170 50 0000 C CNN
+F 2 "" H 10200 4200 30 0000 C CNN
+F 3 "" V 10200 4270 30 0000 C CNN
+ 1 10150 4220
+ 0 1 1 0
+$EndComp
+$Comp
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+U 1 1 675EC36A
+P 10820 3830
+F 0 "Q44" H 10720 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 10770 3980 50 0000 R CNN
+F 2 "" H 11020 3930 29 0000 C CNN
+F 3 "" H 10820 3830 60 0000 C CNN
+ 1 10820 3830
+ 1 0 0 -1
+$EndComp
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+L eSim_Diode D5
+U 1 1 675ED4D2
+P 11240 3830
+F 0 "D5" H 11240 3930 50 0000 C CNN
+F 1 "eSim_Diode" H 11240 3730 50 0000 C CNN
+F 2 "" H 11240 3830 60 0000 C CNN
+F 3 "" H 11240 3830 60 0000 C CNN
+ 1 11240 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D6
+U 1 1 675EEB4B
+P 11790 3830
+F 0 "D6" H 11790 3930 50 0000 C CNN
+F 1 "eSim_Diode" H 11790 3730 50 0000 C CNN
+F 2 "" H 11790 3830 60 0000 C CNN
+F 3 "" H 11790 3830 60 0000 C CNN
+ 1 11790 3830
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R26
+U 1 1 675EFE6E
+P 10570 4230
+F 0 "R26" H 10620 4360 50 0000 C CNN
+F 1 "6.4k" H 10620 4180 50 0000 C CNN
+F 2 "" H 10620 4210 30 0000 C CNN
+F 3 "" V 10620 4280 30 0000 C CNN
+ 1 10570 4230
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R27
+U 1 1 675EFF87
+P 12330 4270
+F 0 "R27" H 12380 4400 50 0000 C CNN
+F 1 "6.4k" H 12380 4220 50 0000 C CNN
+F 2 "" H 12380 4250 30 0000 C CNN
+F 3 "" V 12380 4320 30 0000 C CNN
+ 1 12330 4270
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q48
+U 1 1 675F2477
+P 12180 3830
+F 0 "Q48" H 12080 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 12130 3980 50 0000 R CNN
+F 2 "" H 12380 3930 29 0000 C CNN
+F 3 "" H 12180 3830 60 0000 C CNN
+ 1 12180 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 675F37F6
+P 12900 3340
+F 0 "U1" H 12950 3440 30 0000 C CNN
+F 1 "PORT" H 12900 3340 30 0000 C CNN
+F 2 "" H 12900 3340 60 0000 C CNN
+F 3 "" H 12900 3340 60 0000 C CNN
+ 15 12900 3340
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 675F391A
+P 12900 3520
+F 0 "U1" H 12950 3620 30 0000 C CNN
+F 1 "PORT" H 12900 3520 30 0000 C CNN
+F 2 "" H 12900 3520 60 0000 C CNN
+F 3 "" H 12900 3520 60 0000 C CNN
+ 16 12900 3520
+ -1 0 0 1
+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3150 1080
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+L eSim_Diode D4
+U 1 1 675FA513
+P 1270 4970
+F 0 "D4" H 1270 5070 50 0000 C CNN
+F 1 "eSim_Diode" H 1270 4870 50 0000 C CNN
+F 2 "" H 1270 4970 60 0000 C CNN
+F 3 "" H 1270 4970 60 0000 C CNN
+ 1 1270 4970
+ 0 1 1 0
+$EndComp
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+Wire Wire Line
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+Connection ~ 380 4080
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+Connection ~ 2400 4720
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+L eSim_NPN Q10
+U 1 1 675FEC98
+P 1790 5400
+F 0 "Q10" H 1690 5450 50 0000 R CNN
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+L eSim_PNP Q7
+U 1 1 676EC938
+P 1170 5400
+F 0 "Q7" H 1070 5450 50 0000 R CNN
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+U 1 1 676ED46A
+P 3030 5420
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+U 1 1 676ED630
+P 4340 5430
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+U 1 1 676ED636
+P 5630 5450
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+U 1 1 676ED948
+P 6960 5450
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+U 1 1 676ED94E
+P 8340 5470
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+U 1 1 676ED954
+P 9620 5480
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+U 1 1 676ED95A
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L eSim_NPN Q28
+U 1 1 676FA4E3
+P 6170 5980
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+L resistor R3
+U 1 1 67702BB0
+P 1840 5830
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+ 1 1840 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 677031F4
+P 3080 5830
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+F 2 "" H 3130 5810 30 0000 C CNN
+F 3 "" V 3130 5880 30 0000 C CNN
+ 1 3080 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 67703574
+P 4390 5830
+F 0 "R11" H 4440 5960 50 0000 C CNN
+F 1 "10k" H 4440 5780 50 0000 C CNN
+F 2 "" H 4440 5810 30 0000 C CNN
+F 3 "" V 4440 5880 30 0000 C CNN
+ 1 4390 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 6770357A
+P 5680 5830
+F 0 "R15" H 5730 5960 50 0000 C CNN
+F 1 "10k" H 5730 5780 50 0000 C CNN
+F 2 "" H 5730 5810 30 0000 C CNN
+F 3 "" V 5730 5880 30 0000 C CNN
+ 1 5680 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 677041F3
+P 7010 5830
+F 0 "R19" H 7060 5960 50 0000 C CNN
+F 1 "5k" H 7060 5780 50 0000 C CNN
+F 2 "" H 7060 5810 30 0000 C CNN
+F 3 "" V 7060 5880 30 0000 C CNN
+ 1 7010 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R16
+U 1 1 677049B7
+P 6040 6320
+F 0 "R16" H 6090 6450 50 0000 C CNN
+F 1 "10k" H 6090 6270 50 0000 C CNN
+F 2 "" H 6090 6300 30 0000 C CNN
+F 3 "" V 6090 6370 30 0000 C CNN
+ 1 6040 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 67704B20
+P 5170 6320
+F 0 "R13" H 5220 6450 50 0000 C CNN
+F 1 "5k" H 5220 6270 50 0000 C CNN
+F 2 "" H 5220 6300 30 0000 C CNN
+F 3 "" V 5220 6370 30 0000 C CNN
+ 1 5170 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R9
+U 1 1 67704CEE
+P 3810 6320
+F 0 "R9" H 3860 6450 50 0000 C CNN
+F 1 "5k" H 3860 6270 50 0000 C CNN
+F 2 "" H 3860 6300 30 0000 C CNN
+F 3 "" V 3860 6370 30 0000 C CNN
+ 1 3810 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67704F7E
+P 2590 6320
+F 0 "R5" H 2640 6450 50 0000 C CNN
+F 1 "5k" H 2640 6270 50 0000 C CNN
+F 2 "" H 2640 6300 30 0000 C CNN
+F 3 "" V 2640 6370 30 0000 C CNN
+ 1 2590 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R21
+U 1 1 67705310
+P 7830 6320
+F 0 "R21" H 7880 6450 50 0000 C CNN
+F 1 "5k" H 7880 6270 50 0000 C CNN
+F 2 "" H 7880 6300 30 0000 C CNN
+F 3 "" V 7880 6370 30 0000 C CNN
+ 1 7830 6320
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ -580 6020 -580 6370
+Wire Wire Line
+ -580 6370 2390 6370
+Wire Wire Line
+ 2690 6370 3610 6370
+Wire Wire Line
+ 3910 6370 4970 6370
+Wire Wire Line
+ 5270 6370 5840 6370
+Wire Wire Line
+ 7930 6370 11520 6370
+Wire Wire Line
+ 11520 6370 11520 5700
+Wire Wire Line
+ 1890 5730 1890 5600
+Wire Wire Line
+ 3130 5730 3130 5620
+Wire Wire Line
+ 4440 5730 4440 5630
+Wire Wire Line
+ 5730 5730 5730 5650
+Wire Wire Line
+ 7060 5730 7060 5650
+Wire Wire Line
+ 1890 6030 1890 6370
+Connection ~ 1890 6370
+Wire Wire Line
+ 3130 6030 3130 6370
+Connection ~ 3130 6370
+Wire Wire Line
+ 4440 6030 4440 6370
+Connection ~ 4440 6370
+Wire Wire Line
+ 5730 6030 5730 6370
+Connection ~ 5730 6370
+Wire Wire Line
+ 6640 6370 7630 6370
+Wire Wire Line
+ 7060 6370 7060 6030
+Wire Wire Line
+ 6270 6180 6270 6370
+Wire Wire Line
+ 6270 6370 6140 6370
+Wire Wire Line
+ 6270 5780 6270 5740
+Wire Wire Line
+ 6270 5740 6640 5740
+Wire Wire Line
+ 6640 5740 6640 6370
+Connection ~ 7060 6370
+Wire Wire Line
+ 9720 5680 9720 6370
+Connection ~ 9720 6370
+Wire Wire Line
+ 8440 5670 8440 6370
+Connection ~ 8440 6370
+$Comp
+L PORT U1
+U 14 1 6770EB8E
+P 12190 440
+F 0 "U1" H 12240 540 30 0000 C CNN
+F 1 "PORT" H 12190 440 30 0000 C CNN
+F 2 "" H 12190 440 60 0000 C CNN
+F 3 "" H 12190 440 60 0000 C CNN
+ 14 12190 440
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 12190 2640 12190 690
+Wire Wire Line
+ -180 5620 -180 6370
+Connection ~ -180 6370
+Wire Wire Line
+ 860 6030 860 6370
+Connection ~ 860 6370
+$Comp
+L PORT U1
+U 6 1 67713869
+P 1270 6890
+F 0 "U1" H 1320 6990 30 0000 C CNN
+F 1 "PORT" H 1270 6890 30 0000 C CNN
+F 2 "" H 1270 6890 60 0000 C CNN
+F 3 "" H 1270 6890 60 0000 C CNN
+ 6 1270 6890
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 1270 5600 1270 6640
+Connection ~ 1270 6370
+Wire Wire Line
+ 1890 5200 1890 4030
+Connection ~ 380 6370
+Connection ~ 380 5400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub
new file mode 100644
index 00000000..b282b9c5
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub
@@ -0,0 +1,90 @@
+* Subcircuit DAC0800_Subcircuit
+.subckt DAC0800_Subcircuit net-_q1-pad2_ net-_q3-pad2_ net-_q4-pad2_ net-_d2-pad1_ net-_d3-pad2_ net-_d1-pad2_ net-_q11-pad2_ net-_q16-pad2_ net-_q21-pad2_ net-_q26-pad2_ net-_q32-pad2_ net-_q37-pad2_ net-_q42-pad2_ net-_q47-pad2_ net-_q14-pad1_ net-_q12-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\dac0800_subcircuit\dac0800_subcircuit.cir
+.include PNP.lib
+.include D.lib
+.include NPN.lib
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148
+q1 net-_d1-pad1_ net-_q1-pad2_ net-_d2-pad1_ Q2N2907A
+q3 net-_q2-pad1_ net-_q3-pad2_ net-_d2-pad1_ Q2N2907A
+q2 net-_q2-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q4 net-_d2-pad1_ net-_q4-pad2_ net-_d1-pad2_ Q2N2222
+q8 net-_q8-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d2-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q16 net-_q16-pad1_ net-_q16-pad2_ net-_d2-pad1_ Q2N2907A
+q18 net-_q18-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d2-pad1_ Q2N2907A
+q23 net-_q23-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q26 net-_q26-pad1_ net-_q26-pad2_ net-_d2-pad1_ Q2N2907A
+q29 net-_q29-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q32 net-_q32-pad1_ net-_q32-pad2_ net-_d2-pad1_ Q2N2907A
+q34 net-_q34-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q37 net-_q37-pad1_ net-_q37-pad2_ net-_d2-pad1_ Q2N2907A
+q39 net-_q39-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q42 net-_q42-pad1_ net-_q42-pad2_ net-_d2-pad1_ Q2N2907A
+q45 net-_d5-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q47 net-_d6-pad1_ net-_q47-pad2_ net-_d2-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q8-pad1_ net-_q10-pad1_ Q2N2222
+q12 net-_q12-pad1_ net-_q11-pad1_ net-_q10-pad1_ Q2N2222
+r2 net-_q8-pad1_ net-_d2-pad1_ 800
+r4 net-_q11-pad1_ net-_d2-pad1_ 800
+q6 net-_q1-pad2_ net-_d2-pad1_ net-_q5-pad1_ Q2N2222
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q5-pad3_ net-_d1-pad2_ 5k
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_q14-pad3_ Q2N2222
+q17 net-_q12-pad1_ net-_q16-pad1_ net-_q14-pad3_ Q2N2222
+r6 net-_q13-pad1_ net-_d2-pad1_ 1.6k
+r8 net-_q16-pad1_ net-_d2-pad1_ 1.6k
+q19 net-_q14-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222
+q22 net-_q12-pad1_ net-_q21-pad1_ net-_q19-pad3_ Q2N2222
+r10 net-_q18-pad1_ net-_d2-pad1_ 3.2k
+r12 net-_q21-pad1_ net-_d2-pad1_ 3.2k
+q24 net-_q14-pad1_ net-_q23-pad1_ net-_q24-pad3_ Q2N2222
+q27 net-_q12-pad1_ net-_q26-pad1_ net-_q24-pad3_ Q2N2222
+r14 net-_q23-pad1_ net-_d2-pad1_ 6.4k
+r17 net-_q26-pad1_ net-_d2-pad1_ 6.4k
+q30 net-_q14-pad1_ net-_q29-pad1_ net-_q30-pad3_ Q2N2222
+q33 net-_q14-pad1_ net-_q32-pad1_ net-_q30-pad3_ Q2N2222
+r18 net-_q29-pad1_ net-_d2-pad1_ 6.4k
+r20 net-_q32-pad1_ net-_d2-pad1_ 6.4k
+q35 net-_q14-pad1_ net-_q34-pad1_ net-_q35-pad3_ Q2N2222
+q38 net-_q12-pad1_ net-_q37-pad1_ net-_q35-pad3_ Q2N2222
+r22 net-_q34-pad1_ net-_d2-pad1_ 6.4k
+r23 net-_q37-pad1_ net-_d2-pad1_ 6.4k
+q40 net-_q14-pad1_ net-_q39-pad1_ net-_q40-pad3_ Q2N2222
+q43 net-_q12-pad1_ net-_q42-pad1_ net-_q40-pad3_ Q2N2222
+r24 net-_q39-pad1_ net-_d2-pad1_ 6.4k
+r25 net-_q42-pad1_ net-_d2-pad1_ 6.4k
+q44 net-_q14-pad1_ net-_d5-pad1_ net-_q44-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+d6 net-_d6-pad1_ net-_d5-pad2_ 1N4148
+r26 net-_d5-pad1_ net-_d2-pad1_ 6.4k
+r27 net-_d6-pad1_ net-_d2-pad1_ 6.4k
+q48 net-_q12-pad1_ net-_d6-pad1_ net-_q44-pad3_ Q2N2222
+d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d1-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad2_ net-_d4-pad2_ Q2N2907A
+q15 net-_q14-pad3_ net-_d1-pad2_ net-_q15-pad3_ Q2N2222
+q20 net-_q19-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2222
+q25 net-_q24-pad3_ net-_d1-pad2_ net-_q25-pad3_ Q2N2222
+q31 net-_q30-pad3_ net-_d2-pad1_ net-_q31-pad3_ Q2N2222
+q36 net-_q35-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q41 net-_q40-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q46 net-_d5-pad2_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q28 net-_q28-pad1_ net-_d1-pad2_ net-_q28-pad3_ Q2N2222
+r3 net-_q10-pad3_ net-_d1-pad2_ 10k
+r7 net-_q15-pad3_ net-_r5-pad1_ 10k
+r11 net-_q20-pad3_ net-_r11-pad2_ 10k
+r15 net-_q25-pad3_ net-_r13-pad1_ 10k
+r19 net-_q31-pad3_ net-_q28-pad1_ 5k
+r16 net-_q28-pad3_ net-_r13-pad1_ 10k
+r13 net-_r13-pad1_ net-_r11-pad2_ 5k
+r9 net-_r11-pad2_ net-_r5-pad1_ 5k
+r5 net-_r5-pad1_ net-_d1-pad2_ 5k
+r21 net-_q36-pad3_ net-_q28-pad1_ 5k
+* Control Statements
+
+.ends DAC0800_Subcircuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml
new file mode 100644
index 00000000..d4931ecc
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DAC0800/NPN.lib b/library/SubcircuitLibrary/DAC0800/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/DAC0800/PNP.lib b/library/SubcircuitLibrary/DAC0800/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/DAC0800/analysis b/library/SubcircuitLibrary/DAC0800/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/DAC0800/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit
From 0324c6b8411ca6d09fd4254e0f03ca9feef6093b Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 15:16:14 +0000
Subject: Added OP497 subcircuit
---
library/SubcircuitLibrary/OP497/D.lib | 2 +
library/SubcircuitLibrary/OP497/NPN.lib | 4 +
.../OP497/OP497_Subcircuit-cache.lib | 145 ++++
.../SubcircuitLibrary/OP497/OP497_Subcircuit.cir | 46 ++
.../OP497/OP497_Subcircuit.cir.out | 50 ++
.../SubcircuitLibrary/OP497/OP497_Subcircuit.pro | 73 ++
.../SubcircuitLibrary/OP497/OP497_Subcircuit.sch | 801 +++++++++++++++++++++
.../SubcircuitLibrary/OP497/OP497_Subcircuit.sub | 44 ++
.../OP497/OP497_Subcircuit_Previous_Values.xml | 1 +
library/SubcircuitLibrary/OP497/PNP.lib | 4 +
library/SubcircuitLibrary/OP497/analysis | 1 +
11 files changed, 1171 insertions(+)
create mode 100644 library/SubcircuitLibrary/OP497/D.lib
create mode 100644 library/SubcircuitLibrary/OP497/NPN.lib
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub
create mode 100644 library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/OP497/PNP.lib
create mode 100644 library/SubcircuitLibrary/OP497/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/OP497/D.lib b/library/SubcircuitLibrary/OP497/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/OP497/NPN.lib b/library/SubcircuitLibrary/OP497/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib b/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib
new file mode 100644
index 00000000..76ef5bfc
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib
@@ -0,0 +1,145 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir
new file mode 100644
index 00000000..3e749818
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir
@@ -0,0 +1,46 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\OP497_Subcircuit\OP497_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/04/25 21:20:34
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q12-Pad1_ 2.5k
+Q1 Net-_Q1-Pad1_ ? Net-_Q1-Pad3_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q12-Pad1_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q12-Pad1_ Net-_C3-Pad2_ eSim_NPN
+R2 Net-_R2-Pad1_ Net-_Q1-Pad3_ 2.5k
+R3 Net-_Q1-Pad1_ Net-_Q7-Pad3_ 10k
+Q6 Net-_Q5-Pad3_ Net-_Q1-Pad3_ Net-_C3-Pad2_ eSim_NPN
+Q4 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q3-Pad1_ eSim_NPN
+Q5 Net-_C2-Pad1_ Net-_C1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+R4 Net-_C1-Pad1_ Net-_C1-Pad2_ 10k
+R5 Net-_C1-Pad1_ Net-_C2-Pad1_ 10k
+Q8 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q7-Pad3_ eSim_NPN
+Q7 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_Q7-Pad3_ eSim_PNP
+Q9 Net-_Q10-Pad3_ Net-_Q14-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q10 Net-_Q1-Pad3_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q12 Net-_Q12-Pad1_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q14 Net-_Q14-Pad1_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q11 Net-_Q10-Pad3_ Net-_C3-Pad2_ Net-_C1-Pad1_ eSim_PNP
+Q13 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_C1-Pad1_ eSim_PNP
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10nF
+Q15 Net-_Q15-Pad1_ Net-_C1-Pad2_ Net-_C1-Pad1_ eSim_PNP
+Q18 Net-_C3-Pad1_ Net-_C2-Pad1_ Net-_C1-Pad1_ eSim_PNP
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+R6 Net-_C2-Pad2_ Net-_C3-Pad1_ 10k
+D1 Net-_C1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+D2 Net-_D1-Pad2_ Net-_C3-Pad2_ eSim_Diode
+Q16 Net-_Q15-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q17 Net-_C3-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad2_ eSim_NPN
+C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10nF
+Q19 Net-_Q19-Pad1_ Net-_C3-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q21 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_D3-Pad2_ eSim_PNP
+Q23 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_Q22-Pad3_ eSim_PNP
+D3 Net-_C1-Pad1_ Net-_D3-Pad2_ eSim_Diode
+Q20 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q19-Pad1_ eSim_NPN
+Q22 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q22-Pad3_ eSim_NPN
+U1 Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_Q22-Pad3_ Net-_C1-Pad1_ Net-_C3-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out
new file mode 100644
index 00000000..869eda86
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out
@@ -0,0 +1,50 @@
+* c:\fossee\esim\library\subcircuitlibrary\op497_subcircuit\op497_subcircuit.cir
+
+.include NPN.lib
+.include PNP.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q12-pad1_ 2.5k
+q1 net-_q1-pad1_ ? net-_q1-pad3_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad3_ net-_q12-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q12-pad1_ net-_c3-pad2_ Q2N2222
+r2 net-_r2-pad1_ net-_q1-pad3_ 2.5k
+r3 net-_q1-pad1_ net-_q7-pad3_ 10k
+q6 net-_q5-pad3_ net-_q1-pad3_ net-_c3-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_q3-pad1_ Q2N2222
+q5 net-_c2-pad1_ net-_c1-pad1_ net-_q5-pad3_ Q2N2222
+r4 net-_c1-pad1_ net-_c1-pad2_ 10k
+r5 net-_c1-pad1_ net-_c2-pad1_ 10k
+q8 net-_c1-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222
+q7 net-_c3-pad2_ net-_c3-pad2_ net-_q7-pad3_ Q2N2907A
+q9 net-_q10-pad3_ net-_q14-pad1_ net-_c3-pad2_ Q2N2222
+q10 net-_q1-pad3_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q12 net-_q12-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q14 net-_q14-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad3_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+q13 net-_c3-pad2_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q15 net-_q15-pad1_ net-_c1-pad2_ net-_c1-pad1_ Q2N2907A
+q18 net-_c3-pad1_ net-_c2-pad1_ net-_c1-pad1_ Q2N2907A
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r6 net-_c2-pad2_ net-_c3-pad1_ 10k
+d1 net-_c1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c3-pad2_ 1N4148
+q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+q17 net-_c3-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+c3 net-_c3-pad1_ net-_c3-pad2_ 10uf
+q19 net-_q19-pad1_ net-_c3-pad1_ net-_c3-pad2_ Q2N2222
+q21 net-_c3-pad2_ net-_c3-pad2_ net-_d3-pad2_ Q2N2907A
+q23 net-_c3-pad2_ net-_c3-pad2_ net-_q22-pad3_ Q2N2907A
+d3 net-_c1-pad1_ net-_d3-pad2_ 1N4148
+q20 net-_c1-pad1_ net-_c1-pad1_ net-_q19-pad1_ Q2N2222
+q22 net-_c1-pad1_ net-_c1-pad1_ net-_q22-pad3_ Q2N2222
+* u1 net-_r1-pad1_ net-_r2-pad1_ net-_c1-pad1_ net-_c3-pad2_ net-_q22-pad3_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch
new file mode 100644
index 00000000..4f39bc9c
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch
@@ -0,0 +1,801 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:OP497_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 679F6A14
+P 1680 3080
+F 0 "R1" H 1730 3210 50 0000 C CNN
+F 1 "2.5k" H 1730 3030 50 0000 C CNN
+F 2 "" H 1730 3060 30 0000 C CNN
+F 3 "" V 1730 3130 30 0000 C CNN
+ 1 1680 3080
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 679F6B29
+P 2200 3240
+F 0 "Q1" H 2100 3290 50 0000 R CNN
+F 1 "eSim_NPN" H 2150 3390 50 0000 R CNN
+F 2 "" H 2400 3340 29 0000 C CNN
+F 3 "" H 2200 3240 60 0000 C CNN
+ 1 2200 3240
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 679F6B86
+P 2460 3680
+F 0 "Q2" H 2360 3730 50 0000 R CNN
+F 1 "eSim_NPN" H 2410 3830 50 0000 R CNN
+F 2 "" H 2660 3780 29 0000 C CNN
+F 3 "" H 2460 3680 60 0000 C CNN
+ 1 2460 3680
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 679F6C10
+P 2970 3030
+F 0 "Q3" H 2870 3080 50 0000 R CNN
+F 1 "eSim_NPN" H 2920 3180 50 0000 R CNN
+F 2 "" H 3170 3130 29 0000 C CNN
+F 3 "" H 2970 3030 60 0000 C CNN
+ 1 2970 3030
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 679F6C82
+P 1700 3630
+F 0 "R2" H 1750 3760 50 0000 C CNN
+F 1 "2.5k" H 1750 3580 50 0000 C CNN
+F 2 "" H 1750 3610 30 0000 C CNN
+F 3 "" V 1750 3680 30 0000 C CNN
+ 1 1700 3630
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 67A21583
+P 2850 3470
+F 0 "R3" H 2900 3600 50 0000 C CNN
+F 1 "10k" H 2900 3420 50 0000 C CNN
+F 2 "" H 2900 3450 30 0000 C CNN
+F 3 "" V 2900 3520 30 0000 C CNN
+ 1 2850 3470
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 67A215FD
+P 3850 3030
+F 0 "Q6" H 3750 3080 50 0000 R CNN
+F 1 "eSim_NPN" H 3800 3180 50 0000 R CNN
+F 2 "" H 4050 3130 29 0000 C CNN
+F 3 "" H 3850 3030 60 0000 C CNN
+ 1 3850 3030
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 67A216BC
+P 3170 2530
+F 0 "Q4" H 3070 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 3120 2680 50 0000 R CNN
+F 2 "" H 3370 2630 29 0000 C CNN
+F 3 "" H 3170 2530 60 0000 C CNN
+ 1 3170 2530
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 67A21748
+P 3650 2530
+F 0 "Q5" H 3550 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 3600 2680 50 0000 R CNN
+F 2 "" H 3850 2630 29 0000 C CNN
+F 3 "" H 3650 2530 60 0000 C CNN
+ 1 3650 2530
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67A21A6B
+P 3020 1770
+F 0 "R4" H 3070 1900 50 0000 C CNN
+F 1 "10k" H 3070 1720 50 0000 C CNN
+F 2 "" H 3070 1750 30 0000 C CNN
+F 3 "" V 3070 1820 30 0000 C CNN
+ 1 3020 1770
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67A21AD4
+P 3700 1770
+F 0 "R5" H 3750 1900 50 0000 C CNN
+F 1 "10k" H 3750 1720 50 0000 C CNN
+F 2 "" H 3750 1750 30 0000 C CNN
+F 3 "" V 3750 1820 30 0000 C CNN
+ 1 3700 1770
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 67A21C5A
+P 4260 2530
+F 0 "Q8" H 4160 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 4210 2680 50 0000 R CNN
+F 2 "" H 4460 2630 29 0000 C CNN
+F 3 "" H 4260 2530 60 0000 C CNN
+ 1 4260 2530
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q7
+U 1 1 67A21DA2
+P 3970 4290
+F 0 "Q7" H 3870 4340 50 0000 R CNN
+F 1 "eSim_PNP" H 3920 4440 50 0000 R CNN
+F 2 "" H 4170 4390 29 0000 C CNN
+F 3 "" H 3970 4290 60 0000 C CNN
+ 1 3970 4290
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 67A21DFE
+P 4490 4100
+F 0 "Q9" H 4390 4150 50 0000 R CNN
+F 1 "eSim_NPN" H 4440 4250 50 0000 R CNN
+F 2 "" H 4690 4200 29 0000 C CNN
+F 3 "" H 4490 4100 60 0000 C CNN
+ 1 4490 4100
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q10
+U 1 1 67A220BA
+P 4950 3400
+F 0 "Q10" H 4850 3450 50 0000 R CNN
+F 1 "eSim_PNP" H 4900 3550 50 0000 R CNN
+F 2 "" H 5150 3500 29 0000 C CNN
+F 3 "" H 4950 3400 60 0000 C CNN
+ 1 4950 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q12
+U 1 1 67A221C2
+P 5380 3390
+F 0 "Q12" H 5280 3440 50 0000 R CNN
+F 1 "eSim_PNP" H 5330 3540 50 0000 R CNN
+F 2 "" H 5580 3490 29 0000 C CNN
+F 3 "" H 5380 3390 60 0000 C CNN
+ 1 5380 3390
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q14
+U 1 1 67A22250
+P 5810 3380
+F 0 "Q14" H 5710 3430 50 0000 R CNN
+F 1 "eSim_PNP" H 5760 3530 50 0000 R CNN
+F 2 "" H 6010 3480 29 0000 C CNN
+F 3 "" H 5810 3380 60 0000 C CNN
+ 1 5810 3380
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q11
+U 1 1 67A2261A
+P 5370 2750
+F 0 "Q11" H 5270 2800 50 0000 R CNN
+F 1 "eSim_PNP" H 5320 2900 50 0000 R CNN
+F 2 "" H 5570 2850 29 0000 C CNN
+F 3 "" H 5370 2750 60 0000 C CNN
+ 1 5370 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q13
+U 1 1 67A22620
+P 5800 2740
+F 0 "Q13" H 5700 2790 50 0000 R CNN
+F 1 "eSim_PNP" H 5750 2890 50 0000 R CNN
+F 2 "" H 6000 2840 29 0000 C CNN
+F 3 "" H 5800 2740 60 0000 C CNN
+ 1 5800 2740
+ -1 0 0 1
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 67A2272A
+P 5430 1840
+F 0 "C1" H 5455 1940 50 0000 L CNN
+F 1 "10nF" H 5455 1740 50 0000 L CNN
+F 2 "" H 5468 1690 30 0000 C CNN
+F 3 "" H 5430 1840 60 0000 C CNN
+ 1 5430 1840
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diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub
new file mode 100644
index 00000000..9b3289d6
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub
@@ -0,0 +1,44 @@
+* Subcircuit OP497_Subcircuit
+.subckt OP497_Subcircuit net-_r1-pad1_ net-_r2-pad1_ net-_c1-pad1_ net-_c3-pad2_ net-_q22-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\op497_subcircuit\op497_subcircuit.cir
+.include NPN.lib
+.include PNP.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q12-pad1_ 2.5k
+q1 net-_q1-pad1_ ? net-_q1-pad3_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad3_ net-_q12-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q12-pad1_ net-_c3-pad2_ Q2N2222
+r2 net-_r2-pad1_ net-_q1-pad3_ 2.5k
+r3 net-_q1-pad1_ net-_q7-pad3_ 10k
+q6 net-_q5-pad3_ net-_q1-pad3_ net-_c3-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_q3-pad1_ Q2N2222
+q5 net-_c2-pad1_ net-_c1-pad1_ net-_q5-pad3_ Q2N2222
+r4 net-_c1-pad1_ net-_c1-pad2_ 10k
+r5 net-_c1-pad1_ net-_c2-pad1_ 10k
+q8 net-_c1-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222
+q7 net-_c3-pad2_ net-_c3-pad2_ net-_q7-pad3_ Q2N2907A
+q9 net-_q10-pad3_ net-_q14-pad1_ net-_c3-pad2_ Q2N2222
+q10 net-_q1-pad3_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q12 net-_q12-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q14 net-_q14-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad3_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+q13 net-_c3-pad2_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q15 net-_q15-pad1_ net-_c1-pad2_ net-_c1-pad1_ Q2N2907A
+q18 net-_c3-pad1_ net-_c2-pad1_ net-_c1-pad1_ Q2N2907A
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r6 net-_c2-pad2_ net-_c3-pad1_ 10k
+d1 net-_c1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c3-pad2_ 1N4148
+q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+q17 net-_c3-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+c3 net-_c3-pad1_ net-_c3-pad2_ 10uf
+q19 net-_q19-pad1_ net-_c3-pad1_ net-_c3-pad2_ Q2N2222
+q21 net-_c3-pad2_ net-_c3-pad2_ net-_d3-pad2_ Q2N2907A
+q23 net-_c3-pad2_ net-_c3-pad2_ net-_q22-pad3_ Q2N2907A
+d3 net-_c1-pad1_ net-_d3-pad2_ 1N4148
+q20 net-_c1-pad1_ net-_c1-pad1_ net-_q19-pad1_ Q2N2222
+q22 net-_c1-pad1_ net-_c1-pad1_ net-_q22-pad3_ Q2N2222
+* Control Statements
+
+.ends OP497_Subcircuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml
new file mode 100644
index 00000000..bb0cc8b7
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/OP497/PNP.lib b/library/SubcircuitLibrary/OP497/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/OP497/analysis b/library/SubcircuitLibrary/OP497/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/OP497/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit
From 84781ea74752dd4be0ea0cb826ada4b5ef9aaa5f Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 15:24:36 +0000
Subject: Added SN7404 subcircuit
---
library/SubcircuitLibrary/SN7404/D.lib | 2 +
library/SubcircuitLibrary/SN7404/NPN.lib | 4 +
.../SN7404/SN7404_Subcircuit-cache.lib | 126 ++
.../SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir | 71 ++
.../SN7404/SN7404_Subcircuit.cir.out | 74 ++
.../SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro | 73 ++
.../SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch | 1295 ++++++++++++++++++++
.../SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub | 68 +
.../SN7404/SN7404_Subcircuit_Previous_Values.xml | 1 +
library/SubcircuitLibrary/SN7404/analysis | 1 +
10 files changed, 1715 insertions(+)
create mode 100644 library/SubcircuitLibrary/SN7404/D.lib
create mode 100644 library/SubcircuitLibrary/SN7404/NPN.lib
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub
create mode 100644 library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/SN7404/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/SN7404/D.lib b/library/SubcircuitLibrary/SN7404/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN7404/NPN.lib b/library/SubcircuitLibrary/SN7404/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib
new file mode 100644
index 00000000..0f688db8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir
new file mode 100644
index 00000000..51b43f71
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir
@@ -0,0 +1,71 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7404_Subcircuit\SN7404_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 22:45:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 4k
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D9-Pad2_ eSim_NPN
+Q19 Net-_Q19-Pad1_ Net-_Q17-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q21 Net-_Q21-Pad1_ Net-_Q19-Pad1_ Net-_D11-Pad1_ eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+Q22 Net-_D11-Pad2_ Net-_Q19-Pad3_ GNDPWR eSim_NPN
+R21 ? Net-_Q19-Pad1_ 1.6k
+R23 Net-_R1-Pad1_ Net-_Q21-Pad1_ 130
+R19 Net-_Q19-Pad3_ GNDPWR 1k
+D9 GNDPWR Net-_D9-Pad2_ eSim_Diode
+U1 Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_D3-Pad2_ Net-_D4-Pad2_ Net-_D5-Pad2_ Net-_D6-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D11-Pad2_ Net-_D12-Pad2_ PORT
+R18 Net-_R1-Pad1_ Net-_Q18-Pad2_ 4k
+Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_D10-Pad2_ eSim_NPN
+Q20 Net-_Q20-Pad1_ Net-_Q18-Pad1_ Net-_Q20-Pad3_ eSim_NPN
+Q23 Net-_Q23-Pad1_ Net-_Q20-Pad1_ Net-_D12-Pad1_ eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+Q24 Net-_D12-Pad2_ Net-_Q20-Pad3_ GNDPWR eSim_NPN
+R22 Net-_R1-Pad1_ Net-_Q20-Pad1_ 1.6k
+R24 Net-_R1-Pad1_ Net-_Q23-Pad1_ 130
+R20 Net-_Q20-Pad3_ GNDPWR 1k
+D10 GNDPWR Net-_D10-Pad2_ eSim_Diode
+R9 Net-_R1-Pad1_ Net-_Q9-Pad2_ 4k
+Q9 Net-_Q11-Pad2_ Net-_Q9-Pad2_ Net-_D5-Pad2_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_D7-Pad1_ eSim_NPN
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+Q14 Net-_D7-Pad2_ Net-_Q11-Pad3_ GNDPWR eSim_NPN
+R13 ? Net-_Q11-Pad1_ 1.6k
+R15 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+R11 Net-_Q11-Pad3_ GNDPWR 1k
+D5 GNDPWR Net-_D5-Pad2_ eSim_Diode
+R10 Net-_R1-Pad1_ Net-_Q10-Pad2_ 4k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D6-Pad2_ eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q12-Pad1_ Net-_D8-Pad1_ eSim_NPN
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+Q16 Net-_D8-Pad2_ Net-_Q12-Pad3_ GNDPWR eSim_NPN
+R14 ? Net-_Q12-Pad1_ 1.6k
+R16 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+R12 Net-_Q12-Pad3_ GNDPWR 1k
+D6 GNDPWR Net-_D6-Pad2_ eSim_Diode
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN
+Q5 Net-_Q5-Pad1_ Net-_Q3-Pad1_ Net-_D3-Pad1_ eSim_NPN
+D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode
+Q6 Net-_D3-Pad2_ Net-_Q3-Pad3_ GNDPWR eSim_NPN
+R5 ? Net-_Q3-Pad1_ 1.6k
+R7 Net-_R1-Pad1_ Net-_Q5-Pad1_ 130
+R3 Net-_Q3-Pad3_ GNDPWR 1k
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+R2 Net-_R1-Pad1_ Net-_Q2-Pad2_ 4k
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+Q7 Net-_Q7-Pad1_ Net-_Q4-Pad1_ Net-_D4-Pad1_ eSim_NPN
+D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode
+Q8 Net-_D4-Pad2_ Net-_Q4-Pad3_ GNDPWR eSim_NPN
+R6 ? Net-_Q4-Pad1_ 1.6k
+R8 Net-_R1-Pad1_ Net-_Q7-Pad1_ 130
+R4 Net-_Q4-Pad3_ GNDPWR 1k
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+
+.end
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out
new file mode 100644
index 00000000..c180e7d8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out
@@ -0,0 +1,74 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7404_subcircuit\sn7404_subcircuit.cir
+
+.include NPN.lib
+.include D.lib
+r17 net-_r1-pad1_ net-_q17-pad2_ 4k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q19-pad1_ net-_d11-pad1_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q22 net-_d11-pad2_ net-_q19-pad3_ gndpwr Q2N2222
+r21 ? net-_q19-pad1_ 1.6k
+r23 net-_r1-pad1_ net-_q21-pad1_ 130
+r19 net-_q19-pad3_ gndpwr 1k
+d9 gndpwr net-_d9-pad2_ 1N4148
+* u1 net-_d1-pad2_ net-_d2-pad2_ net-_d3-pad2_ net-_d4-pad2_ net-_d5-pad2_ net-_d6-pad2_ net-_r1-pad1_ gndpwr net-_d7-pad2_ net-_d8-pad2_ net-_d9-pad2_ net-_d10-pad2_ net-_d11-pad2_ net-_d12-pad2_ port
+r18 net-_r1-pad1_ net-_q18-pad2_ 4k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d10-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q23 net-_q23-pad1_ net-_q20-pad1_ net-_d12-pad1_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q24 net-_d12-pad2_ net-_q20-pad3_ gndpwr Q2N2222
+r22 net-_r1-pad1_ net-_q20-pad1_ 1.6k
+r24 net-_r1-pad1_ net-_q23-pad1_ 130
+r20 net-_q20-pad3_ gndpwr 1k
+d10 gndpwr net-_d10-pad2_ 1N4148
+r9 net-_r1-pad1_ net-_q9-pad2_ 4k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d5-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+r13 ? net-_q11-pad1_ 1.6k
+r15 net-_r1-pad1_ net-_q13-pad1_ 130
+r11 net-_q11-pad3_ gndpwr 1k
+d5 gndpwr net-_d5-pad2_ 1N4148
+r10 net-_r1-pad1_ net-_q10-pad2_ 4k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d6-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+r14 ? net-_q12-pad1_ 1.6k
+r16 net-_r1-pad1_ net-_q15-pad1_ 130
+r12 net-_q12-pad3_ gndpwr 1k
+d6 gndpwr net-_d6-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q3-pad1_ net-_d3-pad1_ Q2N2222
+d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148
+q6 net-_d3-pad2_ net-_q3-pad3_ gndpwr Q2N2222
+r5 ? net-_q3-pad1_ 1.6k
+r7 net-_r1-pad1_ net-_q5-pad1_ 130
+r3 net-_q3-pad3_ gndpwr 1k
+d1 gndpwr net-_d1-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q2-pad2_ 4k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q4-pad1_ net-_d4-pad1_ Q2N2222
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+q8 net-_d4-pad2_ net-_q4-pad3_ gndpwr Q2N2222
+r6 ? net-_q4-pad1_ 1.6k
+r8 net-_r1-pad1_ net-_q7-pad1_ 130
+r4 net-_q4-pad3_ gndpwr 1k
+d2 gndpwr net-_d2-pad2_ 1N4148
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch
new file mode 100644
index 00000000..68a86895
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch
@@ -0,0 +1,1295 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R17
+U 1 1 67A8D41A
+P 8310 1340
+F 0 "R17" H 8360 1470 50 0000 C CNN
+F 1 "4k" H 8360 1290 50 0000 C CNN
+F 2 "" H 8360 1320 30 0000 C CNN
+F 3 "" V 8360 1390 30 0000 C CNN
+ 1 8310 1340
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 67A8D45F
+P 8360 2130
+F 0 "Q17" H 8260 2180 50 0000 R CNN
+F 1 "eSim_NPN" H 8310 2280 50 0000 R CNN
+F 2 "" H 8560 2230 29 0000 C CNN
+F 3 "" H 8360 2130 60 0000 C CNN
+ 1 8360 2130
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 67A8D53A
+P 9060 2440
+F 0 "Q19" H 8960 2490 50 0000 R CNN
+F 1 "eSim_NPN" H 9010 2590 50 0000 R CNN
+F 2 "" H 9260 2540 29 0000 C CNN
+F 3 "" H 9060 2440 60 0000 C CNN
+ 1 9060 2440
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q21
+U 1 1 67A8D58D
+P 9670 2100
+F 0 "Q21" H 9570 2150 50 0000 R CNN
+F 1 "eSim_NPN" H 9620 2250 50 0000 R CNN
+F 2 "" H 9870 2200 29 0000 C CNN
+F 3 "" H 9670 2100 60 0000 C CNN
+ 1 9670 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D11
+U 1 1 67A8D5E0
+P 9770 2570
+F 0 "D11" H 9770 2670 50 0000 C CNN
+F 1 "eSim_Diode" H 9770 2470 50 0000 C CNN
+F 2 "" H 9770 2570 60 0000 C CNN
+F 3 "" H 9770 2570 60 0000 C CNN
+ 1 9770 2570
+ 0 1 1 0
+$EndComp
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+F 3 "" V 3560 4480 30 0000 C CNN
+ 1 3510 4430
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67A9B695
+P 2940 6720
+F 0 "R4" H 2990 6850 50 0000 C CNN
+F 1 "1k" H 2990 6670 50 0000 C CNN
+F 2 "" H 2990 6700 30 0000 C CNN
+F 3 "" V 2990 6770 30 0000 C CNN
+ 1 2940 6720
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 67A9B69B
+P 1870 6240
+F 0 "D2" H 1870 6340 50 0000 C CNN
+F 1 "eSim_Diode" H 1870 6140 50 0000 C CNN
+F 2 "" H 1870 6240 60 0000 C CNN
+F 3 "" H 1870 6240 60 0000 C CNN
+ 1 1870 6240
+ 0 -1 -1 0
+$EndComp
+$Comp
+L GNDPWR #PWR06
+U 1 1 67A9B6A1
+P 2020 6950
+F 0 "#PWR06" H 2020 6750 50 0001 C CNN
+F 1 "GNDPWR" H 2020 6820 50 0000 C CNN
+F 2 "" H 2020 6900 50 0001 C CNN
+F 3 "" H 2020 6900 50 0001 C CNN
+ 1 2020 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67A9B6BF
+P 1230 5310
+F 0 "U1" H 1280 5410 30 0000 C CNN
+F 1 "PORT" H 1230 5310 30 0000 C CNN
+F 2 "" H 1230 5310 60 0000 C CNN
+F 3 "" H 1230 5310 60 0000 C CNN
+ 2 1230 5310
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67A9B6C8
+P 4090 6010
+F 0 "U1" H 4140 6110 30 0000 C CNN
+F 1 "PORT" H 4090 6010 30 0000 C CNN
+F 2 "" H 4090 6010 60 0000 C CNN
+F 3 "" H 4090 6010 60 0000 C CNN
+ 4 4090 6010
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 67A9B8CA
+P 5900 680
+F 0 "U1" H 5950 780 30 0000 C CNN
+F 1 "PORT" H 5900 680 30 0000 C CNN
+F 2 "" H 5900 680 60 0000 C CNN
+F 3 "" H 5900 680 60 0000 C CNN
+ 7 5900 680
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 67A9B9F6
+P 6040 7590
+F 0 "U1" H 6090 7690 30 0000 C CNN
+F 1 "PORT" H 6040 7590 30 0000 C CNN
+F 2 "" H 6040 7590 60 0000 C CNN
+F 3 "" H 6040 7590 60 0000 C CNN
+ 8 6040 7590
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 8360 1540 8360 1930
+Wire Wire Line
+ 8560 2230 8710 2230
+Wire Wire Line
+ 8710 2230 8710 2440
+Wire Wire Line
+ 8710 2440 8860 2440
+Wire Wire Line
+ 9160 2240 9160 2100
+Wire Wire Line
+ 9160 2100 9470 2100
+Wire Wire Line
+ 9770 2300 9770 2420
+Wire Wire Line
+ 9770 2720 9770 3120
+Wire Wire Line
+ 9770 3870 9770 3520
+Wire Wire Line
+ 8080 3870 10010 3870
+Wire Wire Line
+ 8080 3310 8080 3870
+Connection ~ 8230 3870
+Wire Wire Line
+ 9200 3840 9200 3870
+Connection ~ 9200 3870
+Wire Wire Line
+ 9160 3320 9470 3320
+Wire Wire Line
+ 9200 3320 9200 3540
+Wire Wire Line
+ 9160 2640 9160 3320
+Connection ~ 9200 3320
+Wire Wire Line
+ 9230 1540 9230 2100
+Connection ~ 9230 2100
+Wire Wire Line
+ 9770 1550 9770 1900
+Wire Wire Line
+ 9770 1040 9770 1250
+Wire Wire Line
+ 9770 1200 8360 1200
+Wire Wire Line
+ 8360 1200 8360 1240
+Wire Wire Line
+ 8160 2230 7690 2230
+Wire Wire Line
+ 8080 3010 8080 2230
+Connection ~ 8080 2230
+Wire Wire Line
+ 10050 2930 9770 2930
+Connection ~ 9770 2930
+Wire Wire Line
+ 8360 4620 8360 5010
+Wire Wire Line
+ 8560 5310 8710 5310
+Wire Wire Line
+ 8710 5310 8710 5520
+Wire Wire Line
+ 8710 5520 8860 5520
+Wire Wire Line
+ 9160 5320 9160 5180
+Wire Wire Line
+ 9160 5180 9470 5180
+Wire Wire Line
+ 9770 5380 9770 5500
+Wire Wire Line
+ 9770 5800 9770 6200
+Wire Wire Line
+ 9770 6600 9770 7210
+Wire Wire Line
+ 8080 6950 9770 6950
+Wire Wire Line
+ 8080 6390 8080 6950
+Connection ~ 8230 6950
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+ 9200 6920 9200 6950
+Connection ~ 9200 6950
+Wire Wire Line
+ 9160 6400 9470 6400
+Wire Wire Line
+ 9200 6400 9200 6620
+Wire Wire Line
+ 9160 5720 9160 6400
+Connection ~ 9200 6400
+Wire Wire Line
+ 9230 4620 9230 5180
+Connection ~ 9230 5180
+Wire Wire Line
+ 9770 4630 9770 4980
+Wire Wire Line
+ 9770 4330 9770 4280
+Wire Wire Line
+ 8360 4280 8360 4320
+Wire Wire Line
+ 8160 5310 7690 5310
+Wire Wire Line
+ 8080 6090 8080 5310
+Connection ~ 8080 5310
+Wire Wire Line
+ 10050 6010 9770 6010
+Connection ~ 9770 6010
+Wire Wire Line
+ 5170 1540 5170 1930
+Wire Wire Line
+ 5370 2230 5520 2230
+Wire Wire Line
+ 5520 2230 5520 2440
+Wire Wire Line
+ 5520 2440 5670 2440
+Wire Wire Line
+ 5970 2240 5970 2100
+Wire Wire Line
+ 5970 2100 6280 2100
+Wire Wire Line
+ 6580 2300 6580 2420
+Wire Wire Line
+ 6580 2720 6580 3120
+Wire Wire Line
+ 6580 3870 6580 3520
+Wire Wire Line
+ 4890 3870 6820 3870
+Wire Wire Line
+ 4890 3310 4890 3870
+Connection ~ 5040 3870
+Wire Wire Line
+ 6010 3840 6010 3870
+Connection ~ 6010 3870
+Wire Wire Line
+ 5970 3320 6280 3320
+Wire Wire Line
+ 6010 3320 6010 3540
+Wire Wire Line
+ 5970 2640 5970 3320
+Connection ~ 6010 3320
+Wire Wire Line
+ 6040 1540 6040 2100
+Connection ~ 6040 2100
+Wire Wire Line
+ 6580 1550 6580 1900
+Wire Wire Line
+ 6580 1200 5170 1200
+Wire Wire Line
+ 5170 1200 5170 1240
+Wire Wire Line
+ 4970 2230 4500 2230
+Wire Wire Line
+ 4890 3010 4890 2230
+Connection ~ 4890 2230
+Wire Wire Line
+ 6860 2930 6580 2930
+Connection ~ 6580 2930
+Wire Wire Line
+ 5170 4620 5170 5010
+Wire Wire Line
+ 5370 5310 5520 5310
+Wire Wire Line
+ 5520 5310 5520 5520
+Wire Wire Line
+ 5520 5520 5670 5520
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6580 5380 6580 5500
+Wire Wire Line
+ 6580 5800 6580 6200
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 6010 6950
+Wire Wire Line
+ 5970 6400 6280 6400
+Wire Wire Line
+ 6010 6400 6010 6620
+Wire Wire Line
+ 5970 5720 5970 6400
+Connection ~ 6010 6400
+Wire Wire Line
+ 6040 4620 6040 5180
+Connection ~ 6040 5180
+Wire Wire Line
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+Wire Wire Line
+ 6580 4330 6580 4280
+Wire Wire Line
+ 5170 4280 6760 4280
+Wire Wire Line
+ 5170 4280 5170 4320
+Wire Wire Line
+ 4970 5310 4500 5310
+Wire Wire Line
+ 4890 6090 4890 5310
+Connection ~ 4890 5310
+Wire Wire Line
+ 6860 6010 6580 6010
+Connection ~ 6580 6010
+Wire Wire Line
+ 2150 1540 2150 1930
+Wire Wire Line
+ 2350 2230 2500 2230
+Wire Wire Line
+ 2500 2230 2500 2440
+Wire Wire Line
+ 2500 2440 2650 2440
+Wire Wire Line
+ 2950 2240 2950 2100
+Wire Wire Line
+ 2950 2100 3260 2100
+Wire Wire Line
+ 3560 2300 3560 2420
+Wire Wire Line
+ 3560 2720 3560 3120
+Wire Wire Line
+ 3560 3870 3560 3520
+Wire Wire Line
+ 1870 3870 3680 3870
+Wire Wire Line
+ 1870 3310 1870 3870
+Connection ~ 2020 3870
+Wire Wire Line
+ 2990 3840 2990 3870
+Connection ~ 2990 3870
+Wire Wire Line
+ 2950 3320 3260 3320
+Wire Wire Line
+ 2990 3320 2990 3540
+Wire Wire Line
+ 2950 2640 2950 3320
+Connection ~ 2990 3320
+Wire Wire Line
+ 3020 1540 3020 2100
+Connection ~ 3020 2100
+Wire Wire Line
+ 3560 1550 3560 1900
+Wire Wire Line
+ 3560 1200 2150 1200
+Wire Wire Line
+ 2150 1200 2150 1240
+Wire Wire Line
+ 1950 2230 1480 2230
+Wire Wire Line
+ 1870 3010 1870 2230
+Connection ~ 1870 2230
+Wire Wire Line
+ 3840 2930 3560 2930
+Connection ~ 3560 2930
+Wire Wire Line
+ 2150 4620 2150 5010
+Wire Wire Line
+ 2350 5310 2500 5310
+Wire Wire Line
+ 2500 5310 2500 5520
+Wire Wire Line
+ 2500 5520 2650 5520
+Wire Wire Line
+ 2950 5320 2950 5180
+Wire Wire Line
+ 2950 5180 3260 5180
+Wire Wire Line
+ 3560 5380 3560 5500
+Wire Wire Line
+ 3560 5800 3560 6200
+Wire Wire Line
+ 3560 6600 3560 7210
+Wire Wire Line
+ 1870 6950 3560 6950
+Wire Wire Line
+ 1870 6390 1870 6950
+Connection ~ 2020 6950
+Wire Wire Line
+ 2990 6920 2990 6950
+Connection ~ 2990 6950
+Wire Wire Line
+ 2950 6400 3260 6400
+Wire Wire Line
+ 2990 6400 2990 6620
+Wire Wire Line
+ 2950 5720 2950 6400
+Connection ~ 2990 6400
+Wire Wire Line
+ 3020 4620 3020 5180
+Connection ~ 3020 5180
+Wire Wire Line
+ 3560 4630 3560 4980
+Wire Wire Line
+ 3560 4330 3560 4280
+Wire Wire Line
+ 2150 4280 3800 4280
+Wire Wire Line
+ 2150 4280 2150 4320
+Wire Wire Line
+ 1950 5310 1480 5310
+Wire Wire Line
+ 1870 6090 1870 5310
+Connection ~ 1870 5310
+Wire Wire Line
+ 3840 6010 3560 6010
+Connection ~ 3560 6010
+Connection ~ 3560 1200
+Connection ~ 6580 1200
+Wire Wire Line
+ 3560 1040 9920 1040
+Connection ~ 3560 1040
+Wire Wire Line
+ 3560 1040 3560 1250
+Wire Wire Line
+ 6580 1250 6580 1040
+Wire Wire Line
+ 5900 930 5900 1040
+Connection ~ 5900 1040
+Connection ~ 6580 1040
+Connection ~ 9770 1200
+Wire Wire Line
+ 3800 4280 3800 1040
+Connection ~ 3800 1040
+Connection ~ 3560 4280
+Wire Wire Line
+ 6760 4280 6760 1040
+Connection ~ 6760 1040
+Connection ~ 6580 4280
+Wire Wire Line
+ 9920 1040 9920 4280
+Connection ~ 9770 1040
+Connection ~ 9770 4280
+Wire Wire Line
+ 3560 7210 10010 7210
+Connection ~ 3560 6950
+Connection ~ 9770 6950
+Connection ~ 6580 7210
+Connection ~ 6580 6950
+Wire Wire Line
+ 6040 7340 6040 7210
+Connection ~ 6040 7210
+Wire Wire Line
+ 3680 3870 3680 7210
+Connection ~ 3680 7210
+Connection ~ 3560 3870
+Wire Wire Line
+ 6820 3870 6820 7210
+Connection ~ 6820 7210
+Connection ~ 6580 3870
+Connection ~ 9770 7210
+Connection ~ 9920 4280
+Wire Wire Line
+ 9920 4280 8360 4280
+Wire Wire Line
+ 9230 4320 9230 4280
+Connection ~ 9230 4280
+Wire Wire Line
+ 10010 7210 10010 3870
+Connection ~ 9770 3870
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub
new file mode 100644
index 00000000..a86a8a62
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub
@@ -0,0 +1,68 @@
+* Subcircuit SN7404_Subcircuit
+.subckt SN7404_Subcircuit net-_d1-pad2_ net-_d2-pad2_ net-_d3-pad2_ net-_d4-pad2_ net-_d5-pad2_ net-_d6-pad2_ net-_r1-pad1_ gndpwr net-_d7-pad2_ net-_d8-pad2_ net-_d9-pad2_ net-_d10-pad2_ net-_d11-pad2_ net-_d12-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7404_subcircuit\sn7404_subcircuit.cir
+.include NPN.lib
+.include D.lib
+r17 net-_r1-pad1_ net-_q17-pad2_ 4k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q19-pad1_ net-_d11-pad1_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q22 net-_d11-pad2_ net-_q19-pad3_ gndpwr Q2N2222
+r21 ? net-_q19-pad1_ 1.6k
+r23 net-_r1-pad1_ net-_q21-pad1_ 130
+r19 net-_q19-pad3_ gndpwr 1k
+d9 gndpwr net-_d9-pad2_ 1N4148
+r18 net-_r1-pad1_ net-_q18-pad2_ 4k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d10-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q23 net-_q23-pad1_ net-_q20-pad1_ net-_d12-pad1_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q24 net-_d12-pad2_ net-_q20-pad3_ gndpwr Q2N2222
+r22 net-_r1-pad1_ net-_q20-pad1_ 1.6k
+r24 net-_r1-pad1_ net-_q23-pad1_ 130
+r20 net-_q20-pad3_ gndpwr 1k
+d10 gndpwr net-_d10-pad2_ 1N4148
+r9 net-_r1-pad1_ net-_q9-pad2_ 4k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d5-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+r13 ? net-_q11-pad1_ 1.6k
+r15 net-_r1-pad1_ net-_q13-pad1_ 130
+r11 net-_q11-pad3_ gndpwr 1k
+d5 gndpwr net-_d5-pad2_ 1N4148
+r10 net-_r1-pad1_ net-_q10-pad2_ 4k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d6-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+r14 ? net-_q12-pad1_ 1.6k
+r16 net-_r1-pad1_ net-_q15-pad1_ 130
+r12 net-_q12-pad3_ gndpwr 1k
+d6 gndpwr net-_d6-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q3-pad1_ net-_d3-pad1_ Q2N2222
+d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148
+q6 net-_d3-pad2_ net-_q3-pad3_ gndpwr Q2N2222
+r5 ? net-_q3-pad1_ 1.6k
+r7 net-_r1-pad1_ net-_q5-pad1_ 130
+r3 net-_q3-pad3_ gndpwr 1k
+d1 gndpwr net-_d1-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q2-pad2_ 4k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q4-pad1_ net-_d4-pad1_ Q2N2222
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+q8 net-_d4-pad2_ net-_q4-pad3_ gndpwr Q2N2222
+r6 ? net-_q4-pad1_ 1.6k
+r8 net-_r1-pad1_ net-_q7-pad1_ 130
+r4 net-_q4-pad3_ gndpwr 1k
+d2 gndpwr net-_d2-pad2_ 1N4148
+* Control Statements
+
+.ends SN7404_Subcircuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml
new file mode 100644
index 00000000..140b1ef3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7404/analysis b/library/SubcircuitLibrary/SN7404/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7404/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit
From 59d6c7860c982e67b8f9e2e5f2b33cb29806304e Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 15:28:50 +0000
Subject: Added SN7408 subcircuit
---
library/SubcircuitLibrary/SN7408/D.lib | 2 +
library/SubcircuitLibrary/SN7408/NPN.lib | 4 +
.../SN7408/SN7408_Subcircuit-cache.lib | 126 ++
.../SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir | 79 ++
.../SN7408/SN7408_Subcircuit.cir.out | 82 ++
.../SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro | 73 ++
.../SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch | 1367 ++++++++++++++++++++
.../SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub | 76 ++
.../SN7408/SN7408_Subcircuit_Previous_Values.xml | 1 +
library/SubcircuitLibrary/SN7408/analysis | 1 +
10 files changed, 1811 insertions(+)
create mode 100644 library/SubcircuitLibrary/SN7408/D.lib
create mode 100644 library/SubcircuitLibrary/SN7408/NPN.lib
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub
create mode 100644 library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/SN7408/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/SN7408/D.lib b/library/SubcircuitLibrary/SN7408/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN7408/NPN.lib b/library/SubcircuitLibrary/SN7408/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib
new file mode 100644
index 00000000..0f688db8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir
new file mode 100644
index 00000000..79fe8ae1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir
@@ -0,0 +1,79 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7408_Subcircuit\SN7408_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 22:43:20
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+R3 Net-_R1-Pad1_ Net-_D5-Pad1_ 2k
+R7 Net-_R1-Pad1_ Net-_Q11-Pad2_ 1.6k
+R11 Net-_R1-Pad1_ Net-_Q11-Pad1_ 130
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D3-Pad2_ eSim_NPN
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+D3 GNDPWR Net-_D3-Pad2_ eSim_Diode
+Q5 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+Q7 Net-_D5-Pad2_ Net-_Q5-Pad3_ GNDPWR eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+Q9 Net-_Q11-Pad2_ Net-_D5-Pad2_ Net-_Q12-Pad2_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_D7-Pad1_ eSim_NPN
+Q12 Net-_D7-Pad2_ Net-_Q12-Pad2_ GNDPWR eSim_NPN
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+R4 Net-_Q5-Pad3_ GNDPWR 800
+R8 Net-_Q12-Pad2_ GNDPWR 1k
+U1 Net-_D1-Pad2_ Net-_D3-Pad2_ Net-_D2-Pad2_ Net-_D4-Pad2_ Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D15-Pad2_ Net-_D13-Pad2_ Net-_D16-Pad2_ Net-_D14-Pad2_ PORT
+R2 Net-_R1-Pad1_ Net-_Q3-Pad2_ 4k
+R5 Net-_R1-Pad1_ Net-_D6-Pad1_ 2k
+R9 Net-_R1-Pad1_ Net-_Q10-Pad1_ 1.6k
+R12 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D4-Pad2_ eSim_NPN
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+D4 GNDPWR Net-_D4-Pad2_ eSim_Diode
+Q6 Net-_D6-Pad1_ Net-_Q3-Pad1_ Net-_Q6-Pad3_ eSim_NPN
+Q8 Net-_D6-Pad2_ Net-_Q6-Pad3_ GNDPWR eSim_NPN
+D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode
+Q10 Net-_Q10-Pad1_ Net-_D6-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q10-Pad1_ Net-_D8-Pad1_ eSim_NPN
+Q14 Net-_D8-Pad2_ Net-_Q10-Pad3_ GNDPWR eSim_NPN
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+R6 Net-_Q6-Pad3_ GNDPWR 800
+R10 Net-_Q10-Pad3_ GNDPWR 1k
+R23 Net-_R1-Pad1_ Net-_Q25-Pad2_ 4k
+R19 Net-_R1-Pad1_ Net-_D11-Pad1_ 2k
+R15 Net-_R1-Pad1_ Net-_Q15-Pad2_ 1.6k
+R13 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+Q25 Net-_Q23-Pad2_ Net-_Q25-Pad2_ Net-_D15-Pad2_ eSim_NPN
+Q26 Net-_Q23-Pad2_ Net-_Q25-Pad2_ Net-_D13-Pad2_ eSim_NPN
+D15 GNDPWR Net-_D15-Pad2_ eSim_Diode
+D13 GNDPWR Net-_D13-Pad2_ eSim_Diode
+Q23 Net-_D11-Pad1_ Net-_Q23-Pad2_ Net-_Q21-Pad2_ eSim_NPN
+Q21 Net-_D11-Pad2_ Net-_Q21-Pad2_ GNDPWR eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+Q19 Net-_Q15-Pad2_ Net-_D11-Pad2_ Net-_Q16-Pad2_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ Net-_D9-Pad1_ eSim_NPN
+Q16 Net-_D9-Pad2_ Net-_Q16-Pad2_ GNDPWR eSim_NPN
+D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode
+R20 Net-_Q21-Pad2_ GNDPWR 800
+R16 Net-_Q16-Pad2_ GNDPWR 1k
+R24 Net-_R1-Pad1_ Net-_Q27-Pad2_ 4k
+R21 Net-_R1-Pad1_ Net-_D12-Pad1_ 2k
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 1.6k
+R14 Net-_R1-Pad1_ Net-_Q17-Pad1_ 130
+Q27 Net-_Q24-Pad2_ Net-_Q27-Pad2_ Net-_D16-Pad2_ eSim_NPN
+Q28 Net-_Q24-Pad2_ Net-_Q27-Pad2_ Net-_D14-Pad2_ eSim_NPN
+D16 GNDPWR Net-_D16-Pad2_ eSim_Diode
+D14 GNDPWR Net-_D14-Pad2_ eSim_Diode
+Q24 Net-_D12-Pad1_ Net-_Q24-Pad2_ Net-_Q22-Pad2_ eSim_NPN
+Q22 Net-_D12-Pad2_ Net-_Q22-Pad2_ GNDPWR eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+Q20 Net-_Q17-Pad2_ Net-_D12-Pad2_ Net-_Q18-Pad2_ eSim_NPN
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D10-Pad1_ eSim_NPN
+Q18 Net-_D10-Pad2_ Net-_Q18-Pad2_ GNDPWR eSim_NPN
+D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode
+R22 Net-_Q22-Pad2_ GNDPWR 800
+R18 Net-_Q18-Pad2_ GNDPWR 1k
+
+.end
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out
new file mode 100644
index 00000000..d25a0635
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out
@@ -0,0 +1,82 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7408_subcircuit\sn7408_subcircuit.cir
+
+.include NPN.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_d5-pad1_ 2k
+r7 net-_r1-pad1_ net-_q11-pad2_ 1.6k
+r11 net-_r1-pad1_ net-_q11-pad1_ 130
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_d3-pad2_ Q2N2222
+d1 gndpwr net-_d1-pad2_ 1N4148
+d3 gndpwr net-_d3-pad2_ 1N4148
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q7 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+q9 net-_q11-pad2_ net-_d5-pad2_ net-_q12-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d7-pad1_ Q2N2222
+q12 net-_d7-pad2_ net-_q12-pad2_ gndpwr Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+r4 net-_q5-pad3_ gndpwr 800
+r8 net-_q12-pad2_ gndpwr 1k
+* u1 net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_ port
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r5 net-_r1-pad1_ net-_d6-pad1_ 2k
+r9 net-_r1-pad1_ net-_q10-pad1_ 1.6k
+r12 net-_r1-pad1_ net-_q13-pad1_ 130
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad2_ net-_d4-pad2_ Q2N2222
+d2 gndpwr net-_d2-pad2_ 1N4148
+d4 gndpwr net-_d4-pad2_ 1N4148
+q6 net-_d6-pad1_ net-_q3-pad1_ net-_q6-pad3_ Q2N2222
+q8 net-_d6-pad2_ net-_q6-pad3_ gndpwr Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d6-pad2_ net-_q10-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_d8-pad1_ Q2N2222
+q14 net-_d8-pad2_ net-_q10-pad3_ gndpwr Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+r6 net-_q6-pad3_ gndpwr 800
+r10 net-_q10-pad3_ gndpwr 1k
+r23 net-_r1-pad1_ net-_q25-pad2_ 4k
+r19 net-_r1-pad1_ net-_d11-pad1_ 2k
+r15 net-_r1-pad1_ net-_q15-pad2_ 1.6k
+r13 net-_r1-pad1_ net-_q15-pad1_ 130
+q25 net-_q23-pad2_ net-_q25-pad2_ net-_d15-pad2_ Q2N2222
+q26 net-_q23-pad2_ net-_q25-pad2_ net-_d13-pad2_ Q2N2222
+d15 gndpwr net-_d15-pad2_ 1N4148
+d13 gndpwr net-_d13-pad2_ 1N4148
+q23 net-_d11-pad1_ net-_q23-pad2_ net-_q21-pad2_ Q2N2222
+q21 net-_d11-pad2_ net-_q21-pad2_ gndpwr Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q19 net-_q15-pad2_ net-_d11-pad2_ net-_q16-pad2_ Q2N2222
+q15 net-_q15-pad1_ net-_q15-pad2_ net-_d9-pad1_ Q2N2222
+q16 net-_d9-pad2_ net-_q16-pad2_ gndpwr Q2N2222
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+r20 net-_q21-pad2_ gndpwr 800
+r16 net-_q16-pad2_ gndpwr 1k
+r24 net-_r1-pad1_ net-_q27-pad2_ 4k
+r21 net-_r1-pad1_ net-_d12-pad1_ 2k
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r14 net-_r1-pad1_ net-_q17-pad1_ 130
+q27 net-_q24-pad2_ net-_q27-pad2_ net-_d16-pad2_ Q2N2222
+q28 net-_q24-pad2_ net-_q27-pad2_ net-_d14-pad2_ Q2N2222
+d16 gndpwr net-_d16-pad2_ 1N4148
+d14 gndpwr net-_d14-pad2_ 1N4148
+q24 net-_d12-pad1_ net-_q24-pad2_ net-_q22-pad2_ Q2N2222
+q22 net-_d12-pad2_ net-_q22-pad2_ gndpwr Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q20 net-_q17-pad2_ net-_d12-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d10-pad1_ Q2N2222
+q18 net-_d10-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+r22 net-_q22-pad2_ gndpwr 800
+r18 net-_q18-pad2_ gndpwr 1k
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch
new file mode 100644
index 00000000..123da2b0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch
@@ -0,0 +1,1367 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7408_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 678204C6
+P 2050 1270
+F 0 "R1" H 2100 1400 50 0000 C CNN
+F 1 "4k" H 2100 1220 50 0000 C CNN
+F 2 "" H 2100 1250 30 0000 C CNN
+F 3 "" V 2100 1320 30 0000 C CNN
+ 1 2050 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 678205B9
+P 2680 1270
+F 0 "R3" H 2730 1400 50 0000 C CNN
+F 1 "2k" H 2730 1220 50 0000 C CNN
+F 2 "" H 2730 1250 30 0000 C CNN
+F 3 "" V 2730 1320 30 0000 C CNN
+ 1 2680 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 67820653
+P 3550 1270
+F 0 "R7" H 3600 1400 50 0000 C CNN
+F 1 "1.6k" H 3600 1220 50 0000 C CNN
+F 2 "" H 3600 1250 30 0000 C CNN
+F 3 "" V 3600 1320 30 0000 C CNN
+ 1 3550 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 678206FC
+P 3920 1270
+F 0 "R11" H 3970 1400 50 0000 C CNN
+F 1 "130" H 3970 1220 50 0000 C CNN
+F 2 "" H 3970 1250 30 0000 C CNN
+F 3 "" V 3970 1320 30 0000 C CNN
+ 1 3920 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 678207BE
+P 2100 2070
+F 0 "Q1" H 2000 2120 50 0000 R CNN
+F 1 "eSim_NPN" H 2050 2220 50 0000 R CNN
+F 2 "" H 2300 2170 29 0000 C CNN
+F 3 "" H 2100 2070 60 0000 C CNN
+ 1 2100 2070
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 67820877
+P 2100 2480
+F 0 "Q2" H 2000 2530 50 0000 R CNN
+F 1 "eSim_NPN" H 2050 2630 50 0000 R CNN
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diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub
new file mode 100644
index 00000000..75d406e7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub
@@ -0,0 +1,76 @@
+* Subcircuit SN7408_Subcircuit
+.subckt SN7408_Subcircuit net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7408_subcircuit\sn7408_subcircuit.cir
+.include NPN.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_d5-pad1_ 2k
+r7 net-_r1-pad1_ net-_q11-pad2_ 1.6k
+r11 net-_r1-pad1_ net-_q11-pad1_ 130
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_d3-pad2_ Q2N2222
+d1 gndpwr net-_d1-pad2_ 1N4148
+d3 gndpwr net-_d3-pad2_ 1N4148
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q7 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+q9 net-_q11-pad2_ net-_d5-pad2_ net-_q12-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d7-pad1_ Q2N2222
+q12 net-_d7-pad2_ net-_q12-pad2_ gndpwr Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+r4 net-_q5-pad3_ gndpwr 800
+r8 net-_q12-pad2_ gndpwr 1k
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r5 net-_r1-pad1_ net-_d6-pad1_ 2k
+r9 net-_r1-pad1_ net-_q10-pad1_ 1.6k
+r12 net-_r1-pad1_ net-_q13-pad1_ 130
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad2_ net-_d4-pad2_ Q2N2222
+d2 gndpwr net-_d2-pad2_ 1N4148
+d4 gndpwr net-_d4-pad2_ 1N4148
+q6 net-_d6-pad1_ net-_q3-pad1_ net-_q6-pad3_ Q2N2222
+q8 net-_d6-pad2_ net-_q6-pad3_ gndpwr Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d6-pad2_ net-_q10-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_d8-pad1_ Q2N2222
+q14 net-_d8-pad2_ net-_q10-pad3_ gndpwr Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+r6 net-_q6-pad3_ gndpwr 800
+r10 net-_q10-pad3_ gndpwr 1k
+r23 net-_r1-pad1_ net-_q25-pad2_ 4k
+r19 net-_r1-pad1_ net-_d11-pad1_ 2k
+r15 net-_r1-pad1_ net-_q15-pad2_ 1.6k
+r13 net-_r1-pad1_ net-_q15-pad1_ 130
+q25 net-_q23-pad2_ net-_q25-pad2_ net-_d15-pad2_ Q2N2222
+q26 net-_q23-pad2_ net-_q25-pad2_ net-_d13-pad2_ Q2N2222
+d15 gndpwr net-_d15-pad2_ 1N4148
+d13 gndpwr net-_d13-pad2_ 1N4148
+q23 net-_d11-pad1_ net-_q23-pad2_ net-_q21-pad2_ Q2N2222
+q21 net-_d11-pad2_ net-_q21-pad2_ gndpwr Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q19 net-_q15-pad2_ net-_d11-pad2_ net-_q16-pad2_ Q2N2222
+q15 net-_q15-pad1_ net-_q15-pad2_ net-_d9-pad1_ Q2N2222
+q16 net-_d9-pad2_ net-_q16-pad2_ gndpwr Q2N2222
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+r20 net-_q21-pad2_ gndpwr 800
+r16 net-_q16-pad2_ gndpwr 1k
+r24 net-_r1-pad1_ net-_q27-pad2_ 4k
+r21 net-_r1-pad1_ net-_d12-pad1_ 2k
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r14 net-_r1-pad1_ net-_q17-pad1_ 130
+q27 net-_q24-pad2_ net-_q27-pad2_ net-_d16-pad2_ Q2N2222
+q28 net-_q24-pad2_ net-_q27-pad2_ net-_d14-pad2_ Q2N2222
+d16 gndpwr net-_d16-pad2_ 1N4148
+d14 gndpwr net-_d14-pad2_ 1N4148
+q24 net-_d12-pad1_ net-_q24-pad2_ net-_q22-pad2_ Q2N2222
+q22 net-_d12-pad2_ net-_q22-pad2_ gndpwr Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q20 net-_q17-pad2_ net-_d12-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d10-pad1_ Q2N2222
+q18 net-_d10-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+r22 net-_q22-pad2_ gndpwr 800
+r18 net-_q18-pad2_ gndpwr 1k
+* Control Statements
+
+.ends SN7408_Subcircuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml
new file mode 100644
index 00000000..d363fca4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7408/analysis b/library/SubcircuitLibrary/SN7408/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7408/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit
From 95299d84570ebed77b6ed0638cf42b3f3b426268 Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 15:32:01 +0000
Subject: Added SN7432 subcircuit
---
library/SubcircuitLibrary/SN7432/D.lib | 2 +
library/SubcircuitLibrary/SN7432/NPN.lib | 4 +
.../SN7432/SN7432_Subcirrcuit-cache.lib | 126 ++
.../SN7432/SN7432_Subcirrcuit.cir | 87 ++
.../SN7432/SN7432_Subcirrcuit.cir.out | 90 ++
.../SN7432/SN7432_Subcirrcuit.pro | 73 +
.../SN7432/SN7432_Subcirrcuit.sch | 1551 ++++++++++++++++++++
.../SN7432/SN7432_Subcirrcuit.sub | 84 ++
.../SN7432/SN7432_Subcirrcuit_Previous_Values.xml | 1 +
library/SubcircuitLibrary/SN7432/analysis | 1 +
10 files changed, 2019 insertions(+)
create mode 100644 library/SubcircuitLibrary/SN7432/D.lib
create mode 100644 library/SubcircuitLibrary/SN7432/NPN.lib
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub
create mode 100644 library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/SN7432/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/SN7432/D.lib b/library/SubcircuitLibrary/SN7432/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN7432/NPN.lib b/library/SubcircuitLibrary/SN7432/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib
new file mode 100644
index 00000000..0f688db8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir
new file mode 100644
index 00000000..71880368
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir
@@ -0,0 +1,87 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7432_Subcirrcuit\SN7432_Subcirrcuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/25 23:23:51
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_D4-Pad2_ eSim_NPN
+Q7 Net-_D6-Pad1_ Net-_Q3-Pad1_ Net-_Q10-Pad2_ eSim_NPN
+Q8 Net-_D6-Pad1_ Net-_Q4-Pad1_ Net-_Q10-Pad2_ eSim_NPN
+D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode
+R2 Net-_R1-Pad1_ Net-_Q3-Pad2_ 4k
+R4 Net-_R1-Pad1_ Net-_Q4-Pad2_ 2k
+R7 Net-_R1-Pad1_ Net-_D6-Pad1_ 2.5k
+Q10 Net-_D6-Pad2_ Net-_Q10-Pad2_ GNDPWR eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_D6-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q12-Pad1_ Net-_D8-Pad1_ eSim_NPN
+R11 Net-_R1-Pad1_ Net-_Q12-Pad1_ 1.6k
+R14 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+D4 GNDPWR Net-_D4-Pad2_ eSim_Diode
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+R8 Net-_Q10-Pad2_ GNDPWR 1k
+R12 Net-_Q12-Pad3_ GNDPWR 1k
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+Q16 Net-_D8-Pad2_ Net-_Q12-Pad3_ GNDPWR eSim_NPN
+Q29 Net-_Q25-Pad2_ Net-_Q29-Pad2_ Net-_D15-Pad2_ eSim_NPN
+Q30 Net-_Q26-Pad2_ Net-_Q30-Pad2_ Net-_D13-Pad2_ eSim_NPN
+Q25 Net-_D11-Pad1_ Net-_Q25-Pad2_ Net-_Q23-Pad2_ eSim_NPN
+Q26 Net-_D11-Pad1_ Net-_Q26-Pad2_ Net-_Q23-Pad2_ eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+R27 Net-_R1-Pad1_ Net-_Q29-Pad2_ 4k
+R25 Net-_R1-Pad1_ Net-_Q30-Pad2_ 2k
+R22 Net-_R1-Pad1_ Net-_D11-Pad1_ 2.5k
+Q23 Net-_D11-Pad2_ Net-_Q23-Pad2_ GNDPWR eSim_NPN
+Q21 Net-_Q17-Pad2_ Net-_D11-Pad2_ Net-_Q18-Pad2_ eSim_NPN
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D9-Pad1_ eSim_NPN
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 1.6k
+R15 Net-_R1-Pad1_ Net-_Q17-Pad1_ 130
+D13 GNDPWR Net-_D13-Pad2_ eSim_Diode
+D15 GNDPWR Net-_D15-Pad2_ eSim_Diode
+R21 Net-_Q23-Pad2_ GNDPWR 1k
+R18 Net-_Q18-Pad2_ GNDPWR 1k
+D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode
+Q18 Net-_D9-Pad2_ Net-_Q18-Pad2_ GNDPWR eSim_NPN
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_D3-Pad2_ eSim_NPN
+Q5 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+Q6 Net-_D5-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+R3 Net-_R1-Pad1_ Net-_Q2-Pad2_ 2k
+R5 Net-_R1-Pad1_ Net-_D5-Pad1_ 2.5k
+Q9 Net-_D5-Pad2_ Net-_Q5-Pad3_ GNDPWR eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_D5-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_D7-Pad1_ eSim_NPN
+R9 Net-_R1-Pad1_ Net-_Q11-Pad1_ 1.6k
+R13 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+D3 GNDPWR Net-_D3-Pad2_ eSim_Diode
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+R6 Net-_Q5-Pad3_ GNDPWR 1k
+R10 Net-_Q11-Pad3_ GNDPWR 1k
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+Q14 Net-_D7-Pad2_ Net-_Q11-Pad3_ GNDPWR eSim_NPN
+Q31 Net-_Q27-Pad2_ Net-_Q31-Pad2_ Net-_D16-Pad2_ eSim_NPN
+Q32 Net-_Q28-Pad2_ Net-_Q32-Pad2_ Net-_D14-Pad2_ eSim_NPN
+Q27 Net-_D12-Pad1_ Net-_Q27-Pad2_ Net-_Q24-Pad2_ eSim_NPN
+Q28 Net-_D12-Pad1_ Net-_Q28-Pad2_ Net-_Q24-Pad2_ eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+R28 Net-_R1-Pad1_ Net-_Q31-Pad2_ 4k
+R26 Net-_R1-Pad1_ Net-_Q32-Pad2_ 2k
+R24 Net-_R1-Pad1_ Net-_D12-Pad1_ 2.5k
+Q24 Net-_D12-Pad2_ Net-_Q24-Pad2_ GNDPWR eSim_NPN
+Q22 Net-_Q19-Pad2_ Net-_D12-Pad2_ Net-_Q20-Pad2_ eSim_NPN
+Q19 Net-_Q19-Pad1_ Net-_Q19-Pad2_ Net-_D10-Pad1_ eSim_NPN
+R19 Net-_R1-Pad1_ Net-_Q19-Pad2_ 1.6k
+R16 Net-_R1-Pad1_ Net-_Q19-Pad1_ 130
+D14 GNDPWR Net-_D14-Pad2_ eSim_Diode
+D16 GNDPWR Net-_D16-Pad2_ eSim_Diode
+R23 Net-_Q24-Pad2_ GNDPWR 1k
+R20 Net-_Q20-Pad2_ GNDPWR 1k
+D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode
+Q20 Net-_D10-Pad2_ Net-_Q20-Pad2_ GNDPWR eSim_NPN
+U1 Net-_D1-Pad2_ Net-_D3-Pad2_ Net-_D2-Pad2_ Net-_D4-Pad2_ Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D15-Pad2_ Net-_D13-Pad2_ Net-_D16-Pad2_ Net-_D14-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out
new file mode 100644
index 00000000..cb10dab9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out
@@ -0,0 +1,90 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7432_subcirrcuit\sn7432_subcirrcuit.cir
+
+.include NPN.lib
+.include D.lib
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222
+q7 net-_d6-pad1_ net-_q3-pad1_ net-_q10-pad2_ Q2N2222
+q8 net-_d6-pad1_ net-_q4-pad1_ net-_q10-pad2_ Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r4 net-_r1-pad1_ net-_q4-pad2_ 2k
+r7 net-_r1-pad1_ net-_d6-pad1_ 2.5k
+q10 net-_d6-pad2_ net-_q10-pad2_ gndpwr Q2N2222
+q12 net-_q12-pad1_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+r11 net-_r1-pad1_ net-_q12-pad1_ 1.6k
+r14 net-_r1-pad1_ net-_q15-pad1_ 130
+d4 gndpwr net-_d4-pad2_ 1N4148
+d2 gndpwr net-_d2-pad2_ 1N4148
+r8 net-_q10-pad2_ gndpwr 1k
+r12 net-_q12-pad3_ gndpwr 1k
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+q29 net-_q25-pad2_ net-_q29-pad2_ net-_d15-pad2_ Q2N2222
+q30 net-_q26-pad2_ net-_q30-pad2_ net-_d13-pad2_ Q2N2222
+q25 net-_d11-pad1_ net-_q25-pad2_ net-_q23-pad2_ Q2N2222
+q26 net-_d11-pad1_ net-_q26-pad2_ net-_q23-pad2_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+r27 net-_r1-pad1_ net-_q29-pad2_ 4k
+r25 net-_r1-pad1_ net-_q30-pad2_ 2k
+r22 net-_r1-pad1_ net-_d11-pad1_ 2.5k
+q23 net-_d11-pad2_ net-_q23-pad2_ gndpwr Q2N2222
+q21 net-_q17-pad2_ net-_d11-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad1_ Q2N2222
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r15 net-_r1-pad1_ net-_q17-pad1_ 130
+d13 gndpwr net-_d13-pad2_ 1N4148
+d15 gndpwr net-_d15-pad2_ 1N4148
+r21 net-_q23-pad2_ gndpwr 1k
+r18 net-_q18-pad2_ gndpwr 1k
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+q18 net-_d9-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d3-pad2_ Q2N2222
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q6 net-_d5-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_q2-pad2_ 2k
+r5 net-_r1-pad1_ net-_d5-pad1_ 2.5k
+q9 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+q11 net-_q11-pad1_ net-_d5-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+r9 net-_r1-pad1_ net-_q11-pad1_ 1.6k
+r13 net-_r1-pad1_ net-_q13-pad1_ 130
+d3 gndpwr net-_d3-pad2_ 1N4148
+d1 gndpwr net-_d1-pad2_ 1N4148
+r6 net-_q5-pad3_ gndpwr 1k
+r10 net-_q11-pad3_ gndpwr 1k
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+q31 net-_q27-pad2_ net-_q31-pad2_ net-_d16-pad2_ Q2N2222
+q32 net-_q28-pad2_ net-_q32-pad2_ net-_d14-pad2_ Q2N2222
+q27 net-_d12-pad1_ net-_q27-pad2_ net-_q24-pad2_ Q2N2222
+q28 net-_d12-pad1_ net-_q28-pad2_ net-_q24-pad2_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+r28 net-_r1-pad1_ net-_q31-pad2_ 4k
+r26 net-_r1-pad1_ net-_q32-pad2_ 2k
+r24 net-_r1-pad1_ net-_d12-pad1_ 2.5k
+q24 net-_d12-pad2_ net-_q24-pad2_ gndpwr Q2N2222
+q22 net-_q19-pad2_ net-_d12-pad2_ net-_q20-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q19-pad2_ net-_d10-pad1_ Q2N2222
+r19 net-_r1-pad1_ net-_q19-pad2_ 1.6k
+r16 net-_r1-pad1_ net-_q19-pad1_ 130
+d14 gndpwr net-_d14-pad2_ 1N4148
+d16 gndpwr net-_d16-pad2_ 1N4148
+r23 net-_q24-pad2_ gndpwr 1k
+r20 net-_q20-pad2_ gndpwr 1k
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+q20 net-_d10-pad2_ net-_q20-pad2_ gndpwr Q2N2222
+* u1 net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
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diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch
new file mode 100644
index 00000000..50ece14b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch
@@ -0,0 +1,1551 @@
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+LIBS:memory
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+LIBS:microcontrollers
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+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7432_Subcirrcuit-cache
+EELAYER 25 0
+EELAYER END
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+Wire Wire Line
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+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub
new file mode 100644
index 00000000..1d1d12c9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub
@@ -0,0 +1,84 @@
+* Subcircuit SN7432_Subcirrcuit
+.subckt SN7432_Subcirrcuit net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7432_subcirrcuit\sn7432_subcirrcuit.cir
+.include NPN.lib
+.include D.lib
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222
+q7 net-_d6-pad1_ net-_q3-pad1_ net-_q10-pad2_ Q2N2222
+q8 net-_d6-pad1_ net-_q4-pad1_ net-_q10-pad2_ Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r4 net-_r1-pad1_ net-_q4-pad2_ 2k
+r7 net-_r1-pad1_ net-_d6-pad1_ 2.5k
+q10 net-_d6-pad2_ net-_q10-pad2_ gndpwr Q2N2222
+q12 net-_q12-pad1_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+r11 net-_r1-pad1_ net-_q12-pad1_ 1.6k
+r14 net-_r1-pad1_ net-_q15-pad1_ 130
+d4 gndpwr net-_d4-pad2_ 1N4148
+d2 gndpwr net-_d2-pad2_ 1N4148
+r8 net-_q10-pad2_ gndpwr 1k
+r12 net-_q12-pad3_ gndpwr 1k
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+q29 net-_q25-pad2_ net-_q29-pad2_ net-_d15-pad2_ Q2N2222
+q30 net-_q26-pad2_ net-_q30-pad2_ net-_d13-pad2_ Q2N2222
+q25 net-_d11-pad1_ net-_q25-pad2_ net-_q23-pad2_ Q2N2222
+q26 net-_d11-pad1_ net-_q26-pad2_ net-_q23-pad2_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+r27 net-_r1-pad1_ net-_q29-pad2_ 4k
+r25 net-_r1-pad1_ net-_q30-pad2_ 2k
+r22 net-_r1-pad1_ net-_d11-pad1_ 2.5k
+q23 net-_d11-pad2_ net-_q23-pad2_ gndpwr Q2N2222
+q21 net-_q17-pad2_ net-_d11-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad1_ Q2N2222
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r15 net-_r1-pad1_ net-_q17-pad1_ 130
+d13 gndpwr net-_d13-pad2_ 1N4148
+d15 gndpwr net-_d15-pad2_ 1N4148
+r21 net-_q23-pad2_ gndpwr 1k
+r18 net-_q18-pad2_ gndpwr 1k
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+q18 net-_d9-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d3-pad2_ Q2N2222
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q6 net-_d5-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_q2-pad2_ 2k
+r5 net-_r1-pad1_ net-_d5-pad1_ 2.5k
+q9 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+q11 net-_q11-pad1_ net-_d5-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+r9 net-_r1-pad1_ net-_q11-pad1_ 1.6k
+r13 net-_r1-pad1_ net-_q13-pad1_ 130
+d3 gndpwr net-_d3-pad2_ 1N4148
+d1 gndpwr net-_d1-pad2_ 1N4148
+r6 net-_q5-pad3_ gndpwr 1k
+r10 net-_q11-pad3_ gndpwr 1k
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+q31 net-_q27-pad2_ net-_q31-pad2_ net-_d16-pad2_ Q2N2222
+q32 net-_q28-pad2_ net-_q32-pad2_ net-_d14-pad2_ Q2N2222
+q27 net-_d12-pad1_ net-_q27-pad2_ net-_q24-pad2_ Q2N2222
+q28 net-_d12-pad1_ net-_q28-pad2_ net-_q24-pad2_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+r28 net-_r1-pad1_ net-_q31-pad2_ 4k
+r26 net-_r1-pad1_ net-_q32-pad2_ 2k
+r24 net-_r1-pad1_ net-_d12-pad1_ 2.5k
+q24 net-_d12-pad2_ net-_q24-pad2_ gndpwr Q2N2222
+q22 net-_q19-pad2_ net-_d12-pad2_ net-_q20-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q19-pad2_ net-_d10-pad1_ Q2N2222
+r19 net-_r1-pad1_ net-_q19-pad2_ 1.6k
+r16 net-_r1-pad1_ net-_q19-pad1_ 130
+d14 gndpwr net-_d14-pad2_ 1N4148
+d16 gndpwr net-_d16-pad2_ 1N4148
+r23 net-_q24-pad2_ gndpwr 1k
+r20 net-_q20-pad2_ gndpwr 1k
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+q20 net-_d10-pad2_ net-_q20-pad2_ gndpwr Q2N2222
+* Control Statements
+
+.ends SN7432_Subcirrcuit
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml
new file mode 100644
index 00000000..40f426fc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7432/analysis b/library/SubcircuitLibrary/SN7432/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7432/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit
From 9c5e5f7676df9284cef1ec408b0b61faea7811a8 Mon Sep 17 00:00:00 2001
From: Manimaran K
Date: Mon, 24 Feb 2025 15:35:07 +0000
Subject: Added SN74LS11 subcircuit
---
library/SubcircuitLibrary/SN74LS11/D.lib | 2 +
library/SubcircuitLibrary/SN74LS11/NPN.lib | 4 +
.../SN74LS11/Subcircuit_SN74LS11-cache.lib | 164 +++
.../SN74LS11/Subcircuit_SN74LS11.cir | 77 ++
.../SN74LS11/Subcircuit_SN74LS11.cir.out | 143 +++
.../SN74LS11/Subcircuit_SN74LS11.pro | 73 ++
.../SN74LS11/Subcircuit_SN74LS11.sch | 1351 ++++++++++++++++++++
.../SN74LS11/Subcircuit_SN74LS11.sub | 137 ++
.../Subcircuit_SN74LS11_Previous_Values.xml | 1 +
library/SubcircuitLibrary/SN74LS11/analysis | 1 +
10 files changed, 1953 insertions(+)
create mode 100644 library/SubcircuitLibrary/SN74LS11/D.lib
create mode 100644 library/SubcircuitLibrary/SN74LS11/NPN.lib
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub
create mode 100644 library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml
create mode 100644 library/SubcircuitLibrary/SN74LS11/analysis
(limited to 'library/SubcircuitLibrary')
diff --git a/library/SubcircuitLibrary/SN74LS11/D.lib b/library/SubcircuitLibrary/SN74LS11/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN74LS11/NPN.lib b/library/SubcircuitLibrary/SN74LS11/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib
new file mode 100644
index 00000000..0d1f2ae8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib
@@ -0,0 +1,164 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir
new file mode 100644
index 00000000..e049f6b4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir
@@ -0,0 +1,77 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\Subcircuit_SN74LS11\Subcircuit_SN74LS11.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 19:11:48
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 20k
+R2 Net-_R1-Pad1_ Net-_Q1-Pad1_ 10k
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad1_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+R4 Net-_R1-Pad1_ Net-_Q2-Pad1_ 8k
+R7 Net-_R1-Pad1_ Net-_Q4-Pad1_ 120
+U2 GNDPWR Net-_U1-Pad1_ zener
+U3 GNDPWR Net-_U1-Pad2_ zener
+U4 GNDPWR Net-_U1-Pad3_ zener
+U7 Net-_Q1-Pad2_ Net-_U1-Pad3_ zener
+U6 Net-_Q1-Pad2_ Net-_U1-Pad2_ zener
+D1 Net-_D1-Pad1_ GNDPWR eSim_Diode
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+R3 Net-_C1-Pad1_ Net-_Q3-Pad2_ 1.5k
+R5 Net-_C1-Pad1_ Net-_Q3-Pad1_ 3k
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ GNDPWR eSim_NPN
+Q6 Net-_C1-Pad2_ Net-_C1-Pad1_ GNDPWR eSim_NPN
+U9 Net-_R6-Pad2_ Net-_Q2-Pad1_ zener
+R6 Net-_C1-Pad2_ Net-_R6-Pad2_ 5k
+Q5 Net-_Q4-Pad1_ Net-_Q4-Pad3_ Net-_C1-Pad2_ eSim_NPN
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_C1-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_C2-Pad2_ Net-_C3-Pad2_ PORT
+U5 Net-_Q1-Pad2_ Net-_U1-Pad1_ zener
+R15 Net-_R1-Pad1_ Net-_Q13-Pad2_ 20k
+R16 Net-_R1-Pad1_ Net-_Q13-Pad1_ 10k
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_D3-Pad1_ eSim_NPN
+Q14 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_C3-Pad1_ eSim_NPN
+Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_Q16-Pad3_ eSim_NPN
+R18 Net-_R1-Pad1_ Net-_Q14-Pad1_ 8k
+R21 Net-_R1-Pad1_ Net-_Q16-Pad1_ 120
+U16 GNDPWR Net-_U1-Pad10_ zener
+U17 GNDPWR Net-_U1-Pad11_ zener
+U18 GNDPWR Net-_U1-Pad12_ zener
+U21 Net-_Q13-Pad2_ Net-_U1-Pad12_ zener
+U20 Net-_Q13-Pad2_ Net-_U1-Pad11_ zener
+D3 Net-_D3-Pad1_ GNDPWR eSim_Diode
+C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10pF
+R17 Net-_C3-Pad1_ Net-_Q15-Pad2_ 1.5k
+R19 Net-_C3-Pad1_ Net-_Q15-Pad1_ 3k
+Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ GNDPWR eSim_NPN
+Q18 Net-_C3-Pad2_ Net-_C3-Pad1_ GNDPWR eSim_NPN
+U22 Net-_R20-Pad2_ Net-_Q14-Pad1_ zener
+R20 Net-_C3-Pad2_ Net-_R20-Pad2_ 5k
+Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_C3-Pad2_ eSim_NPN
+U19 Net-_Q13-Pad2_ Net-_U1-Pad10_ zener
+R8 Net-_R1-Pad1_ Net-_Q7-Pad2_ 20k
+R9 Net-_R1-Pad1_ Net-_Q7-Pad1_ 10k
+Q7 Net-_Q7-Pad1_ Net-_Q7-Pad2_ Net-_D2-Pad1_ eSim_NPN
+Q8 Net-_Q10-Pad2_ Net-_Q7-Pad1_ Net-_C2-Pad1_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R11 Net-_R1-Pad1_ Net-_Q10-Pad2_ 8k
+R14 Net-_R1-Pad1_ Net-_Q10-Pad1_ 120
+U8 GNDPWR Net-_U1-Pad4_ zener
+U10 GNDPWR Net-_U1-Pad5_ zener
+U11 GNDPWR Net-_U1-Pad6_ zener
+U14 Net-_Q7-Pad2_ Net-_U1-Pad6_ zener
+U13 Net-_Q7-Pad2_ Net-_U1-Pad5_ zener
+D2 Net-_D2-Pad1_ GNDPWR eSim_Diode
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+R10 Net-_C2-Pad1_ Net-_Q9-Pad2_ 1.5k
+R12 Net-_C2-Pad1_ Net-_Q9-Pad1_ 3k
+Q9 Net-_Q9-Pad1_ Net-_Q9-Pad2_ GNDPWR eSim_NPN
+Q12 Net-_C2-Pad2_ Net-_C2-Pad1_ GNDPWR eSim_NPN
+U15 Net-_R13-Pad2_ Net-_Q10-Pad2_ zener
+R13 Net-_C2-Pad2_ Net-_R13-Pad2_ 5k
+Q11 Net-_Q10-Pad1_ Net-_Q10-Pad3_ Net-_C2-Pad2_ eSim_NPN
+U12 Net-_Q7-Pad2_ Net-_U1-Pad4_ zener
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out
new file mode 100644
index 00000000..a8250b0d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out
@@ -0,0 +1,143 @@
+* c:\fossee\esim\library\subcircuitlibrary\subcircuit_sn74ls11\subcircuit_sn74ls11.cir
+
+.include D.lib
+.include NPN.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 20k
+r2 net-_r1-pad1_ net-_q1-pad1_ 10k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+r4 net-_r1-pad1_ net-_q2-pad1_ 8k
+r7 net-_r1-pad1_ net-_q4-pad1_ 120
+* u2 gndpwr net-_u1-pad1_ zener
+* u3 gndpwr net-_u1-pad2_ zener
+* u4 gndpwr net-_u1-pad3_ zener
+* u7 net-_q1-pad2_ net-_u1-pad3_ zener
+* u6 net-_q1-pad2_ net-_u1-pad2_ zener
+d1 net-_d1-pad1_ gndpwr 1N4148
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r3 net-_c1-pad1_ net-_q3-pad2_ 1.5k
+r5 net-_c1-pad1_ net-_q3-pad1_ 3k
+q3 net-_q3-pad1_ net-_q3-pad2_ gndpwr Q2N2222
+q6 net-_c1-pad2_ net-_c1-pad1_ gndpwr Q2N2222
+* u9 net-_r6-pad2_ net-_q2-pad1_ zener
+r6 net-_c1-pad2_ net-_r6-pad2_ 5k
+q5 net-_q4-pad1_ net-_q4-pad3_ net-_c1-pad2_ Q2N2222
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_r1-pad1_ gndpwr net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_c2-pad2_ net-_c3-pad2_ port
+* u5 net-_q1-pad2_ net-_u1-pad1_ zener
+r15 net-_r1-pad1_ net-_q13-pad2_ 20k
+r16 net-_r1-pad1_ net-_q13-pad1_ 10k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d3-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_c3-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_q16-pad3_ Q2N2222
+r18 net-_r1-pad1_ net-_q14-pad1_ 8k
+r21 net-_r1-pad1_ net-_q16-pad1_ 120
+* u16 gndpwr net-_u1-pad10_ zener
+* u17 gndpwr net-_u1-pad11_ zener
+* u18 gndpwr net-_u1-pad12_ zener
+* u21 net-_q13-pad2_ net-_u1-pad12_ zener
+* u20 net-_q13-pad2_ net-_u1-pad11_ zener
+d3 net-_d3-pad1_ gndpwr 1N4148
+c3 net-_c3-pad1_ net-_c3-pad2_ 10pf
+r17 net-_c3-pad1_ net-_q15-pad2_ 1.5k
+r19 net-_c3-pad1_ net-_q15-pad1_ 3k
+q15 net-_q15-pad1_ net-_q15-pad2_ gndpwr Q2N2222
+q18 net-_c3-pad2_ net-_c3-pad1_ gndpwr Q2N2222
+* u22 net-_r20-pad2_ net-_q14-pad1_ zener
+r20 net-_c3-pad2_ net-_r20-pad2_ 5k
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_c3-pad2_ Q2N2222
+* u19 net-_q13-pad2_ net-_u1-pad10_ zener
+r8 net-_r1-pad1_ net-_q7-pad2_ 20k
+r9 net-_r1-pad1_ net-_q7-pad1_ 10k
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d2-pad1_ Q2N2222
+q8 net-_q10-pad2_ net-_q7-pad1_ net-_c2-pad1_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r11 net-_r1-pad1_ net-_q10-pad2_ 8k
+r14 net-_r1-pad1_ net-_q10-pad1_ 120
+* u8 gndpwr net-_u1-pad4_ zener
+* u10 gndpwr net-_u1-pad5_ zener
+* u11 gndpwr net-_u1-pad6_ zener
+* u14 net-_q7-pad2_ net-_u1-pad6_ zener
+* u13 net-_q7-pad2_ net-_u1-pad5_ zener
+d2 net-_d2-pad1_ gndpwr 1N4148
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r10 net-_c2-pad1_ net-_q9-pad2_ 1.5k
+r12 net-_c2-pad1_ net-_q9-pad1_ 3k
+q9 net-_q9-pad1_ net-_q9-pad2_ gndpwr Q2N2222
+q12 net-_c2-pad2_ net-_c2-pad1_ gndpwr Q2N2222
+* u15 net-_r13-pad2_ net-_q10-pad2_ zener
+r13 net-_c2-pad2_ net-_r13-pad2_ 5k
+q11 net-_q10-pad1_ net-_q10-pad3_ net-_c2-pad2_ Q2N2222
+* u12 net-_q7-pad2_ net-_u1-pad4_ zener
+a1 gndpwr net-_u1-pad1_ u2
+a2 gndpwr net-_u1-pad2_ u3
+a3 gndpwr net-_u1-pad3_ u4
+a4 net-_q1-pad2_ net-_u1-pad3_ u7
+a5 net-_q1-pad2_ net-_u1-pad2_ u6
+a6 net-_r6-pad2_ net-_q2-pad1_ u9
+a7 net-_q1-pad2_ net-_u1-pad1_ u5
+a8 gndpwr net-_u1-pad10_ u16
+a9 gndpwr net-_u1-pad11_ u17
+a10 gndpwr net-_u1-pad12_ u18
+a11 net-_q13-pad2_ net-_u1-pad12_ u21
+a12 net-_q13-pad2_ net-_u1-pad11_ u20
+a13 net-_r20-pad2_ net-_q14-pad1_ u22
+a14 net-_q13-pad2_ net-_u1-pad10_ u19
+a15 gndpwr net-_u1-pad4_ u8
+a16 gndpwr net-_u1-pad5_ u10
+a17 gndpwr net-_u1-pad6_ u11
+a18 net-_q7-pad2_ net-_u1-pad6_ u14
+a19 net-_q7-pad2_ net-_u1-pad5_ u13
+a20 net-_r13-pad2_ net-_q10-pad2_ u15
+a21 net-_q7-pad2_ net-_u1-pad4_ u12
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u21 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u20 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u22 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch
new file mode 100644
index 00000000..0247342b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch
@@ -0,0 +1,1351 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 67A9FAFF
+P 1980 1120
+F 0 "R1" H 2030 1250 50 0000 C CNN
+F 1 "20k" H 2030 1070 50 0000 C CNN
+F 2 "" H 2030 1100 30 0000 C CNN
+F 3 "" V 2030 1170 30 0000 C CNN
+ 1 1980 1120
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R2
+U 1 1 67A9FB42
+P 2500 1120
+F 0 "R2" H 2550 1250 50 0000 C CNN
+F 1 "10k" H 2550 1070 50 0000 C CNN
+F 2 "" H 2550 1100 30 0000 C CNN
+F 3 "" V 2550 1170 30 0000 C CNN
+ 1 2500 1120
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 67A9FB67
+P 2450 2560
+F 0 "Q1" H 2350 2610 50 0000 R CNN
+F 1 "eSim_NPN" H 2400 2710 50 0000 R CNN
+F 2 "" H 2650 2660 29 0000 C CNN
+F 3 "" H 2450 2560 60 0000 C CNN
+ 1 2450 2560
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 67A9FBA3
+P 2830 2140
+F 0 "Q2" H 2730 2190 50 0000 R CNN
+F 1 "eSim_NPN" H 2780 2290 50 0000 R CNN
+F 2 "" H 3030 2240 29 0000 C CNN
+F 3 "" H 2830 2140 60 0000 C CNN
+ 1 2830 2140
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 67A9FBD9
+P 3500 1690
+F 0 "Q4" H 3400 1740 50 0000 R CNN
+F 1 "eSim_NPN" H 3450 1840 50 0000 R CNN
+F 2 "" H 3700 1790 29 0000 C CNN
+F 3 "" H 3500 1690 60 0000 C CNN
+ 1 3500 1690
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67A9FC1E
+P 3140 1130
+F 0 "R4" H 3190 1260 50 0000 C CNN
+F 1 "8k" H 3190 1080 50 0000 C CNN
+F 2 "" H 3190 1110 30 0000 C CNN
+F 3 "" V 3190 1180 30 0000 C CNN
+ 1 3140 1130
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 67A9FC6A
+P 4310 1130
+F 0 "R7" H 4360 1260 50 0000 C CNN
+F 1 "120" H 4360 1080 50 0000 C CNN
+F 2 "" H 4360 1110 30 0000 C CNN
+F 3 "" V 4360 1180 30 0000 C CNN
+ 1 4310 1130
+ 0 1 1 0
+$EndComp
+$Comp
+L zener U2
+U 1 1 67A9FCCE
+P 1020 3170
+F 0 "U2" H 970 3070 60 0000 C CNN
+F 1 "zener" H 1020 3270 60 0000 C CNN
+F 2 "" H 1070 3170 60 0000 C CNN
+F 3 "" H 1070 3170 60 0000 C CNN
+ 1 1020 3170
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U3
+U 1 1 67A9FD63
+P 1290 3170
+F 0 "U3" H 1240 3070 60 0000 C CNN
+F 1 "zener" H 1290 3270 60 0000 C CNN
+F 2 "" H 1340 3170 60 0000 C CNN
+F 3 "" H 1340 3170 60 0000 C CNN
+ 1 1290 3170
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U4
+U 1 1 67A9FDB0
+P 1500 3170
+F 0 "U4" H 1450 3070 60 0000 C CNN
+F 1 "zener" H 1500 3270 60 0000 C CNN
+F 2 "" H 1550 3170 60 0000 C CNN
+F 3 "" H 1550 3170 60 0000 C CNN
+ 1 1500 3170
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U7
+U 1 1 67A9FDFC
+P 1830 2390
+F 0 "U7" H 1780 2290 60 0000 C CNN
+F 1 "zener" H 1830 2490 60 0000 C CNN
+F 2 "" H 1880 2390 60 0000 C CNN
+F 3 "" H 1880 2390 60 0000 C CNN
+ 1 1830 2390
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U6
+U 1 1 67A9FE59
+P 1830 2140
+F 0 "U6" H 1780 2040 60 0000 C CNN
+F 1 "zener" H 1830 2240 60 0000 C CNN
+F 2 "" H 1880 2140 60 0000 C CNN
+F 3 "" H 1880 2140 60 0000 C CNN
+ 1 1830 2140
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 67A9FEEB
+P 2550 3230
+F 0 "D1" H 2550 3330 50 0000 C CNN
+F 1 "eSim_Diode" H 2550 3130 50 0000 C CNN
+F 2 "" H 2550 3230 60 0000 C CNN
+F 3 "" H 2550 3230 60 0000 C CNN
+ 1 2550 3230
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 67A9FF3E
+P 3470 2690
+F 0 "C1" H 3495 2790 50 0000 L CNN
+F 1 "10pF" H 3495 2590 50 0000 L CNN
+F 2 "" H 3470 2690 50 0001 C CNN
+F 3 "" H 3470 2690 50 0001 C CNN
+ 1 3470 2690
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 67A9FF79
+P 2880 3560
+F 0 "R3" H 2930 3690 50 0000 C CNN
+F 1 "1.5k" H 2930 3510 50 0000 C CNN
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+U 1 1 67A9FFCE
+P 3420 3270
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+L zener U9
+U 1 1 67AA00E5
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+U 1 1 67AA01B1
+P 4140 2300
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+P 4260 1920
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+U 1 1 67AA192A
+P 630 1900
+F 0 "U1" H 680 2000 30 0000 C CNN
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+U 3 1 67AA1D5E
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+U 1 1 67AA3714
+P 1830 1900
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+ 1 1830 1900
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+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2030 2390
+Wire Wire Line
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+Connection ~ 1500 2390
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+F 0 "#PWR01" H 3900 3960 50 0001 C CNN
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+ 1 0 0 -1
+$EndComp
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+Wire Wire Line
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+Connection ~ 1500 4160
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+Connection ~ 1290 4160
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3190 1690
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2930 2690
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4380 2690
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+L resistor R15
+U 1 1 67AA7BED
+P 8240 1370
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+ 1 8240 1370
+ 0 1 1 0
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+U 1 1 67AA7BF3
+P 8760 1370
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+ 1 8760 1370
+ 0 1 1 0
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+U 1 1 67AA7BF9
+P 8710 2810
+F 0 "Q13" H 8610 2860 50 0000 R CNN
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+F 2 "" H 8910 2910 29 0000 C CNN
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+ 1 8710 2810
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+U 1 1 67AA7BFF
+P 9090 2390
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+F 2 "" H 9290 2490 29 0000 C CNN
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+ 1 9090 2390
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+U 1 1 67AA7C05
+P 9760 1940
+F 0 "Q16" H 9660 1990 50 0000 R CNN
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+F 2 "" H 9960 2040 29 0000 C CNN
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+ 1 9760 1940
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+L resistor R18
+U 1 1 67AA7C0B
+P 9400 1380
+F 0 "R18" H 9450 1510 50 0000 C CNN
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+F 2 "" H 9450 1360 30 0000 C CNN
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+ 1 9400 1380
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+$Comp
+L resistor R21
+U 1 1 67AA7C11
+P 10570 1380
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+ 1 10570 1380
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+$EndComp
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+L zener U16
+U 1 1 67AA7C17
+P 7280 3420
+F 0 "U16" H 7230 3320 60 0000 C CNN
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+ 1 7280 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U17
+U 1 1 67AA7C1D
+P 7550 3420
+F 0 "U17" H 7500 3320 60 0000 C CNN
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+F 2 "" H 7600 3420 60 0000 C CNN
+F 3 "" H 7600 3420 60 0000 C CNN
+ 1 7550 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U18
+U 1 1 67AA7C23
+P 7760 3420
+F 0 "U18" H 7710 3320 60 0000 C CNN
+F 1 "zener" H 7760 3520 60 0000 C CNN
+F 2 "" H 7810 3420 60 0000 C CNN
+F 3 "" H 7810 3420 60 0000 C CNN
+ 1 7760 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U21
+U 1 1 67AA7C29
+P 8090 2640
+F 0 "U21" H 8040 2540 60 0000 C CNN
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+F 2 "" H 8140 2640 60 0000 C CNN
+F 3 "" H 8140 2640 60 0000 C CNN
+ 1 8090 2640
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U20
+U 1 1 67AA7C2F
+P 8090 2390
+F 0 "U20" H 8040 2290 60 0000 C CNN
+F 1 "zener" H 8090 2490 60 0000 C CNN
+F 2 "" H 8140 2390 60 0000 C CNN
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+U 1 1 67AA7C35
+P 8810 3480
+F 0 "D3" H 8810 3580 50 0000 C CNN
+F 1 "eSim_Diode" H 8810 3380 50 0000 C CNN
+F 2 "" H 8810 3480 60 0000 C CNN
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+ 1 8810 3480
+ 0 1 1 0
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+L capacitor_polarised C3
+U 1 1 67AA7C3B
+P 9730 2940
+F 0 "C3" H 9755 3040 50 0000 L CNN
+F 1 "10pF" H 9755 2840 50 0000 L CNN
+F 2 "" H 9730 2940 50 0001 C CNN
+F 3 "" H 9730 2940 50 0001 C CNN
+ 1 9730 2940
+ 0 -1 -1 0
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+$Comp
+L resistor R17
+U 1 1 67AA7C41
+P 9140 3810
+F 0 "R17" H 9190 3940 50 0000 C CNN
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+ 1 9140 3810
+ 0 1 1 0
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+$Comp
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+U 1 1 67AA7C47
+P 9680 3520
+F 0 "R19" H 9730 3650 50 0000 C CNN
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+F 2 "" H 9730 3500 30 0000 C CNN
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+ 1 9680 3520
+ 0 1 1 0
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+U 1 1 67AA7C4D
+P 9630 4080
+F 0 "Q15" H 9530 4130 50 0000 R CNN
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+F 2 "" H 9830 4180 29 0000 C CNN
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+ 1 9630 4080
+ 1 0 0 -1
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+U 1 1 67AA7C53
+P 10540 3370
+F 0 "Q18" H 10440 3420 50 0000 R CNN
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+F 2 "" H 10740 3470 29 0000 C CNN
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+ 1 10540 3370
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+$Comp
+L zener U22
+U 1 1 67AA7C59
+P 9840 2600
+F 0 "U22" H 9790 2500 60 0000 C CNN
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+ 1 9840 2600
+ -1 0 0 1
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+$Comp
+L resistor R20
+U 1 1 67AA7C5F
+P 10400 2550
+F 0 "R20" H 10450 2680 50 0000 C CNN
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+F 3 "" V 10450 2600 30 0000 C CNN
+ 1 10400 2550
+ -1 0 0 1
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+L eSim_NPN Q17
+U 1 1 67AA7C65
+P 10520 2170
+F 0 "Q17" H 10420 2220 50 0000 R CNN
+F 1 "eSim_NPN" H 10470 2320 50 0000 R CNN
+F 2 "" H 10720 2270 29 0000 C CNN
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+ 1 10520 2170
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+U 10 1 67AA7C6B
+P 6890 2150
+F 0 "U1" H 6940 2250 30 0000 C CNN
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+ 10 6890 2150
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+U 11 1 67AA7C71
+P 6890 2390
+F 0 "U1" H 6940 2490 30 0000 C CNN
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+F 2 "" H 6890 2390 60 0000 C CNN
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+ 11 6890 2390
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+L PORT U1
+U 12 1 67AA7C77
+P 6890 2640
+F 0 "U1" H 6940 2740 30 0000 C CNN
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+ 12 6890 2640
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+$EndComp
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+U 14 1 67AA7C7D
+P 11040 2600
+F 0 "U1" H 11090 2700 30 0000 C CNN
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+ 14 11040 2600
+ -1 0 0 1
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+U 1 1 67AA7C83
+P 8090 2150
+F 0 "U19" H 8040 2050 60 0000 C CNN
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8290 2390
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+Connection ~ 8290 2640
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+Connection ~ 7760 2640
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+Connection ~ 7280 2150
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+U 1 1 67AA7C97
+P 10160 4410
+F 0 "#PWR02" H 10160 4210 50 0001 C CNN
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+L resistor R8
+U 1 1 67AA90A0
+P 4520 4430
+F 0 "R8" H 4570 4560 50 0000 C CNN
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+ 1 4520 4430
+ 0 1 1 0
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+$Comp
+L resistor R9
+U 1 1 67AA90A6
+P 5040 4430
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+ 1 5040 4430
+ 0 1 1 0
+$EndComp
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+L eSim_NPN Q7
+U 1 1 67AA90AC
+P 4990 5870
+F 0 "Q7" H 4890 5920 50 0000 R CNN
+F 1 "eSim_NPN" H 4940 6020 50 0000 R CNN
+F 2 "" H 5190 5970 29 0000 C CNN
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+ 1 4990 5870
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+L eSim_NPN Q8
+U 1 1 67AA90B2
+P 5370 5450
+F 0 "Q8" H 5270 5500 50 0000 R CNN
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+F 2 "" H 5570 5550 29 0000 C CNN
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+ 1 5370 5450
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+$Comp
+L eSim_NPN Q10
+U 1 1 67AA90B8
+P 6040 5000
+F 0 "Q10" H 5940 5050 50 0000 R CNN
+F 1 "eSim_NPN" H 5990 5150 50 0000 R CNN
+F 2 "" H 6240 5100 29 0000 C CNN
+F 3 "" H 6040 5000 60 0000 C CNN
+ 1 6040 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 67AA90BE
+P 5680 4440
+F 0 "R11" H 5730 4570 50 0000 C CNN
+F 1 "8k" H 5730 4390 50 0000 C CNN
+F 2 "" H 5730 4420 30 0000 C CNN
+F 3 "" V 5730 4490 30 0000 C CNN
+ 1 5680 4440
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R14
+U 1 1 67AA90C4
+P 6850 4440
+F 0 "R14" H 6900 4570 50 0000 C CNN
+F 1 "120" H 6900 4390 50 0000 C CNN
+F 2 "" H 6900 4420 30 0000 C CNN
+F 3 "" V 6900 4490 30 0000 C CNN
+ 1 6850 4440
+ 0 1 1 0
+$EndComp
+$Comp
+L zener U8
+U 1 1 67AA90CA
+P 3560 6480
+F 0 "U8" H 3510 6380 60 0000 C CNN
+F 1 "zener" H 3560 6580 60 0000 C CNN
+F 2 "" H 3610 6480 60 0000 C CNN
+F 3 "" H 3610 6480 60 0000 C CNN
+ 1 3560 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U10
+U 1 1 67AA90D0
+P 3830 6480
+F 0 "U10" H 3780 6380 60 0000 C CNN
+F 1 "zener" H 3830 6580 60 0000 C CNN
+F 2 "" H 3880 6480 60 0000 C CNN
+F 3 "" H 3880 6480 60 0000 C CNN
+ 1 3830 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U11
+U 1 1 67AA90D6
+P 4040 6480
+F 0 "U11" H 3990 6380 60 0000 C CNN
+F 1 "zener" H 4040 6580 60 0000 C CNN
+F 2 "" H 4090 6480 60 0000 C CNN
+F 3 "" H 4090 6480 60 0000 C CNN
+ 1 4040 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U14
+U 1 1 67AA90DC
+P 4370 5700
+F 0 "U14" H 4320 5600 60 0000 C CNN
+F 1 "zener" H 4370 5800 60 0000 C CNN
+F 2 "" H 4420 5700 60 0000 C CNN
+F 3 "" H 4420 5700 60 0000 C CNN
+ 1 4370 5700
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U13
+U 1 1 67AA90E2
+P 4370 5450
+F 0 "U13" H 4320 5350 60 0000 C CNN
+F 1 "zener" H 4370 5550 60 0000 C CNN
+F 2 "" H 4420 5450 60 0000 C CNN
+F 3 "" H 4420 5450 60 0000 C CNN
+ 1 4370 5450
+ -1 0 0 1
+$EndComp
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+L eSim_Diode D2
+U 1 1 67AA90E8
+P 5090 6540
+F 0 "D2" H 5090 6640 50 0000 C CNN
+F 1 "eSim_Diode" H 5090 6440 50 0000 C CNN
+F 2 "" H 5090 6540 60 0000 C CNN
+F 3 "" H 5090 6540 60 0000 C CNN
+ 1 5090 6540
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 67AA90EE
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+$Comp
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+F 3 "" V 5470 6920 30 0000 C CNN
+ 1 5420 6870
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 67AA90FA
+P 5960 6580
+F 0 "R12" H 6010 6710 50 0000 C CNN
+F 1 "3k" H 6010 6530 50 0000 C CNN
+F 2 "" H 6010 6560 30 0000 C CNN
+F 3 "" V 6010 6630 30 0000 C CNN
+ 1 5960 6580
+ 0 1 1 0
+$EndComp
+$Comp
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+F 2 "" H 6110 7240 29 0000 C CNN
+F 3 "" H 5910 7140 60 0000 C CNN
+ 1 5910 7140
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 2 "" H 7020 6530 29 0000 C CNN
+F 3 "" H 6820 6430 60 0000 C CNN
+ 1 6820 6430
+ 1 0 0 -1
+$EndComp
+$Comp
+L zener U15
+U 1 1 67AA910C
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+F 0 "U15" H 6070 5560 60 0000 C CNN
+F 1 "zener" H 6120 5760 60 0000 C CNN
+F 2 "" H 6170 5660 60 0000 C CNN
+F 3 "" H 6170 5660 60 0000 C CNN
+ 1 6120 5660
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 67AA9112
+P 6680 5610
+F 0 "R13" H 6730 5740 50 0000 C CNN
+F 1 "5k" H 6730 5560 50 0000 C CNN
+F 2 "" H 6730 5590 30 0000 C CNN
+F 3 "" V 6730 5660 30 0000 C CNN
+ 1 6680 5610
+ -1 0 0 1
+$EndComp
+$Comp
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+P 6800 5230
+F 0 "Q11" H 6700 5280 50 0000 R CNN
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+F 2 "" H 7000 5330 29 0000 C CNN
+F 3 "" H 6800 5230 60 0000 C CNN
+ 1 6800 5230
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+$EndComp
+$Comp
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+U 4 1 67AA911E
+P 3170 5210
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+F 1 "PORT" H 3170 5210 30 0000 C CNN
+F 2 "" H 3170 5210 60 0000 C CNN
+F 3 "" H 3170 5210 60 0000 C CNN
+ 4 3170 5210
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67AA9124
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+F 1 "PORT" H 3170 5450 30 0000 C CNN
+F 2 "" H 3170 5450 60 0000 C CNN
+F 3 "" H 3170 5450 60 0000 C CNN
+ 5 3170 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67AA912A
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+F 1 "PORT" H 3170 5700 30 0000 C CNN
+F 2 "" H 3170 5700 60 0000 C CNN
+F 3 "" H 3170 5700 60 0000 C CNN
+ 6 3170 5700
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 13 1 67AA9130
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+F 1 "PORT" H 7320 5660 30 0000 C CNN
+F 2 "" H 7320 5660 60 0000 C CNN
+F 3 "" H 7320 5660 60 0000 C CNN
+ 13 7320 5660
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U12
+U 1 1 67AA9136
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+F 0 "U12" H 4320 5110 60 0000 C CNN
+F 1 "zener" H 4370 5310 60 0000 C CNN
+F 2 "" H 4420 5210 60 0000 C CNN
+F 3 "" H 4420 5210 60 0000 C CNN
+ 1 4370 5210
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4070 5450 3420 5450
+Wire Wire Line
+ 4070 5700 3420 5700
+Wire Wire Line
+ 4570 4630 4570 5870
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+ 4070 5210 3420 5210
+Connection ~ 4570 5450
+Connection ~ 4570 5210
+Wire Wire Line
+ 4570 5870 4790 5870
+Connection ~ 4570 5700
+Wire Wire Line
+ 4040 6180 4040 5700
+Connection ~ 4040 5700
+Wire Wire Line
+ 3830 6180 3830 5450
+Connection ~ 3830 5450
+Wire Wire Line
+ 3560 6180 3560 5210
+Connection ~ 3560 5210
+$Comp
+L GNDPWR #PWR03
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+P 6440 7470
+F 0 "#PWR03" H 6440 7270 50 0001 C CNN
+F 1 "GNDPWR" H 6440 7340 50 0000 C CNN
+F 2 "" H 6440 7420 50 0001 C CNN
+F 3 "" H 6440 7420 50 0001 C CNN
+ 1 6440 7470
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+$EndComp
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+ 3560 7470 7600 7470
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+ 4040 7470 4040 6680
+Connection ~ 6440 7470
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+Connection ~ 4040 7470
+Wire Wire Line
+ 3560 7470 3560 6680
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+Wire Wire Line
+ 5090 6690 5090 7470
+Connection ~ 5090 7470
+Wire Wire Line
+ 5090 6070 5090 6390
+Wire Wire Line
+ 5170 5450 5090 5450
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+ 5470 5000 5840 5000
+Wire Wire Line
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+Wire Wire Line
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+ 5610 5660 5610 5000
+Connection ~ 5610 5000
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+Wire Wire Line
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+Wire Wire Line
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+U 8 1 67AAA48F
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+ 8 5330 830
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+$EndComp
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+F 3 "" H 5920 830 60 0000 C CNN
+ 9 5920 830
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+$EndComp
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+Connection ~ 4360 910
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+Connection ~ 5330 1300
+Connection ~ 6900 4220
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+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub
new file mode 100644
index 00000000..a2659577
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub
@@ -0,0 +1,137 @@
+* Subcircuit Subcircuit_SN74LS11
+.subckt Subcircuit_SN74LS11 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_r1-pad1_ gndpwr net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_c2-pad2_ net-_c3-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\subcircuit_sn74ls11\subcircuit_sn74ls11.cir
+.include D.lib
+.include NPN.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 20k
+r2 net-_r1-pad1_ net-_q1-pad1_ 10k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+r4 net-_r1-pad1_ net-_q2-pad1_ 8k
+r7 net-_r1-pad1_ net-_q4-pad1_ 120
+* u2 gndpwr net-_u1-pad1_ zener
+* u3 gndpwr net-_u1-pad2_ zener
+* u4 gndpwr net-_u1-pad3_ zener
+* u7 net-_q1-pad2_ net-_u1-pad3_ zener
+* u6 net-_q1-pad2_ net-_u1-pad2_ zener
+d1 net-_d1-pad1_ gndpwr 1N4148
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r3 net-_c1-pad1_ net-_q3-pad2_ 1.5k
+r5 net-_c1-pad1_ net-_q3-pad1_ 3k
+q3 net-_q3-pad1_ net-_q3-pad2_ gndpwr Q2N2222
+q6 net-_c1-pad2_ net-_c1-pad1_ gndpwr Q2N2222
+* u9 net-_r6-pad2_ net-_q2-pad1_ zener
+r6 net-_c1-pad2_ net-_r6-pad2_ 5k
+q5 net-_q4-pad1_ net-_q4-pad3_ net-_c1-pad2_ Q2N2222
+* u5 net-_q1-pad2_ net-_u1-pad1_ zener
+r15 net-_r1-pad1_ net-_q13-pad2_ 20k
+r16 net-_r1-pad1_ net-_q13-pad1_ 10k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d3-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_c3-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_q16-pad3_ Q2N2222
+r18 net-_r1-pad1_ net-_q14-pad1_ 8k
+r21 net-_r1-pad1_ net-_q16-pad1_ 120
+* u16 gndpwr net-_u1-pad10_ zener
+* u17 gndpwr net-_u1-pad11_ zener
+* u18 gndpwr net-_u1-pad12_ zener
+* u21 net-_q13-pad2_ net-_u1-pad12_ zener
+* u20 net-_q13-pad2_ net-_u1-pad11_ zener
+d3 net-_d3-pad1_ gndpwr 1N4148
+c3 net-_c3-pad1_ net-_c3-pad2_ 10pf
+r17 net-_c3-pad1_ net-_q15-pad2_ 1.5k
+r19 net-_c3-pad1_ net-_q15-pad1_ 3k
+q15 net-_q15-pad1_ net-_q15-pad2_ gndpwr Q2N2222
+q18 net-_c3-pad2_ net-_c3-pad1_ gndpwr Q2N2222
+* u22 net-_r20-pad2_ net-_q14-pad1_ zener
+r20 net-_c3-pad2_ net-_r20-pad2_ 5k
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_c3-pad2_ Q2N2222
+* u19 net-_q13-pad2_ net-_u1-pad10_ zener
+r8 net-_r1-pad1_ net-_q7-pad2_ 20k
+r9 net-_r1-pad1_ net-_q7-pad1_ 10k
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d2-pad1_ Q2N2222
+q8 net-_q10-pad2_ net-_q7-pad1_ net-_c2-pad1_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r11 net-_r1-pad1_ net-_q10-pad2_ 8k
+r14 net-_r1-pad1_ net-_q10-pad1_ 120
+* u8 gndpwr net-_u1-pad4_ zener
+* u10 gndpwr net-_u1-pad5_ zener
+* u11 gndpwr net-_u1-pad6_ zener
+* u14 net-_q7-pad2_ net-_u1-pad6_ zener
+* u13 net-_q7-pad2_ net-_u1-pad5_ zener
+d2 net-_d2-pad1_ gndpwr 1N4148
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r10 net-_c2-pad1_ net-_q9-pad2_ 1.5k
+r12 net-_c2-pad1_ net-_q9-pad1_ 3k
+q9 net-_q9-pad1_ net-_q9-pad2_ gndpwr Q2N2222
+q12 net-_c2-pad2_ net-_c2-pad1_ gndpwr Q2N2222
+* u15 net-_r13-pad2_ net-_q10-pad2_ zener
+r13 net-_c2-pad2_ net-_r13-pad2_ 5k
+q11 net-_q10-pad1_ net-_q10-pad3_ net-_c2-pad2_ Q2N2222
+* u12 net-_q7-pad2_ net-_u1-pad4_ zener
+a1 gndpwr net-_u1-pad1_ u2
+a2 gndpwr net-_u1-pad2_ u3
+a3 gndpwr net-_u1-pad3_ u4
+a4 net-_q1-pad2_ net-_u1-pad3_ u7
+a5 net-_q1-pad2_ net-_u1-pad2_ u6
+a6 net-_r6-pad2_ net-_q2-pad1_ u9
+a7 net-_q1-pad2_ net-_u1-pad1_ u5
+a8 gndpwr net-_u1-pad10_ u16
+a9 gndpwr net-_u1-pad11_ u17
+a10 gndpwr net-_u1-pad12_ u18
+a11 net-_q13-pad2_ net-_u1-pad12_ u21
+a12 net-_q13-pad2_ net-_u1-pad11_ u20
+a13 net-_r20-pad2_ net-_q14-pad1_ u22
+a14 net-_q13-pad2_ net-_u1-pad10_ u19
+a15 gndpwr net-_u1-pad4_ u8
+a16 gndpwr net-_u1-pad5_ u10
+a17 gndpwr net-_u1-pad6_ u11
+a18 net-_q7-pad2_ net-_u1-pad6_ u14
+a19 net-_q7-pad2_ net-_u1-pad5_ u13
+a20 net-_r13-pad2_ net-_q10-pad2_ u15
+a21 net-_q7-pad2_ net-_u1-pad4_ u12
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u21 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u20 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u22 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends Subcircuit_SN74LS11
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml
new file mode 100644
index 00000000..088a27f7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecseczenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS11/analysis b/library/SubcircuitLibrary/SN74LS11/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS11/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
--
cgit