From e279dc2d5fa948fc3e9491d0d36dd42f88a8ecad Mon Sep 17 00:00:00 2001 From: saurabhb17 Date: Fri, 24 Apr 2020 11:46:43 +0530 Subject: Subcircuit for CMOS based NAND gate and its supporting example --- .../CMOS_NAND/CMOS_NAND-cache.lib | 130 +++++++++++ library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir | 16 ++ .../SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir.out | 19 ++ library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.pro | 69 ++++++ library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sch | 254 +++++++++++++++++++++ library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sub | 13 ++ .../CMOS_NAND/CMOS_NAND_Previous_Values.xml | 1 + library/SubcircuitLibrary/CMOS_NAND/NMOS-180nm.lib | 13 ++ library/SubcircuitLibrary/CMOS_NAND/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/CMOS_NAND/analysis | 1 + 10 files changed, 527 insertions(+) create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND-cache.lib create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir.out create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.pro create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sch create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sub create mode 100644 library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CMOS_NAND/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CMOS_NAND/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/CMOS_NAND/analysis (limited to 'library/SubcircuitLibrary') diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND-cache.lib b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND-cache.lib new file mode 100644 index 00000000..99c6453a --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND-cache.lib @@ -0,0 +1,130 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir new file mode 100644 index 00000000..92015d1f --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND\CMOS_NAND.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/23/20 20:21:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P +M2 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ GND eSim_MOS_N +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ GND GND eSim_MOS_N +U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT +v1 Net-_M1-Pad1_ GND DC + +.end diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir.out b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir.out new file mode 100644 index 00000000..d1cde907 --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.cir.out @@ -0,0 +1,19 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1 +m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1 +* u1 net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ port +v1 net-_m1-pad1_ gnd dc 5 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.pro b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sch b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sch new file mode 100644 index 00000000..5e2f6b80 --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sch @@ -0,0 +1,254 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:CMOS_NAND-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M1 +U 1 1 5EA19849 +P 5150 2100 +F 0 "M1" H 5100 2150 50 0000 R CNN +F 1 "eSim_MOS_P" H 5200 2250 50 0000 R CNN +F 2 "" H 5400 2200 29 0000 C CNN +F 3 "" H 5200 2100 60 0000 C CNN + 1 5150 2100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 5EA1984A +P 5950 2050 +F 0 "M4" H 5900 2100 50 0000 R CNN +F 1 "eSim_MOS_P" H 6000 2200 50 0000 R CNN +F 2 "" H 6200 2150 29 0000 C CNN +F 3 "" H 6000 2050 60 0000 C CNN + 1 5950 2050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 5EA1984B +P 5350 2800 +F 0 "M2" H 5350 2650 50 0000 R CNN +F 1 "eSim_MOS_N" H 5450 2750 50 0000 R CNN +F 2 "" H 5650 2500 29 0000 C CNN +F 3 "" H 5450 2600 60 0000 C CNN + 1 5350 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 5EA1984C +P 5350 3450 +F 0 "M3" H 5350 3300 50 0000 R CNN +F 1 "eSim_MOS_N" H 5450 3400 50 0000 R CNN +F 2 "" H 5650 3150 29 0000 C CNN +F 3 "" H 5450 3250 60 0000 C CNN + 1 5350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2300 5300 2550 +Wire Wire Line + 5300 2550 5800 2550 +Wire Wire Line + 5800 2550 5800 2250 +Wire Wire Line + 5400 2250 5450 2250 +Wire Wire Line + 5450 2250 5450 1800 +Wire Wire Line + 5300 1800 5800 1800 +Wire Wire Line + 5300 1800 5300 1900 +Wire Wire Line + 5600 2200 5700 2200 +Wire Wire Line + 5600 1650 5600 2200 +Wire Wire Line + 5800 1800 5800 1850 +Wire Wire Line + 5550 3200 5550 3450 +Wire Wire Line + 5550 2550 5550 2800 +Connection ~ 5550 2550 +Wire Wire Line + 5650 3150 5800 3150 +Wire Wire Line + 5800 3150 5800 4100 +Wire Wire Line + 5550 3850 5550 4100 +Wire Wire Line + 5650 3800 5650 4200 +Connection ~ 5650 4000 +Connection ~ 5450 1800 +Connection ~ 5600 1800 +Wire Wire Line + 7400 2250 7400 1650 +Wire Wire Line + 7400 1650 5600 1650 +Wire Wire Line + 7400 4200 7400 3150 +Wire Wire Line + 5650 4200 7400 4200 +Wire Wire Line + 4650 3650 5250 3650 +Connection ~ 5650 4200 +Wire Wire Line + 3950 2400 4650 2400 +Wire Wire Line + 4650 2400 4650 3000 +Wire Wire Line + 4650 3000 5250 3000 +Wire Wire Line + 4950 2100 5000 2100 +Connection ~ 4950 3650 +Wire Wire Line + 6400 2050 6400 4850 +Wire Wire Line + 6400 2050 6100 2050 +Connection ~ 6050 4200 +Connection ~ 5550 2750 +Wire Wire Line + 4950 3000 4950 2100 +Connection ~ 4950 3000 +Wire Wire Line + 4950 3650 4950 4850 +Wire Wire Line + 4950 4850 6400 4850 +Wire Wire Line + 6000 2750 5550 2750 +Connection ~ 4200 2400 +Wire Wire Line + 4650 3350 4650 3650 +Wire Wire Line + 6000 2750 6000 3000 +$Comp +L PORT U1 +U 1 1 5EA19AC9 +P 3600 2150 +F 0 "U1" H 3650 2250 30 0000 C CNN +F 1 "PORT" H 3600 2150 30 0000 C CNN +F 2 "" H 3600 2150 60 0000 C CNN +F 3 "" H 3600 2150 60 0000 C CNN + 1 3600 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5EA19B16 +P 4150 3350 +F 0 "U1" H 4200 3450 30 0000 C CNN +F 1 "PORT" H 4150 3350 30 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 2 4150 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5EA19B5B +P 6250 3000 +F 0 "U1" H 6300 3100 30 0000 C CNN +F 1 "PORT" H 6250 3000 30 0000 C CNN +F 2 "" H 6250 3000 60 0000 C CNN +F 3 "" H 6250 3000 60 0000 C CNN + 3 6250 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 4400 3350 4650 3350 +Wire Wire Line + 3850 2150 3950 2150 +Wire Wire Line + 3950 2150 3950 2400 +Text Notes 7800 2100 0 60 ~ 0 +vcc +Text Notes 7850 3300 0 60 ~ 0 +gnd +Text Notes 3250 2150 0 60 ~ 0 +in1\n +Text Notes 3800 3400 0 60 ~ 0 +in2 +Text Notes 6150 2850 0 60 ~ 0 +out\n +Wire Wire Line + 5550 4100 5800 4100 +Connection ~ 5650 4100 +$Comp +L DC v1 +U 1 1 5EA1AB6C +P 7550 2700 +F 0 "v1" H 7350 2800 60 0000 C CNN +F 1 "DC" H 7350 2650 60 0000 C CNN +F 2 "R1" H 7250 2700 60 0000 C CNN +F 3 "" H 7550 2700 60 0000 C CNN + 1 7550 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7550 2250 7400 2250 +Wire Wire Line + 7400 3150 7550 3150 +$Comp +L GND #PWR1 +U 1 1 5EA1AC79 +P 6750 4300 +F 0 "#PWR1" H 6750 4050 50 0001 C CNN +F 1 "GND" H 6750 4150 50 0000 C CNN +F 2 "" H 6750 4300 50 0001 C CNN +F 3 "" H 6750 4300 50 0001 C CNN + 1 6750 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 4300 6750 4200 +Connection ~ 6750 4200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sub b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sub new file mode 100644 index 00000000..6d2efb0b --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND.sub @@ -0,0 +1,13 @@ +* Subcircuit CMOS_NAND +.subckt CMOS_NAND net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1 +m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1 +v1 net-_m1-pad1_ gnd dc 5 +* Control Statements + +.ends CMOS_NAND \ No newline at end of file diff --git a/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND_Previous_Values.xml b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND_Previous_Values.xml new file mode 100644 index 00000000..e3478d8c --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/CMOS_NAND_Previous_Values.xml @@ -0,0 +1 @@ +dc5C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib1u0.5uC:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib2.5u0.5uC:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib1u0.5uC:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib2.5u0.5utruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CMOS_NAND/NMOS-180nm.lib b/library/SubcircuitLibrary/CMOS_NAND/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CMOS_NAND/PMOS-180nm.lib b/library/SubcircuitLibrary/CMOS_NAND/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CMOS_NAND/analysis b/library/SubcircuitLibrary/CMOS_NAND/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CMOS_NAND/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file -- cgit