From 890dd9dfe673d2a803fd2f347c4f718080eefb46 Mon Sep 17 00:00:00 2001 From: suprraja Date: Tue, 11 Mar 2025 03:30:16 +0000 Subject: Added SN74LS09 subcircuit --- library/SubcircuitLibrary/SN74LS09/D.lib | 2 + library/SubcircuitLibrary/SN74LS09/NPN.lib | 4 + library/SubcircuitLibrary/SN74LS09/analysis | 1 + .../SN74LS09/sn74ls09__-cache.lib | 143 +++ library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir | 59 ++ .../SubcircuitLibrary/SN74LS09/sn74ls09__.cir.out | 110 ++ library/SubcircuitLibrary/SN74LS09/sn74ls09__.pro | 73 ++ library/SubcircuitLibrary/SN74LS09/sn74ls09__.sch | 1076 ++++++++++++++++++++ library/SubcircuitLibrary/SN74LS09/sn74ls09__.sub | 104 ++ .../SN74LS09/sn74ls09___Previous_Values.xml | 1 + 10 files changed, 1573 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LS09/D.lib create mode 100644 library/SubcircuitLibrary/SN74LS09/NPN.lib create mode 100644 library/SubcircuitLibrary/SN74LS09/analysis create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__-cache.lib create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir.out create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__.pro create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__.sch create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09__.sub create mode 100644 library/SubcircuitLibrary/SN74LS09/sn74ls09___Previous_Values.xml (limited to 'library/SubcircuitLibrary') diff --git a/library/SubcircuitLibrary/SN74LS09/D.lib b/library/SubcircuitLibrary/SN74LS09/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74LS09/NPN.lib b/library/SubcircuitLibrary/SN74LS09/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74LS09/analysis b/library/SubcircuitLibrary/SN74LS09/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__-cache.lib b/library/SubcircuitLibrary/SN74LS09/sn74ls09__-cache.lib new file mode 100644 index 00000000..8fb17493 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__-cache.lib @@ -0,0 +1,143 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GNDPWR +# +DEF GNDPWR #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -200 50 H I C CNN +F1 "GNDPWR" 0 -130 50 H V C CNN +F2 "" 0 -50 50 H I C CNN +F3 "" 0 -50 50 H I C CNN +DRAW +P 2 0 1 0 0 -50 0 0 N +P 3 0 1 8 -40 -50 -50 -80 -50 -80 N +P 3 0 1 8 -20 -50 -30 -80 -30 -80 N +P 3 0 1 8 0 -50 -10 -80 -10 -80 N +P 3 0 1 8 20 -50 10 -80 10 -80 N +P 3 0 1 8 40 -50 -40 -50 -40 -50 N +P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N +X GNDPWR 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir new file mode 100644 index 00000000..f7960c03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir @@ -0,0 +1,59 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\sn74ls09__\sn74ls09__.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/17/25 00:06:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_Q4-Pad2_ 20k +R2 Net-_R1-Pad1_ Net-_Q1-Pad2_ 10k +R3 Net-_R1-Pad1_ Net-_Q1-Pad1_ 8k +R7 Net-_Q1-Pad3_ GNDPWR 5k +D1 Net-_D1-Pad1_ GNDPWR eSim_Diode +U6 GNDPWR Net-_U1-Pad7_ zener +U7 GNDPWR Net-_U1-Pad4_ zener +U2 Net-_Q4-Pad2_ Net-_U1-Pad4_ zener +U4 Net-_Q4-Pad2_ Net-_U1-Pad7_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad2_ Net-_Q4-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad3_ GNDPWR eSim_NPN +U1 Net-_R1-Pad1_ GNDPWR Net-_Q2-Pad1_ Net-_U1-Pad4_ Net-_Q5-Pad1_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_Q8-Pad1_ Net-_U1-Pad10_ Net-_Q11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +R9 Net-_R1-Pad1_ Net-_Q10-Pad2_ 20k +R10 Net-_R1-Pad1_ Net-_Q10-Pad1_ 10k +R11 Net-_R1-Pad1_ Net-_Q7-Pad1_ 8k +R15 Net-_Q7-Pad3_ GNDPWR 5k +D3 Net-_D3-Pad1_ GNDPWR eSim_Diode +U14 GNDPWR Net-_U1-Pad13_ zener +U15 GNDPWR Net-_U1-Pad10_ zener +U10 Net-_Q10-Pad2_ Net-_U1-Pad10_ zener +U12 Net-_Q10-Pad2_ Net-_U1-Pad13_ zener +Q7 Net-_Q7-Pad1_ Net-_Q10-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D3-Pad1_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_Q7-Pad3_ GNDPWR eSim_NPN +R6 Net-_R1-Pad1_ Net-_Q6-Pad2_ 20k +R5 Net-_R1-Pad1_ Net-_Q3-Pad2_ 10k +R4 Net-_R1-Pad1_ Net-_Q3-Pad1_ 8k +R8 Net-_Q3-Pad3_ GNDPWR 5k +D2 Net-_D2-Pad1_ GNDPWR eSim_Diode +U8 GNDPWR Net-_U1-Pad8_ zener +U9 GNDPWR Net-_U1-Pad6_ zener +U3 Net-_Q6-Pad2_ Net-_U1-Pad6_ zener +U5 Net-_Q6-Pad2_ Net-_U1-Pad8_ zener +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q6-Pad2_ Net-_D2-Pad1_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q3-Pad3_ GNDPWR eSim_NPN +R14 Net-_R1-Pad1_ Net-_Q12-Pad2_ 20k +R13 Net-_R1-Pad1_ Net-_Q12-Pad1_ 10k +R12 Net-_R1-Pad1_ Net-_Q9-Pad1_ 8k +R16 Net-_Q11-Pad2_ GNDPWR 5k +D4 Net-_D4-Pad1_ GNDPWR eSim_Diode +U16 GNDPWR Net-_U1-Pad14_ zener +U17 GNDPWR Net-_U1-Pad12_ zener +U11 Net-_Q12-Pad2_ Net-_U1-Pad12_ zener +U13 Net-_Q12-Pad2_ Net-_U1-Pad14_ zener +Q9 Net-_Q9-Pad1_ Net-_Q12-Pad1_ Net-_Q11-Pad2_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_D4-Pad1_ eSim_NPN +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ GNDPWR eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir.out b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir.out new file mode 100644 index 00000000..2e5a4e53 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.cir.out @@ -0,0 +1,110 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls09__\sn74ls09__.cir + +.include NPN.lib +.include D.lib +r1 net-_r1-pad1_ net-_q4-pad2_ 20k +r2 net-_r1-pad1_ net-_q1-pad2_ 10k +r3 net-_r1-pad1_ net-_q1-pad1_ 8k +r7 net-_q1-pad3_ gndpwr 5k +d1 net-_d1-pad1_ gndpwr 1N4148 +* u6 gndpwr net-_u1-pad7_ zener +* u7 gndpwr net-_u1-pad4_ zener +* u2 net-_q4-pad2_ net-_u1-pad4_ zener +* u4 net-_q4-pad2_ net-_u1-pad7_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_q1-pad2_ net-_q4-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad3_ gndpwr Q2N2222 +* u1 net-_r1-pad1_ gndpwr net-_q2-pad1_ net-_u1-pad4_ net-_q5-pad1_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_q8-pad1_ net-_u1-pad10_ net-_q11-pad1_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +r9 net-_r1-pad1_ net-_q10-pad2_ 20k +r10 net-_r1-pad1_ net-_q10-pad1_ 10k +r11 net-_r1-pad1_ net-_q7-pad1_ 8k +r15 net-_q7-pad3_ gndpwr 5k +d3 net-_d3-pad1_ gndpwr 1N4148 +* u14 gndpwr net-_u1-pad13_ zener +* u15 gndpwr net-_u1-pad10_ zener +* u10 net-_q10-pad2_ net-_u1-pad10_ zener +* u12 net-_q10-pad2_ net-_u1-pad13_ zener +q7 net-_q7-pad1_ net-_q10-pad1_ net-_q7-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d3-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_q7-pad3_ gndpwr Q2N2222 +r6 net-_r1-pad1_ net-_q6-pad2_ 20k +r5 net-_r1-pad1_ net-_q3-pad2_ 10k +r4 net-_r1-pad1_ net-_q3-pad1_ 8k +r8 net-_q3-pad3_ gndpwr 5k +d2 net-_d2-pad1_ gndpwr 1N4148 +* u8 gndpwr net-_u1-pad8_ zener +* u9 gndpwr net-_u1-pad6_ zener +* u3 net-_q6-pad2_ net-_u1-pad6_ zener +* u5 net-_q6-pad2_ net-_u1-pad8_ zener +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad2_ net-_q6-pad2_ net-_d2-pad1_ Q2N2222 +q5 net-_q5-pad1_ net-_q3-pad3_ gndpwr Q2N2222 +r14 net-_r1-pad1_ net-_q12-pad2_ 20k +r13 net-_r1-pad1_ net-_q12-pad1_ 10k +r12 net-_r1-pad1_ net-_q9-pad1_ 8k +r16 net-_q11-pad2_ gndpwr 5k +d4 net-_d4-pad1_ gndpwr 1N4148 +* u16 gndpwr net-_u1-pad14_ zener +* u17 gndpwr net-_u1-pad12_ zener +* u11 net-_q12-pad2_ net-_u1-pad12_ zener +* u13 net-_q12-pad2_ net-_u1-pad14_ zener +q9 net-_q9-pad1_ net-_q12-pad1_ net-_q11-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_d4-pad1_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ gndpwr Q2N2222 +a1 gndpwr net-_u1-pad7_ u6 +a2 gndpwr net-_u1-pad4_ u7 +a3 net-_q4-pad2_ net-_u1-pad4_ u2 +a4 net-_q4-pad2_ net-_u1-pad7_ u4 +a5 gndpwr net-_u1-pad13_ u14 +a6 gndpwr net-_u1-pad10_ u15 +a7 net-_q10-pad2_ net-_u1-pad10_ u10 +a8 net-_q10-pad2_ net-_u1-pad13_ u12 +a9 gndpwr net-_u1-pad8_ u8 +a10 gndpwr net-_u1-pad6_ u9 +a11 net-_q6-pad2_ net-_u1-pad6_ u3 +a12 net-_q6-pad2_ net-_u1-pad8_ u5 +a13 gndpwr net-_u1-pad14_ u16 +a14 gndpwr net-_u1-pad12_ u17 +a15 net-_q12-pad2_ net-_u1-pad12_ u11 +a16 net-_q12-pad2_ net-_u1-pad14_ u13 +* Schematic Name: zener, NgSpice Name: zener +.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__.pro b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sch b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sch new file mode 100644 index 00000000..06244fbe --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sch @@ -0,0 +1,1076 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 67B229EC +P 2200 1750 +F 0 "R1" H 2250 1880 50 0000 C CNN +F 1 "20k" H 2250 1700 50 0000 C CNN +F 2 "" H 2250 1730 30 0000 C CNN +F 3 "" V 2250 1800 30 0000 C CNN + 1 2200 1750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67B22A6B +P 2900 1750 +F 0 "R2" H 2950 1880 50 0000 C CNN +F 1 "10k" H 2950 1700 50 0000 C CNN +F 2 "" H 2950 1730 30 0000 C CNN +F 3 "" V 2950 1800 30 0000 C CNN + 1 2900 1750 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 67B22A9F +P 3650 1750 +F 0 "R3" H 3700 1880 50 0000 C CNN +F 1 "8k" H 3700 1700 50 0000 C CNN +F 2 "" H 3700 1730 30 0000 C CNN +F 3 "" V 3700 1800 30 0000 C CNN + 1 3650 1750 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 67B22AD8 +P 3850 2850 +F 0 "R7" H 3900 2980 50 0000 C CNN +F 1 "5k" H 3900 2800 50 0000 C CNN +F 2 "" H 3900 2830 30 0000 C CNN +F 3 "" V 3900 2900 30 0000 C CNN + 1 3850 2850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67B22B28 +P 2850 3450 +F 0 "D1" H 2850 3550 50 0000 C CNN +F 1 "eSim_Diode" H 2850 3350 50 0000 C CNN +F 2 "" H 2850 3450 60 0000 C CNN +F 3 "" H 2850 3450 60 0000 C CNN + 1 2850 3450 + 0 1 1 0 +$EndComp +$Comp +L zener U6 +U 1 1 67B22B59 +P 1250 3600 +F 0 "U6" H 1200 3500 60 0000 C CNN +F 1 "zener" H 1250 3700 60 0000 C CNN +F 2 "" H 1300 3600 60 0000 C CNN +F 3 "" H 1300 3600 60 0000 C CNN + 1 1250 3600 + 0 -1 -1 0 +$EndComp +$Comp +L zener U7 +U 1 1 67B22BD0 +P 750 3650 +F 0 "U7" H 700 3550 60 0000 C CNN +F 1 "zener" H 750 3750 60 0000 C CNN +F 2 "" H 800 3650 60 0000 C CNN +F 3 "" H 800 3650 60 0000 C CNN + 1 750 3650 + 0 -1 -1 0 +$EndComp +$Comp +L zener U2 +U 1 1 67B22DEE +P 1750 2300 +F 0 "U2" H 1700 2200 60 0000 C CNN +F 1 "zener" H 1750 2400 60 0000 C CNN +F 2 "" H 1800 2300 60 0000 C CNN +F 3 "" H 1800 2300 60 0000 C CNN + 1 1750 2300 + -1 0 0 1 +$EndComp +$Comp +L zener U4 +U 1 1 67B22E72 +P 1700 2750 +F 0 "U4" H 1650 2650 60 0000 C CNN +F 1 "zener" H 1700 2850 60 0000 C CNN +F 2 "" H 1750 2750 60 0000 C CNN +F 3 "" H 1750 2750 60 0000 C CNN + 1 1700 2750 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67B23032 +P 3600 2350 +F 0 "Q1" H 3500 2400 50 0000 R CNN +F 1 "eSim_NPN" H 3550 2500 50 0000 R CNN +F 2 "" H 3800 2450 29 0000 C CNN +F 3 "" H 3600 2350 60 0000 C CNN + 1 3600 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67B23263 +P 2600 2750 +F 0 "Q4" H 2500 2800 50 0000 R CNN +F 1 "eSim_NPN" H 2550 2900 50 0000 R CNN +F 2 "" H 2800 2850 29 0000 C CNN +F 3 "" H 2600 2750 60 0000 C CNN + 1 2600 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 67B232F5 +P 4450 2600 +F 0 "Q2" H 4350 2650 50 0000 R CNN +F 1 "eSim_NPN" H 4400 2750 50 0000 R CNN +F 2 "" H 4650 2700 29 0000 C CNN +F 3 "" H 4450 2600 60 0000 C CNN + 1 4450 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67B2334B +P 6750 850 +F 0 "U1" H 6800 950 30 0000 C CNN +F 1 "PORT" H 6750 850 30 0000 C CNN +F 2 "" H 6750 850 60 0000 C CNN +F 3 "" H 6750 850 60 0000 C CNN + 1 6750 850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 67B2366A +P 400 2350 +F 0 "U1" H 450 2450 30 0000 C CNN +F 1 "PORT" H 400 2350 30 0000 C CNN +F 2 "" H 400 2350 60 0000 C CNN +F 3 "" H 400 2350 60 0000 C CNN + 4 400 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67B23860 +P 400 2750 +F 0 "U1" H 450 2850 30 0000 C CNN +F 1 "PORT" H 400 2750 30 0000 C CNN +F 2 "" H 400 2750 60 0000 C CNN +F 3 "" H 400 2750 60 0000 C CNN + 7 400 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67B23BCF +P 5150 2300 +F 0 "U1" H 5200 2400 30 0000 C CNN +F 1 "PORT" H 5150 2300 30 0000 C CNN +F 2 "" H 5150 2300 60 0000 C CNN +F 3 "" H 5150 2300 60 0000 C CNN + 3 5150 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 67B23C5E +P 7200 1250 +F 0 "U1" H 7250 1350 30 0000 C CNN +F 1 "PORT" H 7200 1250 30 0000 C CNN +F 2 "" H 7200 1250 60 0000 C CNN +F 3 "" H 7200 1250 60 0000 C CNN + 2 7200 1250 + -1 0 0 1 +$EndComp +$Comp +L GNDPWR #PWR01 +U 1 1 67B23EA7 +P 3550 4150 +F 0 "#PWR01" H 3550 3950 50 0001 C CNN +F 1 "GNDPWR" H 3550 4020 50 0000 C CNN +F 2 "" H 3550 4100 50 0001 C CNN +F 3 "" H 3550 4100 50 0001 C CNN + 1 3550 4150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 67B24FB3 +P 3200 4750 +F 0 "R9" H 3250 4880 50 0000 C CNN +F 1 "20k" H 3250 4700 50 0000 C CNN +F 2 "" H 3250 4730 30 0000 C CNN +F 3 "" V 3250 4800 30 0000 C CNN + 1 3200 4750 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 67B24FB9 +P 3900 4750 +F 0 "R10" H 3950 4880 50 0000 C CNN +F 1 "10k" H 3950 4700 50 0000 C CNN +F 2 "" H 3950 4730 30 0000 C CNN +F 3 "" V 3950 4800 30 0000 C CNN + 1 3900 4750 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 67B24FBF +P 4650 4750 +F 0 "R11" H 4700 4880 50 0000 C CNN +F 1 "8k" H 4700 4700 50 0000 C CNN +F 2 "" H 4700 4730 30 0000 C CNN +F 3 "" V 4700 4800 30 0000 C CNN + 1 4650 4750 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 67B24FC5 +P 4850 5850 +F 0 "R15" H 4900 5980 50 0000 C CNN +F 1 "5k" H 4900 5800 50 0000 C CNN +F 2 "" H 4900 5830 30 0000 C CNN +F 3 "" V 4900 5900 30 0000 C CNN + 1 4850 5850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 67B24FCB +P 3850 6450 +F 0 "D3" H 3850 6550 50 0000 C CNN +F 1 "eSim_Diode" H 3850 6350 50 0000 C CNN +F 2 "" H 3850 6450 60 0000 C CNN +F 3 "" H 3850 6450 60 0000 C CNN + 1 3850 6450 + 0 1 1 0 +$EndComp +$Comp +L zener U14 +U 1 1 67B24FD1 +P 2250 6600 +F 0 "U14" H 2200 6500 60 0000 C CNN +F 1 "zener" H 2250 6700 60 0000 C CNN +F 2 "" H 2300 6600 60 0000 C CNN +F 3 "" H 2300 6600 60 0000 C CNN + 1 2250 6600 + 0 -1 -1 0 +$EndComp +$Comp +L zener U15 +U 1 1 67B24FD7 +P 1750 6650 +F 0 "U15" H 1700 6550 60 0000 C CNN +F 1 "zener" H 1750 6750 60 0000 C CNN +F 2 "" H 1800 6650 60 0000 C CNN +F 3 "" H 1800 6650 60 0000 C CNN + 1 1750 6650 + 0 -1 -1 0 +$EndComp +$Comp +L zener U10 +U 1 1 67B24FDD +P 2750 5300 +F 0 "U10" H 2700 5200 60 0000 C CNN +F 1 "zener" H 2750 5400 60 0000 C CNN +F 2 "" H 2800 5300 60 0000 C CNN +F 3 "" H 2800 5300 60 0000 C CNN + 1 2750 5300 + -1 0 0 1 +$EndComp +$Comp +L zener U12 +U 1 1 67B24FE3 +P 2700 5750 +F 0 "U12" H 2650 5650 60 0000 C CNN +F 1 "zener" H 2700 5850 60 0000 C CNN +F 2 "" H 2750 5750 60 0000 C CNN +F 3 "" H 2750 5750 60 0000 C CNN + 1 2700 5750 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 67B24FE9 +P 4600 5350 +F 0 "Q7" H 4500 5400 50 0000 R CNN +F 1 "eSim_NPN" H 4550 5500 50 0000 R CNN +F 2 "" H 4800 5450 29 0000 C CNN +F 3 "" H 4600 5350 60 0000 C CNN + 1 4600 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 67B24FEF +P 3600 5750 +F 0 "Q10" H 3500 5800 50 0000 R CNN +F 1 "eSim_NPN" H 3550 5900 50 0000 R CNN +F 2 "" H 3800 5850 29 0000 C CNN +F 3 "" H 3600 5750 60 0000 C CNN + 1 3600 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 67B24FF5 +P 5450 5600 +F 0 "Q8" H 5350 5650 50 0000 R CNN +F 1 "eSim_NPN" H 5400 5750 50 0000 R CNN +F 2 "" H 5650 5700 29 0000 C CNN +F 3 "" H 5450 5600 60 0000 C CNN + 1 5450 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67B25004 +P 1050 5350 +F 0 "U1" H 1100 5450 30 0000 C CNN +F 1 "PORT" H 1050 5350 30 0000 C CNN +F 2 "" H 1050 5350 60 0000 C CNN +F 3 "" H 1050 5350 60 0000 C CNN + 10 1050 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67B2500A +P 1050 5750 +F 0 "U1" H 1100 5850 30 0000 C CNN +F 1 "PORT" H 1050 5750 30 0000 C CNN +F 2 "" H 1050 5750 60 0000 C CNN +F 3 "" H 1050 5750 60 0000 C CNN + 13 1050 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67B25020 +P 6150 5300 +F 0 "U1" H 6200 5400 30 0000 C CNN +F 1 "PORT" H 6150 5300 30 0000 C CNN +F 2 "" H 6150 5300 60 0000 C CNN +F 3 "" H 6150 5300 60 0000 C CNN + 9 6150 5300 + -1 0 0 1 +$EndComp +$Comp +L GNDPWR #PWR02 +U 1 1 67B25034 +P 4550 7150 +F 0 "#PWR02" H 4550 6950 50 0001 C CNN +F 1 "GNDPWR" H 4550 7020 50 0000 C CNN +F 2 "" H 4550 7100 50 0001 C CNN +F 3 "" H 4550 7100 50 0001 C CNN + 1 4550 7150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 67B25379 +P 8900 2000 +F 0 "R6" H 8950 2130 50 0000 C CNN +F 1 "20k" H 8950 1950 50 0000 C CNN +F 2 "" H 8950 1980 30 0000 C CNN +F 3 "" V 8950 2050 30 0000 C CNN + 1 8900 2000 + 0 -1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 67B2537F +P 8200 2000 +F 0 "R5" H 8250 2130 50 0000 C CNN +F 1 "10k" H 8250 1950 50 0000 C CNN +F 2 "" H 8250 1980 30 0000 C CNN +F 3 "" V 8250 2050 30 0000 C CNN + 1 8200 2000 + 0 -1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67B25385 +P 7450 2000 +F 0 "R4" H 7500 2130 50 0000 C CNN +F 1 "8k" H 7500 1950 50 0000 C CNN +F 2 "" H 7500 1980 30 0000 C CNN +F 3 "" V 7500 2050 30 0000 C CNN + 1 7450 2000 + 0 -1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 67B2538B +P 7250 3100 +F 0 "R8" H 7300 3230 50 0000 C CNN +F 1 "5k" H 7300 3050 50 0000 C CNN +F 2 "" H 7300 3080 30 0000 C CNN +F 3 "" V 7300 3150 30 0000 C CNN + 1 7250 3100 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 67B25391 +P 8250 3700 +F 0 "D2" H 8250 3800 50 0000 C CNN +F 1 "eSim_Diode" H 8250 3600 50 0000 C CNN +F 2 "" H 8250 3700 60 0000 C CNN +F 3 "" H 8250 3700 60 0000 C CNN + 1 8250 3700 + 0 -1 1 0 +$EndComp +$Comp +L zener U8 +U 1 1 67B25397 +P 9850 3850 +F 0 "U8" H 9800 3750 60 0000 C CNN +F 1 "zener" H 9850 3950 60 0000 C CNN +F 2 "" H 9900 3850 60 0000 C CNN +F 3 "" H 9900 3850 60 0000 C CNN + 1 9850 3850 + 0 1 -1 0 +$EndComp +$Comp +L zener U9 +U 1 1 67B2539D +P 10350 3900 +F 0 "U9" H 10300 3800 60 0000 C CNN +F 1 "zener" H 10350 4000 60 0000 C CNN +F 2 "" H 10400 3900 60 0000 C CNN +F 3 "" H 10400 3900 60 0000 C CNN + 1 10350 3900 + 0 1 -1 0 +$EndComp +$Comp +L zener U3 +U 1 1 67B253A3 +P 9350 2550 +F 0 "U3" H 9300 2450 60 0000 C CNN +F 1 "zener" H 9350 2650 60 0000 C CNN +F 2 "" H 9400 2550 60 0000 C CNN +F 3 "" H 9400 2550 60 0000 C CNN + 1 9350 2550 + 1 0 0 1 +$EndComp +$Comp +L zener U5 +U 1 1 67B253A9 +P 9400 3000 +F 0 "U5" H 9350 2900 60 0000 C CNN +F 1 "zener" H 9400 3100 60 0000 C CNN +F 2 "" H 9450 3000 60 0000 C CNN +F 3 "" H 9450 3000 60 0000 C CNN + 1 9400 3000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67B253AF +P 7500 2600 +F 0 "Q3" H 7400 2650 50 0000 R CNN +F 1 "eSim_NPN" H 7450 2750 50 0000 R CNN +F 2 "" H 7700 2700 29 0000 C CNN +F 3 "" H 7500 2600 60 0000 C CNN + 1 7500 2600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 67B253B5 +P 8500 3000 +F 0 "Q6" H 8400 3050 50 0000 R CNN +F 1 "eSim_NPN" H 8450 3150 50 0000 R CNN +F 2 "" H 8700 3100 29 0000 C CNN +F 3 "" H 8500 3000 60 0000 C CNN + 1 8500 3000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67B253BB +P 6650 2850 +F 0 "Q5" H 6550 2900 50 0000 R CNN +F 1 "eSim_NPN" H 6600 3000 50 0000 R CNN +F 2 "" H 6850 2950 29 0000 C CNN +F 3 "" H 6650 2850 60 0000 C CNN + 1 6650 2850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67B253CA +P 11050 2600 +F 0 "U1" H 11100 2700 30 0000 C CNN +F 1 "PORT" H 11050 2600 30 0000 C CNN +F 2 "" H 11050 2600 60 0000 C CNN +F 3 "" H 11050 2600 60 0000 C CNN + 6 11050 2600 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67B253D0 +P 11050 3000 +F 0 "U1" H 11100 3100 30 0000 C CNN +F 1 "PORT" H 11050 3000 30 0000 C CNN +F 2 "" H 11050 3000 60 0000 C CNN +F 3 "" H 11050 3000 60 0000 C CNN + 8 11050 3000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67B253E6 +P 5950 2550 +F 0 "U1" H 6000 2650 30 0000 C CNN +F 1 "PORT" H 5950 2550 30 0000 C CNN +F 2 "" H 5950 2550 60 0000 C CNN +F 3 "" H 5950 2550 60 0000 C CNN + 5 5950 2550 + 1 0 0 1 +$EndComp +$Comp +L GNDPWR #PWR03 +U 1 1 67B253FA +P 7550 4400 +F 0 "#PWR03" H 7550 4200 50 0001 C CNN +F 1 "GNDPWR" H 7550 4270 50 0000 C CNN +F 2 "" H 7550 4350 50 0001 C CNN +F 3 "" H 7550 4350 50 0001 C CNN + 1 7550 4400 + -1 0 0 -1 +$EndComp +$Comp +L resistor R14 +U 1 1 67B256A9 +P 9600 5050 +F 0 "R14" H 9650 5180 50 0000 C CNN +F 1 "20k" H 9650 5000 50 0000 C CNN +F 2 "" H 9650 5030 30 0000 C CNN +F 3 "" V 9650 5100 30 0000 C CNN + 1 9600 5050 + 0 -1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 67B256AF +P 8900 5050 +F 0 "R13" H 8950 5180 50 0000 C CNN +F 1 "10k" H 8950 5000 50 0000 C CNN +F 2 "" H 8950 5030 30 0000 C CNN +F 3 "" V 8950 5100 30 0000 C CNN + 1 8900 5050 + 0 -1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 67B256B5 +P 8150 5050 +F 0 "R12" H 8200 5180 50 0000 C CNN +F 1 "8k" H 8200 5000 50 0000 C CNN +F 2 "" H 8200 5030 30 0000 C CNN +F 3 "" V 8200 5100 30 0000 C CNN + 1 8150 5050 + 0 -1 1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 67B256BB +P 7950 6150 +F 0 "R16" H 8000 6280 50 0000 C CNN +F 1 "5k" H 8000 6100 50 0000 C CNN +F 2 "" H 8000 6130 30 0000 C CNN +F 3 "" V 8000 6200 30 0000 C CNN + 1 7950 6150 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 67B256C1 +P 8950 6750 +F 0 "D4" H 8950 6850 50 0000 C CNN +F 1 "eSim_Diode" H 8950 6650 50 0000 C CNN +F 2 "" H 8950 6750 60 0000 C CNN +F 3 "" H 8950 6750 60 0000 C CNN + 1 8950 6750 + 0 -1 1 0 +$EndComp +$Comp +L zener U16 +U 1 1 67B256C7 +P 10550 6900 +F 0 "U16" H 10500 6800 60 0000 C CNN +F 1 "zener" H 10550 7000 60 0000 C CNN +F 2 "" H 10600 6900 60 0000 C CNN +F 3 "" H 10600 6900 60 0000 C CNN + 1 10550 6900 + 0 1 -1 0 +$EndComp +$Comp +L zener U17 +U 1 1 67B256CD +P 11050 6950 +F 0 "U17" H 11000 6850 60 0000 C CNN +F 1 "zener" H 11050 7050 60 0000 C CNN +F 2 "" H 11100 6950 60 0000 C CNN +F 3 "" H 11100 6950 60 0000 C CNN + 1 11050 6950 + 0 1 -1 0 +$EndComp +$Comp +L zener U11 +U 1 1 67B256D3 +P 10050 5600 +F 0 "U11" H 10000 5500 60 0000 C CNN +F 1 "zener" H 10050 5700 60 0000 C CNN +F 2 "" H 10100 5600 60 0000 C CNN +F 3 "" H 10100 5600 60 0000 C CNN + 1 10050 5600 + 1 0 0 1 +$EndComp +$Comp +L zener U13 +U 1 1 67B256D9 +P 10100 6050 +F 0 "U13" H 10050 5950 60 0000 C CNN +F 1 "zener" H 10100 6150 60 0000 C CNN +F 2 "" H 10150 6050 60 0000 C CNN +F 3 "" H 10150 6050 60 0000 C CNN + 1 10100 6050 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 67B256DF +P 8200 5650 +F 0 "Q9" H 8100 5700 50 0000 R CNN +F 1 "eSim_NPN" H 8150 5800 50 0000 R CNN +F 2 "" H 8400 5750 29 0000 C CNN +F 3 "" H 8200 5650 60 0000 C CNN + 1 8200 5650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 67B256E5 +P 9200 6050 +F 0 "Q12" H 9100 6100 50 0000 R CNN +F 1 "eSim_NPN" H 9150 6200 50 0000 R CNN +F 2 "" H 9400 6150 29 0000 C CNN +F 3 "" H 9200 6050 60 0000 C CNN + 1 9200 6050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 67B256EB +P 7350 5900 +F 0 "Q11" H 7250 5950 50 0000 R CNN +F 1 "eSim_NPN" H 7300 6050 50 0000 R CNN +F 2 "" H 7550 6000 29 0000 C CNN +F 3 "" H 7350 5900 60 0000 C CNN + 1 7350 5900 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67B256FA +P 11750 5650 +F 0 "U1" H 11800 5750 30 0000 C CNN +F 1 "PORT" H 11750 5650 30 0000 C CNN +F 2 "" H 11750 5650 60 0000 C CNN +F 3 "" H 11750 5650 60 0000 C CNN + 12 11750 5650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67B25700 +P 11750 6050 +F 0 "U1" H 11800 6150 30 0000 C CNN +F 1 "PORT" H 11750 6050 30 0000 C CNN +F 2 "" H 11750 6050 60 0000 C CNN +F 3 "" H 11750 6050 60 0000 C CNN + 14 11750 6050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67B25716 +P 6650 5600 +F 0 "U1" H 6700 5700 30 0000 C CNN +F 1 "PORT" H 6650 5600 30 0000 C CNN +F 2 "" H 6650 5600 60 0000 C CNN +F 3 "" H 6650 5600 60 0000 C CNN + 11 6650 5600 + 1 0 0 1 +$EndComp +$Comp +L GNDPWR #PWR04 +U 1 1 67B2572A +P 8250 7450 +F 0 "#PWR04" H 8250 7250 50 0001 C CNN +F 1 "GNDPWR" H 8250 7320 50 0000 C CNN +F 2 "" H 8250 7400 50 0001 C CNN +F 3 "" H 8250 7400 50 0001 C CNN + 1 8250 7450 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2250 1650 4850 1650 +Connection ~ 2950 1650 +Wire Wire Line + 4850 1650 4850 1400 +Connection ~ 3700 1650 +Wire Wire Line + 2250 1950 2250 2750 +Wire Wire Line + 2250 2300 1950 2300 +Wire Wire Line + 1900 2750 2400 2750 +Connection ~ 2250 2300 +Connection ~ 2250 2750 +Wire Wire Line + 1450 2350 1450 2300 +Wire Wire Line + 750 3350 750 2350 +Connection ~ 750 2350 +Wire Wire Line + 1250 3300 1250 2750 +Connection ~ 1250 2750 +Wire Wire Line + 2700 2550 2700 2350 +Wire Wire Line + 2700 2350 3400 2350 +Wire Wire Line + 2950 1950 2950 2350 +Connection ~ 2950 2350 +Wire Wire Line + 3700 2150 3700 1950 +Wire Wire Line + 3700 2550 3900 2550 +Wire Wire Line + 3900 2550 3900 2750 +Wire Wire Line + 3900 2600 4250 2600 +Connection ~ 3900 2600 +Wire Wire Line + 4550 2400 4550 2300 +Wire Wire Line + 4550 2300 4900 2300 +Wire Wire Line + 4550 2800 4550 3950 +Wire Wire Line + 750 3950 6200 3950 +Wire Wire Line + 3900 3050 3900 3950 +Connection ~ 4550 3950 +Wire Wire Line + 2850 3600 2850 3950 +Connection ~ 3900 3950 +Wire Wire Line + 2850 3300 2850 2950 +Wire Wire Line + 2850 2950 2700 2950 +Wire Wire Line + 1250 3800 1250 3950 +Connection ~ 2850 3950 +Wire Wire Line + 750 3850 750 3950 +Connection ~ 1250 3950 +Wire Wire Line + 3550 4150 3550 3950 +Connection ~ 3550 3950 +Wire Wire Line + 3250 4650 6950 4650 +Connection ~ 3950 4650 +Wire Wire Line + 11250 4650 11250 4400 +Connection ~ 4700 4650 +Wire Wire Line + 3250 4950 3250 5750 +Wire Wire Line + 3250 5300 2950 5300 +Wire Wire Line + 2900 5750 3400 5750 +Connection ~ 3250 5300 +Connection ~ 3250 5750 +Wire Wire Line + 1300 5350 2450 5350 +Wire Wire Line + 2450 5350 2450 5300 +Wire Wire Line + 1300 5750 2400 5750 +Wire Wire Line + 1750 6350 1750 5350 +Connection ~ 1750 5350 +Wire Wire Line + 2250 6300 2250 5750 +Connection ~ 2250 5750 +Wire Wire Line + 3700 5550 3700 5350 +Wire Wire Line + 3700 5350 4400 5350 +Wire Wire Line + 3950 4950 3950 5350 +Connection ~ 3950 5350 +Wire Wire Line + 4700 5150 4700 4950 +Wire Wire Line + 4700 5550 4900 5550 +Wire Wire Line + 4900 5550 4900 5750 +Wire Wire Line + 4900 5600 5250 5600 +Connection ~ 4900 5600 +Wire Wire Line + 5550 5400 5550 5300 +Wire Wire Line + 5550 5300 5900 5300 +Wire Wire Line + 5550 5800 5550 6950 +Wire Wire Line + 1750 6950 6900 6950 +Wire Wire Line + 4900 6050 4900 6950 +Connection ~ 5550 6950 +Wire Wire Line + 3850 6600 3850 6950 +Connection ~ 4900 6950 +Wire Wire Line + 3850 6300 3850 5950 +Wire Wire Line + 3850 5950 3700 5950 +Wire Wire Line + 2250 6800 2250 6950 +Connection ~ 3850 6950 +Wire Wire Line + 1750 6850 1750 6950 +Connection ~ 2250 6950 +Wire Wire Line + 4550 7150 4550 6950 +Connection ~ 4550 6950 +Wire Wire Line + 6250 1900 8850 1900 +Connection ~ 8150 1900 +Wire Wire Line + 6250 1400 6250 1900 +Connection ~ 7400 1900 +Wire Wire Line + 8850 2200 8850 3000 +Wire Wire Line + 8850 2550 9150 2550 +Wire Wire Line + 9200 3000 8700 3000 +Connection ~ 8850 2550 +Connection ~ 8850 3000 +Wire Wire Line + 10800 2600 9650 2600 +Wire Wire Line + 9650 2600 9650 2550 +Wire Wire Line + 10800 3000 9700 3000 +Wire Wire Line + 10350 3600 10350 2600 +Connection ~ 10350 2600 +Wire Wire Line + 9850 3550 9850 3000 +Connection ~ 9850 3000 +Wire Wire Line + 8400 2800 8400 2600 +Wire Wire Line + 8400 2600 7700 2600 +Wire Wire Line + 8150 2200 8150 2600 +Connection ~ 8150 2600 +Wire Wire Line + 7400 2400 7400 2200 +Wire Wire Line + 7400 2800 7200 2800 +Wire Wire Line + 7200 2800 7200 3000 +Wire Wire Line + 7200 2850 6850 2850 +Connection ~ 7200 2850 +Wire Wire Line + 6550 2650 6550 2550 +Wire Wire Line + 6550 2550 6200 2550 +Wire Wire Line + 6550 3050 6550 4200 +Wire Wire Line + 10350 4200 6200 4200 +Wire Wire Line + 7200 3300 7200 4200 +Connection ~ 6550 4200 +Wire Wire Line + 8250 3850 8250 4200 +Connection ~ 7200 4200 +Wire Wire Line + 8250 3550 8250 3200 +Wire Wire Line + 8250 3200 8400 3200 +Wire Wire Line + 9850 4050 9850 4200 +Connection ~ 8250 4200 +Wire Wire Line + 10350 4100 10350 4200 +Connection ~ 9850 4200 +Wire Wire Line + 7550 4400 7550 4200 +Connection ~ 7550 4200 +Wire Wire Line + 6950 4950 9550 4950 +Connection ~ 8850 4950 +Wire Wire Line + 6950 4650 6950 4950 +Connection ~ 8100 4950 +Wire Wire Line + 9550 5250 9550 6050 +Wire Wire Line + 9550 5600 9850 5600 +Wire Wire Line + 9900 6050 9400 6050 +Connection ~ 9550 5600 +Connection ~ 9550 6050 +Wire Wire Line + 11500 5650 10350 5650 +Wire Wire Line + 10350 5650 10350 5600 +Wire Wire Line + 11500 6050 10400 6050 +Wire Wire Line + 11050 6650 11050 5650 +Connection ~ 11050 5650 +Wire Wire Line + 10550 6600 10550 6050 +Connection ~ 10550 6050 +Wire Wire Line + 9100 5850 9100 5650 +Wire Wire Line + 9100 5650 8400 5650 +Wire Wire Line + 8850 5250 8850 5650 +Connection ~ 8850 5650 +Wire Wire Line + 8100 5450 8100 5250 +Wire Wire Line + 8100 5850 7900 5850 +Wire Wire Line + 7900 5850 7900 6050 +Wire Wire Line + 7900 5900 7550 5900 +Connection ~ 7900 5900 +Wire Wire Line + 7250 5700 7250 5600 +Wire Wire Line + 7250 5600 6900 5600 +Wire Wire Line + 7250 6100 7250 7250 +Wire Wire Line + 11050 7250 6900 7250 +Wire Wire Line + 7900 6350 7900 7250 +Connection ~ 7250 7250 +Wire Wire Line + 8950 6900 8950 7250 +Connection ~ 7900 7250 +Wire Wire Line + 8950 6600 8950 6250 +Wire Wire Line + 8950 6250 9100 6250 +Wire Wire Line + 10550 7100 10550 7250 +Connection ~ 8950 7250 +Wire Wire Line + 11050 7150 11050 7250 +Connection ~ 10550 7250 +Wire Wire Line + 8250 7450 8250 7250 +Connection ~ 8250 7250 +Wire Wire Line + 4850 1400 6250 1400 +Wire Wire Line + 5700 850 5700 4650 +Connection ~ 5700 1400 +Connection ~ 5700 4650 +Wire Wire Line + 5700 850 6500 850 +Wire Wire Line + 6200 4200 6200 3950 +Wire Wire Line + 6900 7250 6900 6950 +Wire Wire Line + 6400 1250 6400 6950 +Connection ~ 6400 4200 +Connection ~ 6400 6950 +Wire Wire Line + 6950 1250 6400 1250 +Wire Wire Line + 650 2750 1400 2750 +Wire Wire Line + 650 2350 1450 2350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sub b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sub new file mode 100644 index 00000000..4d68cd2c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09__.sub @@ -0,0 +1,104 @@ +* Subcircuit sn74ls09__ +.subckt sn74ls09__ net-_r1-pad1_ gndpwr net-_q2-pad1_ net-_u1-pad4_ net-_q5-pad1_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_q8-pad1_ net-_u1-pad10_ net-_q11-pad1_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls09__\sn74ls09__.cir +.include NPN.lib +.include D.lib +r1 net-_r1-pad1_ net-_q4-pad2_ 20k +r2 net-_r1-pad1_ net-_q1-pad2_ 10k +r3 net-_r1-pad1_ net-_q1-pad1_ 8k +r7 net-_q1-pad3_ gndpwr 5k +d1 net-_d1-pad1_ gndpwr 1N4148 +* u6 gndpwr net-_u1-pad7_ zener +* u7 gndpwr net-_u1-pad4_ zener +* u2 net-_q4-pad2_ net-_u1-pad4_ zener +* u4 net-_q4-pad2_ net-_u1-pad7_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_q1-pad2_ net-_q4-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad3_ gndpwr Q2N2222 +r9 net-_r1-pad1_ net-_q10-pad2_ 20k +r10 net-_r1-pad1_ net-_q10-pad1_ 10k +r11 net-_r1-pad1_ net-_q7-pad1_ 8k +r15 net-_q7-pad3_ gndpwr 5k +d3 net-_d3-pad1_ gndpwr 1N4148 +* u14 gndpwr net-_u1-pad13_ zener +* u15 gndpwr net-_u1-pad10_ zener +* u10 net-_q10-pad2_ net-_u1-pad10_ zener +* u12 net-_q10-pad2_ net-_u1-pad13_ zener +q7 net-_q7-pad1_ net-_q10-pad1_ net-_q7-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d3-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_q7-pad3_ gndpwr Q2N2222 +r6 net-_r1-pad1_ net-_q6-pad2_ 20k +r5 net-_r1-pad1_ net-_q3-pad2_ 10k +r4 net-_r1-pad1_ net-_q3-pad1_ 8k +r8 net-_q3-pad3_ gndpwr 5k +d2 net-_d2-pad1_ gndpwr 1N4148 +* u8 gndpwr net-_u1-pad8_ zener +* u9 gndpwr net-_u1-pad6_ zener +* u3 net-_q6-pad2_ net-_u1-pad6_ zener +* u5 net-_q6-pad2_ net-_u1-pad8_ zener +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad2_ net-_q6-pad2_ net-_d2-pad1_ Q2N2222 +q5 net-_q5-pad1_ net-_q3-pad3_ gndpwr Q2N2222 +r14 net-_r1-pad1_ net-_q12-pad2_ 20k +r13 net-_r1-pad1_ net-_q12-pad1_ 10k +r12 net-_r1-pad1_ net-_q9-pad1_ 8k +r16 net-_q11-pad2_ gndpwr 5k +d4 net-_d4-pad1_ gndpwr 1N4148 +* u16 gndpwr net-_u1-pad14_ zener +* u17 gndpwr net-_u1-pad12_ zener +* u11 net-_q12-pad2_ net-_u1-pad12_ zener +* u13 net-_q12-pad2_ net-_u1-pad14_ zener +q9 net-_q9-pad1_ net-_q12-pad1_ net-_q11-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_d4-pad1_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ gndpwr Q2N2222 +a1 gndpwr net-_u1-pad7_ u6 +a2 gndpwr net-_u1-pad4_ u7 +a3 net-_q4-pad2_ net-_u1-pad4_ u2 +a4 net-_q4-pad2_ net-_u1-pad7_ u4 +a5 gndpwr net-_u1-pad13_ u14 +a6 gndpwr net-_u1-pad10_ u15 +a7 net-_q10-pad2_ net-_u1-pad10_ u10 +a8 net-_q10-pad2_ net-_u1-pad13_ u12 +a9 gndpwr net-_u1-pad8_ u8 +a10 gndpwr net-_u1-pad6_ u9 +a11 net-_q6-pad2_ net-_u1-pad6_ u3 +a12 net-_q6-pad2_ net-_u1-pad8_ u5 +a13 gndpwr net-_u1-pad14_ u16 +a14 gndpwr net-_u1-pad12_ u17 +a15 net-_q12-pad2_ net-_u1-pad12_ u11 +a16 net-_q12-pad2_ net-_u1-pad14_ u13 +* Schematic Name: zener, NgSpice Name: zener +.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends sn74ls09__ \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS09/sn74ls09___Previous_Values.xml b/library/SubcircuitLibrary/SN74LS09/sn74ls09___Previous_Values.xml new file mode 100644 index 00000000..6adb68b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS09/sn74ls09___Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecseczenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerzenerD:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib \ No newline at end of file -- cgit