From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/full_adder/half_adder.sub | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 library/SubcircuitLibrary/full_adder/half_adder.sub

(limited to 'library/SubcircuitLibrary/full_adder/half_adder.sub')

diff --git a/library/SubcircuitLibrary/full_adder/half_adder.sub b/library/SubcircuitLibrary/full_adder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/library/SubcircuitLibrary/full_adder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
\ No newline at end of file
-- 
cgit