From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/full_adder/full_adder.sub | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 library/SubcircuitLibrary/full_adder/full_adder.sub

(limited to 'library/SubcircuitLibrary/full_adder/full_adder.sub')

diff --git a/library/SubcircuitLibrary/full_adder/full_adder.sub b/library/SubcircuitLibrary/full_adder/full_adder.sub
new file mode 100644
index 00000000..5f261f78
--- /dev/null
+++ b/library/SubcircuitLibrary/full_adder/full_adder.sub
@@ -0,0 +1,13 @@
+* Subcircuit full_adder
+.subckt full_adder 8 7 5 4 1 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
+.include half_adder.sub
+x1 8 7 6 2 half_adder
+x2 5 6 4 3 half_adder
+* u2  3 2 1 d_or
+a1 [3 2 ] 1 u2
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends full_adder
\ No newline at end of file
-- 
cgit