From 524f8be6ff4b94f38c6df0f2fb1f45170de6b3c6 Mon Sep 17 00:00:00 2001 From: Aditya Minocha Date: Sun, 25 Aug 2024 21:21:21 +0530 Subject: SN74LV3T97EP IC - Configurable Multiple-Function Gate --- .../SN74LV3T97EP_Test/SN74LV3T97EP_Test.net | 211 +++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74LV3T97EP_Test/SN74LV3T97EP_Test.net (limited to 'library/SubcircuitLibrary/SN74LV3T97EP_Test/SN74LV3T97EP_Test.net') diff --git a/library/SubcircuitLibrary/SN74LV3T97EP_Test/SN74LV3T97EP_Test.net b/library/SubcircuitLibrary/SN74LV3T97EP_Test/SN74LV3T97EP_Test.net new file mode 100644 index 00000000..2e29095a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LV3T97EP_Test/SN74LV3T97EP_Test.net @@ -0,0 +1,211 @@ +(export (version D) + (design + (source C:/Users/Aditya/eSim-Workspace/SN74LV3T97EP_Test/SN74LV3T97EP_Test.sch) + (date "05/18/24 03:21:34") + (tool "Eeschema 4.0.7") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source SN74LV3T97EP_Test.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref X1) + (value SN74LV3T97-EP) + (libsource (lib eSim_Subckt) (part SN74LV3T97-EP)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474602)) + (comp (ref v1) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474795)) + (comp (ref v2) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 6647495E)) + (comp (ref v3) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 664749DA)) + (comp (ref v4) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474A0D)) + (comp (ref v5) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474A5A)) + (comp (ref v6) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474AAB)) + (comp (ref v7) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474AC8)) + (comp (ref v10) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474BDE)) + (comp (ref v9) + (value pulse) + (footprint R1) + (libsource (lib eSim_Sources) (part pulse)) + (sheetpath (names /) (tstamps /)) + (tstamp 66474C4C)) + (comp (ref v8) + (value DC) + (footprint R1) + (libsource (lib eSim_Sources) (part DC)) + (sheetpath (names /) (tstamps /)) + (tstamp 66476308)) + (comp (ref R1) + (value 1k) + (libsource (lib eSim_Devices) (part resistor)) + (sheetpath (names /) (tstamps /)) + (tstamp 6647D3AB)) + (comp (ref R2) + (value 1k) + (libsource (lib eSim_Devices) (part resistor)) + (sheetpath (names /) (tstamps /)) + (tstamp 6647D416)) + (comp (ref R3) + (value 1k) + (libsource (lib eSim_Devices) (part resistor)) + (sheetpath (names /) (tstamps /)) + (tstamp 6647D4A1))) + (libparts + (libpart (lib eSim_Sources) (part DC) + (footprints + (fp 1_pin)) + (fields + (field (name Reference) v) + (field (name Value) DC) + (field (name Footprint) R1)) + (pins + (pin (num 1) (name +) (type power_out)) + (pin (num 2) (name -) (type power_out)))) + (libpart (lib eSim_Subckt) (part SN74LV3T97-EP) + (fields + (field (name Reference) X) + (field (name Value) SN74LV3T97-EP)) + (pins + (pin (num 1) (name A1) (type input)) + (pin (num 2) (name B1) (type input)) + (pin (num 3) (name A2) (type input)) + (pin (num 4) (name B2) (type input)) + (pin (num 5) (name A3) (type input)) + (pin (num 6) (name B3) (type input)) + (pin (num 7) (name GND) (type input)) + (pin (num 8) (name Y3) (type output)) + (pin (num 9) (name C3) (type input)) + (pin (num 10) (name Y2) (type output)) + (pin (num 11) (name C2) (type input)) + (pin (num 12) (name Y1) (type output)) + (pin (num 13) (name C1) (type input)) + (pin (num 14) (name Vcc) (type input)))) + (libpart (lib eSim_Devices) (part eSim_R) + (aliases + (alias resistor)) + (footprints + (fp R_*) + (fp Resistor_*)) + (fields + (field (name Reference) R) + (field (name Value) eSim_R)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib eSim_Sources) (part pulse) + (footprints + (fp 1_pin)) + (fields + (field (name Reference) v) + (field (name Value) pulse) + (field (name Footprint) R1)) + (pins + (pin (num 1) (name +) (type passive)) + (pin (num 2) (name -) (type passive))))) + (libraries + (library (logical eSim_Devices) + (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Devices.lib)) + (library (logical eSim_Sources) + (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Sources.lib)) + (library (logical eSim_Subckt) + (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Subckt.lib))) + (nets + (net (code 1) (name "Net-(X1-Pad14)") + (node (ref X1) (pin 14)) + (node (ref v8) (pin 1))) + (net (code 2) (name OP_Y1) + (node (ref X1) (pin 12)) + (node (ref R1) (pin 1))) + (net (code 3) (name GND) + (node (ref v3) (pin 2)) + (node (ref R3) (pin 2)) + (node (ref X1) (pin 7)) + (node (ref v9) (pin 2)) + (node (ref v10) (pin 2)) + (node (ref v7) (pin 2)) + (node (ref v6) (pin 2)) + (node (ref v5) (pin 2)) + (node (ref v4) (pin 2)) + (node (ref v1) (pin 2)) + (node (ref v2) (pin 2)) + (node (ref R2) (pin 2)) + (node (ref v8) (pin 2)) + (node (ref R1) (pin 2))) + (net (code 4) (name OP_Y3) + (node (ref X1) (pin 8)) + (node (ref R3) (pin 1))) + (net (code 5) (name OP_Y2) + (node (ref R2) (pin 1)) + (node (ref X1) (pin 10))) + (net (code 6) (name IP_A3) + (node (ref X1) (pin 5)) + (node (ref v5) (pin 1))) + (net (code 7) (name IP_A1) + (node (ref X1) (pin 1)) + (node (ref v1) (pin 1))) + (net (code 8) (name IP_A2) + (node (ref X1) (pin 3)) + (node (ref v3) (pin 1))) + (net (code 9) (name IP_B1) + (node (ref X1) (pin 2)) + (node (ref v2) (pin 1))) + (net (code 10) (name IP_B2) + (node (ref v4) (pin 1)) + (node (ref X1) (pin 4))) + (net (code 11) (name IP_B3) + (node (ref v6) (pin 1)) + (node (ref X1) (pin 6))) + (net (code 12) (name IP_C1) + (node (ref X1) (pin 13)) + (node (ref v7) (pin 1))) + (net (code 13) (name IP_C2) + (node (ref v9) (pin 1)) + (node (ref X1) (pin 11))) + (net (code 14) (name IP_C3) + (node (ref X1) (pin 9)) + (node (ref v10) (pin 1))))) \ No newline at end of file -- cgit