From 5338d6a340e0fb746bcfa9b6184ee884c45ff44b Mon Sep 17 00:00:00 2001
From: Sumanto Kar
Date: Thu, 21 Nov 2024 21:32:11 +0530
Subject: SN74ALS280 is a parity generator/checker

---
 library/SubcircuitLibrary/SN74ALS280/4_and.cir.out | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN74ALS280/4_and.cir.out

(limited to 'library/SubcircuitLibrary/SN74ALS280/4_and.cir.out')

diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out
new file mode 100644
index 00000000..f40e5bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit