From 5338d6a340e0fb746bcfa9b6184ee884c45ff44b Mon Sep 17 00:00:00 2001
From: Sumanto Kar
Date: Thu, 21 Nov 2024 21:32:11 +0530
Subject: SN74ALS280 is a parity generator/checker

---
 library/SubcircuitLibrary/SN74ALS280/3_and.cir | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN74ALS280/3_and.cir

(limited to 'library/SubcircuitLibrary/SN74ALS280/3_and.cir')

diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.cir b/library/SubcircuitLibrary/SN74ALS280/3_and.cir
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
-- 
cgit