From 84061eca7de0c15700012c8627aade77c60a05c7 Mon Sep 17 00:00:00 2001
From: Sumanto Kar
Date: Tue, 19 Nov 2024 11:46:50 +0530
Subject: Subcircuit Files of ICs(Contributor: Sudheshna Prabakaran) (#285)

* Removed distutils dependency

shutil can be used in place of distutils .

* Integrated Schematic Converters (#271)

Add the files for the Schematic Converters(PSpice to KiCad and LTspice to KiCad converters) to eSim.

* SN7445 is a BCD-To-Decimal Decoders/Drivers

* LM323A is a 3.0 A Positive Voltage Regulator

* LM341 is a 500-mA, 35-V, linear voltage regulator

* LM384 is a power audio amplifier

* CA3140 Series Operational Amplifiers

* LM111, LM211, and LM311 devices are single high-speed voltage comparators

* 74HC688 is an 8-bit magnitude comparator

* 7483:4-BIT BINARY FULL ADDDERS WITH FAST CARRY

* LM102 series are high-gain operational amplifiers

* The LM110 - An Improved IC Voltage Follower

* LM123/LM323A/LM323-N 3-Amp, 5-Volt Positive Regulator

* LM384 is a power audio amplifier

---------

Co-authored-by: Abinash Singh <162575828+avinashlalotra@users.noreply.github.com>
Co-authored-by: SangaviGR <125533330+SangaviGR@users.noreply.github.com>---
 library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out

(limited to 'library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out')

diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit