From 37b9194b0d63f9b18e97892e63719c35dbac8dd7 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Sat, 17 Sep 2022 19:01:45 +0530
Subject: added sky130-fd-pr PDK and analog IPs

---
 .../SKY130_IP/avsddcp_1v8_sky130/.spiceinit        |  6 ++++
 .../avsddcp_1v8_sky130/avsddcp_1v8_sky130.sub      | 33 ++++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/.spiceinit
 create mode 100644 library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/avsddcp_1v8_sky130.sub

(limited to 'library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130')

diff --git a/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/.spiceinit b/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/.spiceinit
new file mode 100644
index 00000000..c0929e3c
--- /dev/null
+++ b/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/.spiceinit
@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa     ; set compatibility for reading PDK libs
+set ng_nomodcheck      ; don't check the model parameters 
+set num_threads=8      ; CPU hardware threads available
+option noinit          ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)
diff --git a/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/avsddcp_1v8_sky130.sub b/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/avsddcp_1v8_sky130.sub
new file mode 100644
index 00000000..c527aa8c
--- /dev/null
+++ b/library/SubcircuitLibrary/SKY130_IP/avsddcp_1v8_sky130/avsddcp_1v8_sky130.sub
@@ -0,0 +1,33 @@
+* ========================================= *
+* IP Core Name: avsddcp_3V3                 *
+* Tech Node: 130nm                          *
+* PDK : Sky130 PDK by Google SkyWater	    *
+* Name of the author : Charaan S            *
+* Company : VLSI System Design Corporation  * 
+* ========================================= *
+
+
+.subckt avsddcp_1v8_sky130 in clk1 clk2 out gnd
+
+* === SKY130 NMOS MODELS === *
+xm1 in in v1 gnd sky130_fd_pr__nfet_01v8 w=1 l=0.18
+xm2 v1 v1 v2 gnd sky130_fd_pr__nfet_01v8 w=1 l=0.18
+xm3 v2 v2 v3 gnd sky130_fd_pr__nfet_01v8 w=1 l=0.18
+xm4 v3 v3 v4 gnd sky130_fd_pr__nfet_01v8 w=1 l=0.18
+xm5 v4 v4 out gnd sky130_fd_pr__nfet_01v8 w=1 l=0.18
+
+
+* === SKY130 CAPACITOR MODELS === *
+xc1  v1 clk1 sky130_fd_pr__cap_mim_m3_1 w=1 l=100
+xc2  v2 clk2 sky130_fd_pr__cap_mim_m3_1 w=1 l=100
+xc3  v3 clk1 sky130_fd_pr__cap_mim_m3_1 w=1 l=100
+xc4  v4 clk2 sky130_fd_pr__cap_mim_m3_1 w=1 l=100
+xcout1  out gnd sky130_fd_pr__cap_mim_m3_1 w=1 l=100
+
+
+* === SKY130 RESISTOR MODEL === *
+*xr1  out gnd gnd sky130_fd_pr__res_high_po_0p69 l=100000
+
+.ends
+
+
-- 
cgit