From 3e72bb6782ca18e215f5e1647ac5efe2ec3dd128 Mon Sep 17 00:00:00 2001
From: Tanisha1511
Date: Sun, 18 May 2025 23:16:32 +0530
Subject: DM7447A as a BCD to 7 segment decoder/ driver IC

---
 library/SubcircuitLibrary/DM7447A/7447-cache.lib   |  162 +++
 library/SubcircuitLibrary/DM7447A/7447.cir         |   63 +
 library/SubcircuitLibrary/DM7447A/7447.cir.out     |  189 +++
 library/SubcircuitLibrary/DM7447A/7447.pro         |   83 ++
 library/SubcircuitLibrary/DM7447A/7447.sch         | 1224 ++++++++++++++++++++
 library/SubcircuitLibrary/DM7447A/7447.sub         |  183 +++
 .../DM7447A/7447_Previous_Values.xml               |    1 +
 library/SubcircuitLibrary/DM7447A/analysis         |    1 +
 8 files changed, 1906 insertions(+)
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447-cache.lib
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447.cir
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447.cir.out
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447.pro
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447.sch
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447.sub
 create mode 100644 library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml
 create mode 100644 library/SubcircuitLibrary/DM7447A/analysis

(limited to 'library/SubcircuitLibrary/DM7447A')

diff --git a/library/SubcircuitLibrary/DM7447A/7447-cache.lib b/library/SubcircuitLibrary/DM7447A/7447-cache.lib
new file mode 100644
index 00000000..a8a60642
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447-cache.lib
@@ -0,0 +1,162 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DM7447A/7447.cir b/library/SubcircuitLibrary/DM7447A/7447.cir
new file mode 100644
index 00000000..2def1963
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447.cir
@@ -0,0 +1,63 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\7447\7447.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/03/25 19:04:33
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U1-Pad1_ Net-_U1-Pad6_ Net-_U10-Pad1_ d_nand		
+U4  Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U11-Pad1_ d_nand		
+U5  Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U12-Pad1_ d_nand		
+U2  Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter		
+U6  Net-_U1-Pad7_ Net-_U6-Pad2_ d_inverter		
+X1  Net-_U1-Pad6_ Net-_U6-Pad2_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U33-Pad1_ 4_and		
+U9  Net-_U13-Pad1_ Net-_U10-Pad1_ Net-_U33-Pad2_ d_and		
+U10  Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U10-Pad3_ d_nand		
+U11  Net-_U11-Pad1_ Net-_U1-Pad5_ Net-_U11-Pad3_ d_nand		
+U12  Net-_U12-Pad1_ Net-_U1-Pad5_ Net-_U12-Pad3_ d_nand		
+U13  Net-_U13-Pad1_ Net-_U1-Pad5_ Net-_U13-Pad3_ d_nand		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+U14  Net-_U11-Pad3_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_and		
+U15  Net-_U10-Pad1_ Net-_U12-Pad3_ Net-_U15-Pad3_ d_and		
+X10  Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ ? 4_and		
+U16  Net-_U11-Pad3_ Net-_U13-Pad3_ Net-_U16-Pad3_ d_and		
+X2  Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U23-Pad2_ 3_and		
+X3  Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U36-Pad2_ 3_and		
+U17  Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_and		
+X4  Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U12-Pad1_ Net-_U27-Pad2_ 3_and		
+X5  Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U24-Pad1_ 3_and		
+X6  Net-_U10-Pad1_ Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U24-Pad2_ 3_and		
+X7  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U37-Pad2_ 3_and		
+U21  Net-_U10-Pad3_ Net-_U21-Pad2_ d_buffer		
+U18  Net-_U11-Pad1_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_and		
+U19  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U19-Pad3_ d_and		
+U20  Net-_U11-Pad3_ Net-_U12-Pad1_ Net-_U20-Pad3_ d_and		
+X8  Net-_U10-Pad3_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U38-Pad2_ 3_and		
+X9  Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U28-Pad1_ 3_and		
+X11  Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U1-Pad6_ Net-_U28-Pad2_ 4_and		
+U27  Net-_U17-Pad3_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nor		
+U26  Net-_U21-Pad2_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_nor		
+U28  Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nor		
+U22  Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U22-Pad3_ d_nor		
+U29  Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U29-Pad3_ d_nor		
+U35  Net-_U29-Pad3_ ? Net-_U35-Pad3_ d_nor		
+U23  Net-_U16-Pad3_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nor		
+U30  Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U30-Pad3_ d_nor		
+U36  Net-_U30-Pad3_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_nor		
+U24  Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_nor		
+U31  Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U31-Pad3_ d_nor		
+U37  Net-_U31-Pad3_ Net-_U37-Pad2_ Net-_U37-Pad3_ d_nor		
+U25  Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad3_ d_nor		
+U32  Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_nor		
+U38  Net-_U32-Pad3_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_nor		
+U33  Net-_U33-Pad1_ Net-_U33-Pad2_ Net-_U1-Pad5_ d_nand		
+U39  Net-_U35-Pad3_ Net-_U1-Pad8_ d_inverter		
+U40  Net-_U36-Pad3_ Net-_U1-Pad9_ d_inverter		
+U34  Net-_U27-Pad3_ Net-_U1-Pad10_ d_inverter		
+U41  Net-_U37-Pad3_ Net-_U1-Pad11_ d_inverter		
+U8  Net-_U26-Pad3_ Net-_U1-Pad12_ d_inverter		
+U42  Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter		
+U7  Net-_U28-Pad3_ Net-_U1-Pad14_ d_inverter		
+
+.end
diff --git a/library/SubcircuitLibrary/DM7447A/7447.cir.out b/library/SubcircuitLibrary/DM7447A/7447.cir.out
new file mode 100644
index 00000000..2090985a
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447.cir.out
@@ -0,0 +1,189 @@
+* c:\fossee\esim\library\subcircuitlibrary\7447\7447.cir
+
+.include 4_and.sub
+.include 3_and.sub
+* u3  net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand
+* u4  net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand
+* u5  net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand
+* u2  net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u6  net-_u1-pad7_ net-_u6-pad2_ d_inverter
+x1 net-_u1-pad6_ net-_u6-pad2_ net-_u11-pad1_ net-_u12-pad1_ net-_u33-pad1_ 4_and
+* u9  net-_u13-pad1_ net-_u10-pad1_ net-_u33-pad2_ d_and
+* u10  net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand
+* u11  net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand
+* u12  net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand
+* u13  net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+* u14  net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and
+* u15  net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and
+x10 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ ? 4_and
+* u16  net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and
+x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad2_ 3_and
+x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad2_ 3_and
+* u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and
+x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u27-pad2_ 3_and
+x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u24-pad1_ 3_and
+x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u24-pad2_ 3_and
+x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u37-pad2_ 3_and
+* u21  net-_u10-pad3_ net-_u21-pad2_ d_buffer
+* u18  net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and
+* u19  net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and
+* u20  net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and
+x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad2_ 3_and
+x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u28-pad1_ 3_and
+x11 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad2_ 4_and
+* u27  net-_u17-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nor
+* u26  net-_u21-pad2_ net-_u18-pad3_ net-_u26-pad3_ d_nor
+* u28  net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor
+* u22  net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor
+* u29  net-_u22-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor
+* u35  net-_u29-pad3_ ? net-_u35-pad3_ d_nor
+* u23  net-_u16-pad3_ net-_u23-pad2_ net-_u23-pad3_ d_nor
+* u30  net-_u23-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_nor
+* u36  net-_u30-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_nor
+* u24  net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u31  net-_u24-pad3_ net-_u24-pad3_ net-_u31-pad3_ d_nor
+* u37  net-_u31-pad3_ net-_u37-pad2_ net-_u37-pad3_ d_nor
+* u25  net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor
+* u32  net-_u25-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_nor
+* u38  net-_u32-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nor
+* u33  net-_u33-pad1_ net-_u33-pad2_ net-_u1-pad5_ d_nand
+* u39  net-_u35-pad3_ net-_u1-pad8_ d_inverter
+* u40  net-_u36-pad3_ net-_u1-pad9_ d_inverter
+* u34  net-_u27-pad3_ net-_u1-pad10_ d_inverter
+* u41  net-_u37-pad3_ net-_u1-pad11_ d_inverter
+* u8  net-_u26-pad3_ net-_u1-pad12_ d_inverter
+* u42  net-_u38-pad3_ net-_u1-pad13_ d_inverter
+* u7  net-_u28-pad3_ net-_u1-pad14_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u3
+a2 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u4
+a3 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u5
+a4 net-_u1-pad4_ net-_u13-pad1_ u2
+a5 net-_u1-pad7_ net-_u6-pad2_ u6
+a6 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u33-pad2_ u9
+a7 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10
+a8 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11
+a9 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12
+a10 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13
+a11 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14
+a12 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15
+a13 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a15 net-_u10-pad3_ net-_u21-pad2_ u21
+a16 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18
+a17 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19
+a18 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20
+a19 [net-_u17-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a20 [net-_u21-pad2_ net-_u18-pad3_ ] net-_u26-pad3_ u26
+a21 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a22 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a23 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29
+a24 [net-_u29-pad3_ ? ] net-_u35-pad3_ u35
+a25 [net-_u16-pad3_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a26 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u30-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a28 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a29 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u31-pad3_ u31
+a30 [net-_u31-pad3_ net-_u37-pad2_ ] net-_u37-pad3_ u37
+a31 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25
+a32 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a33 [net-_u32-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38
+a34 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u1-pad5_ u33
+a35 net-_u35-pad3_ net-_u1-pad8_ u39
+a36 net-_u36-pad3_ net-_u1-pad9_ u40
+a37 net-_u27-pad3_ net-_u1-pad10_ u34
+a38 net-_u37-pad3_ net-_u1-pad11_ u41
+a39 net-_u26-pad3_ net-_u1-pad12_ u8
+a40 net-_u38-pad3_ net-_u1-pad13_ u42
+a41 net-_u28-pad3_ net-_u1-pad14_ u7
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DM7447A/7447.pro b/library/SubcircuitLibrary/DM7447A/7447.pro
new file mode 100644
index 00000000..51d5ef29
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447.pro
@@ -0,0 +1,83 @@
+update=05/06/25 21:02:42
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/DM7447A/7447.sch b/library/SubcircuitLibrary/DM7447A/7447.sch
new file mode 100644
index 00000000..010bba39
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447.sch
@@ -0,0 +1,1224 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:7447-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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+Date ""
+Rev ""
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+F 0 "X7" H 6000 4350 60  0000 C CNN
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+F 2 "" H 5900 4400 60  0000 C CNN
+F 3 "" H 5900 4400 60  0000 C CNN
+	1    5900 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_buffer U21
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+P 6050 4800
+F 0 "U21" H 6050 4750 60  0000 C CNN
+F 1 "d_buffer" H 6050 4850 60  0000 C CNN
+F 2 "" H 6050 4800 60  0000 C CNN
+F 3 "" H 6050 4800 60  0000 C CNN
+	1    6050 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U18
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+P 6000 5250
+F 0 "U18" H 6000 5250 60  0000 C CNN
+F 1 "d_and" H 6050 5350 60  0000 C CNN
+F 2 "" H 6000 5250 60  0000 C CNN
+F 3 "" H 6000 5250 60  0000 C CNN
+	1    6000 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U19
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+P 6000 5500
+F 0 "U19" H 6000 5500 60  0000 C CNN
+F 1 "d_and" H 6050 5600 60  0000 C CNN
+F 2 "" H 6000 5500 60  0000 C CNN
+F 3 "" H 6000 5500 60  0000 C CNN
+	1    6000 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U20
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+P 6000 5750
+F 0 "U20" H 6000 5750 60  0000 C CNN
+F 1 "d_and" H 6050 5850 60  0000 C CNN
+F 2 "" H 6000 5750 60  0000 C CNN
+F 3 "" H 6000 5750 60  0000 C CNN
+	1    6000 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X8
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+P 5900 6100
+F 0 "X8" H 6000 6050 60  0000 C CNN
+F 1 "3_and" H 6050 6250 60  0000 C CNN
+F 2 "" H 5900 6100 60  0000 C CNN
+F 3 "" H 5900 6100 60  0000 C CNN
+	1    5900 6100
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X9
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+F 0 "X9" H 6000 6400 60  0000 C CNN
+F 1 "3_and" H 6050 6600 60  0000 C CNN
+F 2 "" H 5900 6450 60  0000 C CNN
+F 3 "" H 5900 6450 60  0000 C CNN
+	1    5900 6450
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_and X11
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+F 0 "X11" H 6000 6800 60  0000 C CNN
+F 1 "4_and" H 6050 6950 60  0000 C CNN
+F 2 "" H 5950 6850 60  0000 C CNN
+F 3 "" H 5950 6850 60  0000 C CNN
+	1    5950 6850
+	1    0    0    -1  
+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 0 "U27" H 7850 3200 60  0000 C CNN
+F 1 "d_nor" H 7900 3300 60  0000 C CNN
+F 2 "" H 7850 3200 60  0000 C CNN
+F 3 "" H 7850 3200 60  0000 C CNN
+	1    7850 3200
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+$EndComp
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+L d_nor U26
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+F 0 "U26" H 7800 5100 60  0000 C CNN
+F 1 "d_nor" H 7850 5200 60  0000 C CNN
+F 2 "" H 7800 5100 60  0000 C CNN
+F 3 "" H 7800 5100 60  0000 C CNN
+	1    7800 5100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U28
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+F 0 "U28" H 7900 6750 60  0000 C CNN
+F 1 "d_nor" H 7950 6850 60  0000 C CNN
+F 2 "" H 7900 6750 60  0000 C CNN
+F 3 "" H 7900 6750 60  0000 C CNN
+	1    7900 6750
+	1    0    0    -1  
+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+U 1 1 6807B01F
+P 7400 950
+F 0 "U22" H 7400 950 60  0000 C CNN
+F 1 "d_nor" H 7450 1050 60  0000 C CNN
+F 2 "" H 7400 950 60  0000 C CNN
+F 3 "" H 7400 950 60  0000 C CNN
+	1    7400 950 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U29
+U 1 1 6807B09C
+P 8550 900
+F 0 "U29" H 8550 900 60  0000 C CNN
+F 1 "d_nor" H 8600 1000 60  0000 C CNN
+F 2 "" H 8550 900 60  0000 C CNN
+F 3 "" H 8550 900 60  0000 C CNN
+	1    8550 900 
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U35
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+P 9000 1450
+F 0 "U35" H 9000 1450 60  0000 C CNN
+F 1 "d_nor" H 9050 1550 60  0000 C CNN
+F 2 "" H 9000 1450 60  0000 C CNN
+F 3 "" H 9000 1450 60  0000 C CNN
+	1    9000 1450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U23
+U 1 1 6807B65C
+P 7400 2100
+F 0 "U23" H 7400 2100 60  0000 C CNN
+F 1 "d_nor" H 7450 2200 60  0000 C CNN
+F 2 "" H 7400 2100 60  0000 C CNN
+F 3 "" H 7400 2100 60  0000 C CNN
+	1    7400 2100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U30
+U 1 1 6807B662
+P 8550 2050
+F 0 "U30" H 8550 2050 60  0000 C CNN
+F 1 "d_nor" H 8600 2150 60  0000 C CNN
+F 2 "" H 8550 2050 60  0000 C CNN
+F 3 "" H 8550 2050 60  0000 C CNN
+	1    8550 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U36
+U 1 1 6807B668
+P 9000 2600
+F 0 "U36" H 9000 2600 60  0000 C CNN
+F 1 "d_nor" H 9050 2700 60  0000 C CNN
+F 2 "" H 9000 2600 60  0000 C CNN
+F 3 "" H 9000 2600 60  0000 C CNN
+	1    9000 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U24
+U 1 1 6807B7A0
+P 7400 3800
+F 0 "U24" H 7400 3800 60  0000 C CNN
+F 1 "d_nor" H 7450 3900 60  0000 C CNN
+F 2 "" H 7400 3800 60  0000 C CNN
+F 3 "" H 7400 3800 60  0000 C CNN
+	1    7400 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U31
+U 1 1 6807B7A6
+P 8550 3750
+F 0 "U31" H 8550 3750 60  0000 C CNN
+F 1 "d_nor" H 8600 3850 60  0000 C CNN
+F 2 "" H 8550 3750 60  0000 C CNN
+F 3 "" H 8550 3750 60  0000 C CNN
+	1    8550 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U37
+U 1 1 6807B7AC
+P 9000 4300
+F 0 "U37" H 9000 4300 60  0000 C CNN
+F 1 "d_nor" H 9050 4400 60  0000 C CNN
+F 2 "" H 9000 4300 60  0000 C CNN
+F 3 "" H 9000 4300 60  0000 C CNN
+	1    9000 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U25
+U 1 1 6807BABC
+P 7400 5650
+F 0 "U25" H 7400 5650 60  0000 C CNN
+F 1 "d_nor" H 7450 5750 60  0000 C CNN
+F 2 "" H 7400 5650 60  0000 C CNN
+F 3 "" H 7400 5650 60  0000 C CNN
+	1    7400 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U32
+U 1 1 6807BAC2
+P 8550 5600
+F 0 "U32" H 8550 5600 60  0000 C CNN
+F 1 "d_nor" H 8600 5700 60  0000 C CNN
+F 2 "" H 8550 5600 60  0000 C CNN
+F 3 "" H 8550 5600 60  0000 C CNN
+	1    8550 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U38
+U 1 1 6807BAC8
+P 9000 6150
+F 0 "U38" H 9000 6150 60  0000 C CNN
+F 1 "d_nor" H 9050 6250 60  0000 C CNN
+F 2 "" H 9000 6150 60  0000 C CNN
+F 3 "" H 9000 6150 60  0000 C CNN
+	1    9000 6150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6807C68E
+P 10900 1400
+F 0 "U1" H 10950 1500 30  0000 C CNN
+F 1 "PORT" H 10900 1400 30  0000 C CNN
+F 2 "" H 10900 1400 60  0000 C CNN
+F 3 "" H 10900 1400 60  0000 C CNN
+	8    10900 1400
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6807D315
+P 10900 2550
+F 0 "U1" H 10950 2650 30  0000 C CNN
+F 1 "PORT" H 10900 2550 30  0000 C CNN
+F 2 "" H 10900 2550 60  0000 C CNN
+F 3 "" H 10900 2550 60  0000 C CNN
+	9    10900 2550
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6807D3B8
+P 10900 3150
+F 0 "U1" H 10950 3250 30  0000 C CNN
+F 1 "PORT" H 10900 3150 30  0000 C CNN
+F 2 "" H 10900 3150 60  0000 C CNN
+F 3 "" H 10900 3150 60  0000 C CNN
+	10   10900 3150
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6807D457
+P 10900 4250
+F 0 "U1" H 10950 4350 30  0000 C CNN
+F 1 "PORT" H 10900 4250 30  0000 C CNN
+F 2 "" H 10900 4250 60  0000 C CNN
+F 3 "" H 10900 4250 60  0000 C CNN
+	11   10900 4250
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6807D4F4
+P 10900 5050
+F 0 "U1" H 10950 5150 30  0000 C CNN
+F 1 "PORT" H 10900 5050 30  0000 C CNN
+F 2 "" H 10900 5050 60  0000 C CNN
+F 3 "" H 10900 5050 60  0000 C CNN
+	12   10900 5050
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6807D719
+P 10900 6100
+F 0 "U1" H 10950 6200 30  0000 C CNN
+F 1 "PORT" H 10900 6100 30  0000 C CNN
+F 2 "" H 10900 6100 60  0000 C CNN
+F 3 "" H 10900 6100 60  0000 C CNN
+	13   10900 6100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6807D7BA
+P 10900 6700
+F 0 "U1" H 10950 6800 30  0000 C CNN
+F 1 "PORT" H 10900 6700 30  0000 C CNN
+F 2 "" H 10900 6700 60  0000 C CNN
+F 3 "" H 10900 6700 60  0000 C CNN
+	14   10900 6700
+	-1   0    0    1   
+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2400 5300
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	1000 7000 1750 7000
+$Comp
+L d_nand U33
+U 1 1 6808DDE8
+P 2450 5800
+F 0 "U33" H 2450 5800 60  0000 C CNN
+F 1 "d_nand" H 2500 5900 60  0000 C CNN
+F 2 "" H 2450 5800 60  0000 C CNN
+F 3 "" H 2450 5800 60  0000 C CNN
+	1    2450 5800
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	1750 7300 2050 7300
+Wire Wire Line
+	1750 6400 1100 6400
+Connection ~ 1100 6400
+Connection ~ 1750 7000
+$Comp
+L d_inverter U39
+U 1 1 68161C40
+P 10050 1400
+F 0 "U39" H 10050 1300 60  0000 C CNN
+F 1 "d_inverter" H 10050 1550 60  0000 C CNN
+F 2 "" H 10100 1350 60  0000 C CNN
+F 3 "" H 10100 1350 60  0000 C CNN
+	1    10050 1400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9450 1400 9750 1400
+Wire Wire Line
+	10350 1400 10650 1400
+$Comp
+L d_inverter U40
+U 1 1 6816223F
+P 10050 2550
+F 0 "U40" H 10050 2450 60  0000 C CNN
+F 1 "d_inverter" H 10050 2700 60  0000 C CNN
+F 2 "" H 10100 2500 60  0000 C CNN
+F 3 "" H 10100 2500 60  0000 C CNN
+	1    10050 2550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9450 2550 9750 2550
+Wire Wire Line
+	10350 2550 10650 2550
+$Comp
+L d_inverter U34
+U 1 1 6816284C
+P 9800 3150
+F 0 "U34" H 9800 3050 60  0000 C CNN
+F 1 "d_inverter" H 9800 3300 60  0000 C CNN
+F 2 "" H 9850 3100 60  0000 C CNN
+F 3 "" H 9850 3100 60  0000 C CNN
+	1    9800 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8300 3150 9500 3150
+Wire Wire Line
+	10100 3150 10650 3150
+$Comp
+L d_inverter U41
+U 1 1 68162B94
+P 10050 4250
+F 0 "U41" H 10050 4150 60  0000 C CNN
+F 1 "d_inverter" H 10050 4400 60  0000 C CNN
+F 2 "" H 10100 4200 60  0000 C CNN
+F 3 "" H 10100 4200 60  0000 C CNN
+	1    10050 4250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9450 4250 9750 4250
+Wire Wire Line
+	10350 4250 10650 4250
+$Comp
+L d_inverter U8
+U 1 1 6816304F
+P 9700 5050
+F 0 "U8" H 9700 4950 60  0000 C CNN
+F 1 "d_inverter" H 9700 5200 60  0000 C CNN
+F 2 "" H 9750 5000 60  0000 C CNN
+F 3 "" H 9750 5000 60  0000 C CNN
+	1    9700 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8250 5050 9400 5050
+Wire Wire Line
+	10000 5050 10650 5050
+$Comp
+L d_inverter U42
+U 1 1 68163399
+P 10100 6100
+F 0 "U42" H 10100 6000 60  0000 C CNN
+F 1 "d_inverter" H 10100 6250 60  0000 C CNN
+F 2 "" H 10150 6050 60  0000 C CNN
+F 3 "" H 10150 6050 60  0000 C CNN
+	1    10100 6100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9450 6100 9800 6100
+Wire Wire Line
+	10400 6100 10650 6100
+$Comp
+L d_inverter U7
+U 1 1 681636FC
+P 9650 6700
+F 0 "U7" H 9650 6600 60  0000 C CNN
+F 1 "d_inverter" H 9650 6850 60  0000 C CNN
+F 2 "" H 9700 6650 60  0000 C CNN
+F 3 "" H 9700 6650 60  0000 C CNN
+	1    9650 6700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8350 6700 9350 6700
+Wire Wire Line
+	9950 6700 10650 6700
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DM7447A/7447.sub b/library/SubcircuitLibrary/DM7447A/7447.sub
new file mode 100644
index 00000000..8ca0b8b1
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447.sub
@@ -0,0 +1,183 @@
+* Subcircuit 7447
+.subckt 7447 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\7447\7447.cir
+.include 4_and.sub
+.include 3_and.sub
+* u3  net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand
+* u4  net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand
+* u5  net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand
+* u2  net-_u1-pad4_ net-_u13-pad1_ d_inverter
+* u6  net-_u1-pad7_ net-_u6-pad2_ d_inverter
+x1 net-_u1-pad6_ net-_u6-pad2_ net-_u11-pad1_ net-_u12-pad1_ net-_u33-pad1_ 4_and
+* u9  net-_u13-pad1_ net-_u10-pad1_ net-_u33-pad2_ d_and
+* u10  net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand
+* u11  net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand
+* u12  net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand
+* u13  net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand
+* u14  net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and
+* u15  net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and
+x10 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ ? 4_and
+* u16  net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and
+x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad2_ 3_and
+x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad2_ 3_and
+* u17  net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and
+x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u27-pad2_ 3_and
+x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u24-pad1_ 3_and
+x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u24-pad2_ 3_and
+x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u37-pad2_ 3_and
+* u21  net-_u10-pad3_ net-_u21-pad2_ d_buffer
+* u18  net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and
+* u19  net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and
+* u20  net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and
+x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad2_ 3_and
+x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u28-pad1_ 3_and
+x11 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad2_ 4_and
+* u27  net-_u17-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nor
+* u26  net-_u21-pad2_ net-_u18-pad3_ net-_u26-pad3_ d_nor
+* u28  net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor
+* u22  net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor
+* u29  net-_u22-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor
+* u35  net-_u29-pad3_ ? net-_u35-pad3_ d_nor
+* u23  net-_u16-pad3_ net-_u23-pad2_ net-_u23-pad3_ d_nor
+* u30  net-_u23-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_nor
+* u36  net-_u30-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_nor
+* u24  net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor
+* u31  net-_u24-pad3_ net-_u24-pad3_ net-_u31-pad3_ d_nor
+* u37  net-_u31-pad3_ net-_u37-pad2_ net-_u37-pad3_ d_nor
+* u25  net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor
+* u32  net-_u25-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_nor
+* u38  net-_u32-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nor
+* u33  net-_u33-pad1_ net-_u33-pad2_ net-_u1-pad5_ d_nand
+* u39  net-_u35-pad3_ net-_u1-pad8_ d_inverter
+* u40  net-_u36-pad3_ net-_u1-pad9_ d_inverter
+* u34  net-_u27-pad3_ net-_u1-pad10_ d_inverter
+* u41  net-_u37-pad3_ net-_u1-pad11_ d_inverter
+* u8  net-_u26-pad3_ net-_u1-pad12_ d_inverter
+* u42  net-_u38-pad3_ net-_u1-pad13_ d_inverter
+* u7  net-_u28-pad3_ net-_u1-pad14_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u3
+a2 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u4
+a3 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u5
+a4 net-_u1-pad4_ net-_u13-pad1_ u2
+a5 net-_u1-pad7_ net-_u6-pad2_ u6
+a6 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u33-pad2_ u9
+a7 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10
+a8 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11
+a9 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12
+a10 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13
+a11 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14
+a12 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15
+a13 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a15 net-_u10-pad3_ net-_u21-pad2_ u21
+a16 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18
+a17 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19
+a18 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20
+a19 [net-_u17-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27
+a20 [net-_u21-pad2_ net-_u18-pad3_ ] net-_u26-pad3_ u26
+a21 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a22 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22
+a23 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29
+a24 [net-_u29-pad3_ ? ] net-_u35-pad3_ u35
+a25 [net-_u16-pad3_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a26 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u30-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36
+a28 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24
+a29 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u31-pad3_ u31
+a30 [net-_u31-pad3_ net-_u37-pad2_ ] net-_u37-pad3_ u37
+a31 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25
+a32 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a33 [net-_u32-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38
+a34 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u1-pad5_ u33
+a35 net-_u35-pad3_ net-_u1-pad8_ u39
+a36 net-_u36-pad3_ net-_u1-pad9_ u40
+a37 net-_u27-pad3_ net-_u1-pad10_ u34
+a38 net-_u37-pad3_ net-_u1-pad11_ u41
+a39 net-_u26-pad3_ net-_u1-pad12_ u8
+a40 net-_u38-pad3_ net-_u1-pad13_ u42
+a41 net-_u28-pad3_ net-_u1-pad14_ u7
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 7447
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml b/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml
new file mode 100644
index 00000000..6a315fdb
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/7447_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u3 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u9><u8 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u7><u10 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_buffer<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u20><u27 name="type">d_nor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_nor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_nor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u28><u39 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u39><u34 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u33><u22 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u22><u29 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u29><u35 name="type">d_nor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u35><u40 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u40><u23 name="type">d_nor<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23><u30 name="type">d_nor<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u30><u36 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u36><u41 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u41><u24 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u24><u31 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u31><u37 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u37><u42 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u42><u25 name="type">d_nor<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u25><u32 name="type">d_nor<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u32><u38 name="type">d_nor<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u38><u43 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u43><u8 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u8><u39 name="type">d_buffer<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u39><u33 name="type">d_buffer<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u33><u33 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u33><u8 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x10><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x11></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM7447A/analysis b/library/SubcircuitLibrary/DM7447A/analysis
new file mode 100644
index 00000000..9b724012
--- /dev/null
+++ b/library/SubcircuitLibrary/DM7447A/analysis
@@ -0,0 +1 @@
+.tran 1e-03 20e-00 0e-03
\ No newline at end of file
-- 
cgit