From 044059f99adcc13c41252126c12cc6f7bbed6b5f Mon Sep 17 00:00:00 2001
From: Aditya Minocha
Date: Mon, 26 Aug 2024 00:25:40 +0530
Subject: CD4027B - CMOS Dual JK Flip Flop (failed)

---
 .../SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak | 862 +++++++++++++++++++++
 1 file changed, 862 insertions(+)
 create mode 100644 library/SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak

(limited to 'library/SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak')

diff --git a/library/SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak b/library/SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak
new file mode 100644
index 00000000..b441543a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4027B_IC/CD4027B_JK_FF.bak
@@ -0,0 +1,862 @@
+EESchema Schematic File Version 2
+LIBS:CD4027B_JK_FF-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4027B_JK_FF-cache
+EELAYER 25 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
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+Connection ~ 18400 17300
+Wire Wire Line
+	11200 13800 11200 17300
+Connection ~ 12850 17300
+Wire Wire Line
+	9850 12850 10300 12850
+Wire Wire Line
+	10300 12850 10300 17300
+Connection ~ 11200 17300
+Wire Wire Line
+	9800 13450 9800 17300
+Connection ~ 10300 17300
+Wire Wire Line
+	8850 16800 8850 17300
+Connection ~ 9800 17300
+Wire Wire Line
+	7850 16800 7850 17300
+Connection ~ 8850 17300
+Wire Wire Line
+	7850 15050 8450 15050
+Wire Wire Line
+	7850 15650 7850 16050
+Wire Wire Line
+	7850 16050 7500 16050
+Wire Wire Line
+	7500 11100 7500 17300
+Connection ~ 7850 17300
+Wire Wire Line
+	8100 15050 8100 13650
+Wire Wire Line
+	8100 13650 7850 13650
+Connection ~ 8100 15050
+Wire Wire Line
+	7850 14250 7500 14250
+Connection ~ 7500 16050
+Wire Wire Line
+	8150 12950 7500 12950
+Connection ~ 7500 14250
+Wire Wire Line
+	8200 10500 8200 11850
+Connection ~ 8200 10500
+Wire Wire Line
+	8900 10500 8900 9100
+Connection ~ 8900 10500
+Wire Wire Line
+	17050 17300 17050 18350
+Connection ~ 17050 17300
+$Comp
+L PORT U1
+U 8 1 665684DE
+P 8650 9100
+F 0 "U1" H 8700 9200 30  0000 C CNN
+F 1 "PORT" H 8650 9100 30  0000 C CNN
+F 2 "" H 8650 9100 60  0000 C CNN
+F 3 "" H 8650 9100 60  0000 C CNN
+	8    8650 9100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 665688E7
+P 16800 18350
+F 0 "U1" H 16850 18450 30  0000 C CNN
+F 1 "PORT" H 16800 18350 30  0000 C CNN
+F 2 "" H 16800 18350 60  0000 C CNN
+F 3 "" H 16800 18350 60  0000 C CNN
+	9    16800 18350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7850 11100 7500 11100
+Connection ~ 7500 12950
+Wire Wire Line
+	7850 16200 7850 16100
+Wire Wire Line
+	7850 16100 8250 16100
+Wire Wire Line
+	8250 16100 8250 16000
+Wire Wire Line
+	8250 16000 8850 16000
+Wire Wire Line
+	8850 16000 8850 16200
+Wire Wire Line
+	8450 15050 8450 16000
+Connection ~ 8450 16000
+Wire Wire Line
+	8050 13650 8050 13100
+Wire Wire Line
+	8050 13100 9150 13100
+Wire Wire Line
+	9150 13100 9150 10500
+Connection ~ 9150 10500
+Connection ~ 8050 13650
+$EndSCHEMATC
-- 
cgit