From 55568c864d1f19971c15c27df999ea161a07f366 Mon Sep 17 00:00:00 2001
From: Aditya Minocha
Date: Sun, 25 Aug 2024 19:12:57 +0530
Subject: CA3240 IC - Dual Operational Amplifier

---
 .../CA3240_IC_Test/CA3240_IC_Test-cache.lib        | 127 +++++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 library/SubcircuitLibrary/CA3240_IC_Test/CA3240_IC_Test-cache.lib

(limited to 'library/SubcircuitLibrary/CA3240_IC_Test/CA3240_IC_Test-cache.lib')

diff --git a/library/SubcircuitLibrary/CA3240_IC_Test/CA3240_IC_Test-cache.lib b/library/SubcircuitLibrary/CA3240_IC_Test/CA3240_IC_Test-cache.lib
new file mode 100644
index 00000000..ee416c5f
--- /dev/null
+++ b/library/SubcircuitLibrary/CA3240_IC_Test/CA3240_IC_Test-cache.lib
@@ -0,0 +1,127 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C3240_IC
+#
+DEF C3240_IC X 0 40 Y Y 1 F N
+F0 "X" 800 -50 60 H V C CNN
+F1 "C3240_IC" 800 800 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 700 750 0 0 0 0 1 0 N 700 750 700 750
+A 775 750 75 -1799 -1 0 1 0 N 700 750 850 750
+A 775 750 25 -1799 -1 0 1 0 N 750 750 800 750
+S 450 0 1100 750 0 1 0 N
+X Out_A 1 250 600 200 R 50 50 1 1 O
+X In(-)_A 2 250 450 200 R 50 50 1 1 I
+X In(+)_A 3 250 200 200 R 50 50 1 1 I
+X V- 4 250 50 200 R 50 50 1 1 I
+X V+ 5 1300 600 200 L 50 50 1 1 I
+X Out_B 6 1300 450 200 L 50 50 1 1 O
+X In(-)_B 7 1300 200 200 L 50 50 1 1 I
+X In(+)_B 8 1300 50 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
-- 
cgit