From 84061eca7de0c15700012c8627aade77c60a05c7 Mon Sep 17 00:00:00 2001
From: Sumanto Kar
Date: Tue, 19 Nov 2024 11:46:50 +0530
Subject: Subcircuit Files of ICs(Contributor: Sudheshna Prabakaran) (#285)

* Removed distutils dependency

shutil can be used in place of distutils .

* Integrated Schematic Converters (#271)

Add the files for the Schematic Converters(PSpice to KiCad and LTspice to KiCad converters) to eSim.

* SN7445 is a BCD-To-Decimal Decoders/Drivers

* LM323A is a 3.0 A Positive Voltage Regulator

* LM341 is a 500-mA, 35-V, linear voltage regulator

* LM384 is a power audio amplifier

* CA3140 Series Operational Amplifiers

* LM111, LM211, and LM311 devices are single high-speed voltage comparators

* 74HC688 is an 8-bit magnitude comparator

* 7483:4-BIT BINARY FULL ADDDERS WITH FAST CARRY

* LM102 series are high-gain operational amplifiers

* The LM110 - An Improved IC Voltage Follower

* LM123/LM323A/LM323-N 3-Amp, 5-Volt Positive Regulator

* LM384 is a power audio amplifier

---------

Co-authored-by: Abinash Singh <162575828+avinashlalotra@users.noreply.github.com>
Co-authored-by: SangaviGR <125533330+SangaviGR@users.noreply.github.com>---
 .../SubcircuitLibrary/74HC688_sub/74HC688_sub.sub  | 154 +++++++++++++++++++++
 1 file changed, 154 insertions(+)
 create mode 100644 library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub

(limited to 'library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub')

diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
new file mode 100644
index 00000000..68303a9d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
@@ -0,0 +1,154 @@
+* Subcircuit 74HC688_sub
+.subckt 74HC688_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ 
+* c:\fossee\esim\library\subcircuitlibrary\74hc688_sub\74hc688_sub.cir
+* u5  net-_u2-pad8_ net-_u22-pad1_ d_inverter
+* u6  net-_u2-pad9_ net-_u22-pad2_ d_inverter
+* u7  net-_u2-pad10_ net-_u23-pad1_ d_inverter
+* u8  net-_u2-pad11_ net-_u23-pad2_ d_inverter
+* u9  net-_u2-pad12_ net-_u24-pad1_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u15  net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u16  net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u17  net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18  net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19  net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u20  net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u21  net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22  net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_xnor
+* u24  net-_u24-pad1_ net-_u10-pad2_ net-_u24-pad3_ d_xnor
+* u25  net-_u11-pad2_ net-_u12-pad2_ net-_u25-pad3_ d_xnor
+* u26  net-_u13-pad2_ net-_u14-pad2_ net-_u26-pad3_ d_xnor
+* u27  net-_u15-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_xnor
+* u28  net-_u17-pad2_ net-_u18-pad2_ net-_u28-pad3_ d_xnor
+* u29  net-_u19-pad2_ net-_u20-pad2_ net-_u29-pad3_ d_xnor
+* u30  net-_u22-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_and
+* u31  net-_u24-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_and
+* u32  net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_and
+* u33  net-_u28-pad3_ net-_u29-pad3_ net-_u33-pad3_ d_and
+* u34  net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_and
+* u35  net-_u32-pad3_ net-_u33-pad3_ net-_u35-pad3_ d_and
+* u37  net-_u36-pad3_ net-_u21-pad2_ net-_u37-pad3_ d_nand
+* u36  net-_u34-pad3_ net-_u35-pad3_ net-_u36-pad3_ d_and
+* u38  net-_u37-pad3_ net-_u1-pad18_ dac_bridge_1
+* u2  net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ adc_bridge_7
+* u3  net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ adc_bridge_7
+* u4  net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ adc_bridge_3
+a1 net-_u2-pad8_ net-_u22-pad1_ u5
+a2 net-_u2-pad9_ net-_u22-pad2_ u6
+a3 net-_u2-pad10_ net-_u23-pad1_ u7
+a4 net-_u2-pad11_ net-_u23-pad2_ u8
+a5 net-_u2-pad12_ net-_u24-pad1_ u9
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad1_ net-_u11-pad2_ u11
+a8 net-_u12-pad1_ net-_u12-pad2_ u12
+a9 net-_u13-pad1_ net-_u13-pad2_ u13
+a10 net-_u14-pad1_ net-_u14-pad2_ u14
+a11 net-_u15-pad1_ net-_u15-pad2_ u15
+a12 net-_u16-pad1_ net-_u16-pad2_ u16
+a13 net-_u17-pad1_ net-_u17-pad2_ u17
+a14 net-_u18-pad1_ net-_u18-pad2_ u18
+a15 net-_u19-pad1_ net-_u19-pad2_ u19
+a16 net-_u20-pad1_ net-_u20-pad2_ u20
+a17 net-_u21-pad1_ net-_u21-pad2_ u21
+a18 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u24-pad1_ net-_u10-pad2_ ] net-_u24-pad3_ u24
+a21 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u26-pad3_ u26
+a23 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27
+a24 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u28-pad3_ u28
+a25 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u29-pad3_ u29
+a26 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32
+a29 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u33-pad3_ u33
+a30 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a31 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u35-pad3_ u35
+a32 [net-_u36-pad3_ net-_u21-pad2_ ] net-_u37-pad3_ u37
+a33 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u36-pad3_ u36
+a34 [net-_u37-pad3_ ] [net-_u1-pad18_ ] u38
+a35 [net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ ] [net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ ] u2
+a36 [net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ ] u3
+a37 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ ] u4
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u28 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_7, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_7, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_3, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC688_sub
\ No newline at end of file
-- 
cgit