From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/7485/c_gate.sub | 36 +++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 library/SubcircuitLibrary/7485/c_gate.sub

(limited to 'library/SubcircuitLibrary/7485/c_gate.sub')

diff --git a/library/SubcircuitLibrary/7485/c_gate.sub b/library/SubcircuitLibrary/7485/c_gate.sub
new file mode 100644
index 00000000..c6eaa478
--- /dev/null
+++ b/library/SubcircuitLibrary/7485/c_gate.sub
@@ -0,0 +1,36 @@
+* Subcircuit c_gate
+.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ 
+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
+.include 5_and.sub
+x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
+* u8  net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
+* u4  net-_u1-pad3_ net-_u4-pad2_ d_inverter
+* u5  net-_u1-pad4_ net-_u5-pad2_ d_inverter
+* u6  net-_u1-pad5_ net-_u6-pad2_ d_inverter
+* u7  net-_u1-pad6_ net-_u7-pad2_ d_inverter
+a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad2_ net-_u3-pad2_ u3
+a4 net-_u1-pad3_ net-_u4-pad2_ u4
+a5 net-_u1-pad4_ net-_u5-pad2_ u5
+a6 net-_u1-pad5_ net-_u6-pad2_ u6
+a7 net-_u1-pad6_ net-_u7-pad2_ u7
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends c_gate
\ No newline at end of file
-- 
cgit