From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/7485/5_and.sub | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 library/SubcircuitLibrary/7485/5_and.sub

(limited to 'library/SubcircuitLibrary/7485/5_and.sub')

diff --git a/library/SubcircuitLibrary/7485/5_and.sub b/library/SubcircuitLibrary/7485/5_and.sub
new file mode 100644
index 00000000..35b10e17
--- /dev/null
+++ b/library/SubcircuitLibrary/7485/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
-- 
cgit