From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/4to16_demux/5_nand.cir.out | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 library/SubcircuitLibrary/4to16_demux/5_nand.cir.out

(limited to 'library/SubcircuitLibrary/4to16_demux/5_nand.cir.out')

diff --git a/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out
new file mode 100644
index 00000000..164de911
--- /dev/null
+++ b/library/SubcircuitLibrary/4to16_demux/5_nand.cir.out
@@ -0,0 +1,18 @@
+* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir
+
+.include 5_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and
+* u2  net-_u2-pad1_ net-_u1-pad6_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 net-_u2-pad1_ net-_u1-pad6_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit