From 47d4daff2ab483c4cdfb82117ef0d25d53832214 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Fri, 21 Feb 2020 12:36:46 +0530
Subject: restructured eSim libraries

---
 library/SubcircuitLibrary/2bitmul/half_adder.cir | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 library/SubcircuitLibrary/2bitmul/half_adder.cir

(limited to 'library/SubcircuitLibrary/2bitmul/half_adder.cir')

diff --git a/library/SubcircuitLibrary/2bitmul/half_adder.cir b/library/SubcircuitLibrary/2bitmul/half_adder.cir
new file mode 100644
index 00000000..8b2e7e06
--- /dev/null
+++ b/library/SubcircuitLibrary/2bitmul/half_adder.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2  1 4 3 d_xor		
+U3  1 4 2 d_and		
+U1  1 4 3 2 PORT		
+
+.end
-- 
cgit