From dfc268e0863c913a1b8726cd54eea3b40caf7c67 Mon Sep 17 00:00:00 2001
From: rahulp13
Date: Tue, 3 Mar 2020 05:31:58 +0530
Subject: upgrade ngspice to v31

---
 Windows/spice/examples/vdmos/VDMOS-DIO.cir | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Windows/spice/examples/vdmos/VDMOS-DIO.cir

(limited to 'Windows/spice/examples/vdmos/VDMOS-DIO.cir')

diff --git a/Windows/spice/examples/vdmos/VDMOS-DIO.cir b/Windows/spice/examples/vdmos/VDMOS-DIO.cir
new file mode 100644
index 00000000..9b9d4e17
--- /dev/null
+++ b/Windows/spice/examples/vdmos/VDMOS-DIO.cir
@@ -0,0 +1,27 @@
+Capacitance and current comparison between models d and bulk diode in vdmos
+
+D1 ad kd dio
+.model dio d TT=1371n IS=2.13E-08 N=1.564 RS=0.0038 m=0.548 Vj=0.1 Cjo=3200pF
+
+Va ad 0 dc 0 pwl(0 -2 2.5 0.5)
+Vk kd 0 0
+
+m1 d g s IXTP6N100D2
+.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
+
+Vd d 0 dc 0 pwl(0 2 2.5 -0.5)
+Vg g 0 -5  $ transistor is off
+Vs s 0 0
+
+.tran 10m 2.5
+
+.control
+save @d1[cd] @m1[cds] all
+run
+plot abs(i(Vk)) abs(i(Vs)) ylog
+plot @d1[cd] @m1[cds]
+*plot abs(i(Vk)) - abs(i(Vs))
+*plot @d1[cd] - @m1[cds]
+.endc
+
+.end
-- 
cgit