From e9064e423b586c2a31926fb5a1e582e8d1f626f8 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Tue, 12 Mar 2019 12:00:58 +0530
Subject: fix file permissions
---
Examples/BJT_Biascircuit/NPN.lib | 0
Examples/BJT_CB_config/NPN.lib | 0
Examples/BJT_CE_config/NPN.lib | 0
Examples/BJT_Frequency_Response/NPN.lib | 0
Examples/BJT_amplifier/NPN.lib | 0
Examples/CMOS_Inverter/NMOS-180nm.lib | 0
Examples/CMOS_Inverter/PMOS-180nm.lib | 0
Examples/Clampercircuit/D.lib | 0
Examples/Clippercircuit/D.lib | 0
Examples/Diode_characteristics/D.lib | 0
Examples/FET_Amplifier/NJF.lib | 0
Examples/FET_Characteristic/NJF.lib | 0
Examples/FrequencyResponse_JFET/NJF.lib | 0
Examples/FullwaveRectifier_SCR/D.lib | 0
Examples/Fullwavebridgerectifier/D.lib | 0
Examples/HalfwaveRectifier_SCR/D.lib | 0
Examples/Halfwave_Rectifier/D.lib | 0
Examples/Integrator/D.lib | 0
Examples/InvertingAmplifier/D.lib | 0
Examples/Zener_Characteristic/ZenerD1N750.lib | 0
20 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 Examples/BJT_Biascircuit/NPN.lib
mode change 100755 => 100644 Examples/BJT_CB_config/NPN.lib
mode change 100755 => 100644 Examples/BJT_CE_config/NPN.lib
mode change 100755 => 100644 Examples/BJT_Frequency_Response/NPN.lib
mode change 100755 => 100644 Examples/BJT_amplifier/NPN.lib
mode change 100755 => 100644 Examples/CMOS_Inverter/NMOS-180nm.lib
mode change 100755 => 100644 Examples/CMOS_Inverter/PMOS-180nm.lib
mode change 100755 => 100644 Examples/Clampercircuit/D.lib
mode change 100755 => 100644 Examples/Clippercircuit/D.lib
mode change 100755 => 100644 Examples/Diode_characteristics/D.lib
mode change 100755 => 100644 Examples/FET_Amplifier/NJF.lib
mode change 100755 => 100644 Examples/FET_Characteristic/NJF.lib
mode change 100755 => 100644 Examples/FrequencyResponse_JFET/NJF.lib
mode change 100755 => 100644 Examples/FullwaveRectifier_SCR/D.lib
mode change 100755 => 100644 Examples/Fullwavebridgerectifier/D.lib
mode change 100755 => 100644 Examples/HalfwaveRectifier_SCR/D.lib
mode change 100755 => 100644 Examples/Halfwave_Rectifier/D.lib
mode change 100755 => 100644 Examples/Integrator/D.lib
mode change 100755 => 100644 Examples/InvertingAmplifier/D.lib
mode change 100755 => 100644 Examples/Zener_Characteristic/ZenerD1N750.lib
(limited to 'Examples')
diff --git a/Examples/BJT_Biascircuit/NPN.lib b/Examples/BJT_Biascircuit/NPN.lib
old mode 100755
new mode 100644
diff --git a/Examples/BJT_CB_config/NPN.lib b/Examples/BJT_CB_config/NPN.lib
old mode 100755
new mode 100644
diff --git a/Examples/BJT_CE_config/NPN.lib b/Examples/BJT_CE_config/NPN.lib
old mode 100755
new mode 100644
diff --git a/Examples/BJT_Frequency_Response/NPN.lib b/Examples/BJT_Frequency_Response/NPN.lib
old mode 100755
new mode 100644
diff --git a/Examples/BJT_amplifier/NPN.lib b/Examples/BJT_amplifier/NPN.lib
old mode 100755
new mode 100644
diff --git a/Examples/CMOS_Inverter/NMOS-180nm.lib b/Examples/CMOS_Inverter/NMOS-180nm.lib
old mode 100755
new mode 100644
diff --git a/Examples/CMOS_Inverter/PMOS-180nm.lib b/Examples/CMOS_Inverter/PMOS-180nm.lib
old mode 100755
new mode 100644
diff --git a/Examples/Clampercircuit/D.lib b/Examples/Clampercircuit/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Clippercircuit/D.lib b/Examples/Clippercircuit/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Diode_characteristics/D.lib b/Examples/Diode_characteristics/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/FET_Amplifier/NJF.lib b/Examples/FET_Amplifier/NJF.lib
old mode 100755
new mode 100644
diff --git a/Examples/FET_Characteristic/NJF.lib b/Examples/FET_Characteristic/NJF.lib
old mode 100755
new mode 100644
diff --git a/Examples/FrequencyResponse_JFET/NJF.lib b/Examples/FrequencyResponse_JFET/NJF.lib
old mode 100755
new mode 100644
diff --git a/Examples/FullwaveRectifier_SCR/D.lib b/Examples/FullwaveRectifier_SCR/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Fullwavebridgerectifier/D.lib b/Examples/Fullwavebridgerectifier/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/HalfwaveRectifier_SCR/D.lib b/Examples/HalfwaveRectifier_SCR/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Halfwave_Rectifier/D.lib b/Examples/Halfwave_Rectifier/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Integrator/D.lib b/Examples/Integrator/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/InvertingAmplifier/D.lib b/Examples/InvertingAmplifier/D.lib
old mode 100755
new mode 100644
diff --git a/Examples/Zener_Characteristic/ZenerD1N750.lib b/Examples/Zener_Characteristic/ZenerD1N750.lib
old mode 100755
new mode 100644
--
cgit
From 5e116a4676854289fabeb6cce57f3d01ae8f5709 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Mon, 11 Mar 2019 12:11:24 +0530
Subject: remove temporary files
---
Examples/4_bit_JK_ff/4_bit_JK_ff.bak | 767 ---------------------
Examples/BJT_Biascircuit/BJT_Biascircuit.bak | 168 -----
Examples/BJT_CB_config/BJT_CB_config.bak | 171 -----
Examples/BJT_CE_config/BJT_CE_config.bak | 167 -----
.../BJT_Frequency_Response.net | 211 ------
Examples/BJT_amplifier/BJT_amplifier | 0
Examples/BJT_amplifier/BJT_amplifier-cache.bak | 133 ----
Examples/BJT_amplifier/BJT_amplifier.bak | 306 --------
Examples/BJT_amplifier/BJT_amplifier.cir.ckt | 20 -
Examples/BasicGates/BasicGates-cache.bak | 324 ---------
Examples/BasicGates/BasicGates.bak | 422 ------------
Examples/BasicGates/BasicGates.cir.ckt | 59 --
Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp | Bin 12288 -> 0 bytes
Examples/CMOS_Inverter/CMOS_Inverter-cache.bak | 118 ----
Examples/CMOS_Inverter/CMOS_Inverter.bak | 257 -------
Examples/CMOS_Inverter/NMOS-180nm.lib | 13 -
Examples/CMOS_Inverter/PMOS-180nm.lib | 11 -
Examples/CMOS_Inverter/b3v32check.log | 6 -
Examples/Clampercircuit/Clampercircuit.bak | 207 ------
Examples/Clippercircuit/Clippercircuit.bak | 145 ----
Examples/Diac_Triac/.triac.s.swp | Bin 4096 -> 0 bytes
Examples/Diac_Triac/.triac.sub.swp | Bin 12288 -> 0 bytes
Examples/Diac_Triac/diac-cache.lib | 67 --
Examples/Diac_Triac/diac.bak | 138 ----
Examples/Diac_Triac/diac.cir.ckt | 9 -
Examples/Diac_Triac/diac.cir.out~ | 24 -
Examples/Diac_Triac/diac.sub~ | 18 -
Examples/Diac_Triac/diac_Previous_Values.xml | 1 -
Examples/Diac_Triac/triac.bak | 308 ---------
Examples/Diac_Triac/triac.cir.ckt | 26 -
Examples/Diac_Triac/triac.cir.out~ | 41 --
Examples/Diac_Triac/triac.sub~ | 35 -
Examples/Diac_Triac/triac_Previous_Values.xml | 1 -
Examples/Differentiator/Differentiator.bak | 197 ------
Examples/Differentiator/ua741-cache.bak | 100 ---
Examples/Differentiator/ua741.bak | 208 ------
Examples/Differentiator/ua741.cir.ckt | 9 -
Examples/Differentiator/ua741_Previous_Values.xml | 1 -
.../Diode_characteristics.bak | 142 ----
Examples/FET_Amplifier/FET_Amplifier.bak | 200 ------
Examples/FET_Characteristic/FET_Characteristic.bak | 127 ----
.../FrequencyResponse_JFET/FrequencyResponse_JFET | 0
.../FrequencyResponse_JFET.bak | 231 -------
.../FrequencyResponse_JFET.cir (copy).out | 30 -
Examples/FullAdder/FullAdder-cache.lib | 116 ----
Examples/FullAdder/FullAdder.bak | 328 ---------
Examples/FullAdder/full_adder-cache.lib | 61 --
Examples/FullAdder/full_adder_Previous_Values.xml | 1 -
Examples/FullAdder/half_adder-cache.lib | 63 --
Examples/FullAdder/half_adder_Previous_Values.xml | 1 -
.../FullwaveRectifier_SCR-cache.lib | 156 -----
.../FullwaveRectifier_SCR.bak | 280 --------
Examples/FullwaveRectifier_SCR/scr.bak | 243 -------
Examples/FullwaveRectifier_SCR/scr.cir.ckt | 19 -
Examples/FullwaveRectifier_SCR/scr.cir.out~ | 29 -
Examples/FullwaveRectifier_SCR/scr.sub~ | 23 -
.../FullwaveRectifier_SCR/scr_Previous_Values.xml | 1 -
.../Fullwavebridgerectifier.bak | 221 ------
Examples/Half_Adder/Half_Adder.bak | 260 -------
Examples/Half_Adder/_saved_half_adder.sch | 154 -----
Examples/Half_Adder/half_adder-cache.lib | 63 --
Examples/Half_Adder/half_adder.bak | 152 ----
Examples/HalfwaveRectifier_SCR/D.lib | 20 -
.../HalfwaveRectifier_SCR-cache.lib | 134 ----
.../HalfwaveRectifier_SCR.bak | 201 ------
Examples/HalfwaveRectifier_SCR/scr.bak | 243 -------
Examples/HalfwaveRectifier_SCR/scr.cir.ckt | 19 -
Examples/HalfwaveRectifier_SCR/scr.cir.out~ | 29 -
Examples/HalfwaveRectifier_SCR/scr.sub~ | 23 -
Examples/Halfwave_Rectifier/Halfwave_Rectifier.bak | 215 ------
Examples/High_Pass_Filter/High_Pass_Filter.bak | 122 ----
Examples/Integrator/.Integrator.cir.out.swp | Bin 12288 -> 0 bytes
Examples/Integrator/D.lib | 20 -
Examples/Integrator/Integrator.bak | 202 ------
Examples/Integrator/PowerDiode.lib | 20 -
Examples/Integrator/scr.cir.out~ | 29 -
Examples/Integrator/scr.sub~ | 23 -
Examples/Integrator/ua741-cache.bak | 100 ---
Examples/Integrator/ua741.bak | 208 ------
Examples/Integrator/ua741.cir.ckt | 9 -
Examples/Integrator/ua741_Previous_Values.xml | 1 -
Examples/InvertingAmplifier/D.lib | 20 -
Examples/InvertingAmplifier/InvertingAmplifier.bak | 184 -----
Examples/InvertingAmplifier/PowerDiode.lib | 20 -
Examples/InvertingAmplifier/scr.cir.out~ | 29 -
Examples/InvertingAmplifier/scr.sub~ | 23 -
Examples/InvertingAmplifier/ua741-cache.bak | 100 ---
Examples/InvertingAmplifier/ua741.bak | 208 ------
Examples/InvertingAmplifier/ua741.cir.ckt | 9 -
.../InvertingAmplifier/ua741_Previous_Values.xml | 1 -
Examples/JK_Flipflop/JK_Flipflop-cache.lib | 155 -----
Examples/JK_Flipflop/JK_Flipflop.bak | 396 -----------
Examples/Low_Pass_Filter/Low_Pass_Filter.bak | 122 ----
Examples/Parallel_Resonance/Parallel_Resonance.bak | 162 -----
Examples/RC/RC.bak | 123 ----
Examples/RL/RL.bak | 128 ----
Examples/RLC/RLC.bak | 141 ----
Examples/Series_Resonance/Series_Resonance.bak | 141 ----
Examples/Zener_Characteristic/ZenerD1N750.lib | 3 -
.../Zener_Characteristic-cache.lib | 96 ---
.../Zener_Characteristic/Zener_Characteristic.bak | 156 -----
101 files changed, 11424 deletions(-)
delete mode 100644 Examples/4_bit_JK_ff/4_bit_JK_ff.bak
delete mode 100644 Examples/BJT_Biascircuit/BJT_Biascircuit.bak
delete mode 100644 Examples/BJT_CB_config/BJT_CB_config.bak
delete mode 100644 Examples/BJT_CE_config/BJT_CE_config.bak
delete mode 100644 Examples/BJT_Frequency_Response/BJT_Frequency_Response.net
delete mode 100644 Examples/BJT_amplifier/BJT_amplifier
delete mode 100644 Examples/BJT_amplifier/BJT_amplifier-cache.bak
delete mode 100644 Examples/BJT_amplifier/BJT_amplifier.bak
delete mode 100644 Examples/BJT_amplifier/BJT_amplifier.cir.ckt
delete mode 100644 Examples/BasicGates/BasicGates-cache.bak
delete mode 100644 Examples/BasicGates/BasicGates.bak
delete mode 100644 Examples/BasicGates/BasicGates.cir.ckt
delete mode 100644 Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp
delete mode 100644 Examples/CMOS_Inverter/CMOS_Inverter-cache.bak
delete mode 100644 Examples/CMOS_Inverter/CMOS_Inverter.bak
delete mode 100644 Examples/CMOS_Inverter/NMOS-180nm.lib
delete mode 100644 Examples/CMOS_Inverter/PMOS-180nm.lib
delete mode 100644 Examples/CMOS_Inverter/b3v32check.log
delete mode 100644 Examples/Clampercircuit/Clampercircuit.bak
delete mode 100644 Examples/Clippercircuit/Clippercircuit.bak
delete mode 100644 Examples/Diac_Triac/.triac.s.swp
delete mode 100644 Examples/Diac_Triac/.triac.sub.swp
delete mode 100644 Examples/Diac_Triac/diac-cache.lib
delete mode 100644 Examples/Diac_Triac/diac.bak
delete mode 100644 Examples/Diac_Triac/diac.cir.ckt
delete mode 100644 Examples/Diac_Triac/diac.cir.out~
delete mode 100644 Examples/Diac_Triac/diac.sub~
delete mode 100644 Examples/Diac_Triac/diac_Previous_Values.xml
delete mode 100644 Examples/Diac_Triac/triac.bak
delete mode 100644 Examples/Diac_Triac/triac.cir.ckt
delete mode 100644 Examples/Diac_Triac/triac.cir.out~
delete mode 100644 Examples/Diac_Triac/triac.sub~
delete mode 100644 Examples/Diac_Triac/triac_Previous_Values.xml
delete mode 100644 Examples/Differentiator/Differentiator.bak
delete mode 100644 Examples/Differentiator/ua741-cache.bak
delete mode 100644 Examples/Differentiator/ua741.bak
delete mode 100644 Examples/Differentiator/ua741.cir.ckt
delete mode 100644 Examples/Differentiator/ua741_Previous_Values.xml
delete mode 100644 Examples/Diode_characteristics/Diode_characteristics.bak
delete mode 100644 Examples/FET_Amplifier/FET_Amplifier.bak
delete mode 100644 Examples/FET_Characteristic/FET_Characteristic.bak
delete mode 100644 Examples/FrequencyResponse_JFET/FrequencyResponse_JFET
delete mode 100644 Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.bak
delete mode 100644 Examples/FrequencyResponse_JFET/FrequencyResponse_JFET.cir (copy).out
delete mode 100644 Examples/FullAdder/FullAdder-cache.lib
delete mode 100644 Examples/FullAdder/FullAdder.bak
delete mode 100644 Examples/FullAdder/full_adder-cache.lib
delete mode 100644 Examples/FullAdder/full_adder_Previous_Values.xml
delete mode 100644 Examples/FullAdder/half_adder-cache.lib
delete mode 100644 Examples/FullAdder/half_adder_Previous_Values.xml
delete mode 100644 Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR-cache.lib
delete mode 100644 Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.bak
delete mode 100644 Examples/FullwaveRectifier_SCR/scr.bak
delete mode 100644 Examples/FullwaveRectifier_SCR/scr.cir.ckt
delete mode 100644 Examples/FullwaveRectifier_SCR/scr.cir.out~
delete mode 100644 Examples/FullwaveRectifier_SCR/scr.sub~
delete mode 100644 Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml
delete mode 100644 Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.bak
delete mode 100644 Examples/Half_Adder/Half_Adder.bak
delete mode 100644 Examples/Half_Adder/_saved_half_adder.sch
delete mode 100644 Examples/Half_Adder/half_adder-cache.lib
delete mode 100755 Examples/Half_Adder/half_adder.bak
delete mode 100644 Examples/HalfwaveRectifier_SCR/D.lib
delete mode 100644 Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR-cache.lib
delete mode 100644 Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR.bak
delete mode 100644 Examples/HalfwaveRectifier_SCR/scr.bak
delete mode 100644 Examples/HalfwaveRectifier_SCR/scr.cir.ckt
delete mode 100644 Examples/HalfwaveRectifier_SCR/scr.cir.out~
delete mode 100644 Examples/HalfwaveRectifier_SCR/scr.sub~
delete mode 100644 Examples/Halfwave_Rectifier/Halfwave_Rectifier.bak
delete mode 100644 Examples/High_Pass_Filter/High_Pass_Filter.bak
delete mode 100644 Examples/Integrator/.Integrator.cir.out.swp
delete mode 100644 Examples/Integrator/D.lib
delete mode 100644 Examples/Integrator/Integrator.bak
delete mode 100644 Examples/Integrator/PowerDiode.lib
delete mode 100644 Examples/Integrator/scr.cir.out~
delete mode 100644 Examples/Integrator/scr.sub~
delete mode 100644 Examples/Integrator/ua741-cache.bak
delete mode 100644 Examples/Integrator/ua741.bak
delete mode 100644 Examples/Integrator/ua741.cir.ckt
delete mode 100644 Examples/Integrator/ua741_Previous_Values.xml
delete mode 100644 Examples/InvertingAmplifier/D.lib
delete mode 100644 Examples/InvertingAmplifier/InvertingAmplifier.bak
delete mode 100644 Examples/InvertingAmplifier/PowerDiode.lib
delete mode 100644 Examples/InvertingAmplifier/scr.cir.out~
delete mode 100644 Examples/InvertingAmplifier/scr.sub~
delete mode 100644 Examples/InvertingAmplifier/ua741-cache.bak
delete mode 100644 Examples/InvertingAmplifier/ua741.bak
delete mode 100644 Examples/InvertingAmplifier/ua741.cir.ckt
delete mode 100644 Examples/InvertingAmplifier/ua741_Previous_Values.xml
delete mode 100644 Examples/JK_Flipflop/JK_Flipflop-cache.lib
delete mode 100644 Examples/JK_Flipflop/JK_Flipflop.bak
delete mode 100644 Examples/Low_Pass_Filter/Low_Pass_Filter.bak
delete mode 100644 Examples/Parallel_Resonance/Parallel_Resonance.bak
delete mode 100644 Examples/RC/RC.bak
delete mode 100644 Examples/RL/RL.bak
delete mode 100644 Examples/RLC/RLC.bak
delete mode 100644 Examples/Series_Resonance/Series_Resonance.bak
delete mode 100644 Examples/Zener_Characteristic/ZenerD1N750.lib
delete mode 100644 Examples/Zener_Characteristic/Zener_Characteristic-cache.lib
delete mode 100644 Examples/Zener_Characteristic/Zener_Characteristic.bak
(limited to 'Examples')
diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.bak b/Examples/4_bit_JK_ff/4_bit_JK_ff.bak
deleted file mode 100644
index 36be9ab8..00000000
--- a/Examples/4_bit_JK_ff/4_bit_JK_ff.bak
+++ /dev/null
@@ -1,767 +0,0 @@
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-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:4_bit_JK_ff-cache
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deleted file mode 100644
index db6cd27d..00000000
--- a/Examples/BJT_CE_config/BJT_CE_config.bak
+++ /dev/null
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diff --git a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.net b/Examples/BJT_Frequency_Response/BJT_Frequency_Response.net
deleted file mode 100644
index 8108d16b..00000000
--- a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.net
+++ /dev/null
@@ -1,211 +0,0 @@
-(export (version D)
- (design
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\ No newline at end of file
diff --git a/Examples/BJT_amplifier/BJT_amplifier b/Examples/BJT_amplifier/BJT_amplifier
deleted file mode 100644
index e69de29b..00000000
diff --git a/Examples/BJT_amplifier/BJT_amplifier-cache.bak b/Examples/BJT_amplifier/BJT_amplifier-cache.bak
deleted file mode 100644
index a2c30517..00000000
--- a/Examples/BJT_amplifier/BJT_amplifier-cache.bak
+++ /dev/null
@@ -1,133 +0,0 @@
-EESchema-LIBRARY Version 2.3 Date: Tuesday 04 June 2013 10:39:51 PM IST
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-#
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-$FPLIST
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-F1 "GND" 0 -70 30 H I C CNN
-DRAW
-P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
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-DRAW
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-DRAW
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-ENDDRAW
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-$FPLIST
- R?
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- R?-*
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-DRAW
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-X + 1 0 -300 200 U 40 40 1 1 I
-X + 2 0 -300 200 U 40 40 2 1 I
-X + 3 0 -300 200 U 40 40 3 1 I
-X + 4 0 -300 200 U 40 40 4 1 I
-X + 5 0 -300 200 U 40 40 5 1 I
-X + 6 0 -300 200 U 40 40 6 1 I
-X + 7 0 -300 200 U 40 40 7 1 I
-X + 8 0 -300 200 U 40 40 8 1 I
-ENDDRAW
-ENDDEF
-#
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diff --git a/Examples/BJT_amplifier/BJT_amplifier.bak b/Examples/BJT_amplifier/BJT_amplifier.bak
deleted file mode 100644
index ec5aa4fc..00000000
--- a/Examples/BJT_amplifier/BJT_amplifier.bak
+++ /dev/null
@@ -1,306 +0,0 @@
-EESchema Schematic File Version 2
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diff --git a/Examples/BasicGates/BasicGates.cir.ckt b/Examples/BasicGates/BasicGates.cir.ckt
deleted file mode 100644
index 59b85ffa..00000000
--- a/Examples/BasicGates/BasicGates.cir.ckt
+++ /dev/null
@@ -1,59 +0,0 @@
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-r3 8 0 1000
-v2 8 0 pulse(0 5 0 0 0 2 20)
-r2 9 0 1000
-r1 4 0 1000
-v1 4 0 pulse(5 0 0 0 0 2 20)
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-a2 [6] [6_in] u12adc
-a3 [5_in 6_in] 9_out u12
-a4 [9_out] [9] u12dac
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-.model u12adc adc_bridge(in_low=0.8 in_high=2.0)
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-a5 [8] [8_in] u8adc
-a6 [4] [4_in] u8adc
-a7 [8_in 4_in] 10_out u8
-a8 [10_out] [10] u8dac
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-a9 [8] [8_in] u7adc
-a10 [4] [4_in] u7adc
-a11 [8_in 4_in] 2_out u7
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-a13 [2] [2_in] u9adc
-a14 [10] [10_in] u9adc
-a15 [2_in 10_in] 7_out u9
-a16 [7_out] [7] u9dac
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-a17 [7] [7_in] u11adc
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-
-.tran 10e-09 1e-06 0e-00
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diff --git a/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp b/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp
deleted file mode 100644
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deleted file mode 100644
index 40de879d..00000000
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diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.bak b/Examples/CMOS_Inverter/CMOS_Inverter.bak
deleted file mode 100644
index 5d83811f..00000000
--- a/Examples/CMOS_Inverter/CMOS_Inverter.bak
+++ /dev/null
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-EESchema Schematic File Version 2
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-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
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-LIBS:contrib
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diff --git a/Examples/CMOS_Inverter/NMOS-180nm.lib b/Examples/CMOS_Inverter/NMOS-180nm.lib
deleted file mode 100644
index 51e9b119..00000000
--- a/Examples/CMOS_Inverter/NMOS-180nm.lib
+++ /dev/null
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-.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
-+ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
-+ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
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diff --git a/Examples/CMOS_Inverter/PMOS-180nm.lib b/Examples/CMOS_Inverter/PMOS-180nm.lib
deleted file mode 100644
index 032b5b95..00000000
--- a/Examples/CMOS_Inverter/PMOS-180nm.lib
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-.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
-+ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
-+ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
-+ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
-+ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
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-+ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
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diff --git a/Examples/CMOS_Inverter/b3v32check.log b/Examples/CMOS_Inverter/b3v32check.log
deleted file mode 100644
index b08de179..00000000
--- a/Examples/CMOS_Inverter/b3v32check.log
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-BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4)
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diff --git a/Examples/Diac_Triac/diac.cir.out~ b/Examples/Diac_Triac/diac.cir.out~
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index 89cc8142..00000000
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diff --git a/Examples/Diac_Triac/diac.sub~ b/Examples/Diac_Triac/diac.sub~
deleted file mode 100644
index 43c2d279..00000000
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+++ /dev/null
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\ No newline at end of file
diff --git a/Examples/Diac_Triac/diac_Previous_Values.xml b/Examples/Diac_Triac/diac_Previous_Values.xml
deleted file mode 100644
index 96df431c..00000000
--- a/Examples/Diac_Triac/diac_Previous_Values.xml
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deleted file mode 100644
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diff --git a/Examples/Diac_Triac/triac.sub~ b/Examples/Diac_Triac/triac.sub~
deleted file mode 100644
index ebbed05e..00000000
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diff --git a/Examples/FullAdder/full_adder-cache.lib b/Examples/FullAdder/full_adder-cache.lib
deleted file mode 100644
index 623a7f41..00000000
--- a/Examples/FullAdder/full_adder-cache.lib
+++ /dev/null
@@ -1,61 +0,0 @@
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-F3 "" 0 0 60 H V C CNN
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-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
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-#
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-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
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diff --git a/Examples/FullAdder/full_adder_Previous_Values.xml b/Examples/FullAdder/full_adder_Previous_Values.xml
deleted file mode 100644
index b63184d6..00000000
--- a/Examples/FullAdder/full_adder_Previous_Values.xml
+++ /dev/null
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--- a/Examples/FullwaveRectifier_SCR/scr.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
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diff --git a/Examples/FullwaveRectifier_SCR/scr.cir.out~ b/Examples/FullwaveRectifier_SCR/scr.cir.out~
deleted file mode 100644
index d600f25d..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.cir.out~
+++ /dev/null
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diff --git a/Examples/FullwaveRectifier_SCR/scr.sub~ b/Examples/FullwaveRectifier_SCR/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.sub~
+++ /dev/null
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\ No newline at end of file
diff --git a/Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml b/Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml
deleted file mode 100644
index 8ff6e8d3..00000000
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-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# plot_i2
-#
-DEF plot_i2 U 0 40 Y Y 1 F N
-F0 "U" 0 400 60 H V C CNN
-F1 "plot_i2" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 250 100 0 1 0 N
-X + 1 -300 250 200 R 50 50 1 1 I
-X - 2 300 250 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# plot_v1
-#
-DEF plot_v1 U 0 40 Y Y 1 F N
-F0 "U" 0 500 60 H V C CNN
-F1 "plot_v1" 200 350 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 500 100 0 1 0 N
-X ~ ~ 0 200 200 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# zener
-#
-DEF zener U 0 40 Y Y 1 F N
-F0 "U" -50 -100 60 H V C CNN
-F1 "zener" 0 100 60 H V C CNN
-F2 "" 50 0 60 H V C CNN
-F3 "" 50 0 60 H V C CNN
-DRAW
-P 2 0 1 0 100 -50 50 -100 N
-P 2 0 1 0 100 50 100 -50 N
-P 2 0 1 0 100 50 150 100 N
-P 4 0 1 0 0 50 0 -50 100 0 0 50 N
-X ~ IN -200 0 200 R 50 43 1 1 I
-X ~ OUT 300 0 200 L 50 43 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Zener_Characteristic/Zener_Characteristic.bak b/Examples/Zener_Characteristic/Zener_Characteristic.bak
deleted file mode 100644
index 941a0cbc..00000000
--- a/Examples/Zener_Characteristic/Zener_Characteristic.bak
+++ /dev/null
@@ -1,156 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L DC v1
-U 1 1 56C6E03A
-P 5350 3750
-F 0 "v1" H 5150 3850 60 0000 C CNN
-F 1 "DC" H 5150 3700 60 0000 C CNN
-F 2 "R1" H 5050 3750 60 0000 C CNN
-F 3 "" H 5350 3750 60 0000 C CNN
- 1 5350 3750
- 1 0 0 -1
-$EndComp
-$Comp
-L R R1
-U 1 1 56C6E09D
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-F 0 "R1" H 5700 3380 50 0000 C CNN
-F 1 "1k" H 5700 3300 50 0000 C CNN
-F 2 "" H 5700 3230 30 0000 C CNN
-F 3 "" V 5700 3300 30 0000 C CNN
- 1 5650 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L GND #PWR01
-U 1 1 56C6E0D8
-P 6050 4300
-F 0 "#PWR01" H 6050 4050 50 0001 C CNN
-F 1 "GND" H 6050 4150 50 0000 C CNN
-F 2 "" H 6050 4300 50 0000 C CNN
-F 3 "" H 6050 4300 50 0000 C CNN
- 1 6050 4300
- 1 0 0 -1
-$EndComp
-Text GLabel 5300 3100 0 60 Input ~ 0
-in
-Text GLabel 6750 3050 2 60 Input ~ 0
-out
-$Comp
-L plot_i2 U2
-U 1 1 56C6E2C8
-P 6200 3450
-F 0 "U2" H 6200 3850 60 0000 C CNN
-F 1 "plot_i2" H 6200 3550 60 0000 C CNN
-F 2 "" H 6200 3450 60 0000 C CNN
-F 3 "" H 6200 3450 60 0000 C CNN
- 1 6200 3450
- -1 0 0 -1
-$EndComp
-$Comp
-L plot_v1 U3
-U 1 1 56C6E4F3
-P 6550 3200
-F 0 "U3" H 6550 3700 60 0000 C CNN
-F 1 "plot_v1" H 6750 3550 60 0000 C CNN
-F 2 "" H 6550 3200 60 0000 C CNN
-F 3 "" H 6550 3200 60 0000 C CNN
- 1 6550 3200
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5350 3300 5350 3200
-Wire Wire Line
- 6600 3200 6600 3650
-Wire Wire Line
- 5350 4200 5350 4250
-Wire Wire Line
- 5350 4250 6600 4250
-Wire Wire Line
- 6050 4300 6050 4250
-Connection ~ 6050 4250
-Wire Wire Line
- 5300 3100 5450 3100
-Wire Wire Line
- 5450 3100 5450 3200
-Connection ~ 5450 3200
-Wire Wire Line
- 6550 3000 6550 3200
-Connection ~ 6550 3200
-Wire Wire Line
- 6600 4250 6600 4050
-Wire Wire Line
- 5350 3200 5550 3200
-Wire Wire Line
- 5850 3200 5900 3200
-Wire Wire Line
- 6500 3200 6600 3200
-Wire Wire Line
- 6750 3050 6750 3100
-Wire Wire Line
- 6750 3100 6550 3100
-Connection ~ 6550 3100
-$Comp
-L ZENER D1
-U 1 1 56C6EA01
-P 6600 3850
-F 0 "D1" H 6600 3950 50 0000 C CNN
-F 1 "ZENER" H 6600 3750 50 0000 C CNN
-F 2 "" H 6600 3850 50 0000 C CNN
-F 3 "" H 6600 3850 50 0000 C CNN
- 1 6600 3850
- 0 1 1 0
-$EndComp
-$EndSCHEMATC
--
cgit
From ef380a4a6a2ff4c90bde90c41296e94f5db70389 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Mon, 11 Mar 2019 15:57:40 +0530
Subject: Half adder subcircuit filename conflict in Windows
Replaced Half_Adder example with renamed HalfAdder to avoid Windows
case-only filename difference conflict with subcircuit half_adder.
Based on contribution by https://github.com/MaxOLydian/eSim
---
Examples/HalfAdder/HalfAdder-cache.lib | 126 ++++++++++++
Examples/HalfAdder/HalfAdder-rescue.lib | 17 ++
Examples/HalfAdder/HalfAdder.cir | 21 ++
Examples/HalfAdder/HalfAdder.cir.out | 33 ++++
Examples/HalfAdder/HalfAdder.pro | 74 +++++++
Examples/HalfAdder/HalfAdder.proj | 1 +
Examples/HalfAdder/HalfAdder.sch | 313 ++++++++++++++++++++++++++++++
Examples/HalfAdder/analysis | 1 +
Examples/HalfAdder/half_adder.cir | 11 ++
Examples/HalfAdder/half_adder.cir.out | 20 ++
Examples/HalfAdder/half_adder.pro | 69 +++++++
Examples/HalfAdder/half_adder.sch | 152 +++++++++++++++
Examples/HalfAdder/half_adder.sub | 14 ++
Examples/HalfAdder/plot_data_i.txt | 135 +++++++++++++
Examples/HalfAdder/plot_data_v.txt | 135 +++++++++++++
Examples/Half_Adder/Half_Adder-cache.lib | 126 ------------
Examples/Half_Adder/Half_Adder-rescue.lib | 17 --
Examples/Half_Adder/Half_Adder.cir | 21 --
Examples/Half_Adder/Half_Adder.cir.out | 33 ----
Examples/Half_Adder/Half_Adder.pro | 74 -------
Examples/Half_Adder/Half_Adder.proj | 1 -
Examples/Half_Adder/Half_Adder.sch | 313 ------------------------------
Examples/Half_Adder/analysis | 1 -
Examples/Half_Adder/half_adder.cir | 11 --
Examples/Half_Adder/half_adder.cir.out | 20 --
Examples/Half_Adder/half_adder.pro | 69 -------
Examples/Half_Adder/half_adder.sch | 152 ---------------
Examples/Half_Adder/half_adder.sub | 14 --
Examples/Half_Adder/plot_data_i.txt | 135 -------------
Examples/Half_Adder/plot_data_v.txt | 135 -------------
30 files changed, 1122 insertions(+), 1122 deletions(-)
create mode 100644 Examples/HalfAdder/HalfAdder-cache.lib
create mode 100644 Examples/HalfAdder/HalfAdder-rescue.lib
create mode 100644 Examples/HalfAdder/HalfAdder.cir
create mode 100644 Examples/HalfAdder/HalfAdder.cir.out
create mode 100644 Examples/HalfAdder/HalfAdder.pro
create mode 100644 Examples/HalfAdder/HalfAdder.proj
create mode 100644 Examples/HalfAdder/HalfAdder.sch
create mode 100644 Examples/HalfAdder/analysis
create mode 100644 Examples/HalfAdder/half_adder.cir
create mode 100644 Examples/HalfAdder/half_adder.cir.out
create mode 100644 Examples/HalfAdder/half_adder.pro
create mode 100644 Examples/HalfAdder/half_adder.sch
create mode 100644 Examples/HalfAdder/half_adder.sub
create mode 100644 Examples/HalfAdder/plot_data_i.txt
create mode 100644 Examples/HalfAdder/plot_data_v.txt
delete mode 100644 Examples/Half_Adder/Half_Adder-cache.lib
delete mode 100644 Examples/Half_Adder/Half_Adder-rescue.lib
delete mode 100644 Examples/Half_Adder/Half_Adder.cir
delete mode 100644 Examples/Half_Adder/Half_Adder.cir.out
delete mode 100644 Examples/Half_Adder/Half_Adder.pro
delete mode 100644 Examples/Half_Adder/Half_Adder.proj
delete mode 100644 Examples/Half_Adder/Half_Adder.sch
delete mode 100644 Examples/Half_Adder/analysis
delete mode 100644 Examples/Half_Adder/half_adder.cir
delete mode 100644 Examples/Half_Adder/half_adder.cir.out
delete mode 100644 Examples/Half_Adder/half_adder.pro
delete mode 100644 Examples/Half_Adder/half_adder.sch
delete mode 100644 Examples/Half_Adder/half_adder.sub
delete mode 100644 Examples/Half_Adder/plot_data_i.txt
delete mode 100644 Examples/Half_Adder/plot_data_v.txt
(limited to 'Examples')
diff --git a/Examples/HalfAdder/HalfAdder-cache.lib b/Examples/HalfAdder/HalfAdder-cache.lib
new file mode 100644
index 00000000..e9fd9411
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND-RESCUE-HalfAdder
+#
+DEF ~GND-RESCUE-HalfAdder #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND-RESCUE-HalfAdder" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/HalfAdder/HalfAdder-rescue.lib b/Examples/HalfAdder/HalfAdder-rescue.lib
new file mode 100644
index 00000000..8a92f392
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder-rescue.lib
@@ -0,0 +1,17 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND-RESCUE-HalfAdder
+#
+DEF ~GND-RESCUE-HalfAdder #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND-RESCUE-HalfAdder" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/HalfAdder/HalfAdder.cir b/Examples/HalfAdder/HalfAdder.cir
new file mode 100644
index 00000000..51b78f4e
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.cir
@@ -0,0 +1,21 @@
+* /home/fossee/UpdatedExamples/HalfAdder/HalfAdder.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 21:35:33 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder
+U1 IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2
+v1 IN1 GND DC
+v2 IN2 GND DC
+R1 sum GND 1k
+R2 cout GND 1k
+U3 IN1 plot_v1
+U4 IN2 plot_v1
+U5 sum plot_v1
+U6 cout plot_v1
+
+.end
diff --git a/Examples/HalfAdder/HalfAdder.cir.out b/Examples/HalfAdder/HalfAdder.cir.out
new file mode 100644
index 00000000..96066fff
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.cir.out
@@ -0,0 +1,33 @@
+* /home/fossee/updatedexamples/half_adder/half_adder.cir
+
+.include half_adder.sub
+x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
+* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
+v1 in1 gnd dc 5
+v2 in2 gnd dc 0
+r1 sum gnd 1k
+r2 cout gnd 1k
+* u3 in1 plot_v1
+* u4 in2 plot_v1
+* u5 sum plot_v1
+* u6 cout plot_v1
+a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(in1)
+plot v(in2)
+plot v(sum)
+plot v(cout)
+.endc
+.end
diff --git a/Examples/HalfAdder/HalfAdder.pro b/Examples/HalfAdder/HalfAdder.pro
new file mode 100644
index 00000000..8d317673
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.pro
@@ -0,0 +1,74 @@
+update=Thu Mar 3 21:34:08 2016
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Sources
+LibName8=eSim_Subckt
+LibName9=eSim_User
+LibName10=HalfAdder-rescue
+LibName11=power
+LibName12=device
+LibName13=transistors
+LibName14=conn
+LibName15=linear
+LibName16=regul
+LibName17=74xx
+LibName18=cmos4000
+LibName19=adc-dac
+LibName20=memory
+LibName21=xilinx
+LibName22=special
+LibName23=microcontrollers
+LibName24=dsp
+LibName25=microchip
+LibName26=analog_switches
+LibName27=motorola
+LibName28=texas
+LibName29=intel
+LibName30=audio
+LibName31=interface
+LibName32=digital-audio
+LibName33=philips
+LibName34=display
+LibName35=cypress
+LibName36=siliconi
+LibName37=opto
+LibName38=atmel
+LibName39=contrib
+LibName40=valves
+LibName41=eSim_Power
diff --git a/Examples/HalfAdder/HalfAdder.proj b/Examples/HalfAdder/HalfAdder.proj
new file mode 100644
index 00000000..a6ecda7d
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.proj
@@ -0,0 +1 @@
+schematicFile HalfAdder.sch
diff --git a/Examples/HalfAdder/HalfAdder.sch b/Examples/HalfAdder/HalfAdder.sch
new file mode 100644
index 00000000..604b4dcc
--- /dev/null
+++ b/Examples/HalfAdder/HalfAdder.sch
@@ -0,0 +1,313 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:HalfAdder-rescue
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Power
+LIBS:HalfAdder-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L half_adder X1
+U 1 1 558A91C8
+P 5000 3900
+F 0 "X1" H 5900 4400 60 0000 C CNN
+F 1 "half_adder" H 5900 4300 60 0000 C CNN
+F 2 "" H 5000 3900 60 0000 C CNN
+F 3 "" H 5000 3900 60 0000 C CNN
+ 1 5000 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_2 U1
+U 1 1 558A92C9
+P 4550 3500
+F 0 "U1" H 4550 3500 60 0000 C CNN
+F 1 "adc_bridge_2" H 4550 3650 60 0000 C CNN
+F 2 "" H 4550 3500 60 0000 C CNN
+F 3 "" H 4550 3500 60 0000 C CNN
+ 1 4550 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U2
+U 1 1 558A9300
+P 6950 3450
+F 0 "U2" H 6950 3450 60 0000 C CNN
+F 1 "dac_bridge_2" H 7000 3600 60 0000 C CNN
+F 2 "" H 6950 3450 60 0000 C CNN
+F 3 "" H 6950 3450 60 0000 C CNN
+ 1 6950 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v1
+U 1 1 558A9345
+P 3450 3150
+F 0 "v1" H 3250 3250 60 0000 C CNN
+F 1 "DC" H 3250 3100 60 0000 C CNN
+F 2 "R1" H 3150 3150 60 0000 C CNN
+F 3 "" H 3450 3150 60 0000 C CNN
+ 1 3450 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
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+$Comp
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+$Comp
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+$Comp
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+F 2 "" H 2850 3850 60 0000 C CNN
+F 3 "" H 2850 3850 60 0000 C CNN
+ 1 2850 3850
+ 1 0 0 -1
+$EndComp
+Text GLabel 7600 3150 0 60 Input ~ 0
+sum
+Text GLabel 7600 3750 0 60 Input ~ 0
+cout
+Text GLabel 4050 3150 2 60 Input ~ 0
+IN1
+Text GLabel 4100 3750 2 60 Input ~ 0
+IN2
+$Comp
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+F 2 "" H 7850 3330 30 0000 C CNN
+F 3 "" V 7850 3400 30 0000 C CNN
+ 1 7800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 3 "" V 7850 3650 30 0000 C CNN
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+ 1 0 0 -1
+$EndComp
+$Comp
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+F 2 "" H 3900 3300 60 0000 C CNN
+F 3 "" H 3900 3300 60 0000 C CNN
+ 1 3900 3300
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 1 1 56D8619C
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+F 2 "" H 3900 3750 60 0000 C CNN
+F 3 "" H 3900 3750 60 0000 C CNN
+ 1 3900 3750
+ -1 0 0 1
+$EndComp
+$Comp
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+F 2 "" H 7650 3250 60 0000 C CNN
+F 3 "" H 7650 3250 60 0000 C CNN
+ 1 7650 3250
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 2 "" H 7650 3650 60 0000 C CNN
+F 3 "" H 7650 3650 60 0000 C CNN
+ 1 7650 3650
+ -1 0 0 1
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3950 3250
+Wire Wire Line
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+Connection ~ 3950 3750
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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diff --git a/Examples/HalfAdder/analysis b/Examples/HalfAdder/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/HalfAdder/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/HalfAdder/half_adder.cir b/Examples/HalfAdder/half_adder.cir
new file mode 100644
index 00000000..8b2e7e06
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2 1 4 3 d_xor
+U3 1 4 2 d_and
+U1 1 4 3 2 PORT
+
+.end
diff --git a/Examples/HalfAdder/half_adder.cir.out b/Examples/HalfAdder/half_adder.cir.out
new file mode 100644
index 00000000..b1b6b1e7
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.cir.out
@@ -0,0 +1,20 @@
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+
+* u2 1 4 3 d_xor
+* u3 1 4 2 d_and
+* u1 1 4 3 2 port
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.ac lin 0 0Hz 0Hz
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/HalfAdder/half_adder.pro b/Examples/HalfAdder/half_adder.pro
new file mode 100644
index 00000000..695ae0f6
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.pro
@@ -0,0 +1,69 @@
+update=Wed Jun 24 11:27:22 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/Examples/HalfAdder/half_adder.sch b/Examples/HalfAdder/half_adder.sch
new file mode 100644
index 00000000..bf9bcbf0
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.sch
@@ -0,0 +1,152 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 558A946A
+P 5650 3050
+F 0 "U2" H 5650 3050 60 0000 C CNN
+F 1 "d_xor" H 5700 3150 47 0000 C CNN
+F 2 "" H 5650 3050 60 0000 C CNN
+F 3 "" H 5650 3050 60 0000 C CNN
+ 1 5650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 558A94D5
+P 5700 3800
+F 0 "U3" H 5700 3800 60 0000 C CNN
+F 1 "d_and" H 5750 3900 60 0000 C CNN
+F 2 "" H 5700 3800 60 0000 C CNN
+F 3 "" H 5700 3800 60 0000 C CNN
+ 1 5700 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558A94F6
+P 4150 3000
+F 0 "U1" H 4200 3100 30 0000 C CNN
+F 1 "PORT" H 4150 3000 30 0000 C CNN
+F 2 "" H 4150 3000 60 0000 C CNN
+F 3 "" H 4150 3000 60 0000 C CNN
+ 1 4150 3000
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 2 1 558A9543
+P 4150 3450
+F 0 "U1" H 4200 3550 30 0000 C CNN
+F 1 "PORT" H 4150 3450 30 0000 C CNN
+F 2 "" H 4150 3450 60 0000 C CNN
+F 3 "" H 4150 3450 60 0000 C CNN
+ 2 4150 3450
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 3 1 558A9573
+P 6650 3000
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+F 1 "PORT" H 6650 3000 30 0000 C CNN
+F 2 "" H 6650 3000 60 0000 C CNN
+F 3 "" H 6650 3000 60 0000 C CNN
+ 3 6650 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558A9606
+P 6700 3750
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+F 1 "PORT" H 6700 3750 30 0000 C CNN
+F 2 "" H 6700 3750 60 0000 C CNN
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+ 4 6700 3750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+ 4450 3000 4400 3000
+Wire Wire Line
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+Wire Wire Line
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+IN1\n\n
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+$EndSCHEMATC
diff --git a/Examples/HalfAdder/half_adder.sub b/Examples/HalfAdder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2 1 4 3 d_xor
+* u3 1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
\ No newline at end of file
diff --git a/Examples/HalfAdder/plot_data_i.txt b/Examples/HalfAdder/plot_data_i.txt
new file mode 100644
index 00000000..9c89652a
--- /dev/null
+++ b/Examples/HalfAdder/plot_data_i.txt
@@ -0,0 +1,135 @@
+ * /home/fossee/updatedexamples/half_adder/half_adder.cir
+ Transient Analysis Tue Aug 29 19:58:36 2017
+--------------------------------------------------------------------------------
+Index time a2#branch_1_0 a2#branch_1_1 v1#branch
+--------------------------------------------------------------------------------
+0 0.000000e+00 -5.00000e-03 0.000000e+00 0.000000e+00
+1 1.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
+2 2.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
+3 4.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
+4 8.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
+5 1.600000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
+6 3.200000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
+7 6.400000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
+8 1.280000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
+9 2.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
+10 4.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
+11 6.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
+12 8.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
+13 1.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+14 1.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+15 1.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+16 1.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+17 1.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+18 2.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+19 2.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+20 2.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+21 2.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+22 2.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+23 3.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+24 3.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+25 3.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+26 3.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+27 3.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+28 4.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+29 4.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+30 4.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+31 4.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+32 4.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+33 5.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+34 5.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+35 5.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+36 5.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+37 5.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+38 6.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+39 6.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+40 6.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+41 6.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+42 6.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+43 7.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+44 7.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+45 7.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+46 7.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+47 7.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+48 8.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+49 8.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+50 8.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+51 8.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+52 8.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+53 9.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+54 9.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+
+Index time a2#branch_1_0 a2#branch_1_1 v1#branch
+--------------------------------------------------------------------------------
+55 9.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+56 9.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
+58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00
+
+ * /home/fossee/updatedexamples/half_adder/half_adder.cir
+ Transient Analysis Tue Aug 29 19:58:36 2017
+--------------------------------------------------------------------------------
+Index time v2#branch
+--------------------------------------------------------------------------------
+0 0.000000e+00 0.000000e+00
+1 1.000000e-05 0.000000e+00
+2 2.000000e-05 0.000000e+00
+3 4.000000e-05 0.000000e+00
+4 8.000000e-05 0.000000e+00
+5 1.600000e-04 0.000000e+00
+6 3.200000e-04 0.000000e+00
+7 6.400000e-04 0.000000e+00
+8 1.280000e-03 0.000000e+00
+9 2.560000e-03 0.000000e+00
+10 4.560000e-03 0.000000e+00
+11 6.560000e-03 0.000000e+00
+12 8.560000e-03 0.000000e+00
+13 1.056000e-02 0.000000e+00
+14 1.256000e-02 0.000000e+00
+15 1.456000e-02 0.000000e+00
+16 1.656000e-02 0.000000e+00
+17 1.856000e-02 0.000000e+00
+18 2.056000e-02 0.000000e+00
+19 2.256000e-02 0.000000e+00
+20 2.456000e-02 0.000000e+00
+21 2.656000e-02 0.000000e+00
+22 2.856000e-02 0.000000e+00
+23 3.056000e-02 0.000000e+00
+24 3.256000e-02 0.000000e+00
+25 3.456000e-02 0.000000e+00
+26 3.656000e-02 0.000000e+00
+27 3.856000e-02 0.000000e+00
+28 4.056000e-02 0.000000e+00
+29 4.256000e-02 0.000000e+00
+30 4.456000e-02 0.000000e+00
+31 4.656000e-02 0.000000e+00
+32 4.856000e-02 0.000000e+00
+33 5.056000e-02 0.000000e+00
+34 5.256000e-02 0.000000e+00
+35 5.456000e-02 0.000000e+00
+36 5.656000e-02 0.000000e+00
+37 5.856000e-02 0.000000e+00
+38 6.056000e-02 0.000000e+00
+39 6.256000e-02 0.000000e+00
+40 6.456000e-02 0.000000e+00
+41 6.656000e-02 0.000000e+00
+42 6.856000e-02 0.000000e+00
+43 7.056000e-02 0.000000e+00
+44 7.256000e-02 0.000000e+00
+45 7.456000e-02 0.000000e+00
+46 7.656000e-02 0.000000e+00
+47 7.856000e-02 0.000000e+00
+48 8.056000e-02 0.000000e+00
+49 8.256000e-02 0.000000e+00
+50 8.456000e-02 0.000000e+00
+51 8.656000e-02 0.000000e+00
+52 8.856000e-02 0.000000e+00
+53 9.056000e-02 0.000000e+00
+54 9.256000e-02 0.000000e+00
+
+Index time v2#branch
+--------------------------------------------------------------------------------
+55 9.456000e-02 0.000000e+00
+56 9.656000e-02 0.000000e+00
+57 9.856000e-02 0.000000e+00
+58 1.000000e-01 0.000000e+00
diff --git a/Examples/HalfAdder/plot_data_v.txt b/Examples/HalfAdder/plot_data_v.txt
new file mode 100644
index 00000000..ae3453b9
--- /dev/null
+++ b/Examples/HalfAdder/plot_data_v.txt
@@ -0,0 +1,135 @@
+ * /home/fossee/updatedexamples/half_adder/half_adder.cir
+ Transient Analysis Tue Aug 29 19:58:36 2017
+--------------------------------------------------------------------------------
+Index time cout in1 in2
+--------------------------------------------------------------------------------
+0 0.000000e+00 0.000000e+00 5.000000e+00 0.000000e+00
+1 1.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
+2 2.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
+3 4.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
+4 8.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
+5 1.600000e-04 0.000000e+00 5.000000e+00 0.000000e+00
+6 3.200000e-04 0.000000e+00 5.000000e+00 0.000000e+00
+7 6.400000e-04 0.000000e+00 5.000000e+00 0.000000e+00
+8 1.280000e-03 0.000000e+00 5.000000e+00 0.000000e+00
+9 2.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
+10 4.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
+11 6.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
+12 8.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
+13 1.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+14 1.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+15 1.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+16 1.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+17 1.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+18 2.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+19 2.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+20 2.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+21 2.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+22 2.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+23 3.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+24 3.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+25 3.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+26 3.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+27 3.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+28 4.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+29 4.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+30 4.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+31 4.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+32 4.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+33 5.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+34 5.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+35 5.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+36 5.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+37 5.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+38 6.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+39 6.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+40 6.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+41 6.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+42 6.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+43 7.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+44 7.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+45 7.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+46 7.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+47 7.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+48 8.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+49 8.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+50 8.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+51 8.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+52 8.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+53 9.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+54 9.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+
+Index time cout in1 in2
+--------------------------------------------------------------------------------
+55 9.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+56 9.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+57 9.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
+58 1.000000e-01 0.000000e+00 5.000000e+00 0.000000e+00
+
+ * /home/fossee/updatedexamples/half_adder/half_adder.cir
+ Transient Analysis Tue Aug 29 19:58:36 2017
+--------------------------------------------------------------------------------
+Index time sum
+--------------------------------------------------------------------------------
+0 0.000000e+00 5.000000e+00
+1 1.000000e-05 5.000000e+00
+2 2.000000e-05 5.000000e+00
+3 4.000000e-05 5.000000e+00
+4 8.000000e-05 5.000000e+00
+5 1.600000e-04 5.000000e+00
+6 3.200000e-04 5.000000e+00
+7 6.400000e-04 5.000000e+00
+8 1.280000e-03 5.000000e+00
+9 2.560000e-03 5.000000e+00
+10 4.560000e-03 5.000000e+00
+11 6.560000e-03 5.000000e+00
+12 8.560000e-03 5.000000e+00
+13 1.056000e-02 5.000000e+00
+14 1.256000e-02 5.000000e+00
+15 1.456000e-02 5.000000e+00
+16 1.656000e-02 5.000000e+00
+17 1.856000e-02 5.000000e+00
+18 2.056000e-02 5.000000e+00
+19 2.256000e-02 5.000000e+00
+20 2.456000e-02 5.000000e+00
+21 2.656000e-02 5.000000e+00
+22 2.856000e-02 5.000000e+00
+23 3.056000e-02 5.000000e+00
+24 3.256000e-02 5.000000e+00
+25 3.456000e-02 5.000000e+00
+26 3.656000e-02 5.000000e+00
+27 3.856000e-02 5.000000e+00
+28 4.056000e-02 5.000000e+00
+29 4.256000e-02 5.000000e+00
+30 4.456000e-02 5.000000e+00
+31 4.656000e-02 5.000000e+00
+32 4.856000e-02 5.000000e+00
+33 5.056000e-02 5.000000e+00
+34 5.256000e-02 5.000000e+00
+35 5.456000e-02 5.000000e+00
+36 5.656000e-02 5.000000e+00
+37 5.856000e-02 5.000000e+00
+38 6.056000e-02 5.000000e+00
+39 6.256000e-02 5.000000e+00
+40 6.456000e-02 5.000000e+00
+41 6.656000e-02 5.000000e+00
+42 6.856000e-02 5.000000e+00
+43 7.056000e-02 5.000000e+00
+44 7.256000e-02 5.000000e+00
+45 7.456000e-02 5.000000e+00
+46 7.656000e-02 5.000000e+00
+47 7.856000e-02 5.000000e+00
+48 8.056000e-02 5.000000e+00
+49 8.256000e-02 5.000000e+00
+50 8.456000e-02 5.000000e+00
+51 8.656000e-02 5.000000e+00
+52 8.856000e-02 5.000000e+00
+53 9.056000e-02 5.000000e+00
+54 9.256000e-02 5.000000e+00
+
+Index time sum
+--------------------------------------------------------------------------------
+55 9.456000e-02 5.000000e+00
+56 9.656000e-02 5.000000e+00
+57 9.856000e-02 5.000000e+00
+58 1.000000e-01 5.000000e+00
diff --git a/Examples/Half_Adder/Half_Adder-cache.lib b/Examples/Half_Adder/Half_Adder-cache.lib
deleted file mode 100644
index fb78fe0e..00000000
--- a/Examples/Half_Adder/Half_Adder-cache.lib
+++ /dev/null
@@ -1,126 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GND-RESCUE-Half_Adder
-#
-DEF ~GND-RESCUE-Half_Adder #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-Half_Adder" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
-F3 "" 0 0 50 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# adc_bridge_2
-#
-DEF adc_bridge_2 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "adc_bridge_2" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -100 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X IN2 2 -600 -50 200 R 50 50 1 1 I
-X OUT1 3 550 50 200 L 50 50 1 1 O
-X OUT2 4 550 -50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# dac_bridge_2
-#
-DEF dac_bridge_2 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "dac_bridge_2" 50 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -250 200 350 -100 0 1 0 N
-X IN1 1 -450 50 200 R 50 50 1 1 I
-X IN2 2 -450 -50 200 R 50 50 1 1 I
-X OUT1 3 550 50 200 L 50 50 1 1 O
-X OUT4 4 550 -50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# plot_v1
-#
-DEF plot_v1 U 0 40 Y Y 1 F N
-F0 "U" 0 500 60 H V C CNN
-F1 "plot_v1" 200 350 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 500 100 0 1 0 N
-X ~ ~ 0 200 200 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Half_Adder/Half_Adder-rescue.lib b/Examples/Half_Adder/Half_Adder-rescue.lib
deleted file mode 100644
index 71251f6c..00000000
--- a/Examples/Half_Adder/Half_Adder-rescue.lib
+++ /dev/null
@@ -1,17 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND-RESCUE-Half_Adder
-#
-DEF ~GND-RESCUE-Half_Adder #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-Half_Adder" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Half_Adder/Half_Adder.cir b/Examples/Half_Adder/Half_Adder.cir
deleted file mode 100644
index 4658c5cb..00000000
--- a/Examples/Half_Adder/Half_Adder.cir
+++ /dev/null
@@ -1,21 +0,0 @@
-* /home/fossee/UpdatedExamples/Half_Adder/Half_Adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 21:35:33 2016
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder
-U1 IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2
-U2 Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2
-v1 IN1 GND DC
-v2 IN2 GND DC
-R1 sum GND 1k
-R2 cout GND 1k
-U3 IN1 plot_v1
-U4 IN2 plot_v1
-U5 sum plot_v1
-U6 cout plot_v1
-
-.end
diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out
deleted file mode 100644
index 96066fff..00000000
--- a/Examples/Half_Adder/Half_Adder.cir.out
+++ /dev/null
@@ -1,33 +0,0 @@
-* /home/fossee/updatedexamples/half_adder/half_adder.cir
-
-.include half_adder.sub
-x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
-* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
-* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
-v1 in1 gnd dc 5
-v2 in2 gnd dc 0
-r1 sum gnd 1k
-r2 cout gnd 1k
-* u3 in1 plot_v1
-* u4 in2 plot_v1
-* u5 sum plot_v1
-* u6 cout plot_v1
-a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
-a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
-* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
-.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
-* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
-.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-plot v(in1)
-plot v(in2)
-plot v(sum)
-plot v(cout)
-.endc
-.end
diff --git a/Examples/Half_Adder/Half_Adder.pro b/Examples/Half_Adder/Half_Adder.pro
deleted file mode 100644
index ed30ac59..00000000
--- a/Examples/Half_Adder/Half_Adder.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=Thu Mar 3 21:34:08 2016
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Sources
-LibName8=eSim_Subckt
-LibName9=eSim_User
-LibName10=Half_Adder-rescue
-LibName11=power
-LibName12=device
-LibName13=transistors
-LibName14=conn
-LibName15=linear
-LibName16=regul
-LibName17=74xx
-LibName18=cmos4000
-LibName19=adc-dac
-LibName20=memory
-LibName21=xilinx
-LibName22=special
-LibName23=microcontrollers
-LibName24=dsp
-LibName25=microchip
-LibName26=analog_switches
-LibName27=motorola
-LibName28=texas
-LibName29=intel
-LibName30=audio
-LibName31=interface
-LibName32=digital-audio
-LibName33=philips
-LibName34=display
-LibName35=cypress
-LibName36=siliconi
-LibName37=opto
-LibName38=atmel
-LibName39=contrib
-LibName40=valves
-LibName41=eSim_Power
diff --git a/Examples/Half_Adder/Half_Adder.proj b/Examples/Half_Adder/Half_Adder.proj
deleted file mode 100644
index cc4f1c32..00000000
--- a/Examples/Half_Adder/Half_Adder.proj
+++ /dev/null
@@ -1 +0,0 @@
-schematicFile Half_Adder.sch
diff --git a/Examples/Half_Adder/Half_Adder.sch b/Examples/Half_Adder/Half_Adder.sch
deleted file mode 100644
index fa25e435..00000000
--- a/Examples/Half_Adder/Half_Adder.sch
+++ /dev/null
@@ -1,313 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:Half_Adder-rescue
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Power
-LIBS:Half_Adder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L half_adder X1
-U 1 1 558A91C8
-P 5000 3900
-F 0 "X1" H 5900 4400 60 0000 C CNN
-F 1 "half_adder" H 5900 4300 60 0000 C CNN
-F 2 "" H 5000 3900 60 0000 C CNN
-F 3 "" H 5000 3900 60 0000 C CNN
- 1 5000 3900
- 1 0 0 -1
-$EndComp
-$Comp
-L adc_bridge_2 U1
-U 1 1 558A92C9
-P 4550 3500
-F 0 "U1" H 4550 3500 60 0000 C CNN
-F 1 "adc_bridge_2" H 4550 3650 60 0000 C CNN
-F 2 "" H 4550 3500 60 0000 C CNN
-F 3 "" H 4550 3500 60 0000 C CNN
- 1 4550 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L dac_bridge_2 U2
-U 1 1 558A9300
-P 6950 3450
-F 0 "U2" H 6950 3450 60 0000 C CNN
-F 1 "dac_bridge_2" H 7000 3600 60 0000 C CNN
-F 2 "" H 6950 3450 60 0000 C CNN
-F 3 "" H 6950 3450 60 0000 C CNN
- 1 6950 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L DC v1
-U 1 1 558A9345
-P 3450 3150
-F 0 "v1" H 3250 3250 60 0000 C CNN
-F 1 "DC" H 3250 3100 60 0000 C CNN
-F 2 "R1" H 3150 3150 60 0000 C CNN
-F 3 "" H 3450 3150 60 0000 C CNN
- 1 3450 3150
- 0 1 1 0
-$EndComp
-$Comp
-L DC v2
-U 1 1 558A937C
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deleted file mode 100644
index 660a46cc..00000000
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+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
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diff --git a/Examples/Half_Adder/half_adder.cir b/Examples/Half_Adder/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/Examples/Half_Adder/half_adder.cir
+++ /dev/null
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-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
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diff --git a/Examples/Half_Adder/half_adder.cir.out b/Examples/Half_Adder/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/Examples/Half_Adder/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
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-
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-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.ac lin 0 0Hz 0Hz
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-* Control Statements
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-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Half_Adder/half_adder.pro b/Examples/Half_Adder/half_adder.pro
deleted file mode 100644
index 695ae0f6..00000000
--- a/Examples/Half_Adder/half_adder.pro
+++ /dev/null
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-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/Examples/Half_Adder/half_adder.sch b/Examples/Half_Adder/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/Examples/Half_Adder/half_adder.sch
+++ /dev/null
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diff --git a/Examples/Half_Adder/half_adder.sub b/Examples/Half_Adder/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/Examples/Half_Adder/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
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-* u3 1 4 2 d_and
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-* Control Statements
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\ No newline at end of file
diff --git a/Examples/Half_Adder/plot_data_i.txt b/Examples/Half_Adder/plot_data_i.txt
deleted file mode 100644
index 9c89652a..00000000
--- a/Examples/Half_Adder/plot_data_i.txt
+++ /dev/null
@@ -1,135 +0,0 @@
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Tue Aug 29 19:58:36 2017
---------------------------------------------------------------------------------
-Index time a2#branch_1_0 a2#branch_1_1 v1#branch
---------------------------------------------------------------------------------
-0 0.000000e+00 -5.00000e-03 0.000000e+00 0.000000e+00
-1 1.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
-2 2.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
-3 4.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
-4 8.000000e-05 -5.00000e-03 0.000000e+00 0.000000e+00
-5 1.600000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
-6 3.200000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
-7 6.400000e-04 -5.00000e-03 0.000000e+00 0.000000e+00
-8 1.280000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
-9 2.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
-10 4.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
-11 6.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
-12 8.560000e-03 -5.00000e-03 0.000000e+00 0.000000e+00
-13 1.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-14 1.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-15 1.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-16 1.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-17 1.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-18 2.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-19 2.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-20 2.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-21 2.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-22 2.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-23 3.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-24 3.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-25 3.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-26 3.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-27 3.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-28 4.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-29 4.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-30 4.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-31 4.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-32 4.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-33 5.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-34 5.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-35 5.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-36 5.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-37 5.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
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-40 6.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-41 6.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-42 6.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-43 7.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-44 7.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-45 7.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-46 7.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-47 7.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-48 8.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-49 8.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-50 8.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-51 8.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-52 8.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-53 9.056000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-54 9.256000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
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-Index time a2#branch_1_0 a2#branch_1_1 v1#branch
---------------------------------------------------------------------------------
-55 9.456000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-56 9.656000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
-58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00
-
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Tue Aug 29 19:58:36 2017
---------------------------------------------------------------------------------
-Index time v2#branch
---------------------------------------------------------------------------------
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-1 1.000000e-05 0.000000e+00
-2 2.000000e-05 0.000000e+00
-3 4.000000e-05 0.000000e+00
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-7 6.400000e-04 0.000000e+00
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-10 4.560000e-03 0.000000e+00
-11 6.560000e-03 0.000000e+00
-12 8.560000e-03 0.000000e+00
-13 1.056000e-02 0.000000e+00
-14 1.256000e-02 0.000000e+00
-15 1.456000e-02 0.000000e+00
-16 1.656000e-02 0.000000e+00
-17 1.856000e-02 0.000000e+00
-18 2.056000e-02 0.000000e+00
-19 2.256000e-02 0.000000e+00
-20 2.456000e-02 0.000000e+00
-21 2.656000e-02 0.000000e+00
-22 2.856000e-02 0.000000e+00
-23 3.056000e-02 0.000000e+00
-24 3.256000e-02 0.000000e+00
-25 3.456000e-02 0.000000e+00
-26 3.656000e-02 0.000000e+00
-27 3.856000e-02 0.000000e+00
-28 4.056000e-02 0.000000e+00
-29 4.256000e-02 0.000000e+00
-30 4.456000e-02 0.000000e+00
-31 4.656000e-02 0.000000e+00
-32 4.856000e-02 0.000000e+00
-33 5.056000e-02 0.000000e+00
-34 5.256000e-02 0.000000e+00
-35 5.456000e-02 0.000000e+00
-36 5.656000e-02 0.000000e+00
-37 5.856000e-02 0.000000e+00
-38 6.056000e-02 0.000000e+00
-39 6.256000e-02 0.000000e+00
-40 6.456000e-02 0.000000e+00
-41 6.656000e-02 0.000000e+00
-42 6.856000e-02 0.000000e+00
-43 7.056000e-02 0.000000e+00
-44 7.256000e-02 0.000000e+00
-45 7.456000e-02 0.000000e+00
-46 7.656000e-02 0.000000e+00
-47 7.856000e-02 0.000000e+00
-48 8.056000e-02 0.000000e+00
-49 8.256000e-02 0.000000e+00
-50 8.456000e-02 0.000000e+00
-51 8.656000e-02 0.000000e+00
-52 8.856000e-02 0.000000e+00
-53 9.056000e-02 0.000000e+00
-54 9.256000e-02 0.000000e+00
-
-Index time v2#branch
---------------------------------------------------------------------------------
-55 9.456000e-02 0.000000e+00
-56 9.656000e-02 0.000000e+00
-57 9.856000e-02 0.000000e+00
-58 1.000000e-01 0.000000e+00
diff --git a/Examples/Half_Adder/plot_data_v.txt b/Examples/Half_Adder/plot_data_v.txt
deleted file mode 100644
index ae3453b9..00000000
--- a/Examples/Half_Adder/plot_data_v.txt
+++ /dev/null
@@ -1,135 +0,0 @@
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Tue Aug 29 19:58:36 2017
---------------------------------------------------------------------------------
-Index time cout in1 in2
---------------------------------------------------------------------------------
-0 0.000000e+00 0.000000e+00 5.000000e+00 0.000000e+00
-1 1.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
-2 2.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
-3 4.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
-4 8.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00
-5 1.600000e-04 0.000000e+00 5.000000e+00 0.000000e+00
-6 3.200000e-04 0.000000e+00 5.000000e+00 0.000000e+00
-7 6.400000e-04 0.000000e+00 5.000000e+00 0.000000e+00
-8 1.280000e-03 0.000000e+00 5.000000e+00 0.000000e+00
-9 2.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
-10 4.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
-11 6.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
-12 8.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00
-13 1.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-14 1.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-15 1.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-16 1.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-17 1.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-18 2.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-19 2.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-20 2.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-21 2.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-22 2.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-23 3.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-24 3.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-25 3.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-26 3.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-27 3.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-28 4.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-29 4.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-30 4.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-31 4.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-32 4.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-33 5.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-34 5.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-35 5.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-36 5.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-37 5.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-38 6.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-39 6.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-40 6.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-41 6.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-42 6.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-43 7.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-44 7.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-45 7.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-46 7.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-47 7.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-48 8.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-49 8.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-50 8.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-51 8.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-52 8.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-53 9.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-54 9.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-
-Index time cout in1 in2
---------------------------------------------------------------------------------
-55 9.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-56 9.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-57 9.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00
-58 1.000000e-01 0.000000e+00 5.000000e+00 0.000000e+00
-
- * /home/fossee/updatedexamples/half_adder/half_adder.cir
- Transient Analysis Tue Aug 29 19:58:36 2017
---------------------------------------------------------------------------------
-Index time sum
---------------------------------------------------------------------------------
-0 0.000000e+00 5.000000e+00
-1 1.000000e-05 5.000000e+00
-2 2.000000e-05 5.000000e+00
-3 4.000000e-05 5.000000e+00
-4 8.000000e-05 5.000000e+00
-5 1.600000e-04 5.000000e+00
-6 3.200000e-04 5.000000e+00
-7 6.400000e-04 5.000000e+00
-8 1.280000e-03 5.000000e+00
-9 2.560000e-03 5.000000e+00
-10 4.560000e-03 5.000000e+00
-11 6.560000e-03 5.000000e+00
-12 8.560000e-03 5.000000e+00
-13 1.056000e-02 5.000000e+00
-14 1.256000e-02 5.000000e+00
-15 1.456000e-02 5.000000e+00
-16 1.656000e-02 5.000000e+00
-17 1.856000e-02 5.000000e+00
-18 2.056000e-02 5.000000e+00
-19 2.256000e-02 5.000000e+00
-20 2.456000e-02 5.000000e+00
-21 2.656000e-02 5.000000e+00
-22 2.856000e-02 5.000000e+00
-23 3.056000e-02 5.000000e+00
-24 3.256000e-02 5.000000e+00
-25 3.456000e-02 5.000000e+00
-26 3.656000e-02 5.000000e+00
-27 3.856000e-02 5.000000e+00
-28 4.056000e-02 5.000000e+00
-29 4.256000e-02 5.000000e+00
-30 4.456000e-02 5.000000e+00
-31 4.656000e-02 5.000000e+00
-32 4.856000e-02 5.000000e+00
-33 5.056000e-02 5.000000e+00
-34 5.256000e-02 5.000000e+00
-35 5.456000e-02 5.000000e+00
-36 5.656000e-02 5.000000e+00
-37 5.856000e-02 5.000000e+00
-38 6.056000e-02 5.000000e+00
-39 6.256000e-02 5.000000e+00
-40 6.456000e-02 5.000000e+00
-41 6.656000e-02 5.000000e+00
-42 6.856000e-02 5.000000e+00
-43 7.056000e-02 5.000000e+00
-44 7.256000e-02 5.000000e+00
-45 7.456000e-02 5.000000e+00
-46 7.656000e-02 5.000000e+00
-47 7.856000e-02 5.000000e+00
-48 8.056000e-02 5.000000e+00
-49 8.256000e-02 5.000000e+00
-50 8.456000e-02 5.000000e+00
-51 8.656000e-02 5.000000e+00
-52 8.856000e-02 5.000000e+00
-53 9.056000e-02 5.000000e+00
-54 9.256000e-02 5.000000e+00
-
-Index time sum
---------------------------------------------------------------------------------
-55 9.456000e-02 5.000000e+00
-56 9.656000e-02 5.000000e+00
-57 9.856000e-02 5.000000e+00
-58 1.000000e-01 5.000000e+00
--
cgit
From be75bc43e5cd58c8c4e23b3f35911f4e69cd5928 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Tue, 12 Mar 2019 11:41:47 +0530
Subject: add missing lib files
---
Examples/CMOS_Inverter/NMOS-0.5um.lib | 6 ++++++
Examples/CMOS_Inverter/PMOS-0.5um.lib | 6 ++++++
2 files changed, 12 insertions(+)
create mode 100644 Examples/CMOS_Inverter/NMOS-0.5um.lib
create mode 100644 Examples/CMOS_Inverter/PMOS-0.5um.lib
(limited to 'Examples')
diff --git a/Examples/CMOS_Inverter/NMOS-0.5um.lib b/Examples/CMOS_Inverter/NMOS-0.5um.lib
new file mode 100644
index 00000000..2e6f4635
--- /dev/null
+++ b/Examples/CMOS_Inverter/NMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/Examples/CMOS_Inverter/PMOS-0.5um.lib b/Examples/CMOS_Inverter/PMOS-0.5um.lib
new file mode 100644
index 00000000..848e8b05
--- /dev/null
+++ b/Examples/CMOS_Inverter/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25
++ NSUB=1.0E17 )
\ No newline at end of file
--
cgit
From d2b775bde7bde4396c251ddac6685d503d0577d8 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Tue, 12 Mar 2019 14:34:31 +0530
Subject: update files from eSim-Examples
---
Examples/BJT_Biascircuit/BJT_Biascircuit.pro | 2 +-
Examples/BasicGates/BasicGates.pro | 2 +-
Examples/Differentiator/ua741.pro | 2 +-
Examples/FullAdder/full_adder.pro | 12 ++++++------
Examples/FullAdder/half_adder.pro | 12 ++++++------
Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro | 2 +-
Examples/HalfAdder/half_adder.pro | 12 ++++++------
Examples/Integrator/ua741.pro | 2 +-
Examples/InvertingAmplifier/ua741.pro | 2 +-
9 files changed, 24 insertions(+), 24 deletions(-)
(limited to 'Examples')
diff --git a/Examples/BJT_Biascircuit/BJT_Biascircuit.pro b/Examples/BJT_Biascircuit/BJT_Biascircuit.pro
index 9f81a62b..c1ec838a 100644
--- a/Examples/BJT_Biascircuit/BJT_Biascircuit.pro
+++ b/Examples/BJT_Biascircuit/BJT_Biascircuit.pro
@@ -68,4 +68,4 @@ LibName34=linear
LibName35=regul
LibName36=74xx
LibName37=cmos4000
-LibName38=/home/fossee/library/eSim_Plot
+LibName38=eSim_Plot
diff --git a/Examples/BasicGates/BasicGates.pro b/Examples/BasicGates/BasicGates.pro
index 329f39fa..9a900c43 100644
--- a/Examples/BasicGates/BasicGates.pro
+++ b/Examples/BasicGates/BasicGates.pro
@@ -2,7 +2,7 @@ update=Mon Feb 29 21:50:04 2016
last_client=eeschema
[eeschema]
version=1
-LibDir=/home/yogesh/FreeEDA/library
+LibDir=
[eeschema/libraries]
LibName1=BasicGates-rescue
LibName2=eSim_Analog
diff --git a/Examples/Differentiator/ua741.pro b/Examples/Differentiator/ua741.pro
index 5dbb81a5..be9bc92c 100644
--- a/Examples/Differentiator/ua741.pro
+++ b/Examples/Differentiator/ua741.pro
@@ -2,7 +2,7 @@ update=Monday 17 December 2012 06:14:06 PM IST
last_client=eeschema
[eeschema]
version=1
-LibDir=/home/yogesh/FreeEDA/library
+LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
diff --git a/Examples/FullAdder/full_adder.pro b/Examples/FullAdder/full_adder.pro
index c0db0775..0bd0d5af 100644
--- a/Examples/FullAdder/full_adder.pro
+++ b/Examples/FullAdder/full_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
+LibName31=eSim_Analog
+LibName32=eSim_Devices
+LibName33=eSim_Digital
+LibName34=eSim_Hybrid
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/Examples/FullAdder/half_adder.pro b/Examples/FullAdder/half_adder.pro
index 695ae0f6..30094fb9 100644
--- a/Examples/FullAdder/half_adder.pro
+++ b/Examples/FullAdder/half_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
+LibName31=eSim_Analog
+LibName32=eSim_Devices
+LibName33=eSim_Digital
+LibName34=eSim_Hybrid
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro
index 1dea64f7..d3c879a9 100644
--- a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro
@@ -68,4 +68,4 @@ LibName34=linear
LibName35=regul
LibName36=74xx
LibName37=cmos4000
-LibName38=/home/fossee/library/eSim_Plot
+LibName38=eSim_Plot
diff --git a/Examples/HalfAdder/half_adder.pro b/Examples/HalfAdder/half_adder.pro
index 695ae0f6..30094fb9 100644
--- a/Examples/HalfAdder/half_adder.pro
+++ b/Examples/HalfAdder/half_adder.pro
@@ -61,9 +61,9 @@ LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
+LibName31=eSim_Analog
+LibName32=eSim_Devices
+LibName33=eSim_Digital
+LibName34=eSim_Hybrid
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/Examples/Integrator/ua741.pro b/Examples/Integrator/ua741.pro
index 5dbb81a5..be9bc92c 100644
--- a/Examples/Integrator/ua741.pro
+++ b/Examples/Integrator/ua741.pro
@@ -2,7 +2,7 @@ update=Monday 17 December 2012 06:14:06 PM IST
last_client=eeschema
[eeschema]
version=1
-LibDir=/home/yogesh/FreeEDA/library
+LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
diff --git a/Examples/InvertingAmplifier/ua741.pro b/Examples/InvertingAmplifier/ua741.pro
index 5dbb81a5..be9bc92c 100644
--- a/Examples/InvertingAmplifier/ua741.pro
+++ b/Examples/InvertingAmplifier/ua741.pro
@@ -2,7 +2,7 @@ update=Monday 17 December 2012 06:14:06 PM IST
last_client=eeschema
[eeschema]
version=1
-LibDir=/home/yogesh/FreeEDA/library
+LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
--
cgit
From 7b559bc99379a475866479137f3ee2ed4dfbab86 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Tue, 12 Mar 2019 12:30:33 +0530
Subject: remove extra + at the start
---
Examples/BJT_Biascircuit/NPN.lib | 5 +----
Examples/BJT_CB_config/NPN.lib | 5 +----
Examples/BJT_CE_config/NPN.lib | 5 +----
Examples/BJT_Frequency_Response/NPN.lib | 5 +----
Examples/BJT_amplifier/NPN.lib | 5 +----
Examples/CMOS_Inverter/NMOS-0.5um.lib | 7 +------
Examples/CMOS_Inverter/PMOS-0.5um.lib | 7 +------
Examples/Clampercircuit/D.lib | 3 +--
Examples/Clippercircuit/D.lib | 3 +--
Examples/Diac_Triac/PowerDiode.lib | 21 +--------------------
Examples/Diode_characteristics/D.lib | 3 +--
Examples/FET_Amplifier/NJF.lib | 5 +----
Examples/FET_Characteristic/NJF.lib | 5 +----
Examples/FrequencyResponse_JFET/NJF.lib | 5 +----
Examples/FullwaveRectifier_SCR/D.lib | 21 +--------------------
Examples/FullwaveRectifier_SCR/PowerDiode.lib | 21 +--------------------
Examples/Fullwavebridgerectifier/D.lib | 3 +--
Examples/HalfwaveRectifier_SCR/PowerDiode.lib | 21 +--------------------
Examples/Halfwave_Rectifier/D.lib | 3 +--
19 files changed, 19 insertions(+), 134 deletions(-)
(limited to 'Examples')
diff --git a/Examples/BJT_Biascircuit/NPN.lib b/Examples/BJT_Biascircuit/NPN.lib
index 6509fe7a..382b5380 100644
--- a/Examples/BJT_Biascircuit/NPN.lib
+++ b/Examples/BJT_Biascircuit/NPN.lib
@@ -1,4 +1 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
diff --git a/Examples/BJT_CB_config/NPN.lib b/Examples/BJT_CB_config/NPN.lib
index 6509fe7a..382b5380 100644
--- a/Examples/BJT_CB_config/NPN.lib
+++ b/Examples/BJT_CB_config/NPN.lib
@@ -1,4 +1 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
diff --git a/Examples/BJT_CE_config/NPN.lib b/Examples/BJT_CE_config/NPN.lib
index 6509fe7a..382b5380 100644
--- a/Examples/BJT_CE_config/NPN.lib
+++ b/Examples/BJT_CE_config/NPN.lib
@@ -1,4 +1 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
diff --git a/Examples/BJT_Frequency_Response/NPN.lib b/Examples/BJT_Frequency_Response/NPN.lib
index 6509fe7a..382b5380 100644
--- a/Examples/BJT_Frequency_Response/NPN.lib
+++ b/Examples/BJT_Frequency_Response/NPN.lib
@@ -1,4 +1 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
diff --git a/Examples/BJT_amplifier/NPN.lib b/Examples/BJT_amplifier/NPN.lib
index 6509fe7a..382b5380 100644
--- a/Examples/BJT_amplifier/NPN.lib
+++ b/Examples/BJT_amplifier/NPN.lib
@@ -1,4 +1 @@
-.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
-+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
-+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
-+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 )
diff --git a/Examples/CMOS_Inverter/NMOS-0.5um.lib b/Examples/CMOS_Inverter/NMOS-0.5um.lib
index 2e6f4635..a38a9673 100644
--- a/Examples/CMOS_Inverter/NMOS-0.5um.lib
+++ b/Examples/CMOS_Inverter/NMOS-0.5um.lib
@@ -1,6 +1 @@
-.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05
-+ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1
-+ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3
-+ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7
-+ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88
-+ NSUB=1.40E17 )
\ No newline at end of file
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 NSUB=1.40E17 )
diff --git a/Examples/CMOS_Inverter/PMOS-0.5um.lib b/Examples/CMOS_Inverter/PMOS-0.5um.lib
index 848e8b05..12ae53b8 100644
--- a/Examples/CMOS_Inverter/PMOS-0.5um.lib
+++ b/Examples/CMOS_Inverter/PMOS-0.5um.lib
@@ -1,6 +1 @@
-.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u
-+ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1
-+ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3
-+ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7
-+ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25
-+ NSUB=1.0E17 )
\ No newline at end of file
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 NSUB=1.0E17 )
diff --git a/Examples/Clampercircuit/D.lib b/Examples/Clampercircuit/D.lib
index 8a7fb4da..974dd402 100644
--- a/Examples/Clampercircuit/D.lib
+++ b/Examples/Clampercircuit/D.lib
@@ -1,2 +1 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
+.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
diff --git a/Examples/Clippercircuit/D.lib b/Examples/Clippercircuit/D.lib
index 8a7fb4da..974dd402 100644
--- a/Examples/Clippercircuit/D.lib
+++ b/Examples/Clippercircuit/D.lib
@@ -1,2 +1 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
+.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
diff --git a/Examples/Diac_Triac/PowerDiode.lib b/Examples/Diac_Triac/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/Diac_Triac/PowerDiode.lib
+++ b/Examples/Diac_Triac/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/Diode_characteristics/D.lib b/Examples/Diode_characteristics/D.lib
index 8a7fb4da..974dd402 100644
--- a/Examples/Diode_characteristics/D.lib
+++ b/Examples/Diode_characteristics/D.lib
@@ -1,2 +1 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
+.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
diff --git a/Examples/FET_Amplifier/NJF.lib b/Examples/FET_Amplifier/NJF.lib
index dbb2cbae..a9ea544f 100644
--- a/Examples/FET_Amplifier/NJF.lib
+++ b/Examples/FET_Amplifier/NJF.lib
@@ -1,4 +1 @@
-.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+ Af=1)
+.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
diff --git a/Examples/FET_Characteristic/NJF.lib b/Examples/FET_Characteristic/NJF.lib
index dbb2cbae..a9ea544f 100644
--- a/Examples/FET_Characteristic/NJF.lib
+++ b/Examples/FET_Characteristic/NJF.lib
@@ -1,4 +1 @@
-.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+ Af=1)
+.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
diff --git a/Examples/FrequencyResponse_JFET/NJF.lib b/Examples/FrequencyResponse_JFET/NJF.lib
index dbb2cbae..a9ea544f 100644
--- a/Examples/FrequencyResponse_JFET/NJF.lib
+++ b/Examples/FrequencyResponse_JFET/NJF.lib
@@ -1,4 +1 @@
-.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
-+ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
-+ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
-+ Af=1)
+.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 )
diff --git a/Examples/FullwaveRectifier_SCR/D.lib b/Examples/FullwaveRectifier_SCR/D.lib
index ef18bb50..89b96f4a 100644
--- a/Examples/FullwaveRectifier_SCR/D.lib
+++ b/Examples/FullwaveRectifier_SCR/D.lib
@@ -1,20 +1 @@
-.MODEL D1N750 D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ Bv=8.1
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=880.5E-18
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
+.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/FullwaveRectifier_SCR/PowerDiode.lib b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/FullwaveRectifier_SCR/PowerDiode.lib
+++ b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/Fullwavebridgerectifier/D.lib b/Examples/Fullwavebridgerectifier/D.lib
index 8a7fb4da..974dd402 100644
--- a/Examples/Fullwavebridgerectifier/D.lib
+++ b/Examples/Fullwavebridgerectifier/D.lib
@@ -1,2 +1 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
+.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
diff --git a/Examples/HalfwaveRectifier_SCR/PowerDiode.lib b/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
+++ b/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
\ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/Halfwave_Rectifier/D.lib b/Examples/Halfwave_Rectifier/D.lib
index 8a7fb4da..974dd402 100644
--- a/Examples/Halfwave_Rectifier/D.lib
+++ b/Examples/Halfwave_Rectifier/D.lib
@@ -1,2 +1 @@
-.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
-
+.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 )
--
cgit
From aec27ddec95f30c155ad356da24eb7e3ce2247cd Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Wed, 13 Mar 2019 11:09:17 +0530
Subject: rename one of the versions of D.lib to userDiode.lib
---
Examples/FullwaveRectifier_SCR/D.lib | 1 -
Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out | 2 +-
Examples/FullwaveRectifier_SCR/userDiode.lib | 1 +
3 files changed, 2 insertions(+), 2 deletions(-)
delete mode 100644 Examples/FullwaveRectifier_SCR/D.lib
create mode 100644 Examples/FullwaveRectifier_SCR/userDiode.lib
(limited to 'Examples')
diff --git a/Examples/FullwaveRectifier_SCR/D.lib b/Examples/FullwaveRectifier_SCR/D.lib
deleted file mode 100644
index 89b96f4a..00000000
--- a/Examples/FullwaveRectifier_SCR/D.lib
+++ /dev/null
@@ -1 +0,0 @@
-.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
index 2bc6d6d7..46179b0f 100644
--- a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
+++ b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
@@ -1,7 +1,7 @@
* /home/fossee/updatedexamples/fullwaverectifier_scr/fullwaverectifier_scr.cir
.include scr.sub
-.include D.lib
+.include userDiode.lib
x1 gnd pulse out2 scr
v1 in1 in2 sine(0 200 100 0 0)
v2 pulse gnd pulse(0 5 2m 0 0 1m 5m)
diff --git a/Examples/FullwaveRectifier_SCR/userDiode.lib b/Examples/FullwaveRectifier_SCR/userDiode.lib
new file mode 100644
index 00000000..89b96f4a
--- /dev/null
+++ b/Examples/FullwaveRectifier_SCR/userDiode.lib
@@ -0,0 +1 @@
+.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )
--
cgit