From 206afcded42d55572509e3439d752c9a81c84785 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Wed, 30 Dec 2015 12:31:05 +0530
Subject: Added : 1. Power Examples 2. eSim_Power.lib 3. DeviceModel for
 Powerdiode and Zenerdiode 4. Subcicuit for scr, diac, triac

---
 Examples/fullwaverec/scr.sub~ | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Examples/fullwaverec/scr.sub~

(limited to 'Examples/fullwaverec/scr.sub~')

diff --git a/Examples/fullwaverec/scr.sub~ b/Examples/fullwaverec/scr.sub~
new file mode 100644
index 00000000..5e23f45d
--- /dev/null
+++ b/Examples/fullwaverec/scr.sub~
@@ -0,0 +1,24 @@
+* Subcircuit scr
+.subckt scr 3 5 1 
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+.include D.lib
+* f2
+d1 8 2 D1N750
+c1  3 4 10u
+r2  3 4 1
+* f1
+r1  5 6 50
+v1 6 7  dc 0
+v2 9 8  dc 0
+* u1  4 1 9 aswitch
+Vf2 2 3 0
+f2 3 4 Vf2 100
+Vf1 7 3 0
+f1 3 4 Vf1 10
+a1 4 (1 9) u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
+
+* Control Statements
+
+.ends scr
-- 
cgit