From 206afcded42d55572509e3439d752c9a81c84785 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Wed, 30 Dec 2015 12:31:05 +0530
Subject: Added : 1. Power Examples 2. eSim_Power.lib 3. DeviceModel for
 Powerdiode and Zenerdiode 4. Subcicuit for scr, diac, triac

---
 Examples/acvoltcnt1/triac.sub | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Examples/acvoltcnt1/triac.sub

(limited to 'Examples/acvoltcnt1/triac.sub')

diff --git a/Examples/acvoltcnt1/triac.sub b/Examples/acvoltcnt1/triac.sub
new file mode 100644
index 00000000..760908b0
--- /dev/null
+++ b/Examples/acvoltcnt1/triac.sub
@@ -0,0 +1,32 @@
+* Subcircuit triac
+.subckt triac 8 11 10 
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+.include PowerDiode.lib
+* f3
+v3 7 2  dc 0
+* f2
+v2 6 3  dc 0
+c1  8 9 10u
+* f1
+v1 10 4  dc 0
+* u1  9 11 6 aswitch
+* u2  9 2 11 aswitch
+r1  8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 (11 6)  u1
+a2 9 (2 11)  u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+
+* Control Statements
+
+.ends triac
-- 
cgit