From 206afcded42d55572509e3439d752c9a81c84785 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Wed, 30 Dec 2015 12:31:05 +0530
Subject: Added : 1. Power Examples 2. eSim_Power.lib 3. DeviceModel for
 Powerdiode and Zenerdiode 4. Subcicuit for scr, diac, triac

---
 Examples/acvoltcnt1/diac.cir.out | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Examples/acvoltcnt1/diac.cir.out

(limited to 'Examples/acvoltcnt1/diac.cir.out')

diff --git a/Examples/acvoltcnt1/diac.cir.out b/Examples/acvoltcnt1/diac.cir.out
new file mode 100644
index 00000000..a1e31f14
--- /dev/null
+++ b/Examples/acvoltcnt1/diac.cir.out
@@ -0,0 +1,21 @@
+* /opt/esim/src/subcircuitlibrary/diac/diac.cir
+
+* u3  1 2 port
+* u1  1 1 2 aswitch
+* u2  1 1 2 aswitch
+a1 1 (1 2)  u1
+a2 1 (1 2)  u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) 
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) 
+ 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
-- 
cgit