From 206afcded42d55572509e3439d752c9a81c84785 Mon Sep 17 00:00:00 2001
From: Fahim
Date: Wed, 30 Dec 2015 12:31:05 +0530
Subject: Added : 1. Power Examples 2. eSim_Power.lib 3. DeviceModel for
 Powerdiode and Zenerdiode 4. Subcicuit for scr, diac, triac

---
 Examples/acvoltcnt1/diac.bak | 138 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 138 insertions(+)
 create mode 100644 Examples/acvoltcnt1/diac.bak

(limited to 'Examples/acvoltcnt1/diac.bak')

diff --git a/Examples/acvoltcnt1/diac.bak b/Examples/acvoltcnt1/diac.bak
new file mode 100644
index 00000000..16009984
--- /dev/null
+++ b/Examples/acvoltcnt1/diac.bak
@@ -0,0 +1,138 @@
+EESchema Schematic File Version 2  date 09/22/14 16:36:31
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:diac-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 sep 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	4150 2750 4150 3450
+Connection ~ 4400 3750
+Wire Wire Line
+	4900 4250 4900 4450
+Wire Wire Line
+	4900 4450 4400 4450
+Wire Wire Line
+	4400 4450 4400 3450
+Wire Wire Line
+	5200 3400 5200 4050
+Connection ~ 4600 3400
+Wire Wire Line
+	4600 4050 4600 2750
+Wire Wire Line
+	4600 2750 4150 2750
+Wire Wire Line
+	4150 3250 4150 3600
+Wire Wire Line
+	4400 3450 4150 3450
+Connection ~ 4150 3450
+Wire Wire Line
+	4400 3750 4900 3750
+Wire Wire Line
+	4900 3750 4900 3600
+Wire Wire Line
+	4150 4100 4150 4300
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5417D647
+P 4150 4300
+F 0 "#FLG01" H 4150 4570 30  0001 C CNN
+F 1 "PWR_FLAG" H 4150 4530 30  0000 C CNN
+	1    4150 4300
+	0    1    1    0   
+$EndComp
+$Comp
+L PORT U3
+U 2 1 5417D62C
+P 5450 3400
+F 0 "U3" H 5450 3350 30  0000 C CNN
+F 1 "PORT" H 5450 3400 30  0000 C CNN
+	2    5450 3400
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U3
+U 1 1 5417D624
+P 4150 2500
+F 0 "U3" H 4150 2450 30  0000 C CNN
+F 1 "PORT" H 4150 2500 30  0000 C CNN
+	1    4150 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5417D5DC
+P 4150 4300
+F 0 "#PWR02" H 4150 4300 30  0001 C CNN
+F 1 "GND" H 4150 4230 30  0001 C CNN
+	1    4150 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L ANALOGSWITCH U2
+U 1 1 5417D537
+P 4900 4050
+F 0 "U2" H 4700 4100 30  0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 4050 30  0000 C CNN
+	1    4900 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L ANALOGSWITCH U1
+U 1 1 5417D530
+P 4900 3400
+F 0 "U1" H 4700 3450 30  0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 3400 30  0000 C CNN
+	1    4900 3400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
-- 
cgit