From ef380a4a6a2ff4c90bde90c41296e94f5db70389 Mon Sep 17 00:00:00 2001
From: Sunil Shetye
Date: Mon, 11 Mar 2019 15:57:40 +0530
Subject: Half adder subcircuit filename conflict in Windows

Replaced Half_Adder example with renamed HalfAdder to avoid Windows
case-only filename difference conflict with subcircuit half_adder.

Based on contribution by https://github.com/MaxOLydian/eSim
---
 Examples/Half_Adder/half_adder.cir.out | 20 --------------------
 1 file changed, 20 deletions(-)
 delete mode 100644 Examples/Half_Adder/half_adder.cir.out

(limited to 'Examples/Half_Adder/half_adder.cir.out')

diff --git a/Examples/Half_Adder/half_adder.cir.out b/Examples/Half_Adder/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/Examples/Half_Adder/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
-- 
cgit